1//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines an instruction selector for the SPARC target.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SparcSelectionDAGInfo.h"
14#include "SparcTargetMachine.h"
15#include "llvm/CodeGen/MachineRegisterInfo.h"
16#include "llvm/CodeGen/SelectionDAGISel.h"
17#include "llvm/Support/ErrorHandling.h"
18using namespace llvm;
19
20#define DEBUG_TYPE "sparc-isel"
21#define PASS_NAME "SPARC DAG->DAG Pattern Instruction Selection"
22
23//===----------------------------------------------------------------------===//
24// Instruction Selector Implementation
25//===----------------------------------------------------------------------===//
26
27//===--------------------------------------------------------------------===//
28/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
29/// instructions for SelectionDAG operations.
30///
31namespace {
32class SparcDAGToDAGISel : public SelectionDAGISel {
33 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
34 /// make the right decision when generating code for different targets.
35 const SparcSubtarget *Subtarget = nullptr;
36
37public:
38 SparcDAGToDAGISel() = delete;
39
40 explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(tm) {}
41
42 bool runOnMachineFunction(MachineFunction &MF) override {
43 Subtarget = &MF.getSubtarget<SparcSubtarget>();
44 return SelectionDAGISel::runOnMachineFunction(mf&: MF);
45 }
46
47 void Select(SDNode *N) override;
48
49 // Complex Pattern Selectors.
50 bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
51 bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
52 bool SelectForceADDRrr(SDValue N, SDValue &Base, SDValue &Disp);
53
54 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
55 /// inline asm expressions.
56 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
57 InlineAsm::ConstraintCode ConstraintID,
58 std::vector<SDValue> &OutOps) override;
59
60 // Include the pieces autogenerated from the target description.
61#include "SparcGenDAGISel.inc"
62
63private:
64 SDNode* getGlobalBaseReg();
65 bool tryInlineAsm(SDNode *N);
66};
67
68class SparcDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
69public:
70 static char ID;
71 explicit SparcDAGToDAGISelLegacy(SparcTargetMachine &tm)
72 : SelectionDAGISelLegacy(ID, std::make_unique<SparcDAGToDAGISel>(args&: tm)) {}
73};
74} // end anonymous namespace
75
76char SparcDAGToDAGISelLegacy::ID = 0;
77
78INITIALIZE_PASS(SparcDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
79
80SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
81 Register GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF);
82 return CurDAG->getRegister(Reg: GlobalBaseReg,
83 VT: TLI->getPointerTy(DL: CurDAG->getDataLayout()))
84 .getNode();
85}
86
87bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
88 SDValue &Base, SDValue &Offset) {
89 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Val&: Addr)) {
90 Base = CurDAG->getTargetFrameIndex(
91 FI: FIN->getIndex(), VT: TLI->getPointerTy(DL: CurDAG->getDataLayout()));
92 Offset = CurDAG->getTargetConstant(Val: 0, DL: SDLoc(Addr), VT: MVT::i32);
93 return true;
94 }
95 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
96 Addr.getOpcode() == ISD::TargetGlobalAddress ||
97 Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
98 return false; // direct calls.
99
100 if (Addr.getOpcode() == ISD::ADD) {
101 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val: Addr.getOperand(i: 1))) {
102 if (isInt<13>(x: CN->getSExtValue())) {
103 if (FrameIndexSDNode *FIN =
104 dyn_cast<FrameIndexSDNode>(Val: Addr.getOperand(i: 0))) {
105 // Constant offset from frame ref.
106 Base = CurDAG->getTargetFrameIndex(
107 FI: FIN->getIndex(), VT: TLI->getPointerTy(DL: CurDAG->getDataLayout()));
108 } else {
109 Base = Addr.getOperand(i: 0);
110 }
111 Offset = CurDAG->getSignedTargetConstant(Val: CN->getSExtValue(),
112 DL: SDLoc(Addr), VT: MVT::i32);
113 return true;
114 }
115 }
116 if (Addr.getOperand(i: 0).getOpcode() == SPISD::Lo) {
117 Base = Addr.getOperand(i: 1);
118 Offset = Addr.getOperand(i: 0).getOperand(i: 0);
119 return true;
120 }
121 if (Addr.getOperand(i: 1).getOpcode() == SPISD::Lo) {
122 Base = Addr.getOperand(i: 0);
123 Offset = Addr.getOperand(i: 1).getOperand(i: 0);
124 return true;
125 }
126 }
127 Base = Addr;
128 Offset = CurDAG->getTargetConstant(Val: 0, DL: SDLoc(Addr), VT: MVT::i32);
129 return true;
130}
131
132bool SparcDAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) {
133 if (Addr.getOpcode() == ISD::FrameIndex) return false;
134 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
135 Addr.getOpcode() == ISD::TargetGlobalAddress ||
136 Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
137 return false; // direct calls.
138
139 if (Addr.getOpcode() == ISD::ADD) {
140 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val: Addr.getOperand(i: 1)))
141 if (isInt<13>(x: CN->getSExtValue()))
142 return false; // Let the reg+imm pattern catch this!
143 if (Addr.getOperand(i: 0).getOpcode() == SPISD::Lo ||
144 Addr.getOperand(i: 1).getOpcode() == SPISD::Lo)
145 return false; // Let the reg+imm pattern catch this!
146 R1 = Addr.getOperand(i: 0);
147 R2 = Addr.getOperand(i: 1);
148 return true;
149 }
150
151 R1 = Addr;
152 R2 = CurDAG->getRegister(Reg: SP::G0, VT: TLI->getPointerTy(DL: CurDAG->getDataLayout()));
153 return true;
154}
155
156bool SparcDAGToDAGISel::SelectForceADDRrr(SDValue Addr, SDValue &Base,
157 SDValue &Disp) {
158 if (SelectADDRrr(Addr, R1&: Base, R2&: Disp))
159 return true;
160
161 // Otherwise we'll use the full address in base and set the offset part to
162 // zero.
163 Base = Addr;
164 Disp =
165 CurDAG->getRegister(Reg: SP::G0, VT: TLI->getPointerTy(DL: CurDAG->getDataLayout()));
166 return true;
167}
168
169// Re-assemble i64 arguments split up in SelectionDAGBuilder's
170// visitInlineAsm / GetRegistersForValue functions.
171//
172// Note: This function was copied from, and is essentially identical
173// to ARMISelDAGToDAG::SelectInlineAsm. It is very unfortunate that
174// such hacking-up is necessary; a rethink of how inline asm operands
175// are handled may be in order to make doing this more sane.
176//
177// TODO: fix inline asm support so I can simply tell it that 'i64'
178// inputs to asm need to be allocated to the IntPair register type,
179// and have that work. Then, delete this function.
180bool SparcDAGToDAGISel::tryInlineAsm(SDNode *N){
181 std::vector<SDValue> AsmNodeOperands;
182 InlineAsm::Flag Flag;
183 bool Changed = false;
184 unsigned NumOps = N->getNumOperands();
185
186 // Normally, i64 data is bounded to two arbitrary GPRs for "%r"
187 // constraint. However, some instructions (e.g. ldd/std) require
188 // (even/even+1) GPRs.
189
190 // So, here, we check for this case, and mutate the inlineasm to use
191 // a single IntPair register instead, which guarantees such even/odd
192 // placement.
193
194 SDLoc dl(N);
195 SDValue Glue = N->getGluedNode() ? N->getOperand(Num: NumOps - 1) : SDValue();
196
197 SmallVector<bool, 8> OpChanged;
198 // Glue node will be appended late.
199 for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
200 SDValue op = N->getOperand(Num: i);
201 AsmNodeOperands.push_back(x: op);
202
203 if (i < InlineAsm::Op_FirstOperand)
204 continue;
205
206 if (const auto *C = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: i)))
207 Flag = InlineAsm::Flag(C->getZExtValue());
208 else
209 continue;
210
211 // Immediate operands to inline asm in the SelectionDAG are modeled with
212 // two operands. The first is a constant of value InlineAsm::Kind::Imm, and
213 // the second is a constant with the value of the immediate. If we get here
214 // and we have a Kind::Imm, skip the next operand, and continue.
215 if (Flag.isImmKind()) {
216 SDValue op = N->getOperand(Num: ++i);
217 AsmNodeOperands.push_back(x: op);
218 continue;
219 }
220
221 const unsigned NumRegs = Flag.getNumOperandRegisters();
222 if (NumRegs)
223 OpChanged.push_back(Elt: false);
224
225 unsigned DefIdx = 0;
226 bool IsTiedToChangedOp = false;
227 // If it's a use that is tied with a previous def, it has no
228 // reg class constraint.
229 if (Changed && Flag.isUseOperandTiedToDef(Idx&: DefIdx))
230 IsTiedToChangedOp = OpChanged[DefIdx];
231
232 if (!Flag.isRegUseKind() && !Flag.isRegDefKind() &&
233 !Flag.isRegDefEarlyClobberKind())
234 continue;
235
236 unsigned RC;
237 const bool HasRC = Flag.hasRegClassConstraint(RC);
238 if ((!IsTiedToChangedOp && (!HasRC || RC != SP::IntRegsRegClassID))
239 || NumRegs != 2)
240 continue;
241
242 assert((i+2 < NumOps) && "Invalid number of operands in inline asm");
243 SDValue V0 = N->getOperand(Num: i+1);
244 SDValue V1 = N->getOperand(Num: i+2);
245 Register Reg0 = cast<RegisterSDNode>(Val&: V0)->getReg();
246 Register Reg1 = cast<RegisterSDNode>(Val&: V1)->getReg();
247 SDValue PairedReg;
248 MachineRegisterInfo &MRI = MF->getRegInfo();
249
250 if (Flag.isRegDefKind() || Flag.isRegDefEarlyClobberKind()) {
251 // Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
252 // the original GPRs.
253
254 Register GPVR = MRI.createVirtualRegister(RegClass: &SP::IntPairRegClass);
255 PairedReg = CurDAG->getRegister(Reg: GPVR, VT: MVT::v2i32);
256 SDValue Chain = SDValue(N,0);
257
258 SDNode *GU = N->getGluedUser();
259 SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, Reg: GPVR, VT: MVT::v2i32,
260 Glue: Chain.getValue(R: 1));
261
262 // Extract values from a GPRPair reg and copy to the original GPR reg.
263 SDValue Sub0 = CurDAG->getTargetExtractSubreg(SRIdx: SP::sub_even, DL: dl, VT: MVT::i32,
264 Operand: RegCopy);
265 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SRIdx: SP::sub_odd, DL: dl, VT: MVT::i32,
266 Operand: RegCopy);
267 SDValue T0 = CurDAG->getCopyToReg(Chain: Sub0, dl, Reg: Reg0, N: Sub0,
268 Glue: RegCopy.getValue(R: 1));
269 SDValue T1 = CurDAG->getCopyToReg(Chain: Sub1, dl, Reg: Reg1, N: Sub1, Glue: T0.getValue(R: 1));
270
271 // Update the original glue user.
272 std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
273 Ops.push_back(x: T1.getValue(R: 1));
274 CurDAG->UpdateNodeOperands(N: GU, Ops);
275 } else {
276 // For Kind == InlineAsm::Kind::RegUse, we first copy two GPRs into a
277 // GPRPair and then pass the GPRPair to the inline asm.
278 SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
279
280 // As REG_SEQ doesn't take RegisterSDNode, we copy them first.
281 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg: Reg0, VT: MVT::i32,
282 Glue: Chain.getValue(R: 1));
283 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg: Reg1, VT: MVT::i32,
284 Glue: T0.getValue(R: 1));
285 SDValue Pair = SDValue(
286 CurDAG->getMachineNode(
287 Opcode: TargetOpcode::REG_SEQUENCE, dl, VT: MVT::v2i32,
288 Ops: {
289 CurDAG->getTargetConstant(Val: SP::IntPairRegClassID, DL: dl,
290 VT: MVT::i32),
291 T0,
292 CurDAG->getTargetConstant(Val: SP::sub_even, DL: dl, VT: MVT::i32),
293 T1,
294 CurDAG->getTargetConstant(Val: SP::sub_odd, DL: dl, VT: MVT::i32),
295 }),
296 0);
297
298 // Copy REG_SEQ into a GPRPair-typed VR and replace the original two
299 // i32 VRs of inline asm with it.
300 Register GPVR = MRI.createVirtualRegister(RegClass: &SP::IntPairRegClass);
301 PairedReg = CurDAG->getRegister(Reg: GPVR, VT: MVT::v2i32);
302 Chain = CurDAG->getCopyToReg(Chain: T1, dl, Reg: GPVR, N: Pair, Glue: T1.getValue(R: 1));
303
304 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
305 Glue = Chain.getValue(R: 1);
306 }
307
308 Changed = true;
309
310 if(PairedReg.getNode()) {
311 OpChanged[OpChanged.size() -1 ] = true;
312 Flag = InlineAsm::Flag(Flag.getKind(), 1 /* RegNum*/);
313 if (IsTiedToChangedOp)
314 Flag.setMatchingOp(DefIdx);
315 else
316 Flag.setRegClass(SP::IntPairRegClassID);
317 // Replace the current flag.
318 AsmNodeOperands[AsmNodeOperands.size() -1] = CurDAG->getTargetConstant(
319 Val: Flag, DL: dl, VT: MVT::i32);
320 // Add the new register node and skip the original two GPRs.
321 AsmNodeOperands.push_back(x: PairedReg);
322 // Skip the next two GPRs.
323 i += 2;
324 }
325 }
326
327 if (Glue.getNode())
328 AsmNodeOperands.push_back(x: Glue);
329 if (!Changed)
330 return false;
331
332 SelectInlineAsmMemoryOperands(Ops&: AsmNodeOperands, DL: SDLoc(N));
333
334 SDValue New = CurDAG->getNode(Opcode: N->getOpcode(), DL: SDLoc(N),
335 VTList: CurDAG->getVTList(VT1: MVT::Other, VT2: MVT::Glue), Ops: AsmNodeOperands);
336 New->setNodeId(-1);
337 ReplaceNode(F: N, T: New.getNode());
338 return true;
339}
340
341void SparcDAGToDAGISel::Select(SDNode *N) {
342 SDLoc dl(N);
343 if (N->isMachineOpcode()) {
344 N->setNodeId(-1);
345 return; // Already selected.
346 }
347
348 switch (N->getOpcode()) {
349 default: break;
350 case ISD::INLINEASM:
351 case ISD::INLINEASM_BR: {
352 if (tryInlineAsm(N))
353 return;
354 break;
355 }
356 case SPISD::GLOBAL_BASE_REG:
357 ReplaceNode(F: N, T: getGlobalBaseReg());
358 return;
359
360 case ISD::SDIV:
361 case ISD::UDIV: {
362 // sdivx / udivx handle 64-bit divides.
363 if (N->getValueType(ResNo: 0) == MVT::i64)
364 break;
365 // FIXME: should use a custom expander to expose the SRA to the dag.
366 SDValue DivLHS = N->getOperand(Num: 0);
367 SDValue DivRHS = N->getOperand(Num: 1);
368
369 // Set the Y register to the high-part.
370 SDValue TopPart;
371 if (N->getOpcode() == ISD::SDIV) {
372 TopPart = SDValue(CurDAG->getMachineNode(Opcode: SP::SRAri, dl, VT: MVT::i32, Op1: DivLHS,
373 Op2: CurDAG->getTargetConstant(Val: 31, DL: dl, VT: MVT::i32)),
374 0);
375 } else {
376 TopPart = CurDAG->getRegister(Reg: SP::G0, VT: MVT::i32);
377 }
378 TopPart = CurDAG->getCopyToReg(Chain: CurDAG->getEntryNode(), dl, Reg: SP::Y, N: TopPart,
379 Glue: SDValue())
380 .getValue(R: 1);
381
382 // FIXME: Handle div by immediate.
383 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
384 CurDAG->SelectNodeTo(N, MachineOpc: Opcode, VT: MVT::i32, Op1: DivLHS, Op2: DivRHS, Op3: TopPart);
385 return;
386 }
387 }
388
389 SelectCode(N);
390}
391
392
393/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
394/// inline asm expressions.
395bool SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(
396 const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
397 std::vector<SDValue> &OutOps) {
398 SDValue Op0, Op1;
399 switch (ConstraintID) {
400 default: return true;
401 case InlineAsm::ConstraintCode::o:
402 case InlineAsm::ConstraintCode::m: // memory
403 if (!SelectADDRrr(Addr: Op, R1&: Op0, R2&: Op1))
404 SelectADDRri(Addr: Op, Base&: Op0, Offset&: Op1);
405 break;
406 }
407
408 OutOps.push_back(x: Op0);
409 OutOps.push_back(x: Op1);
410 return false;
411}
412
413/// createSparcISelDag - This pass converts a legalized DAG into a
414/// SPARC-specific DAG, ready for instruction scheduling.
415///
416FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
417 return new SparcDAGToDAGISelLegacy(TM);
418}
419