1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the X86 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86InstrInfo.h"
14#include "X86.h"
15#include "X86InstrBuilder.h"
16#include "X86InstrFoldTables.h"
17#include "X86MachineFunctionInfo.h"
18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/Sequence.h"
22#include "llvm/CodeGen/LiveIntervals.h"
23#include "llvm/CodeGen/LivePhysRegs.h"
24#include "llvm/CodeGen/LiveVariables.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineInstr.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineModuleInfo.h"
30#include "llvm/CodeGen/MachineOperand.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/StackMaps.h"
33#include "llvm/IR/DebugInfoMetadata.h"
34#include "llvm/IR/DerivedTypes.h"
35#include "llvm/IR/Function.h"
36#include "llvm/IR/InstrTypes.h"
37#include "llvm/IR/Module.h"
38#include "llvm/MC/MCAsmInfo.h"
39#include "llvm/MC/MCExpr.h"
40#include "llvm/MC/MCInst.h"
41#include "llvm/Support/CommandLine.h"
42#include "llvm/Support/Debug.h"
43#include "llvm/Support/ErrorHandling.h"
44#include "llvm/Support/MathExtras.h"
45#include "llvm/Support/raw_ostream.h"
46#include "llvm/Target/TargetOptions.h"
47#include <optional>
48
49using namespace llvm;
50
51#define DEBUG_TYPE "x86-instr-info"
52
53#define GET_INSTRINFO_CTOR_DTOR
54#include "X86GenInstrInfo.inc"
55
56extern cl::opt<bool> X86EnableAPXForRelocation;
57
58static cl::opt<bool>
59 NoFusing("disable-spill-fusing",
60 cl::desc("Disable fusing of spill code into instructions"),
61 cl::Hidden);
62static cl::opt<bool>
63 PrintFailedFusing("print-failed-fuse-candidates",
64 cl::desc("Print instructions that the allocator wants to"
65 " fuse, but the X86 backend currently can't"),
66 cl::Hidden);
67static cl::opt<bool>
68 ReMatPICStubLoad("remat-pic-stub-load",
69 cl::desc("Re-materialize load from stub in PIC mode"),
70 cl::init(Val: false), cl::Hidden);
71static cl::opt<unsigned>
72 PartialRegUpdateClearance("partial-reg-update-clearance",
73 cl::desc("Clearance between two register writes "
74 "for inserting XOR to avoid partial "
75 "register update"),
76 cl::init(Val: 64), cl::Hidden);
77static cl::opt<unsigned> UndefRegClearance(
78 "undef-reg-clearance",
79 cl::desc("How many idle instructions we would like before "
80 "certain undef register reads"),
81 cl::init(Val: 128), cl::Hidden);
82
83static cl::opt<unsigned> MaxNFConversions(
84 "x86-max-nf-conversions-for-cmp-reuse",
85 cl::desc("Maximum number of NF conversions allowed to reuse EFLAGS from a "
86 "producer dominating a multi-predecessor block"),
87 cl::init(Val: 6), cl::Hidden);
88
89// Pin the vtable to this file.
90void X86InstrInfo::anchor() {}
91
92X86InstrInfo::X86InstrInfo(const X86Subtarget &STI)
93 : X86GenInstrInfo(STI, RI,
94 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
95 : X86::ADJCALLSTACKDOWN32),
96 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
97 : X86::ADJCALLSTACKUP32),
98 X86::CATCHRET, (STI.is64Bit() ? X86::RET64 : X86::RET32)),
99 Subtarget(STI), RI(STI.getTargetTriple()) {}
100
101const TargetRegisterClass *X86InstrInfo::getRegClass(const MCInstrDesc &MCID,
102 unsigned OpNum) const {
103 auto *RC = TargetInstrInfo::getRegClass(MCID, OpNum);
104 // If the target does not have egpr, then r16-r31 will be resereved for all
105 // instructions.
106 if (!RC || !Subtarget.hasEGPR())
107 return RC;
108
109 if (X86II::canUseApxExtendedReg(Desc: MCID))
110 return RC;
111
112 const X86RegisterInfo *RI = Subtarget.getRegisterInfo();
113 return RI->constrainRegClassToNonRex2(RC);
114}
115
116const TargetRegisterClass *X86InstrInfo::getInlineAsmMemoryOperandRegClass(
117 InlineAsm::ConstraintCode C) const {
118 if (Subtarget.isTarget64BitLP64())
119 return &X86::GR64RegClass;
120 // If the target is 64bit but we have been told to use 32bit addresses, we can
121 // still use 64-bit register as long as we know the high bits are zeros.
122 // Reflect that in the returned register class.
123 return Subtarget.is64Bit() ? &X86::LOW32_ADDR_ACCESSRegClass
124 : &X86::GR32RegClass;
125}
126
127bool X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
128 Register &SrcReg, Register &DstReg,
129 unsigned &SubIdx) const {
130 switch (MI.getOpcode()) {
131 default:
132 break;
133 case X86::MOVSX16rr8:
134 case X86::MOVZX16rr8:
135 case X86::MOVSX32rr8:
136 case X86::MOVZX32rr8:
137 case X86::MOVSX64rr8:
138 if (!Subtarget.is64Bit())
139 // It's not always legal to reference the low 8-bit of the larger
140 // register in 32-bit mode.
141 return false;
142 [[fallthrough]];
143 case X86::MOVSX32rr16:
144 case X86::MOVZX32rr16:
145 case X86::MOVSX64rr16:
146 case X86::MOVSX64rr32: {
147 if (MI.getOperand(i: 0).getSubReg() || MI.getOperand(i: 1).getSubReg())
148 // Be conservative.
149 return false;
150 SrcReg = MI.getOperand(i: 1).getReg();
151 DstReg = MI.getOperand(i: 0).getReg();
152 switch (MI.getOpcode()) {
153 default:
154 llvm_unreachable("Unreachable!");
155 case X86::MOVSX16rr8:
156 case X86::MOVZX16rr8:
157 case X86::MOVSX32rr8:
158 case X86::MOVZX32rr8:
159 case X86::MOVSX64rr8:
160 SubIdx = X86::sub_8bit;
161 break;
162 case X86::MOVSX32rr16:
163 case X86::MOVZX32rr16:
164 case X86::MOVSX64rr16:
165 SubIdx = X86::sub_16bit;
166 break;
167 case X86::MOVSX64rr32:
168 SubIdx = X86::sub_32bit;
169 break;
170 }
171 return true;
172 }
173 }
174 return false;
175}
176
177bool X86InstrInfo::isDataInvariant(MachineInstr &MI) {
178 if (MI.mayLoad() || MI.mayStore())
179 return false;
180
181 // Some target-independent operations that trivially lower to data-invariant
182 // instructions.
183 if (MI.isCopyLike() || MI.isInsertSubreg())
184 return true;
185
186 unsigned Opcode = MI.getOpcode();
187 using namespace X86;
188 // On x86 it is believed that imul is constant time w.r.t. the loaded data.
189 // However, they set flags and are perhaps the most surprisingly constant
190 // time operations so we call them out here separately.
191 if (isIMUL(Opcode))
192 return true;
193 // Bit scanning and counting instructions that are somewhat surprisingly
194 // constant time as they scan across bits and do other fairly complex
195 // operations like popcnt, but are believed to be constant time on x86.
196 // However, these set flags.
197 if (isBSF(Opcode) || isBSR(Opcode) || isLZCNT(Opcode) || isPOPCNT(Opcode) ||
198 isTZCNT(Opcode))
199 return true;
200 // Bit manipulation instructions are effectively combinations of basic
201 // arithmetic ops, and should still execute in constant time. These also
202 // set flags.
203 if (isBLCFILL(Opcode) || isBLCI(Opcode) || isBLCIC(Opcode) ||
204 isBLCMSK(Opcode) || isBLCS(Opcode) || isBLSFILL(Opcode) ||
205 isBLSI(Opcode) || isBLSIC(Opcode) || isBLSMSK(Opcode) || isBLSR(Opcode) ||
206 isTZMSK(Opcode))
207 return true;
208 // Bit extracting and clearing instructions should execute in constant time,
209 // and set flags.
210 if (isBEXTR(Opcode) || isBZHI(Opcode))
211 return true;
212 // Shift and rotate.
213 if (isROL(Opcode) || isROR(Opcode) || isSAR(Opcode) || isSHL(Opcode) ||
214 isSHR(Opcode) || isSHLD(Opcode) || isSHRD(Opcode))
215 return true;
216 // Basic arithmetic is constant time on the input but does set flags.
217 if (isADC(Opcode) || isADD(Opcode) || isAND(Opcode) || isOR(Opcode) ||
218 isSBB(Opcode) || isSUB(Opcode) || isXOR(Opcode))
219 return true;
220 // Arithmetic with just 32-bit and 64-bit variants and no immediates.
221 if (isANDN(Opcode))
222 return true;
223 // Unary arithmetic operations.
224 if (isDEC(Opcode) || isINC(Opcode) || isNEG(Opcode))
225 return true;
226 // Unlike other arithmetic, NOT doesn't set EFLAGS.
227 if (isNOT(Opcode))
228 return true;
229 // Various move instructions used to zero or sign extend things. Note that we
230 // intentionally don't support the _NOREX variants as we can't handle that
231 // register constraint anyways.
232 if (isMOVSX(Opcode) || isMOVZX(Opcode) || isMOVSXD(Opcode) || isMOV(Opcode))
233 return true;
234 // Arithmetic instructions that are both constant time and don't set flags.
235 if (isRORX(Opcode) || isSARX(Opcode) || isSHLX(Opcode) || isSHRX(Opcode))
236 return true;
237 // LEA doesn't actually access memory, and its arithmetic is constant time.
238 if (isLEA(Opcode))
239 return true;
240 // By default, assume that the instruction is not data invariant.
241 return false;
242}
243
244bool X86InstrInfo::isDataInvariantLoad(MachineInstr &MI) {
245 switch (MI.getOpcode()) {
246 default:
247 // By default, assume that the load will immediately leak.
248 return false;
249
250 // On x86 it is believed that imul is constant time w.r.t. the loaded data.
251 // However, they set flags and are perhaps the most surprisingly constant
252 // time operations so we call them out here separately.
253 case X86::IMUL16rm:
254 case X86::IMUL16rmi:
255 case X86::IMUL32rm:
256 case X86::IMUL32rmi:
257 case X86::IMUL64rm:
258 case X86::IMUL64rmi32:
259
260 // Bit scanning and counting instructions that are somewhat surprisingly
261 // constant time as they scan across bits and do other fairly complex
262 // operations like popcnt, but are believed to be constant time on x86.
263 // However, these set flags.
264 case X86::BSF16rm:
265 case X86::BSF32rm:
266 case X86::BSF64rm:
267 case X86::BSR16rm:
268 case X86::BSR32rm:
269 case X86::BSR64rm:
270 case X86::LZCNT16rm:
271 case X86::LZCNT32rm:
272 case X86::LZCNT64rm:
273 case X86::POPCNT16rm:
274 case X86::POPCNT32rm:
275 case X86::POPCNT64rm:
276 case X86::TZCNT16rm:
277 case X86::TZCNT32rm:
278 case X86::TZCNT64rm:
279
280 // Bit manipulation instructions are effectively combinations of basic
281 // arithmetic ops, and should still execute in constant time. These also
282 // set flags.
283 case X86::BLCFILL32rm:
284 case X86::BLCFILL64rm:
285 case X86::BLCI32rm:
286 case X86::BLCI64rm:
287 case X86::BLCIC32rm:
288 case X86::BLCIC64rm:
289 case X86::BLCMSK32rm:
290 case X86::BLCMSK64rm:
291 case X86::BLCS32rm:
292 case X86::BLCS64rm:
293 case X86::BLSFILL32rm:
294 case X86::BLSFILL64rm:
295 case X86::BLSI32rm:
296 case X86::BLSI64rm:
297 case X86::BLSIC32rm:
298 case X86::BLSIC64rm:
299 case X86::BLSMSK32rm:
300 case X86::BLSMSK64rm:
301 case X86::BLSR32rm:
302 case X86::BLSR64rm:
303 case X86::TZMSK32rm:
304 case X86::TZMSK64rm:
305
306 // Bit extracting and clearing instructions should execute in constant time,
307 // and set flags.
308 case X86::BEXTR32rm:
309 case X86::BEXTR64rm:
310 case X86::BEXTRI32mi:
311 case X86::BEXTRI64mi:
312 case X86::BZHI32rm:
313 case X86::BZHI64rm:
314
315 // Basic arithmetic is constant time on the input but does set flags.
316 case X86::ADC8rm:
317 case X86::ADC16rm:
318 case X86::ADC32rm:
319 case X86::ADC64rm:
320 case X86::ADD8rm:
321 case X86::ADD16rm:
322 case X86::ADD32rm:
323 case X86::ADD64rm:
324 case X86::AND8rm:
325 case X86::AND16rm:
326 case X86::AND32rm:
327 case X86::AND64rm:
328 case X86::ANDN32rm:
329 case X86::ANDN64rm:
330 case X86::OR8rm:
331 case X86::OR16rm:
332 case X86::OR32rm:
333 case X86::OR64rm:
334 case X86::SBB8rm:
335 case X86::SBB16rm:
336 case X86::SBB32rm:
337 case X86::SBB64rm:
338 case X86::SUB8rm:
339 case X86::SUB16rm:
340 case X86::SUB32rm:
341 case X86::SUB64rm:
342 case X86::XOR8rm:
343 case X86::XOR16rm:
344 case X86::XOR32rm:
345 case X86::XOR64rm:
346
347 // Integer multiply w/o affecting flags is still believed to be constant
348 // time on x86. Called out separately as this is among the most surprising
349 // instructions to exhibit that behavior.
350 case X86::MULX32rm:
351 case X86::MULX64rm:
352
353 // Arithmetic instructions that are both constant time and don't set flags.
354 case X86::RORX32mi:
355 case X86::RORX64mi:
356 case X86::SARX32rm:
357 case X86::SARX64rm:
358 case X86::SHLX32rm:
359 case X86::SHLX64rm:
360 case X86::SHRX32rm:
361 case X86::SHRX64rm:
362
363 // Conversions are believed to be constant time and don't set flags.
364 case X86::CVTTSD2SI64rm:
365 case X86::VCVTTSD2SI64rm:
366 case X86::VCVTTSD2SI64Zrm:
367 case X86::CVTTSD2SIrm:
368 case X86::VCVTTSD2SIrm:
369 case X86::VCVTTSD2SIZrm:
370 case X86::CVTTSS2SI64rm:
371 case X86::VCVTTSS2SI64rm:
372 case X86::VCVTTSS2SI64Zrm:
373 case X86::CVTTSS2SIrm:
374 case X86::VCVTTSS2SIrm:
375 case X86::VCVTTSS2SIZrm:
376 case X86::CVTSI2SDrm:
377 case X86::VCVTSI2SDrm:
378 case X86::VCVTSI2SDZrm:
379 case X86::CVTSI2SSrm:
380 case X86::VCVTSI2SSrm:
381 case X86::VCVTSI2SSZrm:
382 case X86::CVTSI642SDrm:
383 case X86::VCVTSI642SDrm:
384 case X86::VCVTSI642SDZrm:
385 case X86::CVTSI642SSrm:
386 case X86::VCVTSI642SSrm:
387 case X86::VCVTSI642SSZrm:
388 case X86::CVTSS2SDrm:
389 case X86::VCVTSS2SDrm:
390 case X86::VCVTSS2SDZrm:
391 case X86::CVTSD2SSrm:
392 case X86::VCVTSD2SSrm:
393 case X86::VCVTSD2SSZrm:
394 // AVX512 added unsigned integer conversions.
395 case X86::VCVTTSD2USI64Zrm:
396 case X86::VCVTTSD2USIZrm:
397 case X86::VCVTTSS2USI64Zrm:
398 case X86::VCVTTSS2USIZrm:
399 case X86::VCVTUSI2SDZrm:
400 case X86::VCVTUSI642SDZrm:
401 case X86::VCVTUSI2SSZrm:
402 case X86::VCVTUSI642SSZrm:
403
404 // Loads to register don't set flags.
405 case X86::MOV8rm:
406 case X86::MOV8rm_NOREX:
407 case X86::MOV16rm:
408 case X86::MOV32rm:
409 case X86::MOV64rm:
410 case X86::MOVSX16rm8:
411 case X86::MOVSX32rm16:
412 case X86::MOVSX32rm8:
413 case X86::MOVSX32rm8_NOREX:
414 case X86::MOVSX64rm16:
415 case X86::MOVSX64rm32:
416 case X86::MOVSX64rm8:
417 case X86::MOVZX16rm8:
418 case X86::MOVZX32rm16:
419 case X86::MOVZX32rm8:
420 case X86::MOVZX32rm8_NOREX:
421 case X86::MOVZX64rm16:
422 case X86::MOVZX64rm8:
423 return true;
424 }
425}
426
427int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
428 const MachineFunction *MF = MI.getParent()->getParent();
429 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
430
431 if (isFrameInstr(I: MI)) {
432 int SPAdj = alignTo(Size: getFrameSize(I: MI), A: TFI->getStackAlign());
433 SPAdj -= getFrameAdjustment(I: MI);
434 if (!isFrameSetup(I: MI))
435 SPAdj = -SPAdj;
436 return SPAdj;
437 }
438
439 // To know whether a call adjusts the stack, we need information
440 // that is bound to the following ADJCALLSTACKUP pseudo.
441 // Look for the next ADJCALLSTACKUP that follows the call.
442 if (MI.isCall()) {
443 const MachineBasicBlock *MBB = MI.getParent();
444 auto I = ++MachineBasicBlock::const_iterator(MI);
445 for (auto E = MBB->end(); I != E; ++I) {
446 if (I->getOpcode() == getCallFrameDestroyOpcode() || I->isCall())
447 break;
448 }
449
450 // If we could not find a frame destroy opcode, then it has already
451 // been simplified, so we don't care.
452 if (I->getOpcode() != getCallFrameDestroyOpcode())
453 return 0;
454
455 return -(I->getOperand(i: 1).getImm());
456 }
457
458 // Currently handle only PUSHes we can reasonably expect to see
459 // in call sequences
460 switch (MI.getOpcode()) {
461 default:
462 return 0;
463 case X86::PUSH32r:
464 case X86::PUSH32rmm:
465 case X86::PUSH32rmr:
466 case X86::PUSH32i:
467 return 4;
468 case X86::PUSH64r:
469 case X86::PUSH64rmm:
470 case X86::PUSH64rmr:
471 case X86::PUSH64i32:
472 return 8;
473 }
474}
475
476/// Return true and the FrameIndex if the specified
477/// operand and follow operands form a reference to the stack frame.
478bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
479 int &FrameIndex) const {
480 if (MI.getOperand(i: Op + X86::AddrBaseReg).isFI() &&
481 MI.getOperand(i: Op + X86::AddrScaleAmt).isImm() &&
482 MI.getOperand(i: Op + X86::AddrIndexReg).isReg() &&
483 MI.getOperand(i: Op + X86::AddrDisp).isImm() &&
484 MI.getOperand(i: Op + X86::AddrScaleAmt).getImm() == 1 &&
485 MI.getOperand(i: Op + X86::AddrIndexReg).getReg() == 0 &&
486 MI.getOperand(i: Op + X86::AddrDisp).getImm() == 0) {
487 FrameIndex = MI.getOperand(i: Op + X86::AddrBaseReg).getIndex();
488 return true;
489 }
490 return false;
491}
492
493static bool isFrameLoadOpcode(int Opcode, TypeSize &MemBytes) {
494 switch (Opcode) {
495 default:
496 return false;
497 case X86::MOV8rm:
498 case X86::KMOVBkm:
499 case X86::KMOVBkm_EVEX:
500 MemBytes = TypeSize::getFixed(ExactSize: 1);
501 return true;
502 case X86::MOV16rm:
503 case X86::KMOVWkm:
504 case X86::KMOVWkm_EVEX:
505 case X86::VMOVSHZrm:
506 case X86::VMOVSHZrm_alt:
507 MemBytes = TypeSize::getFixed(ExactSize: 2);
508 return true;
509 case X86::MOV32rm:
510 case X86::MOVSSrm:
511 case X86::MOVSSrm_alt:
512 case X86::VMOVSSrm:
513 case X86::VMOVSSrm_alt:
514 case X86::VMOVSSZrm:
515 case X86::VMOVSSZrm_alt:
516 case X86::KMOVDkm:
517 case X86::KMOVDkm_EVEX:
518 MemBytes = TypeSize::getFixed(ExactSize: 4);
519 return true;
520 case X86::MOV64rm:
521 case X86::LD_Fp64m:
522 case X86::MOVSDrm:
523 case X86::MOVSDrm_alt:
524 case X86::VMOVSDrm:
525 case X86::VMOVSDrm_alt:
526 case X86::VMOVSDZrm:
527 case X86::VMOVSDZrm_alt:
528 case X86::MMX_MOVD64rm:
529 case X86::MMX_MOVQ64rm:
530 case X86::KMOVQkm:
531 case X86::KMOVQkm_EVEX:
532 MemBytes = TypeSize::getFixed(ExactSize: 8);
533 return true;
534 case X86::MOVAPSrm:
535 case X86::MOVUPSrm:
536 case X86::MOVAPDrm:
537 case X86::MOVUPDrm:
538 case X86::MOVDQArm:
539 case X86::MOVDQUrm:
540 case X86::VMOVAPSrm:
541 case X86::VMOVUPSrm:
542 case X86::VMOVAPDrm:
543 case X86::VMOVUPDrm:
544 case X86::VMOVDQArm:
545 case X86::VMOVDQUrm:
546 case X86::VMOVAPSZ128rm:
547 case X86::VMOVUPSZ128rm:
548 case X86::VMOVAPSZ128rm_NOVLX:
549 case X86::VMOVUPSZ128rm_NOVLX:
550 case X86::VMOVAPDZ128rm:
551 case X86::VMOVUPDZ128rm:
552 case X86::VMOVDQU8Z128rm:
553 case X86::VMOVDQU16Z128rm:
554 case X86::VMOVDQA32Z128rm:
555 case X86::VMOVDQU32Z128rm:
556 case X86::VMOVDQA64Z128rm:
557 case X86::VMOVDQU64Z128rm:
558 MemBytes = TypeSize::getFixed(ExactSize: 16);
559 return true;
560 case X86::VMOVAPSYrm:
561 case X86::VMOVUPSYrm:
562 case X86::VMOVAPDYrm:
563 case X86::VMOVUPDYrm:
564 case X86::VMOVDQAYrm:
565 case X86::VMOVDQUYrm:
566 case X86::VMOVAPSZ256rm:
567 case X86::VMOVUPSZ256rm:
568 case X86::VMOVAPSZ256rm_NOVLX:
569 case X86::VMOVUPSZ256rm_NOVLX:
570 case X86::VMOVAPDZ256rm:
571 case X86::VMOVUPDZ256rm:
572 case X86::VMOVDQU8Z256rm:
573 case X86::VMOVDQU16Z256rm:
574 case X86::VMOVDQA32Z256rm:
575 case X86::VMOVDQU32Z256rm:
576 case X86::VMOVDQA64Z256rm:
577 case X86::VMOVDQU64Z256rm:
578 MemBytes = TypeSize::getFixed(ExactSize: 32);
579 return true;
580 case X86::VMOVAPSZrm:
581 case X86::VMOVUPSZrm:
582 case X86::VMOVAPDZrm:
583 case X86::VMOVUPDZrm:
584 case X86::VMOVDQU8Zrm:
585 case X86::VMOVDQU16Zrm:
586 case X86::VMOVDQA32Zrm:
587 case X86::VMOVDQU32Zrm:
588 case X86::VMOVDQA64Zrm:
589 case X86::VMOVDQU64Zrm:
590 MemBytes = TypeSize::getFixed(ExactSize: 64);
591 return true;
592 }
593}
594
595static bool isFrameStoreOpcode(int Opcode, TypeSize &MemBytes) {
596 switch (Opcode) {
597 default:
598 return false;
599 case X86::MOV8mr:
600 case X86::KMOVBmk:
601 case X86::KMOVBmk_EVEX:
602 MemBytes = TypeSize::getFixed(ExactSize: 1);
603 return true;
604 case X86::MOV16mr:
605 case X86::KMOVWmk:
606 case X86::KMOVWmk_EVEX:
607 case X86::VMOVSHZmr:
608 MemBytes = TypeSize::getFixed(ExactSize: 2);
609 return true;
610 case X86::MOV32mr:
611 case X86::MOVSSmr:
612 case X86::VMOVSSmr:
613 case X86::VMOVSSZmr:
614 case X86::KMOVDmk:
615 case X86::KMOVDmk_EVEX:
616 MemBytes = TypeSize::getFixed(ExactSize: 4);
617 return true;
618 case X86::MOV64mr:
619 case X86::ST_FpP64m:
620 case X86::MOVSDmr:
621 case X86::VMOVSDmr:
622 case X86::VMOVSDZmr:
623 case X86::MMX_MOVD64mr:
624 case X86::MMX_MOVQ64mr:
625 case X86::MMX_MOVNTQmr:
626 case X86::KMOVQmk:
627 case X86::KMOVQmk_EVEX:
628 MemBytes = TypeSize::getFixed(ExactSize: 8);
629 return true;
630 case X86::MOVAPSmr:
631 case X86::MOVUPSmr:
632 case X86::MOVAPDmr:
633 case X86::MOVUPDmr:
634 case X86::MOVDQAmr:
635 case X86::MOVDQUmr:
636 case X86::VMOVAPSmr:
637 case X86::VMOVUPSmr:
638 case X86::VMOVAPDmr:
639 case X86::VMOVUPDmr:
640 case X86::VMOVDQAmr:
641 case X86::VMOVDQUmr:
642 case X86::VMOVUPSZ128mr:
643 case X86::VMOVAPSZ128mr:
644 case X86::VMOVUPSZ128mr_NOVLX:
645 case X86::VMOVAPSZ128mr_NOVLX:
646 case X86::VMOVUPDZ128mr:
647 case X86::VMOVAPDZ128mr:
648 case X86::VMOVDQA32Z128mr:
649 case X86::VMOVDQU32Z128mr:
650 case X86::VMOVDQA64Z128mr:
651 case X86::VMOVDQU64Z128mr:
652 case X86::VMOVDQU8Z128mr:
653 case X86::VMOVDQU16Z128mr:
654 MemBytes = TypeSize::getFixed(ExactSize: 16);
655 return true;
656 case X86::VMOVUPSYmr:
657 case X86::VMOVAPSYmr:
658 case X86::VMOVUPDYmr:
659 case X86::VMOVAPDYmr:
660 case X86::VMOVDQUYmr:
661 case X86::VMOVDQAYmr:
662 case X86::VMOVUPSZ256mr:
663 case X86::VMOVAPSZ256mr:
664 case X86::VMOVUPSZ256mr_NOVLX:
665 case X86::VMOVAPSZ256mr_NOVLX:
666 case X86::VMOVUPDZ256mr:
667 case X86::VMOVAPDZ256mr:
668 case X86::VMOVDQU8Z256mr:
669 case X86::VMOVDQU16Z256mr:
670 case X86::VMOVDQA32Z256mr:
671 case X86::VMOVDQU32Z256mr:
672 case X86::VMOVDQA64Z256mr:
673 case X86::VMOVDQU64Z256mr:
674 MemBytes = TypeSize::getFixed(ExactSize: 32);
675 return true;
676 case X86::VMOVUPSZmr:
677 case X86::VMOVAPSZmr:
678 case X86::VMOVUPDZmr:
679 case X86::VMOVAPDZmr:
680 case X86::VMOVDQU8Zmr:
681 case X86::VMOVDQU16Zmr:
682 case X86::VMOVDQA32Zmr:
683 case X86::VMOVDQU32Zmr:
684 case X86::VMOVDQA64Zmr:
685 case X86::VMOVDQU64Zmr:
686 MemBytes = TypeSize::getFixed(ExactSize: 64);
687 return true;
688 }
689 return false;
690}
691
692Register X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
693 int &FrameIndex) const {
694 TypeSize Dummy = TypeSize::getZero();
695 return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, MemBytes&: Dummy);
696}
697
698Register X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
699 int &FrameIndex,
700 TypeSize &MemBytes) const {
701 if (isFrameLoadOpcode(Opcode: MI.getOpcode(), MemBytes))
702 if (MI.getOperand(i: 0).getSubReg() == 0 && isFrameOperand(MI, Op: 1, FrameIndex))
703 return MI.getOperand(i: 0).getReg();
704 return Register();
705}
706
707Register X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
708 int &FrameIndex) const {
709 TypeSize Dummy = TypeSize::getZero();
710 if (isFrameLoadOpcode(Opcode: MI.getOpcode(), MemBytes&: Dummy)) {
711 if (Register Reg = isLoadFromStackSlot(MI, FrameIndex))
712 return Reg;
713 // Check for post-frame index elimination operations
714 SmallVector<const MachineMemOperand *, 1> Accesses;
715 if (hasLoadFromStackSlot(MI, Accesses)) {
716 FrameIndex =
717 cast<FixedStackPseudoSourceValue>(Val: Accesses.front()->getPseudoValue())
718 ->getFrameIndex();
719 return MI.getOperand(i: 0).getReg();
720 }
721 }
722 return Register();
723}
724
725Register X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
726 int &FrameIndex) const {
727 TypeSize Dummy = TypeSize::getZero();
728 return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, MemBytes&: Dummy);
729}
730
731Register X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
732 int &FrameIndex,
733 TypeSize &MemBytes) const {
734 if (isFrameStoreOpcode(Opcode: MI.getOpcode(), MemBytes))
735 if (MI.getOperand(i: X86::AddrNumOperands).getSubReg() == 0 &&
736 isFrameOperand(MI, Op: 0, FrameIndex))
737 return MI.getOperand(i: X86::AddrNumOperands).getReg();
738 return Register();
739}
740
741Register X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
742 int &FrameIndex) const {
743 TypeSize Dummy = TypeSize::getZero();
744 if (isFrameStoreOpcode(Opcode: MI.getOpcode(), MemBytes&: Dummy)) {
745 if (Register Reg = isStoreToStackSlot(MI, FrameIndex))
746 return Reg;
747 // Check for post-frame index elimination operations
748 SmallVector<const MachineMemOperand *, 1> Accesses;
749 if (hasStoreToStackSlot(MI, Accesses)) {
750 FrameIndex =
751 cast<FixedStackPseudoSourceValue>(Val: Accesses.front()->getPseudoValue())
752 ->getFrameIndex();
753 return MI.getOperand(i: X86::AddrNumOperands).getReg();
754 }
755 }
756 return Register();
757}
758
759/// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
760static bool regIsPICBase(Register BaseReg, const MachineRegisterInfo &MRI) {
761 // Don't waste compile time scanning use-def chains of physregs.
762 if (!BaseReg.isVirtual())
763 return false;
764 bool isPICBase = false;
765 for (const MachineInstr &DefMI : MRI.def_instructions(Reg: BaseReg)) {
766 if (DefMI.getOpcode() != X86::MOVPC32r)
767 return false;
768 assert(!isPICBase && "More than one PIC base?");
769 isPICBase = true;
770 }
771 return isPICBase;
772}
773
774bool X86InstrInfo::isReMaterializableImpl(
775 const MachineInstr &MI) const {
776 switch (MI.getOpcode()) {
777 default:
778 // This function should only be called for opcodes with the ReMaterializable
779 // flag set.
780 llvm_unreachable("Unknown rematerializable operation!");
781 break;
782 case X86::IMPLICIT_DEF:
783 // Defer to generic logic.
784 break;
785 case X86::LOAD_STACK_GUARD:
786 case X86::LD_Fp032:
787 case X86::LD_Fp064:
788 case X86::LD_Fp080:
789 case X86::LD_Fp132:
790 case X86::LD_Fp164:
791 case X86::LD_Fp180:
792 case X86::AVX1_SETALLONES:
793 case X86::AVX2_SETALLONES:
794 case X86::AVX512_128_SET0:
795 case X86::AVX512_128_SETALLONES:
796 case X86::AVX512_256_SETALLONES:
797 case X86::AVX512_512_SETALLONES:
798 case X86::AVX512_FsFLD0SD:
799 case X86::AVX512_FsFLD0SH:
800 case X86::AVX512_FsFLD0SS:
801 case X86::AVX512_FsFLD0F128:
802 case X86::FsFLD0SD:
803 case X86::FsFLD0SS:
804 case X86::FsFLD0SH:
805 case X86::FsFLD0F128:
806 case X86::KSET0B:
807 case X86::KSET0D:
808 case X86::KSET0Q:
809 case X86::KSET0W:
810 case X86::KSET1B:
811 case X86::KSET1D:
812 case X86::KSET1Q:
813 case X86::KSET1W:
814 case X86::MMX_SET0:
815 case X86::MOV32ImmSExti8:
816 case X86::MOV32r0:
817 case X86::MOV32r1:
818 case X86::MOV32r_1:
819 case X86::MOV32ri64:
820 case X86::MOV64ImmSExti8:
821 case X86::V_SET0:
822 case X86::V_SETALLONES:
823 case X86::MOV16ri:
824 case X86::MOV32ri:
825 case X86::MOV64ri:
826 case X86::MOV64ri32:
827 case X86::MOV8ri:
828 case X86::PTILEZEROV:
829 return true;
830
831 case X86::MOV8rm:
832 case X86::MOV8rm_NOREX:
833 case X86::MOV16rm:
834 case X86::MOV32rm:
835 case X86::MOV64rm:
836 case X86::MOVSSrm:
837 case X86::MOVSSrm_alt:
838 case X86::MOVSDrm:
839 case X86::MOVSDrm_alt:
840 case X86::MOVAPSrm:
841 case X86::MOVUPSrm:
842 case X86::MOVAPDrm:
843 case X86::MOVUPDrm:
844 case X86::MOVDQArm:
845 case X86::MOVDQUrm:
846 case X86::VMOVSSrm:
847 case X86::VMOVSSrm_alt:
848 case X86::VMOVSDrm:
849 case X86::VMOVSDrm_alt:
850 case X86::VMOVAPSrm:
851 case X86::VMOVUPSrm:
852 case X86::VMOVAPDrm:
853 case X86::VMOVUPDrm:
854 case X86::VMOVDQArm:
855 case X86::VMOVDQUrm:
856 case X86::VMOVAPSYrm:
857 case X86::VMOVUPSYrm:
858 case X86::VMOVAPDYrm:
859 case X86::VMOVUPDYrm:
860 case X86::VMOVDQAYrm:
861 case X86::VMOVDQUYrm:
862 case X86::MMX_MOVD64rm:
863 case X86::MMX_MOVQ64rm:
864 case X86::VBROADCASTSSrm:
865 case X86::VBROADCASTSSYrm:
866 case X86::VBROADCASTSDYrm:
867 // AVX-512
868 case X86::VPBROADCASTBZ128rm:
869 case X86::VPBROADCASTBZ256rm:
870 case X86::VPBROADCASTBZrm:
871 case X86::VBROADCASTF32X2Z256rm:
872 case X86::VBROADCASTF32X2Zrm:
873 case X86::VBROADCASTI32X2Z128rm:
874 case X86::VBROADCASTI32X2Z256rm:
875 case X86::VBROADCASTI32X2Zrm:
876 case X86::VPBROADCASTWZ128rm:
877 case X86::VPBROADCASTWZ256rm:
878 case X86::VPBROADCASTWZrm:
879 case X86::VPBROADCASTDZ128rm:
880 case X86::VPBROADCASTDZ256rm:
881 case X86::VPBROADCASTDZrm:
882 case X86::VBROADCASTSSZ128rm:
883 case X86::VBROADCASTSSZ256rm:
884 case X86::VBROADCASTSSZrm:
885 case X86::VPBROADCASTQZ128rm:
886 case X86::VPBROADCASTQZ256rm:
887 case X86::VPBROADCASTQZrm:
888 case X86::VBROADCASTSDZ256rm:
889 case X86::VBROADCASTSDZrm:
890 case X86::VMOVSSZrm:
891 case X86::VMOVSSZrm_alt:
892 case X86::VMOVSDZrm:
893 case X86::VMOVSDZrm_alt:
894 case X86::VMOVSHZrm:
895 case X86::VMOVSHZrm_alt:
896 case X86::VMOVAPDZ128rm:
897 case X86::VMOVAPDZ256rm:
898 case X86::VMOVAPDZrm:
899 case X86::VMOVAPSZ128rm:
900 case X86::VMOVAPSZ256rm:
901 case X86::VMOVAPSZ128rm_NOVLX:
902 case X86::VMOVAPSZ256rm_NOVLX:
903 case X86::VMOVAPSZrm:
904 case X86::VMOVDQA32Z128rm:
905 case X86::VMOVDQA32Z256rm:
906 case X86::VMOVDQA32Zrm:
907 case X86::VMOVDQA64Z128rm:
908 case X86::VMOVDQA64Z256rm:
909 case X86::VMOVDQA64Zrm:
910 case X86::VMOVDQU16Z128rm:
911 case X86::VMOVDQU16Z256rm:
912 case X86::VMOVDQU16Zrm:
913 case X86::VMOVDQU32Z128rm:
914 case X86::VMOVDQU32Z256rm:
915 case X86::VMOVDQU32Zrm:
916 case X86::VMOVDQU64Z128rm:
917 case X86::VMOVDQU64Z256rm:
918 case X86::VMOVDQU64Zrm:
919 case X86::VMOVDQU8Z128rm:
920 case X86::VMOVDQU8Z256rm:
921 case X86::VMOVDQU8Zrm:
922 case X86::VMOVUPDZ128rm:
923 case X86::VMOVUPDZ256rm:
924 case X86::VMOVUPDZrm:
925 case X86::VMOVUPSZ128rm:
926 case X86::VMOVUPSZ256rm:
927 case X86::VMOVUPSZ128rm_NOVLX:
928 case X86::VMOVUPSZ256rm_NOVLX:
929 case X86::VMOVUPSZrm: {
930 // Loads from constant pools are trivially rematerializable.
931 if (MI.getOperand(i: 1 + X86::AddrBaseReg).isReg() &&
932 MI.getOperand(i: 1 + X86::AddrScaleAmt).isImm() &&
933 MI.getOperand(i: 1 + X86::AddrIndexReg).isReg() &&
934 MI.getOperand(i: 1 + X86::AddrIndexReg).getReg() == 0 &&
935 MI.isDereferenceableInvariantLoad()) {
936 Register BaseReg = MI.getOperand(i: 1 + X86::AddrBaseReg).getReg();
937 if (BaseReg == 0 || BaseReg == X86::RIP)
938 return true;
939 // Allow re-materialization of PIC load.
940 if (!(!ReMatPICStubLoad && MI.getOperand(i: 1 + X86::AddrDisp).isGlobal())) {
941 const MachineFunction &MF = *MI.getParent()->getParent();
942 const MachineRegisterInfo &MRI = MF.getRegInfo();
943 if (regIsPICBase(BaseReg, MRI))
944 return true;
945 }
946 }
947 break;
948 }
949
950 case X86::LEA32r:
951 case X86::LEA64r: {
952 if (MI.getOperand(i: 1 + X86::AddrScaleAmt).isImm() &&
953 MI.getOperand(i: 1 + X86::AddrIndexReg).isReg() &&
954 MI.getOperand(i: 1 + X86::AddrIndexReg).getReg() == 0 &&
955 !MI.getOperand(i: 1 + X86::AddrDisp).isReg()) {
956 // lea fi#, lea GV, etc. are all rematerializable.
957 if (!MI.getOperand(i: 1 + X86::AddrBaseReg).isReg())
958 return true;
959 Register BaseReg = MI.getOperand(i: 1 + X86::AddrBaseReg).getReg();
960 if (BaseReg == 0)
961 return true;
962 // Allow re-materialization of lea PICBase + x.
963 const MachineFunction &MF = *MI.getParent()->getParent();
964 const MachineRegisterInfo &MRI = MF.getRegInfo();
965 if (regIsPICBase(BaseReg, MRI))
966 return true;
967 }
968 break;
969 }
970 }
971 return TargetInstrInfo::isReMaterializableImpl(MI);
972}
973
974void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
975 MachineBasicBlock::iterator I,
976 Register DestReg, unsigned SubIdx,
977 const MachineInstr &Orig,
978 LaneBitmask UsedLanes) const {
979 bool ClobbersEFLAGS = Orig.modifiesRegister(Reg: X86::EFLAGS, TRI: &TRI);
980 if (ClobbersEFLAGS && MBB.computeRegisterLiveness(TRI: &TRI, Reg: X86::EFLAGS, Before: I) !=
981 MachineBasicBlock::LQR_Dead) {
982 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
983 // effects.
984 int Value;
985 switch (Orig.getOpcode()) {
986 case X86::MOV32r0:
987 Value = 0;
988 break;
989 case X86::MOV32r1:
990 Value = 1;
991 break;
992 case X86::MOV32r_1:
993 Value = -1;
994 break;
995 default:
996 llvm_unreachable("Unexpected instruction!");
997 }
998
999 const DebugLoc &DL = Orig.getDebugLoc();
1000 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: X86::MOV32ri))
1001 .add(MO: Orig.getOperand(i: 0))
1002 .addImm(Val: Value);
1003 } else {
1004 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig: &Orig);
1005 MBB.insert(I, MI);
1006 }
1007
1008 MachineInstr &NewMI = *std::prev(x: I);
1009 NewMI.substituteRegister(FromReg: Orig.getOperand(i: 0).getReg(), ToReg: DestReg, SubIdx, RegInfo: TRI);
1010}
1011
1012/// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
1013bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
1014 for (const MachineOperand &MO : MI.operands()) {
1015 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS &&
1016 !MO.isDead()) {
1017 return true;
1018 }
1019 }
1020 return false;
1021}
1022
1023/// Check whether the shift count for a machine operand is non-zero.
1024inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
1025 unsigned ShiftAmtOperandIdx) {
1026 // The shift count is six bits with the REX.W prefix and five bits without.
1027 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1028 unsigned Imm = MI.getOperand(i: ShiftAmtOperandIdx).getImm();
1029 return Imm & ShiftCountMask;
1030}
1031
1032/// Check whether the given shift count is appropriate
1033/// can be represented by a LEA instruction.
1034inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1035 // Left shift instructions can be transformed into load-effective-address
1036 // instructions if we can encode them appropriately.
1037 // A LEA instruction utilizes a SIB byte to encode its scale factor.
1038 // The SIB.scale field is two bits wide which means that we can encode any
1039 // shift amount less than 4.
1040 return ShAmt < 4 && ShAmt > 0;
1041}
1042
1043static bool
1044findRedundantFlagInstr(MachineInstr &CmpInstr, MachineInstr &CmpValDefInstr,
1045 const MachineRegisterInfo *MRI, MachineInstr **AndInstr,
1046 const TargetRegisterInfo *TRI, const X86Subtarget &ST,
1047 bool &NoSignFlag, bool &ClearsOverflowFlag) {
1048 if (!(CmpValDefInstr.getOpcode() == X86::SUBREG_TO_REG &&
1049 CmpInstr.getOpcode() == X86::TEST64rr) &&
1050 !(CmpValDefInstr.getOpcode() == X86::COPY &&
1051 CmpInstr.getOpcode() == X86::TEST16rr))
1052 return false;
1053
1054 // CmpInstr is a TEST16rr/TEST64rr instruction, and
1055 // `X86InstrInfo::analyzeCompare` guarantees that it's analyzable only if two
1056 // registers are identical.
1057 assert((CmpInstr.getOperand(0).getReg() == CmpInstr.getOperand(1).getReg()) &&
1058 "CmpInstr is an analyzable TEST16rr/TEST64rr, and "
1059 "`X86InstrInfo::analyzeCompare` requires two reg operands are the"
1060 "same.");
1061
1062 // Caller (`X86InstrInfo::optimizeCompareInstr`) guarantees that
1063 // `CmpValDefInstr` defines the value that's used by `CmpInstr`; in this case
1064 // if `CmpValDefInstr` sets the EFLAGS, it is likely that `CmpInstr` is
1065 // redundant.
1066 assert(
1067 (MRI->getVRegDef(CmpInstr.getOperand(0).getReg()) == &CmpValDefInstr) &&
1068 "Caller guarantees that TEST64rr is a user of SUBREG_TO_REG or TEST16rr "
1069 "is a user of COPY sub16bit.");
1070 MachineInstr *VregDefInstr = nullptr;
1071 if (CmpInstr.getOpcode() == X86::TEST16rr) {
1072 if (!CmpValDefInstr.getOperand(i: 1).getReg().isVirtual())
1073 return false;
1074 VregDefInstr = MRI->getVRegDef(Reg: CmpValDefInstr.getOperand(i: 1).getReg());
1075 if (!VregDefInstr)
1076 return false;
1077 // We can only remove test when AND32ri or AND64ri32 whose imm can fit 16bit
1078 // size, others 32/64 bit ops would test higher bits which test16rr don't
1079 // want to.
1080 if (!((VregDefInstr->getOpcode() == X86::AND32ri ||
1081 VregDefInstr->getOpcode() == X86::AND64ri32) &&
1082 isUInt<16>(x: VregDefInstr->getOperand(i: 2).getImm())))
1083 return false;
1084 }
1085
1086 if (CmpInstr.getOpcode() == X86::TEST64rr) {
1087 // As seen in X86 td files, CmpValDefInstr.getOperand(3) is typically
1088 // sub_32bit or sub_xmm.
1089 if (CmpValDefInstr.getOperand(i: 2).getImm() != X86::sub_32bit)
1090 return false;
1091
1092 VregDefInstr = MRI->getVRegDef(Reg: CmpValDefInstr.getOperand(i: 1).getReg());
1093 }
1094
1095 assert(VregDefInstr && "Must have a definition (SSA)");
1096
1097 // Requires `CmpValDefInstr` and `VregDefInstr` are from the same MBB
1098 // to simplify the subsequent analysis.
1099 //
1100 // FIXME: If `VregDefInstr->getParent()` is the only predecessor of
1101 // `CmpValDefInstr.getParent()`, this could be handled.
1102 if (VregDefInstr->getParent() != CmpValDefInstr.getParent())
1103 return false;
1104
1105 if (X86::isAND(Opcode: VregDefInstr->getOpcode()) &&
1106 (!ST.hasNF() || VregDefInstr->modifiesRegister(Reg: X86::EFLAGS, TRI))) {
1107 // Get a sequence of instructions like
1108 // %reg = and* ... // Set EFLAGS
1109 // ... // EFLAGS not changed
1110 // %extended_reg = subreg_to_reg %reg, %subreg.sub_32bit
1111 // test64rr %extended_reg, %extended_reg, implicit-def $eflags
1112 // or
1113 // %reg = and32* ...
1114 // ... // EFLAGS not changed.
1115 // %src_reg = copy %reg.sub_16bit:gr32
1116 // test16rr %src_reg, %src_reg, implicit-def $eflags
1117 //
1118 // If subsequent readers use a subset of bits that don't change
1119 // after `and*` instructions, it's likely that the test64rr could
1120 // be optimized away.
1121 for (const MachineInstr &Instr :
1122 make_range(x: std::next(x: MachineBasicBlock::iterator(VregDefInstr)),
1123 y: MachineBasicBlock::iterator(CmpValDefInstr))) {
1124 // There are instructions between 'VregDefInstr' and
1125 // 'CmpValDefInstr' that modifies EFLAGS.
1126 if (Instr.modifiesRegister(Reg: X86::EFLAGS, TRI))
1127 return false;
1128 }
1129
1130 *AndInstr = VregDefInstr;
1131
1132 // AND instruction will essentially update SF and clear OF, so
1133 // NoSignFlag should be false in the sense that SF is modified by `AND`.
1134 //
1135 // However, the implementation artifically sets `NoSignFlag` to true
1136 // to poison the SF bit; that is to say, if SF is looked at later, the
1137 // optimization (to erase TEST64rr) will be disabled.
1138 //
1139 // The reason to poison SF bit is that SF bit value could be different
1140 // in the `AND` and `TEST` operation; signed bit is not known for `AND`,
1141 // and is known to be 0 as a result of `TEST64rr`.
1142 //
1143 // FIXME: As opposed to poisoning the SF bit directly, consider peeking into
1144 // the AND instruction and using the static information to guide peephole
1145 // optimization if possible. For example, it's possible to fold a
1146 // conditional move into a copy if the relevant EFLAG bits could be deduced
1147 // from an immediate operand of and operation.
1148 //
1149 NoSignFlag = true;
1150 // ClearsOverflowFlag is true for AND operation (no surprise).
1151 ClearsOverflowFlag = true;
1152 return true;
1153 }
1154 return false;
1155}
1156
1157bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
1158 unsigned Opc, bool AllowSP, Register &NewSrc,
1159 unsigned &NewSrcSubReg, bool &isKill,
1160 MachineOperand &ImplicitOp, LiveVariables *LV,
1161 LiveIntervals *LIS) const {
1162 MachineFunction &MF = *MI.getParent()->getParent();
1163 const TargetRegisterClass *RC;
1164 if (AllowSP) {
1165 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1166 } else {
1167 RC = Opc != X86::LEA32r ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1168 }
1169 Register SrcReg = Src.getReg();
1170 unsigned SubReg = Src.getSubReg();
1171 isKill = MI.killsRegister(Reg: SrcReg, /*TRI=*/nullptr);
1172
1173 NewSrcSubReg = X86::NoSubRegister;
1174
1175 // For both LEA64 and LEA32 the register already has essentially the right
1176 // type (32-bit or 64-bit) we may just need to forbid SP.
1177 if (Opc != X86::LEA64_32r) {
1178 NewSrc = SrcReg;
1179 NewSrcSubReg = SubReg;
1180 assert(!Src.isUndef() && "Undef op doesn't need optimization");
1181
1182 if (NewSrc.isVirtual() && !MF.getRegInfo().constrainRegClass(Reg: NewSrc, RC))
1183 return false;
1184
1185 return true;
1186 }
1187
1188 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1189 // another we need to add 64-bit registers to the final MI.
1190 if (SrcReg.isPhysical()) {
1191 ImplicitOp = Src;
1192 ImplicitOp.setImplicit();
1193
1194 NewSrc = getX86SubSuperRegister(Reg: SrcReg, Size: 64);
1195 assert(!SubReg && "no superregister for source");
1196 assert(NewSrc.isValid() && "Invalid Operand");
1197 assert(!Src.isUndef() && "Undef op doesn't need optimization");
1198 } else {
1199 // Virtual register of the wrong class, we have to create a temporary 64-bit
1200 // vreg to feed into the LEA.
1201 NewSrc = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1202 NewSrcSubReg = X86::NoSubRegister;
1203 MachineInstr *Copy =
1204 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: TargetOpcode::COPY))
1205 .addReg(RegNo: NewSrc, Flags: RegState::Define | RegState::Undef, SubReg: X86::sub_32bit)
1206 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill), SubReg);
1207
1208 // Which is obviously going to be dead after we're done with it.
1209 isKill = true;
1210
1211 if (LV)
1212 LV->replaceKillInstruction(Reg: SrcReg, OldMI&: MI, NewMI&: *Copy);
1213
1214 if (LIS) {
1215 SlotIndex CopyIdx = LIS->InsertMachineInstrInMaps(MI&: *Copy);
1216 SlotIndex Idx = LIS->getInstructionIndex(Instr: MI);
1217 LiveInterval &LI = LIS->getInterval(Reg: SrcReg);
1218 LiveRange::Segment *S = LI.getSegmentContaining(Idx);
1219 if (S->end.getBaseIndex() == Idx)
1220 S->end = CopyIdx.getRegSlot();
1221 }
1222 }
1223
1224 // We've set all the parameters without issue.
1225 return true;
1226}
1227
1228MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1229 MachineInstr &MI,
1230 LiveVariables *LV,
1231 LiveIntervals *LIS,
1232 bool Is8BitOp) const {
1233 // We handle 8-bit adds and various 16-bit opcodes in the switch below.
1234 MachineBasicBlock &MBB = *MI.getParent();
1235 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
1236 assert((Is8BitOp ||
1237 RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
1238 *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
1239 "Unexpected type for LEA transform");
1240
1241 // TODO: For a 32-bit target, we need to adjust the LEA variables with
1242 // something like this:
1243 // Opcode = X86::LEA32r;
1244 // InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1245 // OutRegLEA =
1246 // Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
1247 // : RegInfo.createVirtualRegister(&X86::GR32RegClass);
1248 if (!Subtarget.is64Bit())
1249 return nullptr;
1250
1251 unsigned Opcode = X86::LEA64_32r;
1252 Register InRegLEA = RegInfo.createVirtualRegister(RegClass: &X86::GR64_NOSPRegClass);
1253 Register OutRegLEA = RegInfo.createVirtualRegister(RegClass: &X86::GR32RegClass);
1254 Register InRegLEA2;
1255
1256 // Build and insert into an implicit UNDEF value. This is OK because
1257 // we will be shifting and then extracting the lower 8/16-bits.
1258 // This has the potential to cause partial register stall. e.g.
1259 // movw (%rbp,%rcx,2), %dx
1260 // leal -65(%rdx), %esi
1261 // But testing has shown this *does* help performance in 64-bit mode (at
1262 // least on modern x86 machines).
1263 MachineBasicBlock::iterator MBBI = MI.getIterator();
1264 Register Dest = MI.getOperand(i: 0).getReg();
1265 Register Src = MI.getOperand(i: 1).getReg();
1266 unsigned SrcSubReg = MI.getOperand(i: 1).getSubReg();
1267 Register Src2;
1268 unsigned Src2SubReg;
1269 bool IsDead = MI.getOperand(i: 0).isDead();
1270 bool IsKill = MI.getOperand(i: 1).isKill();
1271 unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
1272 assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
1273 MachineInstr *ImpDef =
1274 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::IMPLICIT_DEF), DestReg: InRegLEA);
1275 MachineInstr *InsMI =
1276 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: TargetOpcode::COPY))
1277 .addReg(RegNo: InRegLEA, Flags: RegState::Define, SubReg)
1278 .addReg(RegNo: Src, Flags: getKillRegState(B: IsKill), SubReg: SrcSubReg);
1279 MachineInstr *ImpDef2 = nullptr;
1280 MachineInstr *InsMI2 = nullptr;
1281
1282 MachineInstrBuilder MIB =
1283 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: get(Opcode), DestReg: OutRegLEA);
1284#define CASE_NF(OP) \
1285 case X86::OP: \
1286 case X86::OP##_NF:
1287 switch (MIOpc) {
1288 default:
1289 llvm_unreachable("Unreachable!");
1290 CASE_NF(SHL8ri)
1291 CASE_NF(SHL16ri) {
1292 unsigned ShAmt = MI.getOperand(i: 2).getImm();
1293 MIB.addReg(RegNo: 0)
1294 .addImm(Val: 1LL << ShAmt)
1295 .addReg(RegNo: InRegLEA, Flags: RegState::Kill)
1296 .addImm(Val: 0)
1297 .addReg(RegNo: 0);
1298 break;
1299 }
1300 CASE_NF(INC8r)
1301 CASE_NF(INC16r)
1302 addRegOffset(MIB, Reg: InRegLEA, isKill: true, Offset: 1);
1303 break;
1304 CASE_NF(DEC8r)
1305 CASE_NF(DEC16r)
1306 addRegOffset(MIB, Reg: InRegLEA, isKill: true, Offset: -1);
1307 break;
1308 CASE_NF(ADD8ri)
1309 CASE_NF(ADD16ri)
1310 case X86::ADD8ri_DB:
1311 case X86::ADD16ri_DB:
1312 addRegOffset(MIB, Reg: InRegLEA, isKill: true, Offset: MI.getOperand(i: 2).getImm());
1313 break;
1314 CASE_NF(ADD8rr)
1315 CASE_NF(ADD16rr)
1316 case X86::ADD8rr_DB:
1317 case X86::ADD16rr_DB: {
1318 Src2 = MI.getOperand(i: 2).getReg();
1319 Src2SubReg = MI.getOperand(i: 2).getSubReg();
1320 bool IsKill2 = MI.getOperand(i: 2).isKill();
1321 assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
1322 if (Src == Src2) {
1323 // ADD8rr/ADD16rr killed %reg1028, %reg1028
1324 // just a single insert_subreg.
1325 addRegReg(MIB, Reg1: InRegLEA, isKill1: true, SubReg1: X86::NoSubRegister, Reg2: InRegLEA, isKill2: false,
1326 SubReg2: X86::NoSubRegister);
1327 } else {
1328 if (Subtarget.is64Bit())
1329 InRegLEA2 = RegInfo.createVirtualRegister(RegClass: &X86::GR64_NOSPRegClass);
1330 else
1331 InRegLEA2 = RegInfo.createVirtualRegister(RegClass: &X86::GR32_NOSPRegClass);
1332 // Build and insert into an implicit UNDEF value. This is OK because
1333 // we will be shifting and then extracting the lower 8/16-bits.
1334 ImpDef2 = BuildMI(BB&: MBB, I: &*MIB, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::IMPLICIT_DEF),
1335 DestReg: InRegLEA2);
1336 InsMI2 = BuildMI(BB&: MBB, I: &*MIB, MIMD: MI.getDebugLoc(), MCID: get(Opcode: TargetOpcode::COPY))
1337 .addReg(RegNo: InRegLEA2, Flags: RegState::Define, SubReg)
1338 .addReg(RegNo: Src2, Flags: getKillRegState(B: IsKill2), SubReg: Src2SubReg);
1339 addRegReg(MIB, Reg1: InRegLEA, isKill1: true, SubReg1: X86::NoSubRegister, Reg2: InRegLEA2, isKill2: true,
1340 SubReg2: X86::NoSubRegister);
1341 }
1342 if (LV && IsKill2 && InsMI2)
1343 LV->replaceKillInstruction(Reg: Src2, OldMI&: MI, NewMI&: *InsMI2);
1344 break;
1345 }
1346 }
1347
1348 MachineInstr *NewMI = MIB;
1349 MachineInstr *ExtMI =
1350 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: TargetOpcode::COPY))
1351 .addReg(RegNo: Dest, Flags: RegState::Define | getDeadRegState(B: IsDead))
1352 .addReg(RegNo: OutRegLEA, Flags: RegState::Kill, SubReg);
1353
1354 if (LV) {
1355 // Update live variables.
1356 LV->getVarInfo(Reg: InRegLEA).Kills.push_back(x: NewMI);
1357 if (InRegLEA2)
1358 LV->getVarInfo(Reg: InRegLEA2).Kills.push_back(x: NewMI);
1359 LV->getVarInfo(Reg: OutRegLEA).Kills.push_back(x: ExtMI);
1360 if (IsKill)
1361 LV->replaceKillInstruction(Reg: Src, OldMI&: MI, NewMI&: *InsMI);
1362 if (IsDead)
1363 LV->replaceKillInstruction(Reg: Dest, OldMI&: MI, NewMI&: *ExtMI);
1364 }
1365
1366 if (LIS) {
1367 LIS->InsertMachineInstrInMaps(MI&: *ImpDef);
1368 SlotIndex InsIdx = LIS->InsertMachineInstrInMaps(MI&: *InsMI);
1369 if (ImpDef2)
1370 LIS->InsertMachineInstrInMaps(MI&: *ImpDef2);
1371 SlotIndex Ins2Idx;
1372 if (InsMI2)
1373 Ins2Idx = LIS->InsertMachineInstrInMaps(MI&: *InsMI2);
1374 SlotIndex NewIdx = LIS->ReplaceMachineInstrInMaps(MI, NewMI&: *NewMI);
1375 SlotIndex ExtIdx = LIS->InsertMachineInstrInMaps(MI&: *ExtMI);
1376
1377 // Drop the dead EFLAGS def MI had; the replacement does not define EFLAGS.
1378 LIS->removePhysRegDefAt(Reg: X86::EFLAGS, Pos: NewIdx.getRegSlot());
1379
1380 LIS->getInterval(Reg: InRegLEA);
1381 LIS->getInterval(Reg: OutRegLEA);
1382 if (InRegLEA2)
1383 LIS->getInterval(Reg: InRegLEA2);
1384
1385 // Move the use of Src up to InsMI.
1386 LiveInterval &SrcLI = LIS->getInterval(Reg: Src);
1387 LiveRange::Segment *SrcSeg = SrcLI.getSegmentContaining(Idx: NewIdx);
1388 if (SrcSeg->end == NewIdx.getRegSlot())
1389 SrcSeg->end = InsIdx.getRegSlot();
1390
1391 if (InsMI2) {
1392 // Move the use of Src2 up to InsMI2.
1393 LiveInterval &Src2LI = LIS->getInterval(Reg: Src2);
1394 LiveRange::Segment *Src2Seg = Src2LI.getSegmentContaining(Idx: NewIdx);
1395 if (Src2Seg->end == NewIdx.getRegSlot())
1396 Src2Seg->end = Ins2Idx.getRegSlot();
1397 }
1398
1399 // Move the definition of Dest down to ExtMI.
1400 LiveInterval &DestLI = LIS->getInterval(Reg: Dest);
1401 LiveRange::Segment *DestSeg =
1402 DestLI.getSegmentContaining(Idx: NewIdx.getRegSlot());
1403 assert(DestSeg->start == NewIdx.getRegSlot() &&
1404 DestSeg->valno->def == NewIdx.getRegSlot());
1405 DestSeg->start = ExtIdx.getRegSlot();
1406 DestSeg->valno->def = ExtIdx.getRegSlot();
1407 }
1408
1409 return ExtMI;
1410}
1411
1412/// This method must be implemented by targets that
1413/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1414/// may be able to convert a two-address instruction into a true
1415/// three-address instruction on demand. This allows the X86 target (for
1416/// example) to convert ADD and SHL instructions into LEA instructions if they
1417/// would require register copies due to two-addressness.
1418///
1419/// This method returns a null pointer if the transformation cannot be
1420/// performed, otherwise it returns the new instruction.
1421///
1422MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
1423 LiveVariables *LV,
1424 LiveIntervals *LIS) const {
1425 // The following opcodes also sets the condition code register(s). Only
1426 // convert them to equivalent lea if the condition code register def's
1427 // are dead!
1428 if (hasLiveCondCodeDef(MI))
1429 return nullptr;
1430
1431 MachineFunction &MF = *MI.getParent()->getParent();
1432 // All instructions input are two-addr instructions. Get the known operands.
1433 const MachineOperand &Dest = MI.getOperand(i: 0);
1434 const MachineOperand &Src = MI.getOperand(i: 1);
1435
1436 // Ideally, operations with undef should be folded before we get here, but we
1437 // can't guarantee it. Bail out because optimizing undefs is a waste of time.
1438 // Without this, we have to forward undef state to new register operands to
1439 // avoid machine verifier errors.
1440 if (Src.isUndef())
1441 return nullptr;
1442 if (MI.getNumOperands() > 2)
1443 if (MI.getOperand(i: 2).isReg() && MI.getOperand(i: 2).isUndef())
1444 return nullptr;
1445
1446 MachineInstr *NewMI = nullptr;
1447 Register SrcReg, SrcReg2;
1448 unsigned SrcSubReg, SrcSubReg2;
1449 bool Is64Bit = Subtarget.is64Bit();
1450
1451 bool Is8BitOp = false;
1452 unsigned NumRegOperands = 2;
1453 unsigned MIOpc = MI.getOpcode();
1454 switch (MIOpc) {
1455 default:
1456 llvm_unreachable("Unreachable!");
1457 CASE_NF(SHL64ri) {
1458 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1459 unsigned ShAmt = getTruncatedShiftCount(MI, ShiftAmtOperandIdx: 2);
1460 if (!isTruncatedShiftCountForLEA(ShAmt))
1461 return nullptr;
1462
1463 // LEA can't handle RSP.
1464 if (Src.getReg().isVirtual() && !MF.getRegInfo().constrainRegClass(
1465 Reg: Src.getReg(), RC: &X86::GR64_NOSPRegClass))
1466 return nullptr;
1467
1468 NewMI = BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::LEA64r))
1469 .add(MO: Dest)
1470 .addReg(RegNo: 0)
1471 .addImm(Val: 1LL << ShAmt)
1472 .add(MO: Src)
1473 .addImm(Val: 0)
1474 .addReg(RegNo: 0);
1475 break;
1476 }
1477 CASE_NF(SHL32ri) {
1478 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1479 unsigned ShAmt = getTruncatedShiftCount(MI, ShiftAmtOperandIdx: 2);
1480 if (!isTruncatedShiftCountForLEA(ShAmt))
1481 return nullptr;
1482
1483 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1484
1485 // LEA can't handle ESP.
1486 bool isKill;
1487 MachineOperand ImplicitOp = MachineOperand::CreateReg(Reg: 0, isDef: false);
1488 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, NewSrc&: SrcReg, NewSrcSubReg&: SrcSubReg,
1489 isKill, ImplicitOp, LV, LIS))
1490 return nullptr;
1491
1492 MachineInstrBuilder MIB =
1493 BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
1494 .add(MO: Dest)
1495 .addReg(RegNo: 0)
1496 .addImm(Val: 1LL << ShAmt)
1497 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill), SubReg: SrcSubReg)
1498 .addImm(Val: 0)
1499 .addReg(RegNo: 0);
1500 if (ImplicitOp.getReg() != 0)
1501 MIB.add(MO: ImplicitOp);
1502 NewMI = MIB;
1503
1504 // Add kills if classifyLEAReg created a new register.
1505 if (LV && SrcReg != Src.getReg())
1506 LV->getVarInfo(Reg: SrcReg).Kills.push_back(x: NewMI);
1507 break;
1508 }
1509 CASE_NF(SHL8ri)
1510 Is8BitOp = true;
1511 [[fallthrough]];
1512 CASE_NF(SHL16ri) {
1513 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1514 unsigned ShAmt = getTruncatedShiftCount(MI, ShiftAmtOperandIdx: 2);
1515 if (!isTruncatedShiftCountForLEA(ShAmt))
1516 return nullptr;
1517 return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1518 }
1519 CASE_NF(INC64r)
1520 CASE_NF(INC32r) {
1521 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
1522 unsigned Opc = (MIOpc == X86::INC64r || MIOpc == X86::INC64r_NF)
1523 ? X86::LEA64r
1524 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1525 bool isKill;
1526 MachineOperand ImplicitOp = MachineOperand::CreateReg(Reg: 0, isDef: false);
1527 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, NewSrc&: SrcReg, NewSrcSubReg&: SrcSubReg,
1528 isKill, ImplicitOp, LV, LIS))
1529 return nullptr;
1530
1531 MachineInstrBuilder MIB = BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
1532 .add(MO: Dest)
1533 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill));
1534 if (ImplicitOp.getReg() != 0)
1535 MIB.add(MO: ImplicitOp);
1536
1537 NewMI = addOffset(MIB, Offset: 1);
1538
1539 // Add kills if classifyLEAReg created a new register.
1540 if (LV && SrcReg != Src.getReg())
1541 LV->getVarInfo(Reg: SrcReg).Kills.push_back(x: NewMI);
1542 break;
1543 }
1544 CASE_NF(DEC64r)
1545 CASE_NF(DEC32r) {
1546 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
1547 unsigned Opc = (MIOpc == X86::DEC64r || MIOpc == X86::DEC64r_NF)
1548 ? X86::LEA64r
1549 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1550
1551 bool isKill;
1552 MachineOperand ImplicitOp = MachineOperand::CreateReg(Reg: 0, isDef: false);
1553 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, NewSrc&: SrcReg, NewSrcSubReg&: SrcSubReg,
1554 isKill, ImplicitOp, LV, LIS))
1555 return nullptr;
1556
1557 MachineInstrBuilder MIB = BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
1558 .add(MO: Dest)
1559 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill));
1560 if (ImplicitOp.getReg() != 0)
1561 MIB.add(MO: ImplicitOp);
1562
1563 NewMI = addOffset(MIB, Offset: -1);
1564
1565 // Add kills if classifyLEAReg created a new register.
1566 if (LV && SrcReg != Src.getReg())
1567 LV->getVarInfo(Reg: SrcReg).Kills.push_back(x: NewMI);
1568 break;
1569 }
1570 CASE_NF(DEC8r)
1571 CASE_NF(INC8r)
1572 Is8BitOp = true;
1573 [[fallthrough]];
1574 CASE_NF(DEC16r)
1575 CASE_NF(INC16r)
1576 return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1577 CASE_NF(ADD64rr)
1578 CASE_NF(ADD32rr)
1579 case X86::ADD64rr_DB:
1580 case X86::ADD32rr_DB: {
1581 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1582 unsigned Opc;
1583 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_NF ||
1584 MIOpc == X86::ADD64rr_DB)
1585 Opc = X86::LEA64r;
1586 else
1587 Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1588
1589 const MachineOperand &Src2 = MI.getOperand(i: 2);
1590 bool isKill2;
1591 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(Reg: 0, isDef: false);
1592 if (!classifyLEAReg(MI, Src: Src2, Opc, /*AllowSP=*/false, NewSrc&: SrcReg2, NewSrcSubReg&: SrcSubReg2,
1593 isKill&: isKill2, ImplicitOp&: ImplicitOp2, LV, LIS))
1594 return nullptr;
1595
1596 bool isKill;
1597 MachineOperand ImplicitOp = MachineOperand::CreateReg(Reg: 0, isDef: false);
1598 if (Src.getReg() == Src2.getReg()) {
1599 // Don't call classify LEAReg a second time on the same register, in case
1600 // the first call inserted a COPY from Src2 and marked it as killed.
1601 isKill = isKill2;
1602 SrcReg = SrcReg2;
1603 SrcSubReg = SrcSubReg2;
1604 } else {
1605 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, NewSrc&: SrcReg, NewSrcSubReg&: SrcSubReg,
1606 isKill, ImplicitOp, LV, LIS))
1607 return nullptr;
1608 }
1609
1610 MachineInstrBuilder MIB = BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc)).add(MO: Dest);
1611 if (ImplicitOp.getReg() != 0)
1612 MIB.add(MO: ImplicitOp);
1613 if (ImplicitOp2.getReg() != 0)
1614 MIB.add(MO: ImplicitOp2);
1615
1616 NewMI =
1617 addRegReg(MIB, Reg1: SrcReg, isKill1: isKill, SubReg1: SrcSubReg, Reg2: SrcReg2, isKill2, SubReg2: SrcSubReg2);
1618
1619 // Add kills if classifyLEAReg created a new register.
1620 if (LV) {
1621 if (SrcReg2 != Src2.getReg())
1622 LV->getVarInfo(Reg: SrcReg2).Kills.push_back(x: NewMI);
1623 if (SrcReg != SrcReg2 && SrcReg != Src.getReg())
1624 LV->getVarInfo(Reg: SrcReg).Kills.push_back(x: NewMI);
1625 }
1626 NumRegOperands = 3;
1627 break;
1628 }
1629 CASE_NF(ADD8rr)
1630 case X86::ADD8rr_DB:
1631 Is8BitOp = true;
1632 [[fallthrough]];
1633 CASE_NF(ADD16rr)
1634 case X86::ADD16rr_DB:
1635 return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1636 CASE_NF(ADD64ri32)
1637 case X86::ADD64ri32_DB:
1638 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1639 NewMI = addOffset(
1640 MIB: BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::LEA64r)).add(MO: Dest).add(MO: Src),
1641 Offset: MI.getOperand(i: 2));
1642 break;
1643 CASE_NF(ADD32ri)
1644 case X86::ADD32ri_DB: {
1645 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1646 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1647
1648 bool isKill;
1649 MachineOperand ImplicitOp = MachineOperand::CreateReg(Reg: 0, isDef: false);
1650 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, NewSrc&: SrcReg, NewSrcSubReg&: SrcSubReg,
1651 isKill, ImplicitOp, LV, LIS))
1652 return nullptr;
1653
1654 MachineInstrBuilder MIB =
1655 BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
1656 .add(MO: Dest)
1657 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill), SubReg: SrcSubReg);
1658 if (ImplicitOp.getReg() != 0)
1659 MIB.add(MO: ImplicitOp);
1660
1661 NewMI = addOffset(MIB, Offset: MI.getOperand(i: 2));
1662
1663 // Add kills if classifyLEAReg created a new register.
1664 if (LV && SrcReg != Src.getReg())
1665 LV->getVarInfo(Reg: SrcReg).Kills.push_back(x: NewMI);
1666 break;
1667 }
1668 CASE_NF(ADD8ri)
1669 case X86::ADD8ri_DB:
1670 Is8BitOp = true;
1671 [[fallthrough]];
1672 CASE_NF(ADD16ri)
1673 case X86::ADD16ri_DB:
1674 return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1675 CASE_NF(SUB8ri)
1676 CASE_NF(SUB16ri)
1677 /// FIXME: Support these similar to ADD8ri/ADD16ri*.
1678 return nullptr;
1679 CASE_NF(SUB32ri) {
1680 if (!MI.getOperand(i: 2).isImm())
1681 return nullptr;
1682 int64_t Imm = MI.getOperand(i: 2).getImm();
1683 if (!isInt<32>(x: -Imm))
1684 return nullptr;
1685
1686 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1687 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1688
1689 bool isKill;
1690 MachineOperand ImplicitOp = MachineOperand::CreateReg(Reg: 0, isDef: false);
1691 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, NewSrc&: SrcReg, NewSrcSubReg&: SrcSubReg,
1692 isKill, ImplicitOp, LV, LIS))
1693 return nullptr;
1694
1695 MachineInstrBuilder MIB =
1696 BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
1697 .add(MO: Dest)
1698 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill), SubReg: SrcSubReg);
1699 if (ImplicitOp.getReg() != 0)
1700 MIB.add(MO: ImplicitOp);
1701
1702 NewMI = addOffset(MIB, Offset: -Imm);
1703
1704 // Add kills if classifyLEAReg created a new register.
1705 if (LV && SrcReg != Src.getReg())
1706 LV->getVarInfo(Reg: SrcReg).Kills.push_back(x: NewMI);
1707 break;
1708 }
1709
1710 CASE_NF(SUB64ri32) {
1711 if (!MI.getOperand(i: 2).isImm())
1712 return nullptr;
1713 int64_t Imm = MI.getOperand(i: 2).getImm();
1714 if (!isInt<32>(x: -Imm))
1715 return nullptr;
1716
1717 assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!");
1718
1719 MachineInstrBuilder MIB =
1720 BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::LEA64r)).add(MO: Dest).add(MO: Src);
1721 NewMI = addOffset(MIB, Offset: -Imm);
1722 break;
1723 }
1724
1725 case X86::VMOVDQU8Z128rmk:
1726 case X86::VMOVDQU8Z256rmk:
1727 case X86::VMOVDQU8Zrmk:
1728 case X86::VMOVDQU16Z128rmk:
1729 case X86::VMOVDQU16Z256rmk:
1730 case X86::VMOVDQU16Zrmk:
1731 case X86::VMOVDQU32Z128rmk:
1732 case X86::VMOVDQA32Z128rmk:
1733 case X86::VMOVDQU32Z256rmk:
1734 case X86::VMOVDQA32Z256rmk:
1735 case X86::VMOVDQU32Zrmk:
1736 case X86::VMOVDQA32Zrmk:
1737 case X86::VMOVDQU64Z128rmk:
1738 case X86::VMOVDQA64Z128rmk:
1739 case X86::VMOVDQU64Z256rmk:
1740 case X86::VMOVDQA64Z256rmk:
1741 case X86::VMOVDQU64Zrmk:
1742 case X86::VMOVDQA64Zrmk:
1743 case X86::VMOVUPDZ128rmk:
1744 case X86::VMOVAPDZ128rmk:
1745 case X86::VMOVUPDZ256rmk:
1746 case X86::VMOVAPDZ256rmk:
1747 case X86::VMOVUPDZrmk:
1748 case X86::VMOVAPDZrmk:
1749 case X86::VMOVUPSZ128rmk:
1750 case X86::VMOVAPSZ128rmk:
1751 case X86::VMOVUPSZ256rmk:
1752 case X86::VMOVAPSZ256rmk:
1753 case X86::VMOVUPSZrmk:
1754 case X86::VMOVAPSZrmk:
1755 case X86::VBROADCASTSDZ256rmk:
1756 case X86::VBROADCASTSDZrmk:
1757 case X86::VBROADCASTSSZ128rmk:
1758 case X86::VBROADCASTSSZ256rmk:
1759 case X86::VBROADCASTSSZrmk:
1760 case X86::VPBROADCASTDZ128rmk:
1761 case X86::VPBROADCASTDZ256rmk:
1762 case X86::VPBROADCASTDZrmk:
1763 case X86::VPBROADCASTQZ128rmk:
1764 case X86::VPBROADCASTQZ256rmk:
1765 case X86::VPBROADCASTQZrmk: {
1766 unsigned Opc;
1767 switch (MIOpc) {
1768 default:
1769 llvm_unreachable("Unreachable!");
1770 case X86::VMOVDQU8Z128rmk:
1771 Opc = X86::VPBLENDMBZ128rmk;
1772 break;
1773 case X86::VMOVDQU8Z256rmk:
1774 Opc = X86::VPBLENDMBZ256rmk;
1775 break;
1776 case X86::VMOVDQU8Zrmk:
1777 Opc = X86::VPBLENDMBZrmk;
1778 break;
1779 case X86::VMOVDQU16Z128rmk:
1780 Opc = X86::VPBLENDMWZ128rmk;
1781 break;
1782 case X86::VMOVDQU16Z256rmk:
1783 Opc = X86::VPBLENDMWZ256rmk;
1784 break;
1785 case X86::VMOVDQU16Zrmk:
1786 Opc = X86::VPBLENDMWZrmk;
1787 break;
1788 case X86::VMOVDQU32Z128rmk:
1789 Opc = X86::VPBLENDMDZ128rmk;
1790 break;
1791 case X86::VMOVDQU32Z256rmk:
1792 Opc = X86::VPBLENDMDZ256rmk;
1793 break;
1794 case X86::VMOVDQU32Zrmk:
1795 Opc = X86::VPBLENDMDZrmk;
1796 break;
1797 case X86::VMOVDQU64Z128rmk:
1798 Opc = X86::VPBLENDMQZ128rmk;
1799 break;
1800 case X86::VMOVDQU64Z256rmk:
1801 Opc = X86::VPBLENDMQZ256rmk;
1802 break;
1803 case X86::VMOVDQU64Zrmk:
1804 Opc = X86::VPBLENDMQZrmk;
1805 break;
1806 case X86::VMOVUPDZ128rmk:
1807 Opc = X86::VBLENDMPDZ128rmk;
1808 break;
1809 case X86::VMOVUPDZ256rmk:
1810 Opc = X86::VBLENDMPDZ256rmk;
1811 break;
1812 case X86::VMOVUPDZrmk:
1813 Opc = X86::VBLENDMPDZrmk;
1814 break;
1815 case X86::VMOVUPSZ128rmk:
1816 Opc = X86::VBLENDMPSZ128rmk;
1817 break;
1818 case X86::VMOVUPSZ256rmk:
1819 Opc = X86::VBLENDMPSZ256rmk;
1820 break;
1821 case X86::VMOVUPSZrmk:
1822 Opc = X86::VBLENDMPSZrmk;
1823 break;
1824 case X86::VMOVDQA32Z128rmk:
1825 Opc = X86::VPBLENDMDZ128rmk;
1826 break;
1827 case X86::VMOVDQA32Z256rmk:
1828 Opc = X86::VPBLENDMDZ256rmk;
1829 break;
1830 case X86::VMOVDQA32Zrmk:
1831 Opc = X86::VPBLENDMDZrmk;
1832 break;
1833 case X86::VMOVDQA64Z128rmk:
1834 Opc = X86::VPBLENDMQZ128rmk;
1835 break;
1836 case X86::VMOVDQA64Z256rmk:
1837 Opc = X86::VPBLENDMQZ256rmk;
1838 break;
1839 case X86::VMOVDQA64Zrmk:
1840 Opc = X86::VPBLENDMQZrmk;
1841 break;
1842 case X86::VMOVAPDZ128rmk:
1843 Opc = X86::VBLENDMPDZ128rmk;
1844 break;
1845 case X86::VMOVAPDZ256rmk:
1846 Opc = X86::VBLENDMPDZ256rmk;
1847 break;
1848 case X86::VMOVAPDZrmk:
1849 Opc = X86::VBLENDMPDZrmk;
1850 break;
1851 case X86::VMOVAPSZ128rmk:
1852 Opc = X86::VBLENDMPSZ128rmk;
1853 break;
1854 case X86::VMOVAPSZ256rmk:
1855 Opc = X86::VBLENDMPSZ256rmk;
1856 break;
1857 case X86::VMOVAPSZrmk:
1858 Opc = X86::VBLENDMPSZrmk;
1859 break;
1860 case X86::VBROADCASTSDZ256rmk:
1861 Opc = X86::VBLENDMPDZ256rmbk;
1862 break;
1863 case X86::VBROADCASTSDZrmk:
1864 Opc = X86::VBLENDMPDZrmbk;
1865 break;
1866 case X86::VBROADCASTSSZ128rmk:
1867 Opc = X86::VBLENDMPSZ128rmbk;
1868 break;
1869 case X86::VBROADCASTSSZ256rmk:
1870 Opc = X86::VBLENDMPSZ256rmbk;
1871 break;
1872 case X86::VBROADCASTSSZrmk:
1873 Opc = X86::VBLENDMPSZrmbk;
1874 break;
1875 case X86::VPBROADCASTDZ128rmk:
1876 Opc = X86::VPBLENDMDZ128rmbk;
1877 break;
1878 case X86::VPBROADCASTDZ256rmk:
1879 Opc = X86::VPBLENDMDZ256rmbk;
1880 break;
1881 case X86::VPBROADCASTDZrmk:
1882 Opc = X86::VPBLENDMDZrmbk;
1883 break;
1884 case X86::VPBROADCASTQZ128rmk:
1885 Opc = X86::VPBLENDMQZ128rmbk;
1886 break;
1887 case X86::VPBROADCASTQZ256rmk:
1888 Opc = X86::VPBLENDMQZ256rmbk;
1889 break;
1890 case X86::VPBROADCASTQZrmk:
1891 Opc = X86::VPBLENDMQZrmbk;
1892 break;
1893 }
1894
1895 NewMI = BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
1896 .add(MO: Dest)
1897 .add(MO: MI.getOperand(i: 2))
1898 .add(MO: Src)
1899 .add(MO: MI.getOperand(i: 3))
1900 .add(MO: MI.getOperand(i: 4))
1901 .add(MO: MI.getOperand(i: 5))
1902 .add(MO: MI.getOperand(i: 6))
1903 .add(MO: MI.getOperand(i: 7));
1904 NumRegOperands = 4;
1905 break;
1906 }
1907
1908 case X86::VMOVDQU8Z128rrk:
1909 case X86::VMOVDQU8Z256rrk:
1910 case X86::VMOVDQU8Zrrk:
1911 case X86::VMOVDQU16Z128rrk:
1912 case X86::VMOVDQU16Z256rrk:
1913 case X86::VMOVDQU16Zrrk:
1914 case X86::VMOVDQU32Z128rrk:
1915 case X86::VMOVDQA32Z128rrk:
1916 case X86::VMOVDQU32Z256rrk:
1917 case X86::VMOVDQA32Z256rrk:
1918 case X86::VMOVDQU32Zrrk:
1919 case X86::VMOVDQA32Zrrk:
1920 case X86::VMOVDQU64Z128rrk:
1921 case X86::VMOVDQA64Z128rrk:
1922 case X86::VMOVDQU64Z256rrk:
1923 case X86::VMOVDQA64Z256rrk:
1924 case X86::VMOVDQU64Zrrk:
1925 case X86::VMOVDQA64Zrrk:
1926 case X86::VMOVUPDZ128rrk:
1927 case X86::VMOVAPDZ128rrk:
1928 case X86::VMOVUPDZ256rrk:
1929 case X86::VMOVAPDZ256rrk:
1930 case X86::VMOVUPDZrrk:
1931 case X86::VMOVAPDZrrk:
1932 case X86::VMOVUPSZ128rrk:
1933 case X86::VMOVAPSZ128rrk:
1934 case X86::VMOVUPSZ256rrk:
1935 case X86::VMOVAPSZ256rrk:
1936 case X86::VMOVUPSZrrk:
1937 case X86::VMOVAPSZrrk: {
1938 unsigned Opc;
1939 switch (MIOpc) {
1940 default:
1941 llvm_unreachable("Unreachable!");
1942 case X86::VMOVDQU8Z128rrk:
1943 Opc = X86::VPBLENDMBZ128rrk;
1944 break;
1945 case X86::VMOVDQU8Z256rrk:
1946 Opc = X86::VPBLENDMBZ256rrk;
1947 break;
1948 case X86::VMOVDQU8Zrrk:
1949 Opc = X86::VPBLENDMBZrrk;
1950 break;
1951 case X86::VMOVDQU16Z128rrk:
1952 Opc = X86::VPBLENDMWZ128rrk;
1953 break;
1954 case X86::VMOVDQU16Z256rrk:
1955 Opc = X86::VPBLENDMWZ256rrk;
1956 break;
1957 case X86::VMOVDQU16Zrrk:
1958 Opc = X86::VPBLENDMWZrrk;
1959 break;
1960 case X86::VMOVDQU32Z128rrk:
1961 Opc = X86::VPBLENDMDZ128rrk;
1962 break;
1963 case X86::VMOVDQU32Z256rrk:
1964 Opc = X86::VPBLENDMDZ256rrk;
1965 break;
1966 case X86::VMOVDQU32Zrrk:
1967 Opc = X86::VPBLENDMDZrrk;
1968 break;
1969 case X86::VMOVDQU64Z128rrk:
1970 Opc = X86::VPBLENDMQZ128rrk;
1971 break;
1972 case X86::VMOVDQU64Z256rrk:
1973 Opc = X86::VPBLENDMQZ256rrk;
1974 break;
1975 case X86::VMOVDQU64Zrrk:
1976 Opc = X86::VPBLENDMQZrrk;
1977 break;
1978 case X86::VMOVUPDZ128rrk:
1979 Opc = X86::VBLENDMPDZ128rrk;
1980 break;
1981 case X86::VMOVUPDZ256rrk:
1982 Opc = X86::VBLENDMPDZ256rrk;
1983 break;
1984 case X86::VMOVUPDZrrk:
1985 Opc = X86::VBLENDMPDZrrk;
1986 break;
1987 case X86::VMOVUPSZ128rrk:
1988 Opc = X86::VBLENDMPSZ128rrk;
1989 break;
1990 case X86::VMOVUPSZ256rrk:
1991 Opc = X86::VBLENDMPSZ256rrk;
1992 break;
1993 case X86::VMOVUPSZrrk:
1994 Opc = X86::VBLENDMPSZrrk;
1995 break;
1996 case X86::VMOVDQA32Z128rrk:
1997 Opc = X86::VPBLENDMDZ128rrk;
1998 break;
1999 case X86::VMOVDQA32Z256rrk:
2000 Opc = X86::VPBLENDMDZ256rrk;
2001 break;
2002 case X86::VMOVDQA32Zrrk:
2003 Opc = X86::VPBLENDMDZrrk;
2004 break;
2005 case X86::VMOVDQA64Z128rrk:
2006 Opc = X86::VPBLENDMQZ128rrk;
2007 break;
2008 case X86::VMOVDQA64Z256rrk:
2009 Opc = X86::VPBLENDMQZ256rrk;
2010 break;
2011 case X86::VMOVDQA64Zrrk:
2012 Opc = X86::VPBLENDMQZrrk;
2013 break;
2014 case X86::VMOVAPDZ128rrk:
2015 Opc = X86::VBLENDMPDZ128rrk;
2016 break;
2017 case X86::VMOVAPDZ256rrk:
2018 Opc = X86::VBLENDMPDZ256rrk;
2019 break;
2020 case X86::VMOVAPDZrrk:
2021 Opc = X86::VBLENDMPDZrrk;
2022 break;
2023 case X86::VMOVAPSZ128rrk:
2024 Opc = X86::VBLENDMPSZ128rrk;
2025 break;
2026 case X86::VMOVAPSZ256rrk:
2027 Opc = X86::VBLENDMPSZ256rrk;
2028 break;
2029 case X86::VMOVAPSZrrk:
2030 Opc = X86::VBLENDMPSZrrk;
2031 break;
2032 }
2033
2034 NewMI = BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
2035 .add(MO: Dest)
2036 .add(MO: MI.getOperand(i: 2))
2037 .add(MO: Src)
2038 .add(MO: MI.getOperand(i: 3));
2039 NumRegOperands = 4;
2040 break;
2041 }
2042 }
2043#undef CASE_NF
2044
2045 if (!NewMI)
2046 return nullptr;
2047
2048 if (LV) { // Update live variables
2049 for (unsigned I = 0; I < NumRegOperands; ++I) {
2050 MachineOperand &Op = MI.getOperand(i: I);
2051 if (Op.isReg() && (Op.isDead() || Op.isKill()))
2052 LV->replaceKillInstruction(Reg: Op.getReg(), OldMI&: MI, NewMI&: *NewMI);
2053 }
2054 }
2055
2056 MachineBasicBlock &MBB = *MI.getParent();
2057 MBB.insert(I: MI.getIterator(), M: NewMI); // Insert the new inst
2058
2059 if (LIS) {
2060 // The replacement does not define EFLAGS; drop the dead EFLAGS def MI had.
2061 SlotIndex Idx = LIS->getInstructionIndex(Instr: MI);
2062 LIS->ReplaceMachineInstrInMaps(MI, NewMI&: *NewMI);
2063
2064 LIS->removePhysRegDefAt(Reg: X86::EFLAGS, Pos: Idx.getRegSlot());
2065 if (SrcReg)
2066 LIS->getInterval(Reg: SrcReg);
2067 if (SrcReg2)
2068 LIS->getInterval(Reg: SrcReg2);
2069 }
2070
2071 return NewMI;
2072}
2073
2074/// This determines which of three possible cases of a three source commute
2075/// the source indexes correspond to taking into account any mask operands.
2076/// All prevents commuting a passthru operand. Returns -1 if the commute isn't
2077/// possible.
2078/// Case 0 - Possible to commute the first and second operands.
2079/// Case 1 - Possible to commute the first and third operands.
2080/// Case 2 - Possible to commute the second and third operands.
2081static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
2082 unsigned SrcOpIdx2) {
2083 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
2084 if (SrcOpIdx1 > SrcOpIdx2)
2085 std::swap(a&: SrcOpIdx1, b&: SrcOpIdx2);
2086
2087 unsigned Op1 = 1, Op2 = 2, Op3 = 3;
2088 if (X86II::isKMasked(TSFlags)) {
2089 Op2++;
2090 Op3++;
2091 }
2092
2093 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
2094 return 0;
2095 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
2096 return 1;
2097 if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
2098 return 2;
2099 llvm_unreachable("Unknown three src commute case.");
2100}
2101
2102unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
2103 const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
2104 const X86InstrFMA3Group &FMA3Group) const {
2105
2106 unsigned Opc = MI.getOpcode();
2107
2108 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
2109 // analysis. The commute optimization is legal only if all users of FMA*_Int
2110 // use only the lowest element of the FMA*_Int instruction. Such analysis are
2111 // not implemented yet. So, just return 0 in that case.
2112 // When such analysis are available this place will be the right place for
2113 // calling it.
2114 assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
2115 "Intrinsic instructions can't commute operand 1");
2116
2117 // Determine which case this commute is or if it can't be done.
2118 unsigned Case =
2119 getThreeSrcCommuteCase(TSFlags: MI.getDesc().TSFlags, SrcOpIdx1, SrcOpIdx2);
2120 assert(Case < 3 && "Unexpected case number!");
2121
2122 // Define the FMA forms mapping array that helps to map input FMA form
2123 // to output FMA form to preserve the operation semantics after
2124 // commuting the operands.
2125 const unsigned Form132Index = 0;
2126 const unsigned Form213Index = 1;
2127 const unsigned Form231Index = 2;
2128 static const unsigned FormMapping[][3] = {
2129 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
2130 // FMA132 A, C, b; ==> FMA231 C, A, b;
2131 // FMA213 B, A, c; ==> FMA213 A, B, c;
2132 // FMA231 C, A, b; ==> FMA132 A, C, b;
2133 {Form231Index, Form213Index, Form132Index},
2134 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
2135 // FMA132 A, c, B; ==> FMA132 B, c, A;
2136 // FMA213 B, a, C; ==> FMA231 C, a, B;
2137 // FMA231 C, a, B; ==> FMA213 B, a, C;
2138 {Form132Index, Form231Index, Form213Index},
2139 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
2140 // FMA132 a, C, B; ==> FMA213 a, B, C;
2141 // FMA213 b, A, C; ==> FMA132 b, C, A;
2142 // FMA231 c, A, B; ==> FMA231 c, B, A;
2143 {Form213Index, Form132Index, Form231Index}};
2144
2145 unsigned FMAForms[3];
2146 FMAForms[0] = FMA3Group.get132Opcode();
2147 FMAForms[1] = FMA3Group.get213Opcode();
2148 FMAForms[2] = FMA3Group.get231Opcode();
2149
2150 // Everything is ready, just adjust the FMA opcode and return it.
2151 for (unsigned FormIndex = 0; FormIndex < 3; FormIndex++)
2152 if (Opc == FMAForms[FormIndex])
2153 return FMAForms[FormMapping[Case][FormIndex]];
2154
2155 llvm_unreachable("Illegal FMA3 format");
2156}
2157
2158static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
2159 unsigned SrcOpIdx2) {
2160 // Determine which case this commute is or if it can't be done.
2161 unsigned Case =
2162 getThreeSrcCommuteCase(TSFlags: MI.getDesc().TSFlags, SrcOpIdx1, SrcOpIdx2);
2163 assert(Case < 3 && "Unexpected case value!");
2164
2165 // For each case we need to swap two pairs of bits in the final immediate.
2166 static const uint8_t SwapMasks[3][4] = {
2167 {0x04, 0x10, 0x08, 0x20}, // Swap bits 2/4 and 3/5.
2168 {0x02, 0x10, 0x08, 0x40}, // Swap bits 1/4 and 3/6.
2169 {0x02, 0x04, 0x20, 0x40}, // Swap bits 1/2 and 5/6.
2170 };
2171
2172 uint8_t Imm = MI.getOperand(i: MI.getNumOperands() - 1).getImm();
2173 // Clear out the bits we are swapping.
2174 uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
2175 SwapMasks[Case][2] | SwapMasks[Case][3]);
2176 // If the immediate had a bit of the pair set, then set the opposite bit.
2177 if (Imm & SwapMasks[Case][0])
2178 NewImm |= SwapMasks[Case][1];
2179 if (Imm & SwapMasks[Case][1])
2180 NewImm |= SwapMasks[Case][0];
2181 if (Imm & SwapMasks[Case][2])
2182 NewImm |= SwapMasks[Case][3];
2183 if (Imm & SwapMasks[Case][3])
2184 NewImm |= SwapMasks[Case][2];
2185 MI.getOperand(i: MI.getNumOperands() - 1).setImm(NewImm);
2186}
2187
2188// Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
2189// commuted.
2190static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
2191#define VPERM_CASES(Suffix) \
2192 case X86::VPERMI2##Suffix##Z128rr: \
2193 case X86::VPERMT2##Suffix##Z128rr: \
2194 case X86::VPERMI2##Suffix##Z256rr: \
2195 case X86::VPERMT2##Suffix##Z256rr: \
2196 case X86::VPERMI2##Suffix##Zrr: \
2197 case X86::VPERMT2##Suffix##Zrr: \
2198 case X86::VPERMI2##Suffix##Z128rm: \
2199 case X86::VPERMT2##Suffix##Z128rm: \
2200 case X86::VPERMI2##Suffix##Z256rm: \
2201 case X86::VPERMT2##Suffix##Z256rm: \
2202 case X86::VPERMI2##Suffix##Zrm: \
2203 case X86::VPERMT2##Suffix##Zrm: \
2204 case X86::VPERMI2##Suffix##Z128rrkz: \
2205 case X86::VPERMT2##Suffix##Z128rrkz: \
2206 case X86::VPERMI2##Suffix##Z256rrkz: \
2207 case X86::VPERMT2##Suffix##Z256rrkz: \
2208 case X86::VPERMI2##Suffix##Zrrkz: \
2209 case X86::VPERMT2##Suffix##Zrrkz: \
2210 case X86::VPERMI2##Suffix##Z128rmkz: \
2211 case X86::VPERMT2##Suffix##Z128rmkz: \
2212 case X86::VPERMI2##Suffix##Z256rmkz: \
2213 case X86::VPERMT2##Suffix##Z256rmkz: \
2214 case X86::VPERMI2##Suffix##Zrmkz: \
2215 case X86::VPERMT2##Suffix##Zrmkz:
2216
2217#define VPERM_CASES_BROADCAST(Suffix) \
2218 VPERM_CASES(Suffix) \
2219 case X86::VPERMI2##Suffix##Z128rmb: \
2220 case X86::VPERMT2##Suffix##Z128rmb: \
2221 case X86::VPERMI2##Suffix##Z256rmb: \
2222 case X86::VPERMT2##Suffix##Z256rmb: \
2223 case X86::VPERMI2##Suffix##Zrmb: \
2224 case X86::VPERMT2##Suffix##Zrmb: \
2225 case X86::VPERMI2##Suffix##Z128rmbkz: \
2226 case X86::VPERMT2##Suffix##Z128rmbkz: \
2227 case X86::VPERMI2##Suffix##Z256rmbkz: \
2228 case X86::VPERMT2##Suffix##Z256rmbkz: \
2229 case X86::VPERMI2##Suffix##Zrmbkz: \
2230 case X86::VPERMT2##Suffix##Zrmbkz:
2231
2232 switch (Opcode) {
2233 default:
2234 return false;
2235 VPERM_CASES(B)
2236 VPERM_CASES_BROADCAST(D)
2237 VPERM_CASES_BROADCAST(PD)
2238 VPERM_CASES_BROADCAST(PS)
2239 VPERM_CASES_BROADCAST(Q)
2240 VPERM_CASES(W)
2241 return true;
2242 }
2243#undef VPERM_CASES_BROADCAST
2244#undef VPERM_CASES
2245}
2246
2247// Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
2248// from the I opcode to the T opcode and vice versa.
2249static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
2250#define VPERM_CASES(Orig, New) \
2251 case X86::Orig##Z128rr: \
2252 return X86::New##Z128rr; \
2253 case X86::Orig##Z128rrkz: \
2254 return X86::New##Z128rrkz; \
2255 case X86::Orig##Z128rm: \
2256 return X86::New##Z128rm; \
2257 case X86::Orig##Z128rmkz: \
2258 return X86::New##Z128rmkz; \
2259 case X86::Orig##Z256rr: \
2260 return X86::New##Z256rr; \
2261 case X86::Orig##Z256rrkz: \
2262 return X86::New##Z256rrkz; \
2263 case X86::Orig##Z256rm: \
2264 return X86::New##Z256rm; \
2265 case X86::Orig##Z256rmkz: \
2266 return X86::New##Z256rmkz; \
2267 case X86::Orig##Zrr: \
2268 return X86::New##Zrr; \
2269 case X86::Orig##Zrrkz: \
2270 return X86::New##Zrrkz; \
2271 case X86::Orig##Zrm: \
2272 return X86::New##Zrm; \
2273 case X86::Orig##Zrmkz: \
2274 return X86::New##Zrmkz;
2275
2276#define VPERM_CASES_BROADCAST(Orig, New) \
2277 VPERM_CASES(Orig, New) \
2278 case X86::Orig##Z128rmb: \
2279 return X86::New##Z128rmb; \
2280 case X86::Orig##Z128rmbkz: \
2281 return X86::New##Z128rmbkz; \
2282 case X86::Orig##Z256rmb: \
2283 return X86::New##Z256rmb; \
2284 case X86::Orig##Z256rmbkz: \
2285 return X86::New##Z256rmbkz; \
2286 case X86::Orig##Zrmb: \
2287 return X86::New##Zrmb; \
2288 case X86::Orig##Zrmbkz: \
2289 return X86::New##Zrmbkz;
2290
2291 switch (Opcode) {
2292 VPERM_CASES(VPERMI2B, VPERMT2B)
2293 VPERM_CASES_BROADCAST(VPERMI2D, VPERMT2D)
2294 VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
2295 VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
2296 VPERM_CASES_BROADCAST(VPERMI2Q, VPERMT2Q)
2297 VPERM_CASES(VPERMI2W, VPERMT2W)
2298 VPERM_CASES(VPERMT2B, VPERMI2B)
2299 VPERM_CASES_BROADCAST(VPERMT2D, VPERMI2D)
2300 VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
2301 VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
2302 VPERM_CASES_BROADCAST(VPERMT2Q, VPERMI2Q)
2303 VPERM_CASES(VPERMT2W, VPERMI2W)
2304 }
2305
2306 llvm_unreachable("Unreachable!");
2307#undef VPERM_CASES_BROADCAST
2308#undef VPERM_CASES
2309}
2310
2311MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
2312 unsigned OpIdx1,
2313 unsigned OpIdx2) const {
2314 auto CloneIfNew = [&](MachineInstr &MI) {
2315 return std::exchange(obj&: NewMI, new_val: false)
2316 ? MI.getParent()->getParent()->CloneMachineInstr(Orig: &MI)
2317 : &MI;
2318 };
2319 MachineInstr *WorkingMI = nullptr;
2320 unsigned Opc = MI.getOpcode();
2321
2322#define CASE_ND(OP) \
2323 case X86::OP: \
2324 case X86::OP##_ND:
2325
2326 switch (Opc) {
2327 // SHLD B, C, I <-> SHRD C, B, (BitWidth - I)
2328 CASE_ND(SHRD16rri8)
2329 CASE_ND(SHLD16rri8)
2330 CASE_ND(SHRD32rri8)
2331 CASE_ND(SHLD32rri8)
2332 CASE_ND(SHRD64rri8)
2333 CASE_ND(SHLD64rri8) {
2334 unsigned Size;
2335 switch (Opc) {
2336 default:
2337 llvm_unreachable("Unreachable!");
2338#define FROM_TO_SIZE(A, B, S) \
2339 case X86::A: \
2340 Opc = X86::B; \
2341 Size = S; \
2342 break; \
2343 case X86::A##_ND: \
2344 Opc = X86::B##_ND; \
2345 Size = S; \
2346 break; \
2347 case X86::B: \
2348 Opc = X86::A; \
2349 Size = S; \
2350 break; \
2351 case X86::B##_ND: \
2352 Opc = X86::A##_ND; \
2353 Size = S; \
2354 break;
2355
2356 FROM_TO_SIZE(SHRD16rri8, SHLD16rri8, 16)
2357 FROM_TO_SIZE(SHRD32rri8, SHLD32rri8, 32)
2358 FROM_TO_SIZE(SHRD64rri8, SHLD64rri8, 64)
2359#undef FROM_TO_SIZE
2360 }
2361 WorkingMI = CloneIfNew(MI);
2362 WorkingMI->setDesc(get(Opcode: Opc));
2363 WorkingMI->getOperand(i: 3).setImm(Size - MI.getOperand(i: 3).getImm());
2364 break;
2365 }
2366 case X86::PFSUBrr:
2367 case X86::PFSUBRrr:
2368 // PFSUB x, y: x = x - y
2369 // PFSUBR x, y: x = y - x
2370 WorkingMI = CloneIfNew(MI);
2371 WorkingMI->setDesc(
2372 get(Opcode: X86::PFSUBRrr == Opc ? X86::PFSUBrr : X86::PFSUBRrr));
2373 break;
2374 case X86::BLENDPDrri:
2375 case X86::BLENDPSrri:
2376 case X86::PBLENDWrri:
2377 case X86::VBLENDPDrri:
2378 case X86::VBLENDPSrri:
2379 case X86::VBLENDPDYrri:
2380 case X86::VBLENDPSYrri:
2381 case X86::VPBLENDDrri:
2382 case X86::VPBLENDWrri:
2383 case X86::VPBLENDDYrri:
2384 case X86::VPBLENDWYrri: {
2385 int8_t Mask;
2386 switch (Opc) {
2387 default:
2388 llvm_unreachable("Unreachable!");
2389 case X86::BLENDPDrri:
2390 Mask = (int8_t)0x03;
2391 break;
2392 case X86::BLENDPSrri:
2393 Mask = (int8_t)0x0F;
2394 break;
2395 case X86::PBLENDWrri:
2396 Mask = (int8_t)0xFF;
2397 break;
2398 case X86::VBLENDPDrri:
2399 Mask = (int8_t)0x03;
2400 break;
2401 case X86::VBLENDPSrri:
2402 Mask = (int8_t)0x0F;
2403 break;
2404 case X86::VBLENDPDYrri:
2405 Mask = (int8_t)0x0F;
2406 break;
2407 case X86::VBLENDPSYrri:
2408 Mask = (int8_t)0xFF;
2409 break;
2410 case X86::VPBLENDDrri:
2411 Mask = (int8_t)0x0F;
2412 break;
2413 case X86::VPBLENDWrri:
2414 Mask = (int8_t)0xFF;
2415 break;
2416 case X86::VPBLENDDYrri:
2417 Mask = (int8_t)0xFF;
2418 break;
2419 case X86::VPBLENDWYrri:
2420 Mask = (int8_t)0xFF;
2421 break;
2422 }
2423 // Only the least significant bits of Imm are used.
2424 // Using int8_t to ensure it will be sign extended to the int64_t that
2425 // setImm takes in order to match isel behavior.
2426 int8_t Imm = MI.getOperand(i: 3).getImm() & Mask;
2427 WorkingMI = CloneIfNew(MI);
2428 WorkingMI->getOperand(i: 3).setImm(Mask ^ Imm);
2429 break;
2430 }
2431 case X86::INSERTPSrri:
2432 case X86::VINSERTPSrri:
2433 case X86::VINSERTPSZrri: {
2434 unsigned Imm = MI.getOperand(i: MI.getNumOperands() - 1).getImm();
2435 unsigned ZMask = Imm & 15;
2436 unsigned DstIdx = (Imm >> 4) & 3;
2437 unsigned SrcIdx = (Imm >> 6) & 3;
2438
2439 // We can commute insertps if we zero 2 of the elements, the insertion is
2440 // "inline" and we don't override the insertion with a zero.
2441 if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
2442 llvm::popcount(Value: ZMask) == 2) {
2443 unsigned AltIdx = llvm::countr_zero(Val: (ZMask | (1 << DstIdx)) ^ 15);
2444 assert(AltIdx < 4 && "Illegal insertion index");
2445 unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
2446 WorkingMI = CloneIfNew(MI);
2447 WorkingMI->getOperand(i: MI.getNumOperands() - 1).setImm(AltImm);
2448 break;
2449 }
2450 return nullptr;
2451 }
2452 case X86::MOVSDrr:
2453 case X86::MOVSSrr:
2454 case X86::VMOVSDrr:
2455 case X86::VMOVSSrr: {
2456 // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
2457 if (Subtarget.hasSSE41()) {
2458 unsigned Mask;
2459 switch (Opc) {
2460 default:
2461 llvm_unreachable("Unreachable!");
2462 case X86::MOVSDrr:
2463 Opc = X86::BLENDPDrri;
2464 Mask = 0x02;
2465 break;
2466 case X86::MOVSSrr:
2467 Opc = X86::BLENDPSrri;
2468 Mask = 0x0E;
2469 break;
2470 case X86::VMOVSDrr:
2471 Opc = X86::VBLENDPDrri;
2472 Mask = 0x02;
2473 break;
2474 case X86::VMOVSSrr:
2475 Opc = X86::VBLENDPSrri;
2476 Mask = 0x0E;
2477 break;
2478 }
2479
2480 WorkingMI = CloneIfNew(MI);
2481 WorkingMI->setDesc(get(Opcode: Opc));
2482 WorkingMI->addOperand(Op: MachineOperand::CreateImm(Val: Mask));
2483 break;
2484 }
2485
2486 assert(Opc == X86::MOVSDrr && "Only MOVSD can commute to SHUFPD");
2487 WorkingMI = CloneIfNew(MI);
2488 WorkingMI->setDesc(get(Opcode: X86::SHUFPDrri));
2489 WorkingMI->addOperand(Op: MachineOperand::CreateImm(Val: 0x02));
2490 break;
2491 }
2492 case X86::SHUFPDrri: {
2493 // Commute to MOVSD.
2494 assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!");
2495 WorkingMI = CloneIfNew(MI);
2496 WorkingMI->setDesc(get(Opcode: X86::MOVSDrr));
2497 WorkingMI->removeOperand(OpNo: 3);
2498 break;
2499 }
2500 case X86::PCLMULQDQrri:
2501 case X86::VPCLMULQDQrri:
2502 case X86::VPCLMULQDQYrri:
2503 case X86::VPCLMULQDQZrri:
2504 case X86::VPCLMULQDQZ128rri:
2505 case X86::VPCLMULQDQZ256rri: {
2506 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2507 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2508 unsigned Imm = MI.getOperand(i: 3).getImm();
2509 unsigned Src1Hi = Imm & 0x01;
2510 unsigned Src2Hi = Imm & 0x10;
2511 WorkingMI = CloneIfNew(MI);
2512 WorkingMI->getOperand(i: 3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
2513 break;
2514 }
2515 case X86::VPCMPBZ128rri:
2516 case X86::VPCMPUBZ128rri:
2517 case X86::VPCMPBZ256rri:
2518 case X86::VPCMPUBZ256rri:
2519 case X86::VPCMPBZrri:
2520 case X86::VPCMPUBZrri:
2521 case X86::VPCMPDZ128rri:
2522 case X86::VPCMPUDZ128rri:
2523 case X86::VPCMPDZ256rri:
2524 case X86::VPCMPUDZ256rri:
2525 case X86::VPCMPDZrri:
2526 case X86::VPCMPUDZrri:
2527 case X86::VPCMPQZ128rri:
2528 case X86::VPCMPUQZ128rri:
2529 case X86::VPCMPQZ256rri:
2530 case X86::VPCMPUQZ256rri:
2531 case X86::VPCMPQZrri:
2532 case X86::VPCMPUQZrri:
2533 case X86::VPCMPWZ128rri:
2534 case X86::VPCMPUWZ128rri:
2535 case X86::VPCMPWZ256rri:
2536 case X86::VPCMPUWZ256rri:
2537 case X86::VPCMPWZrri:
2538 case X86::VPCMPUWZrri:
2539 case X86::VPCMPBZ128rrik:
2540 case X86::VPCMPUBZ128rrik:
2541 case X86::VPCMPBZ256rrik:
2542 case X86::VPCMPUBZ256rrik:
2543 case X86::VPCMPBZrrik:
2544 case X86::VPCMPUBZrrik:
2545 case X86::VPCMPDZ128rrik:
2546 case X86::VPCMPUDZ128rrik:
2547 case X86::VPCMPDZ256rrik:
2548 case X86::VPCMPUDZ256rrik:
2549 case X86::VPCMPDZrrik:
2550 case X86::VPCMPUDZrrik:
2551 case X86::VPCMPQZ128rrik:
2552 case X86::VPCMPUQZ128rrik:
2553 case X86::VPCMPQZ256rrik:
2554 case X86::VPCMPUQZ256rrik:
2555 case X86::VPCMPQZrrik:
2556 case X86::VPCMPUQZrrik:
2557 case X86::VPCMPWZ128rrik:
2558 case X86::VPCMPUWZ128rrik:
2559 case X86::VPCMPWZ256rrik:
2560 case X86::VPCMPUWZ256rrik:
2561 case X86::VPCMPWZrrik:
2562 case X86::VPCMPUWZrrik:
2563 WorkingMI = CloneIfNew(MI);
2564 // Flip comparison mode immediate (if necessary).
2565 WorkingMI->getOperand(i: MI.getNumOperands() - 1)
2566 .setImm(X86::getSwappedVPCMPImm(
2567 Imm: MI.getOperand(i: MI.getNumOperands() - 1).getImm() & 0x7));
2568 break;
2569 case X86::VPCOMBri:
2570 case X86::VPCOMUBri:
2571 case X86::VPCOMDri:
2572 case X86::VPCOMUDri:
2573 case X86::VPCOMQri:
2574 case X86::VPCOMUQri:
2575 case X86::VPCOMWri:
2576 case X86::VPCOMUWri:
2577 WorkingMI = CloneIfNew(MI);
2578 // Flip comparison mode immediate (if necessary).
2579 WorkingMI->getOperand(i: 3).setImm(
2580 X86::getSwappedVPCOMImm(Imm: MI.getOperand(i: 3).getImm() & 0x7));
2581 break;
2582 case X86::VCMPSDZrri:
2583 case X86::VCMPSSZrri:
2584 case X86::VCMPPDZrri:
2585 case X86::VCMPPSZrri:
2586 case X86::VCMPSHZrri:
2587 case X86::VCMPPHZrri:
2588 case X86::VCMPPHZ128rri:
2589 case X86::VCMPPHZ256rri:
2590 case X86::VCMPPDZ128rri:
2591 case X86::VCMPPSZ128rri:
2592 case X86::VCMPPDZ256rri:
2593 case X86::VCMPPSZ256rri:
2594 case X86::VCMPPDZrrik:
2595 case X86::VCMPPSZrrik:
2596 case X86::VCMPPHZrrik:
2597 case X86::VCMPPDZ128rrik:
2598 case X86::VCMPPSZ128rrik:
2599 case X86::VCMPPHZ128rrik:
2600 case X86::VCMPPDZ256rrik:
2601 case X86::VCMPPSZ256rrik:
2602 case X86::VCMPPHZ256rrik:
2603 WorkingMI = CloneIfNew(MI);
2604 WorkingMI->getOperand(i: MI.getNumExplicitOperands() - 1)
2605 .setImm(X86::getSwappedVCMPImm(
2606 Imm: MI.getOperand(i: MI.getNumExplicitOperands() - 1).getImm() & 0x1f));
2607 break;
2608 case X86::VPERM2F128rri:
2609 case X86::VPERM2I128rri:
2610 // Flip permute source immediate.
2611 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
2612 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
2613 WorkingMI = CloneIfNew(MI);
2614 WorkingMI->getOperand(i: 3).setImm((MI.getOperand(i: 3).getImm() & 0xFF) ^ 0x22);
2615 break;
2616 case X86::MOVHLPSrr:
2617 case X86::UNPCKHPDrr:
2618 case X86::VMOVHLPSrr:
2619 case X86::VUNPCKHPDrr:
2620 case X86::VMOVHLPSZrr:
2621 case X86::VUNPCKHPDZ128rr:
2622 assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
2623
2624 switch (Opc) {
2625 default:
2626 llvm_unreachable("Unreachable!");
2627 case X86::MOVHLPSrr:
2628 Opc = X86::UNPCKHPDrr;
2629 break;
2630 case X86::UNPCKHPDrr:
2631 Opc = X86::MOVHLPSrr;
2632 break;
2633 case X86::VMOVHLPSrr:
2634 Opc = X86::VUNPCKHPDrr;
2635 break;
2636 case X86::VUNPCKHPDrr:
2637 Opc = X86::VMOVHLPSrr;
2638 break;
2639 case X86::VMOVHLPSZrr:
2640 Opc = X86::VUNPCKHPDZ128rr;
2641 break;
2642 case X86::VUNPCKHPDZ128rr:
2643 Opc = X86::VMOVHLPSZrr;
2644 break;
2645 }
2646 WorkingMI = CloneIfNew(MI);
2647 WorkingMI->setDesc(get(Opcode: Opc));
2648 break;
2649 CASE_ND(CMOV16rr)
2650 CASE_ND(CMOV32rr)
2651 CASE_ND(CMOV64rr) {
2652 WorkingMI = CloneIfNew(MI);
2653 unsigned OpNo = MI.getDesc().getNumOperands() - 1;
2654 X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(i: OpNo).getImm());
2655 WorkingMI->getOperand(i: OpNo).setImm(X86::GetOppositeBranchCondition(CC));
2656 break;
2657 }
2658 case X86::VPTERNLOGDZrri:
2659 case X86::VPTERNLOGDZrmi:
2660 case X86::VPTERNLOGDZ128rri:
2661 case X86::VPTERNLOGDZ128rmi:
2662 case X86::VPTERNLOGDZ256rri:
2663 case X86::VPTERNLOGDZ256rmi:
2664 case X86::VPTERNLOGQZrri:
2665 case X86::VPTERNLOGQZrmi:
2666 case X86::VPTERNLOGQZ128rri:
2667 case X86::VPTERNLOGQZ128rmi:
2668 case X86::VPTERNLOGQZ256rri:
2669 case X86::VPTERNLOGQZ256rmi:
2670 case X86::VPTERNLOGDZrrik:
2671 case X86::VPTERNLOGDZ128rrik:
2672 case X86::VPTERNLOGDZ256rrik:
2673 case X86::VPTERNLOGQZrrik:
2674 case X86::VPTERNLOGQZ128rrik:
2675 case X86::VPTERNLOGQZ256rrik:
2676 case X86::VPTERNLOGDZrrikz:
2677 case X86::VPTERNLOGDZrmikz:
2678 case X86::VPTERNLOGDZ128rrikz:
2679 case X86::VPTERNLOGDZ128rmikz:
2680 case X86::VPTERNLOGDZ256rrikz:
2681 case X86::VPTERNLOGDZ256rmikz:
2682 case X86::VPTERNLOGQZrrikz:
2683 case X86::VPTERNLOGQZrmikz:
2684 case X86::VPTERNLOGQZ128rrikz:
2685 case X86::VPTERNLOGQZ128rmikz:
2686 case X86::VPTERNLOGQZ256rrikz:
2687 case X86::VPTERNLOGQZ256rmikz:
2688 case X86::VPTERNLOGDZ128rmbi:
2689 case X86::VPTERNLOGDZ256rmbi:
2690 case X86::VPTERNLOGDZrmbi:
2691 case X86::VPTERNLOGQZ128rmbi:
2692 case X86::VPTERNLOGQZ256rmbi:
2693 case X86::VPTERNLOGQZrmbi:
2694 case X86::VPTERNLOGDZ128rmbikz:
2695 case X86::VPTERNLOGDZ256rmbikz:
2696 case X86::VPTERNLOGDZrmbikz:
2697 case X86::VPTERNLOGQZ128rmbikz:
2698 case X86::VPTERNLOGQZ256rmbikz:
2699 case X86::VPTERNLOGQZrmbikz: {
2700 WorkingMI = CloneIfNew(MI);
2701 commuteVPTERNLOG(MI&: *WorkingMI, SrcOpIdx1: OpIdx1, SrcOpIdx2: OpIdx2);
2702 break;
2703 }
2704 default:
2705 if (isCommutableVPERMV3Instruction(Opcode: Opc)) {
2706 WorkingMI = CloneIfNew(MI);
2707 WorkingMI->setDesc(get(Opcode: getCommutedVPERMV3Opcode(Opcode: Opc)));
2708 break;
2709 }
2710
2711 if (auto *FMA3Group = getFMA3Group(Opcode: Opc, TSFlags: MI.getDesc().TSFlags)) {
2712 WorkingMI = CloneIfNew(MI);
2713 WorkingMI->setDesc(
2714 get(Opcode: getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1: OpIdx1, SrcOpIdx2: OpIdx2, FMA3Group: *FMA3Group)));
2715 break;
2716 }
2717 }
2718 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2719}
2720
2721bool X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
2722 unsigned &SrcOpIdx1,
2723 unsigned &SrcOpIdx2,
2724 bool IsIntrinsic) const {
2725 uint64_t TSFlags = MI.getDesc().TSFlags;
2726
2727 unsigned FirstCommutableVecOp = 1;
2728 unsigned LastCommutableVecOp = 3;
2729 unsigned KMaskOp = -1U;
2730 if (X86II::isKMasked(TSFlags)) {
2731 // For k-zero-masked operations it is Ok to commute the first vector
2732 // operand. Unless this is an intrinsic instruction.
2733 // For regular k-masked operations a conservative choice is done as the
2734 // elements of the first vector operand, for which the corresponding bit
2735 // in the k-mask operand is set to 0, are copied to the result of the
2736 // instruction.
2737 // TODO/FIXME: The commute still may be legal if it is known that the
2738 // k-mask operand is set to either all ones or all zeroes.
2739 // It is also Ok to commute the 1st operand if all users of MI use only
2740 // the elements enabled by the k-mask operand. For example,
2741 // v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
2742 // : v1[i];
2743 // VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
2744 // // Ok, to commute v1 in FMADD213PSZrk.
2745
2746 // The k-mask operand has index = 2 for masked and zero-masked operations.
2747 KMaskOp = 2;
2748
2749 // The operand with index = 1 is used as a source for those elements for
2750 // which the corresponding bit in the k-mask is set to 0.
2751 if (X86II::isKMergeMasked(TSFlags) || IsIntrinsic)
2752 FirstCommutableVecOp = 3;
2753
2754 LastCommutableVecOp++;
2755 } else if (IsIntrinsic) {
2756 // Commuting the first operand of an intrinsic instruction isn't possible
2757 // unless we can prove that only the lowest element of the result is used.
2758 FirstCommutableVecOp = 2;
2759 }
2760
2761 if (isMem(MI, Op: LastCommutableVecOp))
2762 LastCommutableVecOp--;
2763
2764 // Only the first RegOpsNum operands are commutable.
2765 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
2766 // that the operand is not specified/fixed.
2767 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
2768 (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
2769 SrcOpIdx1 == KMaskOp))
2770 return false;
2771 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
2772 (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
2773 SrcOpIdx2 == KMaskOp))
2774 return false;
2775
2776 // Look for two different register operands assumed to be commutable
2777 // regardless of the FMA opcode. The FMA opcode is adjusted later.
2778 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
2779 SrcOpIdx2 == CommuteAnyOperandIndex) {
2780 unsigned CommutableOpIdx2 = SrcOpIdx2;
2781
2782 // At least one of operands to be commuted is not specified and
2783 // this method is free to choose appropriate commutable operands.
2784 if (SrcOpIdx1 == SrcOpIdx2)
2785 // Both of operands are not fixed. By default set one of commutable
2786 // operands to the last register operand of the instruction.
2787 CommutableOpIdx2 = LastCommutableVecOp;
2788 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
2789 // Only one of operands is not fixed.
2790 CommutableOpIdx2 = SrcOpIdx1;
2791
2792 // CommutableOpIdx2 is well defined now. Let's choose another commutable
2793 // operand and assign its index to CommutableOpIdx1.
2794 Register Op2Reg = MI.getOperand(i: CommutableOpIdx2).getReg();
2795
2796 unsigned CommutableOpIdx1;
2797 for (CommutableOpIdx1 = LastCommutableVecOp;
2798 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
2799 // Just ignore and skip the k-mask operand.
2800 if (CommutableOpIdx1 == KMaskOp)
2801 continue;
2802
2803 // The commuted operands must have different registers.
2804 // Otherwise, the commute transformation does not change anything and
2805 // is useless then.
2806 if (Op2Reg != MI.getOperand(i: CommutableOpIdx1).getReg())
2807 break;
2808 }
2809
2810 // No appropriate commutable operands were found.
2811 if (CommutableOpIdx1 < FirstCommutableVecOp)
2812 return false;
2813
2814 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
2815 // to return those values.
2816 if (!fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1,
2817 CommutableOpIdx2))
2818 return false;
2819 }
2820
2821 return true;
2822}
2823
2824bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI,
2825 unsigned &SrcOpIdx1,
2826 unsigned &SrcOpIdx2) const {
2827 const MCInstrDesc &Desc = MI.getDesc();
2828 if (!Desc.isCommutable())
2829 return false;
2830
2831 switch (MI.getOpcode()) {
2832 case X86::CMPSDrri:
2833 case X86::CMPSSrri:
2834 case X86::CMPPDrri:
2835 case X86::CMPPSrri:
2836 case X86::VCMPSDrri:
2837 case X86::VCMPSSrri:
2838 case X86::VCMPPDrri:
2839 case X86::VCMPPSrri:
2840 case X86::VCMPPDYrri:
2841 case X86::VCMPPSYrri:
2842 case X86::VCMPSDZrri:
2843 case X86::VCMPSSZrri:
2844 case X86::VCMPPDZrri:
2845 case X86::VCMPPSZrri:
2846 case X86::VCMPSHZrri:
2847 case X86::VCMPPHZrri:
2848 case X86::VCMPPHZ128rri:
2849 case X86::VCMPPHZ256rri:
2850 case X86::VCMPPDZ128rri:
2851 case X86::VCMPPSZ128rri:
2852 case X86::VCMPPDZ256rri:
2853 case X86::VCMPPSZ256rri:
2854 case X86::VCMPPDZrrik:
2855 case X86::VCMPPSZrrik:
2856 case X86::VCMPPHZrrik:
2857 case X86::VCMPPDZ128rrik:
2858 case X86::VCMPPSZ128rrik:
2859 case X86::VCMPPHZ128rrik:
2860 case X86::VCMPPDZ256rrik:
2861 case X86::VCMPPSZ256rrik:
2862 case X86::VCMPPHZ256rrik: {
2863 unsigned OpOffset = X86II::isKMasked(TSFlags: Desc.TSFlags) ? 1 : 0;
2864
2865 // Float comparison can be safely commuted for
2866 // Ordered/Unordered/Equal/NotEqual tests
2867 unsigned Imm = MI.getOperand(i: 3 + OpOffset).getImm() & 0x7;
2868 switch (Imm) {
2869 default:
2870 // EVEX versions can be commuted.
2871 if ((Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX)
2872 break;
2873 return false;
2874 case 0x00: // EQUAL
2875 case 0x03: // UNORDERED
2876 case 0x04: // NOT EQUAL
2877 case 0x07: // ORDERED
2878 break;
2879 }
2880
2881 // The indices of the commutable operands are 1 and 2 (or 2 and 3
2882 // when masked).
2883 // Assign them to the returned operand indices here.
2884 return fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1: 1 + OpOffset,
2885 CommutableOpIdx2: 2 + OpOffset);
2886 }
2887 case X86::MOVSSrr:
2888 // X86::MOVSDrr is always commutable. MOVSS is only commutable if we can
2889 // form sse4.1 blend. We assume VMOVSSrr/VMOVSDrr is always commutable since
2890 // AVX implies sse4.1.
2891 if (Subtarget.hasSSE41())
2892 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2893 return false;
2894 case X86::SHUFPDrri:
2895 // We can commute this to MOVSD.
2896 if (MI.getOperand(i: 3).getImm() == 0x02)
2897 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2898 return false;
2899 case X86::MOVHLPSrr:
2900 case X86::UNPCKHPDrr:
2901 case X86::VMOVHLPSrr:
2902 case X86::VUNPCKHPDrr:
2903 case X86::VMOVHLPSZrr:
2904 case X86::VUNPCKHPDZ128rr:
2905 if (Subtarget.hasSSE2())
2906 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2907 return false;
2908 case X86::VPTERNLOGDZrri:
2909 case X86::VPTERNLOGDZrmi:
2910 case X86::VPTERNLOGDZ128rri:
2911 case X86::VPTERNLOGDZ128rmi:
2912 case X86::VPTERNLOGDZ256rri:
2913 case X86::VPTERNLOGDZ256rmi:
2914 case X86::VPTERNLOGQZrri:
2915 case X86::VPTERNLOGQZrmi:
2916 case X86::VPTERNLOGQZ128rri:
2917 case X86::VPTERNLOGQZ128rmi:
2918 case X86::VPTERNLOGQZ256rri:
2919 case X86::VPTERNLOGQZ256rmi:
2920 case X86::VPTERNLOGDZrrik:
2921 case X86::VPTERNLOGDZ128rrik:
2922 case X86::VPTERNLOGDZ256rrik:
2923 case X86::VPTERNLOGQZrrik:
2924 case X86::VPTERNLOGQZ128rrik:
2925 case X86::VPTERNLOGQZ256rrik:
2926 case X86::VPTERNLOGDZrrikz:
2927 case X86::VPTERNLOGDZrmikz:
2928 case X86::VPTERNLOGDZ128rrikz:
2929 case X86::VPTERNLOGDZ128rmikz:
2930 case X86::VPTERNLOGDZ256rrikz:
2931 case X86::VPTERNLOGDZ256rmikz:
2932 case X86::VPTERNLOGQZrrikz:
2933 case X86::VPTERNLOGQZrmikz:
2934 case X86::VPTERNLOGQZ128rrikz:
2935 case X86::VPTERNLOGQZ128rmikz:
2936 case X86::VPTERNLOGQZ256rrikz:
2937 case X86::VPTERNLOGQZ256rmikz:
2938 case X86::VPTERNLOGDZ128rmbi:
2939 case X86::VPTERNLOGDZ256rmbi:
2940 case X86::VPTERNLOGDZrmbi:
2941 case X86::VPTERNLOGQZ128rmbi:
2942 case X86::VPTERNLOGQZ256rmbi:
2943 case X86::VPTERNLOGQZrmbi:
2944 case X86::VPTERNLOGDZ128rmbikz:
2945 case X86::VPTERNLOGDZ256rmbikz:
2946 case X86::VPTERNLOGDZrmbikz:
2947 case X86::VPTERNLOGQZ128rmbikz:
2948 case X86::VPTERNLOGQZ256rmbikz:
2949 case X86::VPTERNLOGQZrmbikz:
2950 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2951 case X86::VPDPWSSDYrr:
2952 case X86::VPDPWSSDrr:
2953 case X86::VPDPWSSDSYrr:
2954 case X86::VPDPWSSDSrr:
2955 case X86::VPDPWUUDrr:
2956 case X86::VPDPWUUDYrr:
2957 case X86::VPDPWUUDSrr:
2958 case X86::VPDPWUUDSYrr:
2959 case X86::VPDPBSSDSrr:
2960 case X86::VPDPBSSDSYrr:
2961 case X86::VPDPBSSDrr:
2962 case X86::VPDPBSSDYrr:
2963 case X86::VPDPBUUDSrr:
2964 case X86::VPDPBUUDSYrr:
2965 case X86::VPDPBUUDrr:
2966 case X86::VPDPBUUDYrr:
2967 case X86::VPDPBSSDSZ128rr:
2968 case X86::VPDPBSSDSZ128rrk:
2969 case X86::VPDPBSSDSZ128rrkz:
2970 case X86::VPDPBSSDSZ256rr:
2971 case X86::VPDPBSSDSZ256rrk:
2972 case X86::VPDPBSSDSZ256rrkz:
2973 case X86::VPDPBSSDSZrr:
2974 case X86::VPDPBSSDSZrrk:
2975 case X86::VPDPBSSDSZrrkz:
2976 case X86::VPDPBSSDZ128rr:
2977 case X86::VPDPBSSDZ128rrk:
2978 case X86::VPDPBSSDZ128rrkz:
2979 case X86::VPDPBSSDZ256rr:
2980 case X86::VPDPBSSDZ256rrk:
2981 case X86::VPDPBSSDZ256rrkz:
2982 case X86::VPDPBSSDZrr:
2983 case X86::VPDPBSSDZrrk:
2984 case X86::VPDPBSSDZrrkz:
2985 case X86::VPDPBUUDSZ128rr:
2986 case X86::VPDPBUUDSZ128rrk:
2987 case X86::VPDPBUUDSZ128rrkz:
2988 case X86::VPDPBUUDSZ256rr:
2989 case X86::VPDPBUUDSZ256rrk:
2990 case X86::VPDPBUUDSZ256rrkz:
2991 case X86::VPDPBUUDSZrr:
2992 case X86::VPDPBUUDSZrrk:
2993 case X86::VPDPBUUDSZrrkz:
2994 case X86::VPDPBUUDZ128rr:
2995 case X86::VPDPBUUDZ128rrk:
2996 case X86::VPDPBUUDZ128rrkz:
2997 case X86::VPDPBUUDZ256rr:
2998 case X86::VPDPBUUDZ256rrk:
2999 case X86::VPDPBUUDZ256rrkz:
3000 case X86::VPDPBUUDZrr:
3001 case X86::VPDPBUUDZrrk:
3002 case X86::VPDPBUUDZrrkz:
3003 case X86::VPDPWSSDZ128rr:
3004 case X86::VPDPWSSDZ128rrk:
3005 case X86::VPDPWSSDZ128rrkz:
3006 case X86::VPDPWSSDZ256rr:
3007 case X86::VPDPWSSDZ256rrk:
3008 case X86::VPDPWSSDZ256rrkz:
3009 case X86::VPDPWSSDZrr:
3010 case X86::VPDPWSSDZrrk:
3011 case X86::VPDPWSSDZrrkz:
3012 case X86::VPDPWSSDSZ128rr:
3013 case X86::VPDPWSSDSZ128rrk:
3014 case X86::VPDPWSSDSZ128rrkz:
3015 case X86::VPDPWSSDSZ256rr:
3016 case X86::VPDPWSSDSZ256rrk:
3017 case X86::VPDPWSSDSZ256rrkz:
3018 case X86::VPDPWSSDSZrr:
3019 case X86::VPDPWSSDSZrrk:
3020 case X86::VPDPWSSDSZrrkz:
3021 case X86::VPDPWUUDZ128rr:
3022 case X86::VPDPWUUDZ128rrk:
3023 case X86::VPDPWUUDZ128rrkz:
3024 case X86::VPDPWUUDZ256rr:
3025 case X86::VPDPWUUDZ256rrk:
3026 case X86::VPDPWUUDZ256rrkz:
3027 case X86::VPDPWUUDZrr:
3028 case X86::VPDPWUUDZrrk:
3029 case X86::VPDPWUUDZrrkz:
3030 case X86::VPDPWUUDSZ128rr:
3031 case X86::VPDPWUUDSZ128rrk:
3032 case X86::VPDPWUUDSZ128rrkz:
3033 case X86::VPDPWUUDSZ256rr:
3034 case X86::VPDPWUUDSZ256rrk:
3035 case X86::VPDPWUUDSZ256rrkz:
3036 case X86::VPDPWUUDSZrr:
3037 case X86::VPDPWUUDSZrrk:
3038 case X86::VPDPWUUDSZrrkz:
3039 case X86::VPMADD52HUQrr:
3040 case X86::VPMADD52HUQYrr:
3041 case X86::VPMADD52HUQZ128r:
3042 case X86::VPMADD52HUQZ128rk:
3043 case X86::VPMADD52HUQZ128rkz:
3044 case X86::VPMADD52HUQZ256r:
3045 case X86::VPMADD52HUQZ256rk:
3046 case X86::VPMADD52HUQZ256rkz:
3047 case X86::VPMADD52HUQZr:
3048 case X86::VPMADD52HUQZrk:
3049 case X86::VPMADD52HUQZrkz:
3050 case X86::VPMADD52LUQrr:
3051 case X86::VPMADD52LUQYrr:
3052 case X86::VPMADD52LUQZ128r:
3053 case X86::VPMADD52LUQZ128rk:
3054 case X86::VPMADD52LUQZ128rkz:
3055 case X86::VPMADD52LUQZ256r:
3056 case X86::VPMADD52LUQZ256rk:
3057 case X86::VPMADD52LUQZ256rkz:
3058 case X86::VPMADD52LUQZr:
3059 case X86::VPMADD52LUQZrk:
3060 case X86::VPMADD52LUQZrkz:
3061 case X86::VFMADDCPHZr:
3062 case X86::VFMADDCPHZrk:
3063 case X86::VFMADDCPHZrkz:
3064 case X86::VFMADDCPHZ128r:
3065 case X86::VFMADDCPHZ128rk:
3066 case X86::VFMADDCPHZ128rkz:
3067 case X86::VFMADDCPHZ256r:
3068 case X86::VFMADDCPHZ256rk:
3069 case X86::VFMADDCPHZ256rkz:
3070 case X86::VFMADDCSHZr:
3071 case X86::VFMADDCSHZrk:
3072 case X86::VFMADDCSHZrkz: {
3073 unsigned CommutableOpIdx1 = 2;
3074 unsigned CommutableOpIdx2 = 3;
3075 if (X86II::isKMasked(TSFlags: Desc.TSFlags)) {
3076 // Skip the mask register.
3077 ++CommutableOpIdx1;
3078 ++CommutableOpIdx2;
3079 }
3080 if (!fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1,
3081 CommutableOpIdx2))
3082 return false;
3083 if (!MI.getOperand(i: SrcOpIdx1).isReg() || !MI.getOperand(i: SrcOpIdx2).isReg())
3084 // No idea.
3085 return false;
3086 return true;
3087 }
3088
3089 default:
3090 const X86InstrFMA3Group *FMA3Group =
3091 getFMA3Group(Opcode: MI.getOpcode(), TSFlags: MI.getDesc().TSFlags);
3092 if (FMA3Group)
3093 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
3094 IsIntrinsic: FMA3Group->isIntrinsic());
3095
3096 // Handled masked instructions since we need to skip over the mask input
3097 // and the preserved input.
3098 if (X86II::isKMasked(TSFlags: Desc.TSFlags)) {
3099 // First assume that the first input is the mask operand and skip past it.
3100 unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
3101 unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
3102 // Check if the first input is tied. If there isn't one then we only
3103 // need to skip the mask operand which we did above.
3104 if ((MI.getDesc().getOperandConstraint(OpNum: Desc.getNumDefs(),
3105 Constraint: MCOI::TIED_TO) != -1)) {
3106 // If this is zero masking instruction with a tied operand, we need to
3107 // move the first index back to the first input since this must
3108 // be a 3 input instruction and we want the first two non-mask inputs.
3109 // Otherwise this is a 2 input instruction with a preserved input and
3110 // mask, so we need to move the indices to skip one more input.
3111 if (X86II::isKMergeMasked(TSFlags: Desc.TSFlags)) {
3112 ++CommutableOpIdx1;
3113 ++CommutableOpIdx2;
3114 } else {
3115 --CommutableOpIdx1;
3116 }
3117 }
3118
3119 if (!fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1,
3120 CommutableOpIdx2))
3121 return false;
3122
3123 if (!MI.getOperand(i: SrcOpIdx1).isReg() ||
3124 !MI.getOperand(i: SrcOpIdx2).isReg())
3125 // No idea.
3126 return false;
3127 return true;
3128 }
3129
3130 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3131 }
3132 return false;
3133}
3134
3135static bool isConvertibleLEA(MachineInstr *MI) {
3136 unsigned Opcode = MI->getOpcode();
3137 if (Opcode != X86::LEA32r && Opcode != X86::LEA64r &&
3138 Opcode != X86::LEA64_32r)
3139 return false;
3140
3141 const MachineOperand &Scale = MI->getOperand(i: 1 + X86::AddrScaleAmt);
3142 const MachineOperand &Disp = MI->getOperand(i: 1 + X86::AddrDisp);
3143 const MachineOperand &Segment = MI->getOperand(i: 1 + X86::AddrSegmentReg);
3144
3145 if (Segment.getReg() != 0 || !Disp.isImm() || Disp.getImm() != 0 ||
3146 Scale.getImm() > 1)
3147 return false;
3148
3149 return true;
3150}
3151
3152bool X86InstrInfo::hasCommutePreference(MachineInstr &MI, bool &Commute) const {
3153 // Currently we're interested in following sequence only.
3154 // r3 = lea r1, r2
3155 // r5 = add r3, r4
3156 // Both r3 and r4 are killed in add, we hope the add instruction has the
3157 // operand order
3158 // r5 = add r4, r3
3159 // So later in X86FixupLEAs the lea instruction can be rewritten as add.
3160 unsigned Opcode = MI.getOpcode();
3161 if (Opcode != X86::ADD32rr && Opcode != X86::ADD64rr)
3162 return false;
3163
3164 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3165 Register Reg1 = MI.getOperand(i: 1).getReg();
3166 Register Reg2 = MI.getOperand(i: 2).getReg();
3167
3168 // Check if Reg1 comes from LEA in the same MBB.
3169 if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg: Reg1)) {
3170 if (isConvertibleLEA(MI: Inst) && Inst->getParent() == MI.getParent()) {
3171 Commute = true;
3172 return true;
3173 }
3174 }
3175
3176 // Check if Reg2 comes from LEA in the same MBB.
3177 if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg: Reg2)) {
3178 if (isConvertibleLEA(MI: Inst) && Inst->getParent() == MI.getParent()) {
3179 Commute = false;
3180 return true;
3181 }
3182 }
3183
3184 return false;
3185}
3186
3187int X86::getCondSrcNoFromDesc(const MCInstrDesc &MCID) {
3188 unsigned Opcode = MCID.getOpcode();
3189 if (!(X86::isJCC(Opcode) || X86::isSETCC(Opcode) || X86::isSETZUCC(Opcode) ||
3190 X86::isCMOVCC(Opcode) || X86::isCFCMOVCC(Opcode) ||
3191 X86::isCCMPCC(Opcode) || X86::isCTESTCC(Opcode)))
3192 return -1;
3193 // Assume that condition code is always the last use operand.
3194 unsigned NumUses = MCID.getNumOperands() - MCID.getNumDefs();
3195 return NumUses - 1;
3196}
3197
3198X86::CondCode X86::getCondFromMI(const MachineInstr &MI) {
3199 const MCInstrDesc &MCID = MI.getDesc();
3200 int CondNo = getCondSrcNoFromDesc(MCID);
3201 if (CondNo < 0)
3202 return X86::COND_INVALID;
3203 CondNo += MCID.getNumDefs();
3204 return static_cast<X86::CondCode>(MI.getOperand(i: CondNo).getImm());
3205}
3206
3207X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
3208 return X86::isJCC(Opcode: MI.getOpcode()) ? X86::getCondFromMI(MI)
3209 : X86::COND_INVALID;
3210}
3211
3212X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
3213 return X86::isSETCC(Opcode: MI.getOpcode()) || X86::isSETZUCC(Opcode: MI.getOpcode())
3214 ? X86::getCondFromMI(MI)
3215 : X86::COND_INVALID;
3216}
3217
3218X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
3219 return X86::isCMOVCC(Opcode: MI.getOpcode()) ? X86::getCondFromMI(MI)
3220 : X86::COND_INVALID;
3221}
3222
3223X86::CondCode X86::getCondFromCFCMov(const MachineInstr &MI) {
3224 return X86::isCFCMOVCC(Opcode: MI.getOpcode()) ? X86::getCondFromMI(MI)
3225 : X86::COND_INVALID;
3226}
3227
3228X86::CondCode X86::getCondFromCCMP(const MachineInstr &MI) {
3229 return X86::isCCMPCC(Opcode: MI.getOpcode()) || X86::isCTESTCC(Opcode: MI.getOpcode())
3230 ? X86::getCondFromMI(MI)
3231 : X86::COND_INVALID;
3232}
3233
3234int X86::getCCMPCondFlagsFromCondCode(X86::CondCode CC) {
3235 // CCMP/CTEST has two conditional operands:
3236 // - SCC: source conditonal code (same as CMOV)
3237 // - DCF: destination conditional flags, which has 4 valid bits
3238 //
3239 // +----+----+----+----+
3240 // | OF | SF | ZF | CF |
3241 // +----+----+----+----+
3242 //
3243 // If SCC(source conditional code) evaluates to false, CCMP/CTEST will updates
3244 // the conditional flags by as follows:
3245 //
3246 // OF = DCF.OF
3247 // SF = DCF.SF
3248 // ZF = DCF.ZF
3249 // CF = DCF.CF
3250 // PF = DCF.CF
3251 // AF = 0 (Auxiliary Carry Flag)
3252 //
3253 // Otherwise, the CMP or TEST is executed and it updates the
3254 // CSPAZO flags normally.
3255 //
3256 // NOTE:
3257 // If SCC = P, then SCC evaluates to true regardless of the CSPAZO value.
3258 // If SCC = NP, then SCC evaluates to false regardless of the CSPAZO value.
3259
3260 enum { CF = 1, ZF = 2, SF = 4, OF = 8, PF = CF };
3261
3262 switch (CC) {
3263 default:
3264 llvm_unreachable("Illegal condition code!");
3265 case X86::COND_NO:
3266 case X86::COND_NE:
3267 case X86::COND_GE:
3268 case X86::COND_G:
3269 case X86::COND_AE:
3270 case X86::COND_A:
3271 case X86::COND_NS:
3272 case X86::COND_NP:
3273 return 0;
3274 case X86::COND_O:
3275 return OF;
3276 case X86::COND_B:
3277 case X86::COND_BE:
3278 return CF;
3279 break;
3280 case X86::COND_E:
3281 case X86::COND_LE:
3282 return ZF;
3283 case X86::COND_S:
3284 case X86::COND_L:
3285 return SF;
3286 case X86::COND_P:
3287 return PF;
3288 }
3289}
3290
3291#define GET_X86_NF_TRANSFORM_TABLE
3292#define GET_X86_ND2NONND_TABLE
3293#include "X86GenInstrMapping.inc"
3294
3295static unsigned getNewOpcFromTable(ArrayRef<X86TableEntry> Table,
3296 unsigned Opc) {
3297 const auto I = llvm::lower_bound(Range&: Table, Value&: Opc);
3298 return (I == Table.end() || I->OldOpc != Opc) ? 0U : I->NewOpc;
3299}
3300unsigned X86::getNFVariant(unsigned Opc) {
3301#if defined(EXPENSIVE_CHECKS) && !defined(NDEBUG)
3302 // Make sure the tables are sorted.
3303 static std::atomic<bool> NFTableChecked(false);
3304 if (!NFTableChecked.load(std::memory_order_relaxed)) {
3305 assert(llvm::is_sorted(X86NFTransformTable) &&
3306 "X86NFTransformTable is not sorted!");
3307 NFTableChecked.store(true, std::memory_order_relaxed);
3308 }
3309#endif
3310 return getNewOpcFromTable(Table: X86NFTransformTable, Opc);
3311}
3312
3313unsigned X86::getNFVariantIfClobberRemovable(const MachineInstr &MI,
3314 const TargetRegisterInfo *TRI) {
3315 if (!MI.registerDefIsDead(Reg: X86::EFLAGS, TRI))
3316 return 0;
3317 // For the instructions are ADDrm/ADDmr with relocation, we'll skip the
3318 // optimization for replacing non-NF with NF. This is to keep backward
3319 // compatiblity with old version of linkers without APX relocation type
3320 // support on Linux OS.
3321 if (!X86EnableAPXForRelocation && isAddMemInstrWithRelocation(MI))
3322 return 0;
3323 return X86::getNFVariant(Opc: MI.getOpcode());
3324}
3325
3326unsigned X86::getNonNDVariant(unsigned Opc) {
3327#if defined(EXPENSIVE_CHECKS) && !defined(NDEBUG)
3328 // Make sure the tables are sorted.
3329 static std::atomic<bool> NDTableChecked(false);
3330 if (!NDTableChecked.load(std::memory_order_relaxed)) {
3331 assert(llvm::is_sorted(X86ND2NonNDTable) &&
3332 "X86ND2NonNDTableis not sorted!");
3333 NDTableChecked.store(true, std::memory_order_relaxed);
3334 }
3335#endif
3336 return getNewOpcFromTable(Table: X86ND2NonNDTable, Opc);
3337}
3338
3339/// Return the inverse of the specified condition,
3340/// e.g. turning COND_E to COND_NE.
3341X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3342 switch (CC) {
3343 default:
3344 llvm_unreachable("Illegal condition code!");
3345 case X86::COND_E:
3346 return X86::COND_NE;
3347 case X86::COND_NE:
3348 return X86::COND_E;
3349 case X86::COND_L:
3350 return X86::COND_GE;
3351 case X86::COND_LE:
3352 return X86::COND_G;
3353 case X86::COND_G:
3354 return X86::COND_LE;
3355 case X86::COND_GE:
3356 return X86::COND_L;
3357 case X86::COND_B:
3358 return X86::COND_AE;
3359 case X86::COND_BE:
3360 return X86::COND_A;
3361 case X86::COND_A:
3362 return X86::COND_BE;
3363 case X86::COND_AE:
3364 return X86::COND_B;
3365 case X86::COND_S:
3366 return X86::COND_NS;
3367 case X86::COND_NS:
3368 return X86::COND_S;
3369 case X86::COND_P:
3370 return X86::COND_NP;
3371 case X86::COND_NP:
3372 return X86::COND_P;
3373 case X86::COND_O:
3374 return X86::COND_NO;
3375 case X86::COND_NO:
3376 return X86::COND_O;
3377 case X86::COND_NE_OR_P:
3378 return X86::COND_E_AND_NP;
3379 case X86::COND_E_AND_NP:
3380 return X86::COND_NE_OR_P;
3381 }
3382}
3383
3384/// Assuming the flags are set by MI(a,b), return the condition code if we
3385/// modify the instructions such that flags are set by MI(b,a).
3386static X86::CondCode getSwappedCondition(X86::CondCode CC) {
3387 switch (CC) {
3388 default:
3389 return X86::COND_INVALID;
3390 case X86::COND_E:
3391 return X86::COND_E;
3392 case X86::COND_NE:
3393 return X86::COND_NE;
3394 case X86::COND_L:
3395 return X86::COND_G;
3396 case X86::COND_LE:
3397 return X86::COND_GE;
3398 case X86::COND_G:
3399 return X86::COND_L;
3400 case X86::COND_GE:
3401 return X86::COND_LE;
3402 case X86::COND_B:
3403 return X86::COND_A;
3404 case X86::COND_BE:
3405 return X86::COND_AE;
3406 case X86::COND_A:
3407 return X86::COND_B;
3408 case X86::COND_AE:
3409 return X86::COND_BE;
3410 }
3411}
3412
3413std::pair<X86::CondCode, bool>
3414X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
3415 X86::CondCode CC = X86::COND_INVALID;
3416 bool NeedSwap = false;
3417 switch (Predicate) {
3418 default:
3419 break;
3420 // Floating-point Predicates
3421 case CmpInst::FCMP_UEQ:
3422 CC = X86::COND_E;
3423 break;
3424 case CmpInst::FCMP_OLT:
3425 NeedSwap = true;
3426 [[fallthrough]];
3427 case CmpInst::FCMP_OGT:
3428 CC = X86::COND_A;
3429 break;
3430 case CmpInst::FCMP_OLE:
3431 NeedSwap = true;
3432 [[fallthrough]];
3433 case CmpInst::FCMP_OGE:
3434 CC = X86::COND_AE;
3435 break;
3436 case CmpInst::FCMP_UGT:
3437 NeedSwap = true;
3438 [[fallthrough]];
3439 case CmpInst::FCMP_ULT:
3440 CC = X86::COND_B;
3441 break;
3442 case CmpInst::FCMP_UGE:
3443 NeedSwap = true;
3444 [[fallthrough]];
3445 case CmpInst::FCMP_ULE:
3446 CC = X86::COND_BE;
3447 break;
3448 case CmpInst::FCMP_ONE:
3449 CC = X86::COND_NE;
3450 break;
3451 case CmpInst::FCMP_UNO:
3452 CC = X86::COND_P;
3453 break;
3454 case CmpInst::FCMP_ORD:
3455 CC = X86::COND_NP;
3456 break;
3457 case CmpInst::FCMP_OEQ:
3458 [[fallthrough]];
3459 case CmpInst::FCMP_UNE:
3460 CC = X86::COND_INVALID;
3461 break;
3462
3463 // Integer Predicates
3464 case CmpInst::ICMP_EQ:
3465 CC = X86::COND_E;
3466 break;
3467 case CmpInst::ICMP_NE:
3468 CC = X86::COND_NE;
3469 break;
3470 case CmpInst::ICMP_UGT:
3471 CC = X86::COND_A;
3472 break;
3473 case CmpInst::ICMP_UGE:
3474 CC = X86::COND_AE;
3475 break;
3476 case CmpInst::ICMP_ULT:
3477 CC = X86::COND_B;
3478 break;
3479 case CmpInst::ICMP_ULE:
3480 CC = X86::COND_BE;
3481 break;
3482 case CmpInst::ICMP_SGT:
3483 CC = X86::COND_G;
3484 break;
3485 case CmpInst::ICMP_SGE:
3486 CC = X86::COND_GE;
3487 break;
3488 case CmpInst::ICMP_SLT:
3489 CC = X86::COND_L;
3490 break;
3491 case CmpInst::ICMP_SLE:
3492 CC = X86::COND_LE;
3493 break;
3494 }
3495
3496 return std::make_pair(x&: CC, y&: NeedSwap);
3497}
3498
3499/// Return a cmov opcode for the given register size in bytes, and operand type.
3500unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand,
3501 bool HasNDD) {
3502 switch (RegBytes) {
3503 default:
3504 llvm_unreachable("Illegal register size!");
3505#define GET_ND_IF_ENABLED(OPC) (HasNDD ? OPC##_ND : OPC)
3506 case 2:
3507 return HasMemoryOperand ? GET_ND_IF_ENABLED(X86::CMOV16rm)
3508 : GET_ND_IF_ENABLED(X86::CMOV16rr);
3509 case 4:
3510 return HasMemoryOperand ? GET_ND_IF_ENABLED(X86::CMOV32rm)
3511 : GET_ND_IF_ENABLED(X86::CMOV32rr);
3512 case 8:
3513 return HasMemoryOperand ? GET_ND_IF_ENABLED(X86::CMOV64rm)
3514 : GET_ND_IF_ENABLED(X86::CMOV64rr);
3515 }
3516}
3517
3518unsigned X86::getMOVriOpcode(bool Use64BitReg, int64_t Imm) {
3519 if (!Use64BitReg)
3520 return X86::MOV32ri;
3521
3522 if (isUInt<32>(x: Imm))
3523 return X86::MOV32ri64;
3524 if (isInt<32>(x: Imm))
3525 return X86::MOV64ri32;
3526 return X86::MOV64ri;
3527}
3528
3529/// Get the VPCMP immediate for the given condition.
3530unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
3531 switch (CC) {
3532 default:
3533 llvm_unreachable("Unexpected SETCC condition");
3534 case ISD::SETNE:
3535 return 4;
3536 case ISD::SETEQ:
3537 return 0;
3538 case ISD::SETULT:
3539 case ISD::SETLT:
3540 return 1;
3541 case ISD::SETUGT:
3542 case ISD::SETGT:
3543 return 6;
3544 case ISD::SETUGE:
3545 case ISD::SETGE:
3546 return 5;
3547 case ISD::SETULE:
3548 case ISD::SETLE:
3549 return 2;
3550 }
3551}
3552
3553/// Get the VPCMP immediate if the operands are swapped.
3554unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
3555 switch (Imm) {
3556 default:
3557 llvm_unreachable("Unreachable!");
3558 case 0x01:
3559 Imm = 0x06;
3560 break; // LT -> NLE
3561 case 0x02:
3562 Imm = 0x05;
3563 break; // LE -> NLT
3564 case 0x05:
3565 Imm = 0x02;
3566 break; // NLT -> LE
3567 case 0x06:
3568 Imm = 0x01;
3569 break; // NLE -> LT
3570 case 0x00: // EQ
3571 case 0x03: // FALSE
3572 case 0x04: // NE
3573 case 0x07: // TRUE
3574 break;
3575 }
3576
3577 return Imm;
3578}
3579
3580/// Get the VPCOM immediate if the operands are swapped.
3581unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
3582 switch (Imm) {
3583 default:
3584 llvm_unreachable("Unreachable!");
3585 case 0x00:
3586 Imm = 0x02;
3587 break; // LT -> GT
3588 case 0x01:
3589 Imm = 0x03;
3590 break; // LE -> GE
3591 case 0x02:
3592 Imm = 0x00;
3593 break; // GT -> LT
3594 case 0x03:
3595 Imm = 0x01;
3596 break; // GE -> LE
3597 case 0x04: // EQ
3598 case 0x05: // NE
3599 case 0x06: // FALSE
3600 case 0x07: // TRUE
3601 break;
3602 }
3603
3604 return Imm;
3605}
3606
3607/// Get the VCMP immediate if the operands are swapped.
3608unsigned X86::getSwappedVCMPImm(unsigned Imm) {
3609 // Only need the lower 2 bits to distinquish.
3610 switch (Imm & 0x3) {
3611 default:
3612 llvm_unreachable("Unreachable!");
3613 case 0x00:
3614 case 0x03:
3615 // EQ/NE/TRUE/FALSE/ORD/UNORD don't change immediate when commuted.
3616 break;
3617 case 0x01:
3618 case 0x02:
3619 // Need to toggle bits 3:0. Bit 4 stays the same.
3620 Imm ^= 0xf;
3621 break;
3622 }
3623
3624 return Imm;
3625}
3626
3627unsigned X86::getVectorRegisterWidth(const MCOperandInfo &Info) {
3628 if (Info.RegClass == X86::VR128RegClassID ||
3629 Info.RegClass == X86::VR128XRegClassID)
3630 return 128;
3631 if (Info.RegClass == X86::VR256RegClassID ||
3632 Info.RegClass == X86::VR256XRegClassID)
3633 return 256;
3634 if (Info.RegClass == X86::VR512RegClassID)
3635 return 512;
3636 llvm_unreachable("Unknown register class!");
3637}
3638
3639/// Return true if the Reg is X87 register.
3640static bool isX87Reg(Register Reg) {
3641 return (Reg == X86::FPCW || Reg == X86::FPSW ||
3642 (Reg >= X86::ST0 && Reg <= X86::ST7));
3643}
3644
3645/// check if the instruction is X87 instruction
3646bool X86::isX87Instruction(MachineInstr &MI) {
3647 // Call and inlineasm defs X87 register, so we special case it here because
3648 // otherwise calls are incorrectly flagged as x87 instructions
3649 // as a result.
3650 if (MI.isCall() || MI.isInlineAsm())
3651 return false;
3652 for (const MachineOperand &MO : MI.operands()) {
3653 if (!MO.isReg())
3654 continue;
3655 if (isX87Reg(Reg: MO.getReg()))
3656 return true;
3657 }
3658 return false;
3659}
3660
3661int X86::getFirstAddrOperandIdx(const MachineInstr &MI) {
3662 auto IsMemOp = [](const MCOperandInfo &OpInfo) {
3663 return OpInfo.OperandType == MCOI::OPERAND_MEMORY;
3664 };
3665
3666 const MCInstrDesc &Desc = MI.getDesc();
3667
3668 // Directly invoke the MC-layer routine for real (i.e., non-pseudo)
3669 // instructions (fast case).
3670 if (!X86II::isPseudo(TSFlags: Desc.TSFlags)) {
3671 int MemRefIdx = X86II::getMemoryOperandIdx(Desc);
3672 if (MemRefIdx >= 0)
3673 return MemRefIdx;
3674#ifdef EXPENSIVE_CHECKS
3675 assert(none_of(Desc.operands(), IsMemOp) &&
3676 "Got false negative from X86II::getMemoryOperandIdx()!");
3677#endif
3678 return -1;
3679 }
3680
3681 // Otherwise, handle pseudo instructions by examining the type of their
3682 // operands (slow case). An instruction cannot have a memory reference if it
3683 // has fewer than AddrNumOperands (= 5) explicit operands.
3684 unsigned NumOps = Desc.getNumOperands();
3685 if (NumOps < X86::AddrNumOperands) {
3686#ifdef EXPENSIVE_CHECKS
3687 assert(none_of(Desc.operands(), IsMemOp) &&
3688 "Expected no operands to have OPERAND_MEMORY type!");
3689#endif
3690 return -1;
3691 }
3692
3693 // The first operand with type OPERAND_MEMORY indicates the start of a memory
3694 // reference. We expect the following AddrNumOperand-1 operands to also have
3695 // OPERAND_MEMORY type.
3696 for (unsigned I = 0, E = NumOps - X86::AddrNumOperands; I != E; ++I) {
3697 if (IsMemOp(Desc.operands()[I])) {
3698#ifdef EXPENSIVE_CHECKS
3699 assert(std::all_of(Desc.operands().begin() + I,
3700 Desc.operands().begin() + I + X86::AddrNumOperands,
3701 IsMemOp) &&
3702 "Expected all five operands in the memory reference to have "
3703 "OPERAND_MEMORY type!");
3704#endif
3705 return I;
3706 }
3707 }
3708
3709 return -1;
3710}
3711
3712const Constant *X86::getConstantFromPool(const MachineInstr &MI,
3713 unsigned OpNo) {
3714 assert(MI.getNumOperands() >= (OpNo + X86::AddrNumOperands) &&
3715 "Unexpected number of operands!");
3716
3717 const MachineOperand &Index = MI.getOperand(i: OpNo + X86::AddrIndexReg);
3718 if (!Index.isReg() || Index.getReg() != X86::NoRegister)
3719 return nullptr;
3720
3721 const MachineOperand &Disp = MI.getOperand(i: OpNo + X86::AddrDisp);
3722 if (!Disp.isCPI() || Disp.getOffset() != 0)
3723 return nullptr;
3724
3725 ArrayRef<MachineConstantPoolEntry> Constants =
3726 MI.getParent()->getParent()->getConstantPool()->getConstants();
3727 const MachineConstantPoolEntry &ConstantEntry = Constants[Disp.getIndex()];
3728
3729 // Bail if this is a machine constant pool entry, we won't be able to dig out
3730 // anything useful.
3731 if (ConstantEntry.isMachineConstantPoolEntry())
3732 return nullptr;
3733
3734 return ConstantEntry.Val.ConstVal;
3735}
3736
3737bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
3738 switch (MI.getOpcode()) {
3739 case X86::TCRETURNdi:
3740 case X86::TCRETURNri:
3741 case X86::TCRETURNmi:
3742 case X86::TCRETURNdi64:
3743 case X86::TCRETURNri64:
3744 case X86::TCRETURNri64_ImpCall:
3745 case X86::TCRETURNmi64:
3746 return true;
3747 default:
3748 return false;
3749 }
3750}
3751
3752bool X86InstrInfo::canMakeTailCallConditional(
3753 SmallVectorImpl<MachineOperand> &BranchCond,
3754 const MachineInstr &TailCall) const {
3755
3756 const MachineFunction *MF = TailCall.getMF();
3757
3758 if (MF->getTarget().getCodeModel() == CodeModel::Kernel) {
3759 // Kernel patches thunk calls in runtime, these should never be conditional.
3760 const MachineOperand &Target = TailCall.getOperand(i: 0);
3761 if (Target.isSymbol()) {
3762 StringRef Symbol(Target.getSymbolName());
3763 // this is currently only relevant to r11/kernel indirect thunk.
3764 if (Symbol == "__x86_indirect_thunk_r11")
3765 return false;
3766 }
3767 }
3768
3769 if (TailCall.getOpcode() != X86::TCRETURNdi &&
3770 TailCall.getOpcode() != X86::TCRETURNdi64) {
3771 // Only direct calls can be done with a conditional branch.
3772 return false;
3773 }
3774
3775 if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
3776 // Conditional tail calls confuse the Win64 unwinder.
3777 return false;
3778 }
3779
3780 assert(BranchCond.size() == 1);
3781 if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
3782 // Can't make a conditional tail call with this condition.
3783 return false;
3784 }
3785
3786 const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3787 if (X86FI->getTCReturnAddrDelta() != 0 ||
3788 TailCall.getOperand(i: 1).getImm() != 0) {
3789 // A conditional tail call cannot do any stack adjustment.
3790 return false;
3791 }
3792
3793 return true;
3794}
3795
3796void X86InstrInfo::replaceBranchWithTailCall(
3797 MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
3798 const MachineInstr &TailCall) const {
3799 assert(canMakeTailCallConditional(BranchCond, TailCall));
3800
3801 MachineBasicBlock::iterator I = MBB.end();
3802 while (I != MBB.begin()) {
3803 --I;
3804 if (I->isDebugInstr())
3805 continue;
3806 if (!I->isBranch())
3807 assert(0 && "Can't find the branch to replace!");
3808
3809 X86::CondCode CC = X86::getCondFromBranch(MI: *I);
3810 assert(BranchCond.size() == 1);
3811 if (CC != BranchCond[0].getImm())
3812 continue;
3813
3814 break;
3815 }
3816
3817 unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
3818 : X86::TCRETURNdi64cc;
3819
3820 auto MIB = BuildMI(BB&: MBB, I, MIMD: MBB.findDebugLoc(MBBI: I), MCID: get(Opcode: Opc));
3821 MIB->addOperand(Op: TailCall.getOperand(i: 0)); // Destination.
3822 MIB.addImm(Val: 0); // Stack offset (not used).
3823 MIB->addOperand(Op: BranchCond[0]); // Condition.
3824 MIB.copyImplicitOps(OtherMI: TailCall); // Regmask and (imp-used) parameters.
3825
3826 // Add implicit uses and defs of all live regs potentially clobbered by the
3827 // call. This way they still appear live across the call.
3828 LivePhysRegs LiveRegs(getRegisterInfo());
3829 LiveRegs.addLiveOuts(MBB);
3830 SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
3831 LiveRegs.stepForward(MI: *MIB, Clobbers);
3832 for (const auto &C : Clobbers) {
3833 MIB.addReg(RegNo: C.first, Flags: RegState::Implicit);
3834 MIB.addReg(RegNo: C.first, Flags: RegState::Implicit | RegState::Define);
3835 }
3836
3837 I->eraseFromParent();
3838}
3839
3840// Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
3841// not be a fallthrough MBB now due to layout changes). Return nullptr if the
3842// fallthrough MBB cannot be identified.
3843static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
3844 MachineBasicBlock *TBB) {
3845 // Look for non-EHPad successors other than TBB. If we find exactly one, it
3846 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
3847 // and fallthrough MBB. If we find more than one, we cannot identify the
3848 // fallthrough MBB and should return nullptr.
3849 MachineBasicBlock *FallthroughBB = nullptr;
3850 for (MachineBasicBlock *Succ : MBB->successors()) {
3851 if (Succ->isEHPad() || (Succ == TBB && FallthroughBB))
3852 continue;
3853 // Return a nullptr if we found more than one fallthrough successor.
3854 if (FallthroughBB && FallthroughBB != TBB)
3855 return nullptr;
3856 FallthroughBB = Succ;
3857 }
3858 return FallthroughBB;
3859}
3860
3861bool X86InstrInfo::analyzeBranchImpl(
3862 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
3863 SmallVectorImpl<MachineOperand> &Cond,
3864 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
3865
3866 // Start from the bottom of the block and work up, examining the
3867 // terminator instructions.
3868 MachineBasicBlock::iterator I = MBB.end();
3869 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
3870 while (I != MBB.begin()) {
3871 --I;
3872 if (I->isDebugInstr())
3873 continue;
3874
3875 // Working from the bottom, when we see a non-terminator instruction, we're
3876 // done.
3877 if (!isUnpredicatedTerminator(MI: *I))
3878 break;
3879
3880 // A terminator that isn't a branch can't easily be handled by this
3881 // analysis.
3882 if (!I->isBranch())
3883 return true;
3884
3885 // Handle unconditional branches.
3886 if (I->getOpcode() == X86::JMP_1) {
3887 UnCondBrIter = I;
3888
3889 if (!AllowModify) {
3890 TBB = I->getOperand(i: 0).getMBB();
3891 continue;
3892 }
3893
3894 // If the block has any instructions after a JMP, delete them.
3895 MBB.erase(I: std::next(x: I), E: MBB.end());
3896
3897 Cond.clear();
3898 FBB = nullptr;
3899
3900 // Delete the JMP if it's equivalent to a fall-through.
3901 if (MBB.isLayoutSuccessor(MBB: I->getOperand(i: 0).getMBB())) {
3902 TBB = nullptr;
3903 I->eraseFromParent();
3904 I = MBB.end();
3905 UnCondBrIter = MBB.end();
3906 continue;
3907 }
3908
3909 // TBB is used to indicate the unconditional destination.
3910 TBB = I->getOperand(i: 0).getMBB();
3911 continue;
3912 }
3913
3914 // Handle conditional branches.
3915 X86::CondCode BranchCode = X86::getCondFromBranch(MI: *I);
3916 if (BranchCode == X86::COND_INVALID)
3917 return true; // Can't handle indirect branch.
3918
3919 // In practice we should never have an undef eflags operand, if we do
3920 // abort here as we are not prepared to preserve the flag.
3921 if (I->findRegisterUseOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr)->isUndef())
3922 return true;
3923
3924 // Working from the bottom, handle the first conditional branch.
3925 if (Cond.empty()) {
3926 FBB = TBB;
3927 TBB = I->getOperand(i: 0).getMBB();
3928 Cond.push_back(Elt: MachineOperand::CreateImm(Val: BranchCode));
3929 CondBranches.push_back(Elt: &*I);
3930 continue;
3931 }
3932
3933 // Handle subsequent conditional branches. Only handle the case where all
3934 // conditional branches branch to the same destination and their condition
3935 // opcodes fit one of the special multi-branch idioms.
3936 assert(Cond.size() == 1);
3937 assert(TBB);
3938
3939 // If the conditions are the same, we can leave them alone.
3940 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3941 auto NewTBB = I->getOperand(i: 0).getMBB();
3942 if (OldBranchCode == BranchCode && TBB == NewTBB)
3943 continue;
3944
3945 // If they differ, see if they fit one of the known patterns. Theoretically,
3946 // we could handle more patterns here, but we shouldn't expect to see them
3947 // if instruction selection has done a reasonable job.
3948 if (TBB == NewTBB &&
3949 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
3950 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
3951 BranchCode = X86::COND_NE_OR_P;
3952 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
3953 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
3954 if (NewTBB != (FBB ? FBB : getFallThroughMBB(MBB: &MBB, TBB)))
3955 return true;
3956
3957 // X86::COND_E_AND_NP usually has two different branch destinations.
3958 //
3959 // JP B1
3960 // JE B2
3961 // JMP B1
3962 // B1:
3963 // B2:
3964 //
3965 // Here this condition branches to B2 only if NP && E. It has another
3966 // equivalent form:
3967 //
3968 // JNE B1
3969 // JNP B2
3970 // JMP B1
3971 // B1:
3972 // B2:
3973 //
3974 // Similarly it branches to B2 only if E && NP. That is why this condition
3975 // is named with COND_E_AND_NP.
3976 BranchCode = X86::COND_E_AND_NP;
3977 } else
3978 return true;
3979
3980 // Update the MachineOperand.
3981 Cond[0].setImm(BranchCode);
3982 CondBranches.push_back(Elt: &*I);
3983 }
3984
3985 return false;
3986}
3987
3988bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
3989 MachineBasicBlock *&TBB,
3990 MachineBasicBlock *&FBB,
3991 SmallVectorImpl<MachineOperand> &Cond,
3992 bool AllowModify) const {
3993 SmallVector<MachineInstr *, 4> CondBranches;
3994 return analyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
3995}
3996
3997static int getJumpTableIndexFromAddr(const MachineInstr &MI) {
3998 int MemRefBegin = X86II::getMemoryOperandIdx(Desc: MI.getDesc());
3999 assert(MemRefBegin >= 0 && "Expected a memory operand");
4000
4001 const MachineOperand &MO = MI.getOperand(i: MemRefBegin + X86::AddrDisp);
4002 if (!MO.isJTI())
4003 return -1;
4004
4005 return MO.getIndex();
4006}
4007
4008static int getJumpTableIndexFromReg(const MachineRegisterInfo &MRI,
4009 Register Reg) {
4010 if (!Reg.isVirtual())
4011 return -1;
4012 MachineInstr *MI = MRI.getUniqueVRegDef(Reg);
4013 if (MI == nullptr)
4014 return -1;
4015 unsigned Opcode = MI->getOpcode();
4016 if (Opcode != X86::LEA64r && Opcode != X86::LEA32r)
4017 return -1;
4018 return getJumpTableIndexFromAddr(MI: *MI);
4019}
4020
4021int X86InstrInfo::getJumpTableIndex(const MachineInstr &MI) const {
4022 unsigned Opcode = MI.getOpcode();
4023 // Switch-jump pattern for non-PIC code looks like:
4024 // JMP64m $noreg, 8, %X, %jump-table.X, $noreg
4025 if (Opcode == X86::JMP64m || Opcode == X86::JMP32m) {
4026 return getJumpTableIndexFromAddr(MI);
4027 }
4028 // The pattern for PIC code looks like:
4029 // %0 = LEA64r $rip, 1, $noreg, %jump-table.X
4030 // %1 = MOVSX64rm32 %0, 4, XX, 0, $noreg
4031 // %2 = ADD64rr %1, %0
4032 // JMP64r %2
4033 if (Opcode == X86::JMP64r || Opcode == X86::JMP32r) {
4034 Register Reg = MI.getOperand(i: 0).getReg();
4035 if (!Reg.isVirtual())
4036 return -1;
4037 const MachineFunction &MF = *MI.getParent()->getParent();
4038 const MachineRegisterInfo &MRI = MF.getRegInfo();
4039 MachineInstr *Add = MRI.getUniqueVRegDef(Reg);
4040 if (Add == nullptr)
4041 return -1;
4042 if (Add->getOpcode() != X86::ADD64rr && Add->getOpcode() != X86::ADD32rr)
4043 return -1;
4044 int JTI1 = getJumpTableIndexFromReg(MRI, Reg: Add->getOperand(i: 1).getReg());
4045 if (JTI1 >= 0)
4046 return JTI1;
4047 int JTI2 = getJumpTableIndexFromReg(MRI, Reg: Add->getOperand(i: 2).getReg());
4048 if (JTI2 >= 0)
4049 return JTI2;
4050 }
4051 return -1;
4052}
4053
4054bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
4055 MachineBranchPredicate &MBP,
4056 bool AllowModify) const {
4057 using namespace std::placeholders;
4058
4059 SmallVector<MachineOperand, 4> Cond;
4060 SmallVector<MachineInstr *, 4> CondBranches;
4061 if (analyzeBranchImpl(MBB, TBB&: MBP.TrueDest, FBB&: MBP.FalseDest, Cond, CondBranches,
4062 AllowModify))
4063 return true;
4064
4065 if (Cond.size() != 1)
4066 return true;
4067
4068 assert(MBP.TrueDest && "expected!");
4069
4070 if (!MBP.FalseDest)
4071 MBP.FalseDest = MBB.getNextNode();
4072
4073 const TargetRegisterInfo *TRI = &getRegisterInfo();
4074
4075 MachineInstr *ConditionDef = nullptr;
4076 bool SingleUseCondition = true;
4077
4078 for (MachineInstr &MI : llvm::drop_begin(RangeOrContainer: llvm::reverse(C&: MBB))) {
4079 if (MI.modifiesRegister(Reg: X86::EFLAGS, TRI)) {
4080 ConditionDef = &MI;
4081 break;
4082 }
4083
4084 if (MI.readsRegister(Reg: X86::EFLAGS, TRI))
4085 SingleUseCondition = false;
4086 }
4087
4088 if (!ConditionDef)
4089 return true;
4090
4091 if (SingleUseCondition) {
4092 for (auto *Succ : MBB.successors())
4093 if (Succ->isLiveIn(Reg: X86::EFLAGS))
4094 SingleUseCondition = false;
4095 }
4096
4097 MBP.ConditionDef = ConditionDef;
4098 MBP.SingleUseCondition = SingleUseCondition;
4099
4100 // Currently we only recognize the simple pattern:
4101 //
4102 // test %reg, %reg
4103 // je %label
4104 //
4105 const unsigned TestOpcode =
4106 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4107
4108 if (ConditionDef->getOpcode() == TestOpcode &&
4109 ConditionDef->getNumOperands() == 3 &&
4110 ConditionDef->getOperand(i: 0).isIdenticalTo(Other: ConditionDef->getOperand(i: 1)) &&
4111 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4112 MBP.LHS = ConditionDef->getOperand(i: 0);
4113 MBP.RHS = MachineOperand::CreateImm(Val: 0);
4114 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4115 ? MachineBranchPredicate::PRED_NE
4116 : MachineBranchPredicate::PRED_EQ;
4117 return false;
4118 }
4119
4120 return true;
4121}
4122
4123unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
4124 int *BytesRemoved) const {
4125 assert(!BytesRemoved && "code size not handled");
4126
4127 MachineBasicBlock::iterator I = MBB.end();
4128 unsigned Count = 0;
4129
4130 while (I != MBB.begin()) {
4131 --I;
4132 if (I->isDebugInstr())
4133 continue;
4134 if (I->getOpcode() != X86::JMP_1 &&
4135 X86::getCondFromBranch(MI: *I) == X86::COND_INVALID)
4136 break;
4137 // Remove the branch.
4138 I->eraseFromParent();
4139 I = MBB.end();
4140 ++Count;
4141 }
4142
4143 return Count;
4144}
4145
4146unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
4147 MachineBasicBlock *TBB,
4148 MachineBasicBlock *FBB,
4149 ArrayRef<MachineOperand> Cond,
4150 const DebugLoc &DL, int *BytesAdded) const {
4151 // Shouldn't be a fall through.
4152 assert(TBB && "insertBranch must not be told to insert a fallthrough");
4153 assert((Cond.size() == 1 || Cond.size() == 0) &&
4154 "X86 branch conditions have one component!");
4155 assert(!BytesAdded && "code size not handled");
4156
4157 if (Cond.empty()) {
4158 // Unconditional branch?
4159 assert(!FBB && "Unconditional branch with multiple successors!");
4160 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JMP_1)).addMBB(MBB: TBB);
4161 return 1;
4162 }
4163
4164 // If FBB is null, it is implied to be a fall-through block.
4165 bool FallThru = FBB == nullptr;
4166
4167 // Conditional branch.
4168 unsigned Count = 0;
4169 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4170 switch (CC) {
4171 case X86::COND_NE_OR_P:
4172 // Synthesize NE_OR_P with two branches.
4173 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JCC_1)).addMBB(MBB: TBB).addImm(Val: X86::COND_NE);
4174 ++Count;
4175 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JCC_1)).addMBB(MBB: TBB).addImm(Val: X86::COND_P);
4176 ++Count;
4177 break;
4178 case X86::COND_E_AND_NP:
4179 // Use the next block of MBB as FBB if it is null.
4180 if (FBB == nullptr) {
4181 FBB = getFallThroughMBB(MBB: &MBB, TBB);
4182 assert(FBB && "MBB cannot be the last block in function when the false "
4183 "body is a fall-through.");
4184 }
4185 // Synthesize COND_E_AND_NP with two branches.
4186 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JCC_1)).addMBB(MBB: FBB).addImm(Val: X86::COND_NE);
4187 ++Count;
4188 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JCC_1)).addMBB(MBB: TBB).addImm(Val: X86::COND_NP);
4189 ++Count;
4190 break;
4191 default: {
4192 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JCC_1)).addMBB(MBB: TBB).addImm(Val: CC);
4193 ++Count;
4194 }
4195 }
4196 if (!FallThru) {
4197 // Two-way Conditional branch. Insert the second branch.
4198 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JMP_1)).addMBB(MBB: FBB);
4199 ++Count;
4200 }
4201 return Count;
4202}
4203
4204bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
4205 ArrayRef<MachineOperand> Cond,
4206 Register DstReg, Register TrueReg,
4207 Register FalseReg, int &CondCycles,
4208 int &TrueCycles, int &FalseCycles) const {
4209 // Not all subtargets have cmov instructions.
4210 if (!Subtarget.canUseCMOV())
4211 return false;
4212 if (Cond.size() != 1)
4213 return false;
4214 // We cannot do the composite conditions, at least not in SSA form.
4215 if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
4216 return false;
4217
4218 // Check register classes.
4219 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4220 const TargetRegisterClass *RC =
4221 RI.getCommonSubClass(A: MRI.getRegClass(Reg: TrueReg), B: MRI.getRegClass(Reg: FalseReg));
4222 if (!RC)
4223 return false;
4224
4225 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4226 if (X86::GR16RegClass.hasSubClassEq(RC) ||
4227 X86::GR32RegClass.hasSubClassEq(RC) ||
4228 X86::GR64RegClass.hasSubClassEq(RC)) {
4229 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4230 // Bridge. Probably Ivy Bridge as well.
4231 CondCycles = 2;
4232 TrueCycles = 2;
4233 FalseCycles = 2;
4234 return true;
4235 }
4236
4237 // Can't do vectors.
4238 return false;
4239}
4240
4241void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
4242 MachineBasicBlock::iterator I,
4243 const DebugLoc &DL, Register DstReg,
4244 ArrayRef<MachineOperand> Cond, Register TrueReg,
4245 Register FalseReg) const {
4246 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4247 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
4248 const TargetRegisterClass &RC = *MRI.getRegClass(Reg: DstReg);
4249 assert(Cond.size() == 1 && "Invalid Cond array");
4250 unsigned Opc =
4251 X86::getCMovOpcode(RegBytes: TRI.getRegSizeInBits(RC) / 8,
4252 HasMemoryOperand: false /*HasMemoryOperand*/, HasNDD: Subtarget.hasNDD());
4253 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Opc), DestReg: DstReg)
4254 .addReg(RegNo: FalseReg)
4255 .addReg(RegNo: TrueReg)
4256 .addImm(Val: Cond[0].getImm());
4257}
4258
4259/// Test if the given register is a physical h register.
4260static bool isHReg(Register Reg) {
4261 return X86::GR8_ABCD_HRegClass.contains(Reg);
4262}
4263
4264// Try and copy between VR128/VR64 and GR64 registers.
4265static unsigned CopyToFromAsymmetricReg(Register DestReg, Register SrcReg,
4266 const X86Subtarget &Subtarget) {
4267 bool HasAVX = Subtarget.hasAVX();
4268 bool HasAVX512 = Subtarget.hasAVX512();
4269 bool HasEGPR = Subtarget.hasEGPR();
4270
4271 // SrcReg(MaskReg) -> DestReg(GR64)
4272 // SrcReg(MaskReg) -> DestReg(GR32)
4273
4274 // All KMASK RegClasses hold the same k registers, can be tested against
4275 // anyone.
4276 if (X86::VK16RegClass.contains(Reg: SrcReg)) {
4277 if (X86::GR64RegClass.contains(Reg: DestReg)) {
4278 assert(Subtarget.hasBWI());
4279 return HasEGPR ? X86::KMOVQrk_EVEX : X86::KMOVQrk;
4280 }
4281 if (X86::GR32RegClass.contains(Reg: DestReg))
4282 return Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVDrk_EVEX : X86::KMOVDrk)
4283 : (HasEGPR ? X86::KMOVWrk_EVEX : X86::KMOVWrk);
4284 }
4285
4286 // SrcReg(GR64) -> DestReg(MaskReg)
4287 // SrcReg(GR32) -> DestReg(MaskReg)
4288
4289 // All KMASK RegClasses hold the same k registers, can be tested against
4290 // anyone.
4291 if (X86::VK16RegClass.contains(Reg: DestReg)) {
4292 if (X86::GR64RegClass.contains(Reg: SrcReg)) {
4293 assert(Subtarget.hasBWI());
4294 return HasEGPR ? X86::KMOVQkr_EVEX : X86::KMOVQkr;
4295 }
4296 if (X86::GR32RegClass.contains(Reg: SrcReg))
4297 return Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVDkr_EVEX : X86::KMOVDkr)
4298 : (HasEGPR ? X86::KMOVWkr_EVEX : X86::KMOVWkr);
4299 }
4300
4301 // SrcReg(VR128) -> DestReg(GR64)
4302 // SrcReg(VR64) -> DestReg(GR64)
4303 // SrcReg(GR64) -> DestReg(VR128)
4304 // SrcReg(GR64) -> DestReg(VR64)
4305
4306 if (X86::GR64RegClass.contains(Reg: DestReg)) {
4307 if (X86::VR128XRegClass.contains(Reg: SrcReg))
4308 // Copy from a VR128 register to a GR64 register.
4309 return HasAVX512 ? X86::VMOVPQIto64Zrr
4310 : HasAVX ? X86::VMOVPQIto64rr
4311 : X86::MOVPQIto64rr;
4312 if (X86::VR64RegClass.contains(Reg: SrcReg))
4313 // Copy from a VR64 register to a GR64 register.
4314 return X86::MMX_MOVD64from64rr;
4315 } else if (X86::GR64RegClass.contains(Reg: SrcReg)) {
4316 // Copy from a GR64 register to a VR128 register.
4317 if (X86::VR128XRegClass.contains(Reg: DestReg))
4318 return HasAVX512 ? X86::VMOV64toPQIZrr
4319 : HasAVX ? X86::VMOV64toPQIrr
4320 : X86::MOV64toPQIrr;
4321 // Copy from a GR64 register to a VR64 register.
4322 if (X86::VR64RegClass.contains(Reg: DestReg))
4323 return X86::MMX_MOVD64to64rr;
4324 }
4325
4326 // SrcReg(VR128) -> DestReg(GR32)
4327 // SrcReg(GR32) -> DestReg(VR128)
4328
4329 if (X86::GR32RegClass.contains(Reg: DestReg) &&
4330 X86::VR128XRegClass.contains(Reg: SrcReg))
4331 // Copy from a VR128 register to a GR32 register.
4332 return HasAVX512 ? X86::VMOVPDI2DIZrr
4333 : HasAVX ? X86::VMOVPDI2DIrr
4334 : X86::MOVPDI2DIrr;
4335
4336 if (X86::VR128XRegClass.contains(Reg: DestReg) &&
4337 X86::GR32RegClass.contains(Reg: SrcReg))
4338 // Copy from a GR32 register to a VR128 register.
4339 return HasAVX512 ? X86::VMOVDI2PDIZrr
4340 : HasAVX ? X86::VMOVDI2PDIrr
4341 : X86::MOVDI2PDIrr;
4342
4343 return 0;
4344}
4345
4346void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4347 MachineBasicBlock::iterator MI,
4348 const DebugLoc &DL, Register DestReg,
4349 Register SrcReg, bool KillSrc,
4350 bool RenamableDest, bool RenamableSrc) const {
4351 // First deal with the normal symmetric copies.
4352 bool HasAVX = Subtarget.hasAVX();
4353 bool HasVLX = Subtarget.hasVLX();
4354 bool HasEGPR = Subtarget.hasEGPR();
4355 unsigned Opc = 0;
4356 if (X86::GR64RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4357 Opc = X86::MOV64rr;
4358 else if (X86::GR32RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4359 Opc = X86::MOV32rr;
4360 else if (X86::GR16RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4361 Opc = X86::MOV16rr;
4362 else if (X86::GR8RegClass.contains(Reg1: DestReg, Reg2: SrcReg)) {
4363 // Copying to or from a physical H register on x86-64 requires a NOREX
4364 // move. Otherwise use a normal move.
4365 if ((isHReg(Reg: DestReg) || isHReg(Reg: SrcReg)) && Subtarget.is64Bit()) {
4366 Opc = X86::MOV8rr_NOREX;
4367 // Both operands must be encodable without an REX prefix.
4368 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4369 "8-bit H register can not be copied outside GR8_NOREX");
4370 } else
4371 Opc = X86::MOV8rr;
4372 } else if (X86::VR64RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4373 Opc = X86::MMX_MOVQ64rr;
4374 else if (X86::VR128XRegClass.contains(Reg1: DestReg, Reg2: SrcReg)) {
4375 if (HasVLX)
4376 Opc = X86::VMOVAPSZ128rr;
4377 else if (X86::VR128RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4378 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
4379 else {
4380 // If this an extended register and we don't have VLX we need to use a
4381 // 512-bit move.
4382 Opc = X86::VMOVAPSZrr;
4383 const TargetRegisterInfo *TRI = &getRegisterInfo();
4384 DestReg =
4385 TRI->getMatchingSuperReg(Reg: DestReg, SubIdx: X86::sub_xmm, RC: &X86::VR512RegClass);
4386 SrcReg =
4387 TRI->getMatchingSuperReg(Reg: SrcReg, SubIdx: X86::sub_xmm, RC: &X86::VR512RegClass);
4388 }
4389 } else if (X86::VR256XRegClass.contains(Reg1: DestReg, Reg2: SrcReg)) {
4390 if (HasVLX)
4391 Opc = X86::VMOVAPSZ256rr;
4392 else if (X86::VR256RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4393 Opc = X86::VMOVAPSYrr;
4394 else {
4395 // If this an extended register and we don't have VLX we need to use a
4396 // 512-bit move.
4397 Opc = X86::VMOVAPSZrr;
4398 const TargetRegisterInfo *TRI = &getRegisterInfo();
4399 DestReg =
4400 TRI->getMatchingSuperReg(Reg: DestReg, SubIdx: X86::sub_ymm, RC: &X86::VR512RegClass);
4401 SrcReg =
4402 TRI->getMatchingSuperReg(Reg: SrcReg, SubIdx: X86::sub_ymm, RC: &X86::VR512RegClass);
4403 }
4404 } else if (X86::VR512RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4405 Opc = X86::VMOVAPSZrr;
4406 // All KMASK RegClasses hold the same k registers, can be tested against
4407 // anyone.
4408 else if (X86::VK16RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4409 Opc = Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVQkk_EVEX : X86::KMOVQkk)
4410 : (HasEGPR ? X86::KMOVWkk_EVEX : X86::KMOVWkk);
4411
4412 if (!Opc)
4413 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
4414
4415 if (Opc) {
4416 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: get(Opcode: Opc), DestReg)
4417 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc));
4418 return;
4419 }
4420
4421 if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
4422 // FIXME: We use a fatal error here because historically LLVM has tried
4423 // lower some of these physreg copies and we want to ensure we get
4424 // reasonable bug reports if someone encounters a case no other testing
4425 // found. This path should be removed after the LLVM 7 release.
4426 report_fatal_error(reason: "Unable to copy EFLAGS physical register!");
4427 }
4428
4429 LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
4430 << RI.getName(DestReg) << '\n');
4431 report_fatal_error(reason: "Cannot emit physreg copy instruction");
4432}
4433
4434std::optional<DestSourcePair>
4435X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
4436 if (MI.isMoveReg()) {
4437 // FIXME: Dirty hack for apparent invariant that doesn't hold when
4438 // subreg_to_reg is coalesced with ordinary copies, such that the bits that
4439 // were asserted as 0 are now undef.
4440 if (MI.getOperand(i: 0).isUndef() && MI.getOperand(i: 0).getSubReg())
4441 return std::nullopt;
4442
4443 return DestSourcePair{MI.getOperand(i: 0), MI.getOperand(i: 1)};
4444 }
4445 return std::nullopt;
4446}
4447
4448static unsigned getLoadStoreOpcodeForFP16(bool Load, const X86Subtarget &STI) {
4449 if (STI.hasFP16())
4450 return Load ? X86::VMOVSHZrm_alt : X86::VMOVSHZmr;
4451 if (Load)
4452 return X86::MOVSHPrm;
4453 return X86::MOVSHPmr;
4454}
4455
4456static unsigned getLoadStoreRegOpcode(Register Reg,
4457 const TargetRegisterClass *RC,
4458 bool IsStackAligned,
4459 const X86Subtarget &STI, bool Load) {
4460 bool HasAVX = STI.hasAVX();
4461 bool HasAVX512 = STI.hasAVX512();
4462 bool HasVLX = STI.hasVLX();
4463 bool HasEGPR = STI.hasEGPR();
4464
4465 assert(RC != nullptr && "Invalid target register class");
4466 switch (STI.getRegisterInfo()->getSpillSize(RC: *RC)) {
4467 default:
4468 llvm_unreachable("Unknown spill size");
4469 case 1:
4470 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
4471 if (STI.is64Bit())
4472 // Copying to or from a physical H register on x86-64 requires a NOREX
4473 // move. Otherwise use a normal move.
4474 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4475 return Load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4476 return Load ? X86::MOV8rm : X86::MOV8mr;
4477 case 2:
4478 if (X86::VK16RegClass.hasSubClassEq(RC))
4479 return Load ? (HasEGPR ? X86::KMOVWkm_EVEX : X86::KMOVWkm)
4480 : (HasEGPR ? X86::KMOVWmk_EVEX : X86::KMOVWmk);
4481 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4482 return Load ? X86::MOV16rm : X86::MOV16mr;
4483 case 4:
4484 if (X86::GR32RegClass.hasSubClassEq(RC))
4485 return Load ? X86::MOV32rm : X86::MOV32mr;
4486 if (X86::FR32XRegClass.hasSubClassEq(RC))
4487 return Load ? (HasAVX512 ? X86::VMOVSSZrm_alt
4488 : HasAVX ? X86::VMOVSSrm_alt
4489 : X86::MOVSSrm_alt)
4490 : (HasAVX512 ? X86::VMOVSSZmr
4491 : HasAVX ? X86::VMOVSSmr
4492 : X86::MOVSSmr);
4493 if (X86::RFP32RegClass.hasSubClassEq(RC))
4494 return Load ? X86::LD_Fp32m : X86::ST_Fp32m;
4495 if (X86::VK32RegClass.hasSubClassEq(RC)) {
4496 assert(STI.hasBWI() && "KMOVD requires BWI");
4497 return Load ? (HasEGPR ? X86::KMOVDkm_EVEX : X86::KMOVDkm)
4498 : (HasEGPR ? X86::KMOVDmk_EVEX : X86::KMOVDmk);
4499 }
4500 // All of these mask pair classes have the same spill size, the same kind
4501 // of kmov instructions can be used with all of them.
4502 if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
4503 X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
4504 X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
4505 X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
4506 X86::VK16PAIRRegClass.hasSubClassEq(RC))
4507 return Load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
4508 if (X86::FR16RegClass.hasSubClassEq(RC) ||
4509 X86::FR16XRegClass.hasSubClassEq(RC))
4510 return getLoadStoreOpcodeForFP16(Load, STI);
4511 llvm_unreachable("Unknown 4-byte regclass");
4512 case 8:
4513 if (X86::GR64RegClass.hasSubClassEq(RC))
4514 return Load ? X86::MOV64rm : X86::MOV64mr;
4515 if (X86::FR64XRegClass.hasSubClassEq(RC))
4516 return Load ? (HasAVX512 ? X86::VMOVSDZrm_alt
4517 : HasAVX ? X86::VMOVSDrm_alt
4518 : X86::MOVSDrm_alt)
4519 : (HasAVX512 ? X86::VMOVSDZmr
4520 : HasAVX ? X86::VMOVSDmr
4521 : X86::MOVSDmr);
4522 if (X86::VR64RegClass.hasSubClassEq(RC))
4523 return Load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4524 if (X86::RFP64RegClass.hasSubClassEq(RC))
4525 return Load ? X86::LD_Fp64m : X86::ST_Fp64m;
4526 if (X86::VK64RegClass.hasSubClassEq(RC)) {
4527 assert(STI.hasBWI() && "KMOVQ requires BWI");
4528 return Load ? (HasEGPR ? X86::KMOVQkm_EVEX : X86::KMOVQkm)
4529 : (HasEGPR ? X86::KMOVQmk_EVEX : X86::KMOVQmk);
4530 }
4531 llvm_unreachable("Unknown 8-byte regclass");
4532 case 10:
4533 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
4534 return Load ? X86::LD_Fp80m : X86::ST_FpP80m;
4535 case 16: {
4536 if (X86::VR128XRegClass.hasSubClassEq(RC)) {
4537 // If stack is realigned we can use aligned stores.
4538 if (IsStackAligned)
4539 return Load ? (HasVLX ? X86::VMOVAPSZ128rm
4540 : HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX
4541 : HasAVX ? X86::VMOVAPSrm
4542 : X86::MOVAPSrm)
4543 : (HasVLX ? X86::VMOVAPSZ128mr
4544 : HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX
4545 : HasAVX ? X86::VMOVAPSmr
4546 : X86::MOVAPSmr);
4547 else
4548 return Load ? (HasVLX ? X86::VMOVUPSZ128rm
4549 : HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX
4550 : HasAVX ? X86::VMOVUPSrm
4551 : X86::MOVUPSrm)
4552 : (HasVLX ? X86::VMOVUPSZ128mr
4553 : HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX
4554 : HasAVX ? X86::VMOVUPSmr
4555 : X86::MOVUPSmr);
4556 }
4557 llvm_unreachable("Unknown 16-byte regclass");
4558 }
4559 case 32:
4560 assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
4561 // If stack is realigned we can use aligned stores.
4562 if (IsStackAligned)
4563 return Load ? (HasVLX ? X86::VMOVAPSZ256rm
4564 : HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX
4565 : X86::VMOVAPSYrm)
4566 : (HasVLX ? X86::VMOVAPSZ256mr
4567 : HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX
4568 : X86::VMOVAPSYmr);
4569 else
4570 return Load ? (HasVLX ? X86::VMOVUPSZ256rm
4571 : HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX
4572 : X86::VMOVUPSYrm)
4573 : (HasVLX ? X86::VMOVUPSZ256mr
4574 : HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX
4575 : X86::VMOVUPSYmr);
4576 case 64:
4577 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
4578 assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
4579 if (IsStackAligned)
4580 return Load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4581 else
4582 return Load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4583 case 1024:
4584 assert(X86::TILERegClass.hasSubClassEq(RC) && "Unknown 1024-byte regclass");
4585 assert(STI.hasAMXTILE() && "Using 8*1024-bit register requires AMX-TILE");
4586#define GET_EGPR_IF_ENABLED(OPC) (STI.hasEGPR() ? OPC##_EVEX : OPC)
4587 return Load ? GET_EGPR_IF_ENABLED(X86::TILELOADD)
4588 : GET_EGPR_IF_ENABLED(X86::TILESTORED);
4589#undef GET_EGPR_IF_ENABLED
4590 }
4591}
4592
4593std::optional<ExtAddrMode>
4594X86InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI,
4595 const TargetRegisterInfo *TRI) const {
4596 int MemRefBegin = X86II::getMemoryOperandIdx(Desc: MemI.getDesc());
4597 if (MemRefBegin < 0)
4598 return std::nullopt;
4599
4600 auto &BaseOp = MemI.getOperand(i: MemRefBegin + X86::AddrBaseReg);
4601 if (!BaseOp.isReg()) // Can be an MO_FrameIndex
4602 return std::nullopt;
4603
4604 const MachineOperand &DispMO = MemI.getOperand(i: MemRefBegin + X86::AddrDisp);
4605 // Displacement can be symbolic
4606 if (!DispMO.isImm())
4607 return std::nullopt;
4608
4609 ExtAddrMode AM;
4610 AM.BaseReg = BaseOp.getReg();
4611 AM.ScaledReg = MemI.getOperand(i: MemRefBegin + X86::AddrIndexReg).getReg();
4612 AM.Scale = MemI.getOperand(i: MemRefBegin + X86::AddrScaleAmt).getImm();
4613 AM.Displacement = DispMO.getImm();
4614 return AM;
4615}
4616
4617bool X86InstrInfo::verifyInstruction(const MachineInstr &MI,
4618 StringRef &ErrInfo) const {
4619 std::optional<ExtAddrMode> AMOrNone = getAddrModeFromMemoryOp(MemI: MI, TRI: nullptr);
4620 if (!AMOrNone)
4621 return true;
4622
4623 ExtAddrMode AM = *AMOrNone;
4624 assert(AM.Form == ExtAddrMode::Formula::Basic);
4625 if (AM.ScaledReg != X86::NoRegister) {
4626 switch (AM.Scale) {
4627 case 1:
4628 case 2:
4629 case 4:
4630 case 8:
4631 break;
4632 default:
4633 ErrInfo = "Scale factor in address must be 1, 2, 4 or 8";
4634 return false;
4635 }
4636 }
4637 if (!isInt<32>(x: AM.Displacement)) {
4638 ErrInfo = "Displacement in address must fit into 32-bit signed "
4639 "integer";
4640 return false;
4641 }
4642
4643 return true;
4644}
4645
4646bool X86InstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
4647 const Register Reg,
4648 int64_t &ImmVal) const {
4649 Register MovReg = Reg;
4650 const MachineInstr *MovMI = &MI;
4651
4652 // Follow use-def for SUBREG_TO_REG to find the real move immediate
4653 // instruction. It is quite common for x86-64.
4654 if (MI.isSubregToReg()) {
4655 // We use following pattern to setup 64b immediate.
4656 // %8:gr32 = MOV32r0 implicit-def dead $eflags
4657 // %6:gr64 = SUBREG_TO_REG killed %8:gr32, %subreg.sub_32bit
4658 unsigned SubIdx = MI.getOperand(i: 2).getImm();
4659 MovReg = MI.getOperand(i: 1).getReg();
4660 if (SubIdx != X86::sub_32bit)
4661 return false;
4662 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
4663 MovMI = MRI.getUniqueVRegDef(Reg: MovReg);
4664 if (!MovMI)
4665 return false;
4666 }
4667
4668 if (MovMI->getOpcode() == X86::MOV32r0 &&
4669 MovMI->getOperand(i: 0).getReg() == MovReg) {
4670 ImmVal = 0;
4671 return true;
4672 }
4673
4674 if (MovMI->getOpcode() != X86::MOV32ri &&
4675 MovMI->getOpcode() != X86::MOV64ri &&
4676 MovMI->getOpcode() != X86::MOV32ri64 && MovMI->getOpcode() != X86::MOV8ri)
4677 return false;
4678 // Mov Src can be a global address.
4679 if (!MovMI->getOperand(i: 1).isImm() || MovMI->getOperand(i: 0).getReg() != MovReg)
4680 return false;
4681 ImmVal = MovMI->getOperand(i: 1).getImm();
4682 return true;
4683}
4684
4685bool X86InstrInfo::preservesZeroValueInReg(
4686 const MachineInstr *MI, const Register NullValueReg,
4687 const TargetRegisterInfo *TRI) const {
4688 if (!MI->modifiesRegister(Reg: NullValueReg, TRI))
4689 return true;
4690 switch (MI->getOpcode()) {
4691 // Shift right/left of a null unto itself is still a null, i.e. rax = shl rax
4692 // X.
4693 case X86::SHR64ri:
4694 case X86::SHR32ri:
4695 case X86::SHL64ri:
4696 case X86::SHL32ri:
4697 assert(MI->getOperand(0).isDef() && MI->getOperand(1).isUse() &&
4698 "expected for shift opcode!");
4699 return MI->getOperand(i: 0).getReg() == NullValueReg &&
4700 MI->getOperand(i: 1).getReg() == NullValueReg;
4701 // Zero extend of a sub-reg of NullValueReg into itself does not change the
4702 // null value.
4703 case X86::MOV32rr:
4704 return llvm::all_of(Range: MI->operands(), P: [&](const MachineOperand &MO) {
4705 return TRI->isSubRegisterEq(RegA: NullValueReg, RegB: MO.getReg());
4706 });
4707 default:
4708 return false;
4709 }
4710 llvm_unreachable("Should be handled above!");
4711}
4712
4713bool X86InstrInfo::getMemOperandsWithOffsetWidth(
4714 const MachineInstr &MemOp, SmallVectorImpl<const MachineOperand *> &BaseOps,
4715 int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
4716 const TargetRegisterInfo *TRI) const {
4717 int MemRefBegin = X86II::getMemoryOperandIdx(Desc: MemOp.getDesc());
4718 if (MemRefBegin < 0)
4719 return false;
4720
4721 const MachineOperand *BaseOp =
4722 &MemOp.getOperand(i: MemRefBegin + X86::AddrBaseReg);
4723 if (!BaseOp->isReg()) // Can be an MO_FrameIndex
4724 return false;
4725
4726 if (MemOp.getOperand(i: MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
4727 return false;
4728
4729 if (MemOp.getOperand(i: MemRefBegin + X86::AddrIndexReg).getReg() !=
4730 X86::NoRegister)
4731 return false;
4732
4733 const MachineOperand &DispMO = MemOp.getOperand(i: MemRefBegin + X86::AddrDisp);
4734
4735 // Displacement can be symbolic
4736 if (!DispMO.isImm())
4737 return false;
4738
4739 Offset = DispMO.getImm();
4740
4741 if (!BaseOp->isReg())
4742 return false;
4743
4744 OffsetIsScalable = false;
4745 // FIXME: Relying on memoperands() may not be right thing to do here. Check
4746 // with X86 maintainers, and fix it accordingly. For now, it is ok, since
4747 // there is no use of `Width` for X86 back-end at the moment.
4748 Width = !MemOp.memoperands_empty() ? MemOp.memoperands().front()->getSize()
4749 : LocationSize::precise(Value: 0);
4750 BaseOps.push_back(Elt: BaseOp);
4751 return true;
4752}
4753
4754static unsigned getStoreRegOpcode(Register SrcReg,
4755 const TargetRegisterClass *RC,
4756 bool IsStackAligned,
4757 const X86Subtarget &STI) {
4758 return getLoadStoreRegOpcode(Reg: SrcReg, RC, IsStackAligned, STI, Load: false);
4759}
4760
4761static unsigned getLoadRegOpcode(Register DestReg,
4762 const TargetRegisterClass *RC,
4763 bool IsStackAligned, const X86Subtarget &STI) {
4764 return getLoadStoreRegOpcode(Reg: DestReg, RC, IsStackAligned, STI, Load: true);
4765}
4766
4767static bool isAMXOpcode(unsigned Opc) {
4768 switch (Opc) {
4769 default:
4770 return false;
4771 case X86::TILELOADD:
4772 case X86::TILESTORED:
4773 case X86::TILELOADD_EVEX:
4774 case X86::TILESTORED_EVEX:
4775 return true;
4776 }
4777}
4778
4779void X86InstrInfo::loadStoreTileReg(MachineBasicBlock &MBB,
4780 MachineBasicBlock::iterator MI,
4781 unsigned Opc, Register Reg, int FrameIdx,
4782 bool isKill) const {
4783 switch (Opc) {
4784 default:
4785 llvm_unreachable("Unexpected special opcode!");
4786 case X86::TILESTORED:
4787 case X86::TILESTORED_EVEX: {
4788 // tilestored %tmm, (%sp, %idx)
4789 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
4790 Register VirtReg = RegInfo.createVirtualRegister(RegClass: &X86::GR64_NOSPRegClass);
4791 BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: get(Opcode: X86::MOV64ri), DestReg: VirtReg).addImm(Val: 64);
4792 MachineInstr *NewMI =
4793 addFrameReference(MIB: BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: get(Opcode: Opc)), FI: FrameIdx)
4794 .addReg(RegNo: Reg, Flags: getKillRegState(B: isKill));
4795 MachineOperand &MO = NewMI->getOperand(i: X86::AddrIndexReg);
4796 MO.setReg(VirtReg);
4797 MO.setIsKill(true);
4798 break;
4799 }
4800 case X86::TILELOADD:
4801 case X86::TILELOADD_EVEX: {
4802 // tileloadd (%sp, %idx), %tmm
4803 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
4804 Register VirtReg = RegInfo.createVirtualRegister(RegClass: &X86::GR64_NOSPRegClass);
4805 BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: get(Opcode: X86::MOV64ri), DestReg: VirtReg).addImm(Val: 64);
4806 MachineInstr *NewMI = addFrameReference(
4807 MIB: BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: get(Opcode: Opc), DestReg: Reg), FI: FrameIdx);
4808 MachineOperand &MO = NewMI->getOperand(i: 1 + X86::AddrIndexReg);
4809 MO.setReg(VirtReg);
4810 MO.setIsKill(true);
4811 break;
4812 }
4813 }
4814}
4815
4816void X86InstrInfo::storeRegToStackSlot(
4817 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
4818 bool isKill, int FrameIdx, const TargetRegisterClass *RC,
4819
4820 Register VReg, MachineInstr::MIFlag Flags) const {
4821 const MachineFunction &MF = *MBB.getParent();
4822 const MachineFrameInfo &MFI = MF.getFrameInfo();
4823 assert(MFI.getObjectSize(FrameIdx) >= RI.getSpillSize(*RC) &&
4824 "Stack slot too small for store");
4825
4826 unsigned Alignment = std::max<uint32_t>(a: RI.getSpillSize(RC: *RC), b: 16);
4827 bool isAligned =
4828 (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
4829 (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(ObjectIdx: FrameIdx));
4830
4831 unsigned Opc = getStoreRegOpcode(SrcReg, RC, IsStackAligned: isAligned, STI: Subtarget);
4832 if (isAMXOpcode(Opc))
4833 loadStoreTileReg(MBB, MI, Opc, Reg: SrcReg, FrameIdx, isKill);
4834 else
4835 addFrameReference(MIB: BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: get(Opcode: Opc)), FI: FrameIdx)
4836 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill))
4837 .setMIFlag(Flags);
4838}
4839
4840void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
4841 MachineBasicBlock::iterator MI,
4842 Register DestReg, int FrameIdx,
4843 const TargetRegisterClass *RC,
4844 Register VReg, unsigned SubReg,
4845 MachineInstr::MIFlag Flags) const {
4846 const MachineFunction &MF = *MBB.getParent();
4847 const MachineFrameInfo &MFI = MF.getFrameInfo();
4848 assert(MFI.getObjectSize(FrameIdx) >= RI.getSpillSize(*RC) &&
4849 "Load size exceeds stack slot");
4850 unsigned Alignment = std::max<uint32_t>(a: RI.getSpillSize(RC: *RC), b: 16);
4851 bool isAligned =
4852 (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
4853 (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(ObjectIdx: FrameIdx));
4854
4855 unsigned Opc = getLoadRegOpcode(DestReg, RC, IsStackAligned: isAligned, STI: Subtarget);
4856 if (isAMXOpcode(Opc))
4857 loadStoreTileReg(MBB, MI, Opc, Reg: DestReg, FrameIdx);
4858 else
4859 addFrameReference(MIB: BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: get(Opcode: Opc), DestReg), FI: FrameIdx)
4860 .setMIFlag(Flags);
4861}
4862
4863bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
4864 Register &SrcReg2, int64_t &CmpMask,
4865 int64_t &CmpValue) const {
4866 switch (MI.getOpcode()) {
4867 default:
4868 break;
4869 case X86::CMP64ri32:
4870 case X86::CMP32ri:
4871 case X86::CMP16ri:
4872 case X86::CMP8ri:
4873 SrcReg = MI.getOperand(i: 0).getReg();
4874 SrcReg2 = 0;
4875 if (MI.getOperand(i: 1).isImm()) {
4876 CmpMask = ~0;
4877 CmpValue = MI.getOperand(i: 1).getImm();
4878 } else {
4879 CmpMask = CmpValue = 0;
4880 }
4881 return true;
4882 // A SUB can be used to perform comparison.
4883 CASE_ND(SUB64rm)
4884 CASE_ND(SUB32rm)
4885 CASE_ND(SUB16rm)
4886 CASE_ND(SUB8rm)
4887 SrcReg = MI.getOperand(i: 1).getReg();
4888 SrcReg2 = 0;
4889 CmpMask = 0;
4890 CmpValue = 0;
4891 return true;
4892 CASE_ND(SUB64rr)
4893 CASE_ND(SUB32rr)
4894 CASE_ND(SUB16rr)
4895 CASE_ND(SUB8rr)
4896 SrcReg = MI.getOperand(i: 1).getReg();
4897 SrcReg2 = MI.getOperand(i: 2).getReg();
4898 CmpMask = 0;
4899 CmpValue = 0;
4900 return true;
4901 CASE_ND(SUB64ri32)
4902 CASE_ND(SUB32ri)
4903 CASE_ND(SUB16ri)
4904 CASE_ND(SUB8ri)
4905 SrcReg = MI.getOperand(i: 1).getReg();
4906 SrcReg2 = 0;
4907 if (MI.getOperand(i: 2).isImm()) {
4908 CmpMask = ~0;
4909 CmpValue = MI.getOperand(i: 2).getImm();
4910 } else {
4911 CmpMask = CmpValue = 0;
4912 }
4913 return true;
4914 case X86::CMP64rr:
4915 case X86::CMP32rr:
4916 case X86::CMP16rr:
4917 case X86::CMP8rr:
4918 SrcReg = MI.getOperand(i: 0).getReg();
4919 SrcReg2 = MI.getOperand(i: 1).getReg();
4920 CmpMask = 0;
4921 CmpValue = 0;
4922 return true;
4923 case X86::TEST8rr:
4924 case X86::TEST16rr:
4925 case X86::TEST32rr:
4926 case X86::TEST64rr:
4927 SrcReg = MI.getOperand(i: 0).getReg();
4928 if (MI.getOperand(i: 1).getReg() != SrcReg)
4929 return false;
4930 // Compare against zero.
4931 SrcReg2 = 0;
4932 CmpMask = ~0;
4933 CmpValue = 0;
4934 return true;
4935 case X86::TEST64ri32:
4936 case X86::TEST32ri:
4937 case X86::TEST16ri:
4938 case X86::TEST8ri:
4939 SrcReg = MI.getOperand(i: 0).getReg();
4940 SrcReg2 = 0;
4941 // Force identical compare.
4942 CmpMask = 0;
4943 CmpValue = 0;
4944 return true;
4945 }
4946 return false;
4947}
4948
4949bool X86InstrInfo::isRedundantFlagInstr(const MachineInstr &FlagI,
4950 Register SrcReg, Register SrcReg2,
4951 int64_t ImmMask, int64_t ImmValue,
4952 const MachineInstr &OI, bool *IsSwapped,
4953 int64_t *ImmDelta) const {
4954 switch (OI.getOpcode()) {
4955 case X86::CMP64rr:
4956 case X86::CMP32rr:
4957 case X86::CMP16rr:
4958 case X86::CMP8rr:
4959 CASE_ND(SUB64rr)
4960 CASE_ND(SUB32rr)
4961 CASE_ND(SUB16rr)
4962 CASE_ND(SUB8rr) {
4963 Register OISrcReg;
4964 Register OISrcReg2;
4965 int64_t OIMask;
4966 int64_t OIValue;
4967 if (!analyzeCompare(MI: OI, SrcReg&: OISrcReg, SrcReg2&: OISrcReg2, CmpMask&: OIMask, CmpValue&: OIValue) ||
4968 OIMask != ImmMask || OIValue != ImmValue)
4969 return false;
4970 if (SrcReg == OISrcReg && SrcReg2 == OISrcReg2) {
4971 *IsSwapped = false;
4972 return true;
4973 }
4974 if (SrcReg == OISrcReg2 && SrcReg2 == OISrcReg) {
4975 *IsSwapped = true;
4976 return true;
4977 }
4978 return false;
4979 }
4980 case X86::CMP64ri32:
4981 case X86::CMP32ri:
4982 case X86::CMP16ri:
4983 case X86::CMP8ri:
4984 case X86::TEST64ri32:
4985 case X86::TEST32ri:
4986 case X86::TEST16ri:
4987 case X86::TEST8ri:
4988 CASE_ND(SUB64ri32)
4989 CASE_ND(SUB32ri)
4990 CASE_ND(SUB16ri)
4991 CASE_ND(SUB8ri)
4992 case X86::TEST64rr:
4993 case X86::TEST32rr:
4994 case X86::TEST16rr:
4995 case X86::TEST8rr: {
4996 if (ImmMask != 0) {
4997 Register OISrcReg;
4998 Register OISrcReg2;
4999 int64_t OIMask;
5000 int64_t OIValue;
5001 if (analyzeCompare(MI: OI, SrcReg&: OISrcReg, SrcReg2&: OISrcReg2, CmpMask&: OIMask, CmpValue&: OIValue) &&
5002 SrcReg == OISrcReg && ImmMask == OIMask) {
5003 if (OIValue == ImmValue) {
5004 *ImmDelta = 0;
5005 return true;
5006 } else if (static_cast<uint64_t>(ImmValue) ==
5007 static_cast<uint64_t>(OIValue) - 1) {
5008 *ImmDelta = -1;
5009 return true;
5010 } else if (static_cast<uint64_t>(ImmValue) ==
5011 static_cast<uint64_t>(OIValue) + 1) {
5012 *ImmDelta = 1;
5013 return true;
5014 } else {
5015 return false;
5016 }
5017 }
5018 }
5019 return FlagI.isIdenticalTo(Other: OI);
5020 }
5021 default:
5022 return false;
5023 }
5024}
5025
5026inline static bool isCmpRedundantAfterLTZCNT(Register SrcReg, Register SrcReg2,
5027 int64_t ImmMask, int64_t ImmValue,
5028 const MachineInstr &OI) {
5029 switch (OI.getOpcode()) {
5030 default:
5031 return false;
5032 case X86::LZCNT16rr:
5033 case X86::LZCNT32rr:
5034 case X86::LZCNT64rr:
5035 case X86::TZCNT16rr:
5036 case X86::TZCNT32rr:
5037 case X86::TZCNT64rr: {
5038 if (ImmMask != 0 && !SrcReg2.isValid() && ImmValue == 1 &&
5039 OI.getOperand(i: 1).isReg() && SrcReg == OI.getOperand(i: 1).getReg()) {
5040 return true;
5041 }
5042 return false;
5043 }
5044 }
5045}
5046
5047#define CASE_EVEX(OP) \
5048 case X86::OP: \
5049 case X86::OP##_EVEX:
5050
5051/// Check whether the definition can be converted
5052/// to remove a comparison against zero.
5053inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag,
5054 bool &ClearsOverflowFlag) {
5055 NoSignFlag = false;
5056 ClearsOverflowFlag = false;
5057
5058 // "ELF Handling for Thread-Local Storage" specifies that x86-64 GOTTPOFF, and
5059 // i386 GOTNTPOFF/INDNTPOFF relocations can convert an ADD to a LEA during
5060 // Initial Exec to Local Exec relaxation. In these cases, we must not depend
5061 // on the EFLAGS modification of ADD actually happening in the final binary.
5062 if (MI.getOpcode() == X86::ADD64rm || MI.getOpcode() == X86::ADD32rm) {
5063 unsigned Flags = MI.getOperand(i: 5).getTargetFlags();
5064 if (Flags == X86II::MO_GOTTPOFF || Flags == X86II::MO_INDNTPOFF ||
5065 Flags == X86II::MO_GOTNTPOFF)
5066 return false;
5067 }
5068
5069 switch (MI.getOpcode()) {
5070 default:
5071 return false;
5072
5073 // The shift instructions only modify ZF if their shift count is non-zero.
5074 // N.B.: The processor truncates the shift count depending on the encoding.
5075 CASE_ND(SAR8ri)
5076 CASE_ND(SAR16ri)
5077 CASE_ND(SAR32ri)
5078 CASE_ND(SAR64ri)
5079 CASE_ND(SHR8ri)
5080 CASE_ND(SHR16ri)
5081 CASE_ND(SHR32ri)
5082 CASE_ND(SHR64ri)
5083 return getTruncatedShiftCount(MI, ShiftAmtOperandIdx: 2) != 0;
5084
5085 // Some left shift instructions can be turned into LEA instructions but only
5086 // if their flags aren't used. Avoid transforming such instructions.
5087 CASE_ND(SHL8ri)
5088 CASE_ND(SHL16ri)
5089 CASE_ND(SHL32ri)
5090 CASE_ND(SHL64ri) {
5091 unsigned ShAmt = getTruncatedShiftCount(MI, ShiftAmtOperandIdx: 2);
5092 // Converting to LEA only pays off when the shifted operand stays live,
5093 // since it spares a register copy; when the shift is the operand's only
5094 // user, reusing the flags is strictly better.
5095 if (isTruncatedShiftCountForLEA(ShAmt)) {
5096 Register SrcReg = MI.getOperand(i: 1).getReg();
5097 const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
5098 if (!SrcReg.isVirtual() || !MRI.hasOneNonDBGUse(RegNo: SrcReg))
5099 return false;
5100 }
5101 return ShAmt != 0;
5102 }
5103
5104 CASE_ND(SHRD16rri8)
5105 CASE_ND(SHRD32rri8)
5106 CASE_ND(SHRD64rri8)
5107 CASE_ND(SHLD16rri8)
5108 CASE_ND(SHLD32rri8)
5109 CASE_ND(SHLD64rri8)
5110 return getTruncatedShiftCount(MI, ShiftAmtOperandIdx: 3) != 0;
5111
5112 CASE_ND(SUB64ri32)
5113 CASE_ND(SUB32ri)
5114 CASE_ND(SUB16ri)
5115 CASE_ND(SUB8ri)
5116 CASE_ND(SUB64rr)
5117 CASE_ND(SUB32rr)
5118 CASE_ND(SUB16rr)
5119 CASE_ND(SUB8rr)
5120 CASE_ND(SUB64rm)
5121 CASE_ND(SUB32rm)
5122 CASE_ND(SUB16rm)
5123 CASE_ND(SUB8rm)
5124 CASE_ND(DEC64r)
5125 CASE_ND(DEC32r)
5126 CASE_ND(DEC16r)
5127 CASE_ND(DEC8r)
5128 CASE_ND(ADD64ri32)
5129 CASE_ND(ADD32ri)
5130 CASE_ND(ADD16ri)
5131 CASE_ND(ADD8ri)
5132 CASE_ND(ADD64rr)
5133 CASE_ND(ADD32rr)
5134 CASE_ND(ADD16rr)
5135 CASE_ND(ADD8rr)
5136 CASE_ND(ADD64rm)
5137 CASE_ND(ADD32rm)
5138 CASE_ND(ADD16rm)
5139 CASE_ND(ADD8rm)
5140 CASE_ND(INC64r)
5141 CASE_ND(INC32r)
5142 CASE_ND(INC16r)
5143 CASE_ND(INC8r)
5144 CASE_ND(ADC64ri32)
5145 CASE_ND(ADC32ri)
5146 CASE_ND(ADC16ri)
5147 CASE_ND(ADC8ri)
5148 CASE_ND(ADC64rr)
5149 CASE_ND(ADC32rr)
5150 CASE_ND(ADC16rr)
5151 CASE_ND(ADC8rr)
5152 CASE_ND(ADC64rm)
5153 CASE_ND(ADC32rm)
5154 CASE_ND(ADC16rm)
5155 CASE_ND(ADC8rm)
5156 CASE_ND(SBB64ri32)
5157 CASE_ND(SBB32ri)
5158 CASE_ND(SBB16ri)
5159 CASE_ND(SBB8ri)
5160 CASE_ND(SBB64rr)
5161 CASE_ND(SBB32rr)
5162 CASE_ND(SBB16rr)
5163 CASE_ND(SBB8rr)
5164 CASE_ND(SBB64rm)
5165 CASE_ND(SBB32rm)
5166 CASE_ND(SBB16rm)
5167 CASE_ND(SBB8rm)
5168 CASE_ND(NEG8r)
5169 CASE_ND(NEG16r)
5170 CASE_ND(NEG32r)
5171 CASE_ND(NEG64r)
5172 case X86::LZCNT16rr:
5173 case X86::LZCNT16rm:
5174 case X86::LZCNT32rr:
5175 case X86::LZCNT32rm:
5176 case X86::LZCNT64rr:
5177 case X86::LZCNT64rm:
5178 case X86::POPCNT16rr:
5179 case X86::POPCNT16rm:
5180 case X86::POPCNT32rr:
5181 case X86::POPCNT32rm:
5182 case X86::POPCNT64rr:
5183 case X86::POPCNT64rm:
5184 case X86::TZCNT16rr:
5185 case X86::TZCNT16rm:
5186 case X86::TZCNT32rr:
5187 case X86::TZCNT32rm:
5188 case X86::TZCNT64rr:
5189 case X86::TZCNT64rm:
5190 return true;
5191 CASE_ND(AND64ri32)
5192 CASE_ND(AND32ri)
5193 CASE_ND(AND16ri)
5194 CASE_ND(AND8ri)
5195 CASE_ND(AND64rr)
5196 CASE_ND(AND32rr)
5197 CASE_ND(AND16rr)
5198 CASE_ND(AND8rr)
5199 CASE_ND(AND64rm)
5200 CASE_ND(AND32rm)
5201 CASE_ND(AND16rm)
5202 CASE_ND(AND8rm)
5203 CASE_ND(XOR64ri32)
5204 CASE_ND(XOR32ri)
5205 CASE_ND(XOR16ri)
5206 CASE_ND(XOR8ri)
5207 CASE_ND(XOR64rr)
5208 CASE_ND(XOR32rr)
5209 CASE_ND(XOR16rr)
5210 CASE_ND(XOR8rr)
5211 CASE_ND(XOR64rm)
5212 CASE_ND(XOR32rm)
5213 CASE_ND(XOR16rm)
5214 CASE_ND(XOR8rm)
5215 CASE_ND(OR64ri32)
5216 CASE_ND(OR32ri)
5217 CASE_ND(OR16ri)
5218 CASE_ND(OR8ri)
5219 CASE_ND(OR64rr)
5220 CASE_ND(OR32rr)
5221 CASE_ND(OR16rr)
5222 CASE_ND(OR8rr)
5223 CASE_ND(OR64rm)
5224 CASE_ND(OR32rm)
5225 CASE_ND(OR16rm)
5226 CASE_ND(OR8rm)
5227 CASE_EVEX(ANDN32rr)
5228 CASE_EVEX(ANDN32rm)
5229 CASE_EVEX(ANDN64rr)
5230 CASE_EVEX(ANDN64rm)
5231 CASE_EVEX(BLSI32rr)
5232 CASE_EVEX(BLSI32rm)
5233 CASE_EVEX(BLSI64rr)
5234 CASE_EVEX(BLSI64rm)
5235 CASE_EVEX(BLSMSK32rr)
5236 CASE_EVEX(BLSMSK32rm)
5237 CASE_EVEX(BLSMSK64rr)
5238 CASE_EVEX(BLSMSK64rm)
5239 CASE_EVEX(BLSR32rr)
5240 CASE_EVEX(BLSR32rm)
5241 CASE_EVEX(BLSR64rr)
5242 CASE_EVEX(BLSR64rm)
5243 case X86::BLCFILL32rr:
5244 case X86::BLCFILL32rm:
5245 case X86::BLCFILL64rr:
5246 case X86::BLCFILL64rm:
5247 case X86::BLCI32rr:
5248 case X86::BLCI32rm:
5249 case X86::BLCI64rr:
5250 case X86::BLCI64rm:
5251 case X86::BLCIC32rr:
5252 case X86::BLCIC32rm:
5253 case X86::BLCIC64rr:
5254 case X86::BLCIC64rm:
5255 case X86::BLCMSK32rr:
5256 case X86::BLCMSK32rm:
5257 case X86::BLCMSK64rr:
5258 case X86::BLCMSK64rm:
5259 case X86::BLCS32rr:
5260 case X86::BLCS32rm:
5261 case X86::BLCS64rr:
5262 case X86::BLCS64rm:
5263 case X86::BLSFILL32rr:
5264 case X86::BLSFILL32rm:
5265 case X86::BLSFILL64rr:
5266 case X86::BLSFILL64rm:
5267 case X86::BLSIC32rr:
5268 case X86::BLSIC32rm:
5269 case X86::BLSIC64rr:
5270 case X86::BLSIC64rm:
5271 CASE_EVEX(BZHI32rr)
5272 CASE_EVEX(BZHI32rm)
5273 CASE_EVEX(BZHI64rr)
5274 CASE_EVEX(BZHI64rm)
5275 case X86::T1MSKC32rr:
5276 case X86::T1MSKC32rm:
5277 case X86::T1MSKC64rr:
5278 case X86::T1MSKC64rm:
5279 case X86::TZMSK32rr:
5280 case X86::TZMSK32rm:
5281 case X86::TZMSK64rr:
5282 case X86::TZMSK64rm:
5283 // These instructions clear the overflow flag just like TEST.
5284 // FIXME: These are not the only instructions in this switch that clear the
5285 // overflow flag.
5286 ClearsOverflowFlag = true;
5287 return true;
5288 CASE_EVEX(BEXTR32rr)
5289 CASE_EVEX(BEXTR64rr)
5290 CASE_EVEX(BEXTR32rm)
5291 CASE_EVEX(BEXTR64rm)
5292 case X86::BEXTRI32ri:
5293 case X86::BEXTRI32mi:
5294 case X86::BEXTRI64ri:
5295 case X86::BEXTRI64mi:
5296 // BEXTR doesn't update the sign flag so we can't use it. It does clear
5297 // the overflow flag, but that's not useful without the sign flag.
5298 NoSignFlag = true;
5299 return true;
5300 }
5301}
5302
5303/// Check whether the use can be converted to remove a comparison against zero.
5304/// Returns the EFLAGS condition and the operand that we are comparing against zero.
5305static std::pair<X86::CondCode, unsigned> isUseDefConvertible(const MachineInstr &MI) {
5306 switch (MI.getOpcode()) {
5307 default:
5308 return std::make_pair(x: X86::COND_INVALID, y: ~0U);
5309 CASE_ND(NEG8r)
5310 CASE_ND(NEG16r)
5311 CASE_ND(NEG32r)
5312 CASE_ND(NEG64r)
5313 return std::make_pair(x: X86::COND_AE, y: 1U);
5314 case X86::LZCNT16rr:
5315 case X86::LZCNT32rr:
5316 case X86::LZCNT64rr:
5317 return std::make_pair(x: X86::COND_B, y: 1U);
5318 case X86::POPCNT16rr:
5319 case X86::POPCNT32rr:
5320 case X86::POPCNT64rr:
5321 return std::make_pair(x: X86::COND_E, y: 1U);
5322 case X86::TZCNT16rr:
5323 case X86::TZCNT32rr:
5324 case X86::TZCNT64rr:
5325 return std::make_pair(x: X86::COND_B, y: 1U);
5326 case X86::BSF16rr:
5327 case X86::BSF32rr:
5328 case X86::BSF64rr:
5329 case X86::BSR16rr:
5330 case X86::BSR32rr:
5331 case X86::BSR64rr:
5332 return std::make_pair(x: X86::COND_E, y: 2U);
5333 CASE_EVEX(BLSI32rr)
5334 CASE_EVEX(BLSI64rr)
5335 return std::make_pair(x: X86::COND_AE, y: 1U);
5336 CASE_EVEX(BLSR32rr)
5337 CASE_EVEX(BLSR64rr)
5338 CASE_EVEX(BLSMSK32rr)
5339 CASE_EVEX(BLSMSK64rr)
5340 return std::make_pair(x: X86::COND_B, y: 1U);
5341 // TODO: TBM instructions.
5342 }
5343}
5344#undef CASE_EVEX
5345
5346MachineInstr *X86InstrInfo::findDominatingRedundantFlagInstr(
5347 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask,
5348 int64_t CmpValue, MachineBasicBlock *MultiPredMBB, bool &IsSwapped,
5349 int64_t &ImmDelta,
5350 SmallVectorImpl<std::pair<MachineInstr *, unsigned>> &InstsToUpdate) const {
5351 assert(Subtarget.hasNF() && "NF feature required");
5352 const TargetRegisterInfo *TRI = &getRegisterInfo();
5353
5354 // The caller already scanned MultiPredMBB without finding the producer, so it
5355 // must live in a block that strictly dominates MultiPredMBB. Walk
5356 // predecessors backward to find it and prove dominance, avoiding a
5357 // whole-function MachineDominatorTree that would be rebuilt in O(function
5358 // size) per compare.
5359 //
5360 // The producer's block dominates MultiPredMBB iff every backward path funnels
5361 // through it before a function-entry block, so expand predecessors but stop
5362 // at a block holding the producer. Bail if a predecessor-less block is
5363 // reached without the producer (a path bypasses it) or the producer is found
5364 // in two blocks (neither dominates alone). Within a block, scan backward,
5365 // collecting the NF-convertible EFLAGS clobbers above the producer and
5366 // bailing on any other clobber (it would shadow the producer's flags from
5367 // CmpInstr).
5368 //
5369 // Clobbers are staged in Pending and committed only on success. Visited
5370 // (seeded with MultiPredMBB) stops the walk from revisiting a block or
5371 // re-entering the single-predecessor chain, so none is collected twice.
5372 //
5373 // Each NF conversion trades a compact legacy/EVEX-compressed encoding for a
5374 // wider EVEX (often NDD three-operand) one, growing code size, while the
5375 // reuse only removes a single compare. Cap the total number of conversions
5376 // (those the caller already collected on the single-predecessor chain plus
5377 // those the walk stages) so the reuse cannot bloat code just to delete one
5378 // compare.
5379 MachineInstr *Sub = nullptr;
5380 MachineBasicBlock *SubMBB = nullptr;
5381 SmallVector<std::pair<MachineInstr *, unsigned>, 4> Pending;
5382 SmallPtrSet<MachineBasicBlock *, 8> Visited;
5383 SmallVector<MachineBasicBlock *, 8> Worklist;
5384 Visited.insert(Ptr: MultiPredMBB);
5385 for (MachineBasicBlock *Pred : MultiPredMBB->predecessors())
5386 if (Visited.insert(Ptr: Pred).second)
5387 Worklist.push_back(Elt: Pred);
5388 while (!Worklist.empty()) {
5389 MachineBasicBlock *MBB = Worklist.pop_back_val();
5390 MachineInstr *Producer = nullptr;
5391 for (MachineInstr &Inst : reverse(C&: *MBB)) {
5392 if (!Inst.modifiesRegister(Reg: X86::EFLAGS, TRI))
5393 continue;
5394 if (isRedundantFlagInstr(FlagI: CmpInstr, SrcReg, SrcReg2, ImmMask: CmpMask, ImmValue: CmpValue,
5395 OI: Inst, IsSwapped: &IsSwapped, ImmDelta: &ImmDelta)) {
5396 Producer = &Inst;
5397 break;
5398 }
5399 unsigned NewOpc = X86::getNFVariantIfClobberRemovable(MI: Inst, TRI);
5400 if (!NewOpc)
5401 return nullptr;
5402 if (InstsToUpdate.size() + Pending.size() >= MaxNFConversions)
5403 return nullptr;
5404 Pending.push_back(Elt: std::make_pair(x: &Inst, y&: NewOpc));
5405 }
5406 if (Producer) {
5407 // A producer in a second block means neither dominates alone.
5408 if (Sub && SubMBB != MBB)
5409 return nullptr;
5410 Sub = Producer;
5411 SubMBB = MBB;
5412 continue;
5413 }
5414 // Entry reached without the producer: some path bypasses it.
5415 if (MBB->pred_empty())
5416 return nullptr;
5417 for (MachineBasicBlock *Pred : MBB->predecessors())
5418 if (Visited.insert(Ptr: Pred).second)
5419 Worklist.push_back(Elt: Pred);
5420 }
5421 if (!Sub)
5422 return nullptr;
5423
5424 // The forward condition-code fixup in the caller (OpsToUpdate) only rewrites
5425 // EFLAGS users within CmpMBB. When the producer's flags require a condition
5426 // swap or an immediate adjustment, EFLAGS users elsewhere in the dominated
5427 // region or in CmpMBB's successors (when EFLAGS is live-out) would also need
5428 // rewriting, which is not handled here. Restrict the multi-predecessor case
5429 // to producers that yield identical flags.
5430 if (IsSwapped || ImmDelta != 0)
5431 return nullptr;
5432
5433 InstsToUpdate.append(in_start: Pending.begin(), in_end: Pending.end());
5434 return Sub;
5435}
5436
5437/// Check if there exists an earlier instruction that
5438/// operates on the same source operands and sets flags in the same way as
5439/// Compare; remove Compare if possible.
5440bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
5441 Register SrcReg2, int64_t CmpMask,
5442 int64_t CmpValue,
5443 const MachineRegisterInfo *MRI) const {
5444 // Check whether we can replace SUB with CMP.
5445 switch (CmpInstr.getOpcode()) {
5446 default:
5447 break;
5448 CASE_ND(SUB64ri32)
5449 CASE_ND(SUB32ri)
5450 CASE_ND(SUB16ri)
5451 CASE_ND(SUB8ri)
5452 CASE_ND(SUB64rm)
5453 CASE_ND(SUB32rm)
5454 CASE_ND(SUB16rm)
5455 CASE_ND(SUB8rm)
5456 CASE_ND(SUB64rr)
5457 CASE_ND(SUB32rr)
5458 CASE_ND(SUB16rr)
5459 CASE_ND(SUB8rr) {
5460 if (!MRI->use_nodbg_empty(RegNo: CmpInstr.getOperand(i: 0).getReg()))
5461 return false;
5462 // There is no use of the destination register, we can replace SUB with CMP.
5463 unsigned NewOpcode = 0;
5464#define FROM_TO(A, B) \
5465 CASE_ND(A) NewOpcode = X86::B; \
5466 break;
5467 switch (CmpInstr.getOpcode()) {
5468 default:
5469 llvm_unreachable("Unreachable!");
5470 FROM_TO(SUB64rm, CMP64rm)
5471 FROM_TO(SUB32rm, CMP32rm)
5472 FROM_TO(SUB16rm, CMP16rm)
5473 FROM_TO(SUB8rm, CMP8rm)
5474 FROM_TO(SUB64rr, CMP64rr)
5475 FROM_TO(SUB32rr, CMP32rr)
5476 FROM_TO(SUB16rr, CMP16rr)
5477 FROM_TO(SUB8rr, CMP8rr)
5478 FROM_TO(SUB64ri32, CMP64ri32)
5479 FROM_TO(SUB32ri, CMP32ri)
5480 FROM_TO(SUB16ri, CMP16ri)
5481 FROM_TO(SUB8ri, CMP8ri)
5482 }
5483#undef FROM_TO
5484 CmpInstr.setDesc(get(Opcode: NewOpcode));
5485 CmpInstr.removeOperand(OpNo: 0);
5486 // Mutating this instruction invalidates any debug data associated with it.
5487 CmpInstr.dropDebugNumber();
5488 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
5489 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5490 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5491 return false;
5492 }
5493 }
5494
5495 // The following code tries to remove the comparison by re-using EFLAGS
5496 // from earlier instructions.
5497
5498 bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
5499
5500 // Transformation currently requires SSA values.
5501 if (SrcReg2.isPhysical())
5502 return false;
5503 MachineInstr *SrcRegDef = MRI->getVRegDef(Reg: SrcReg);
5504 if (!SrcRegDef)
5505 return false;
5506
5507 MachineInstr *MI = nullptr;
5508 MachineInstr *Sub = nullptr;
5509 MachineInstr *Movr0Inst = nullptr;
5510 MachineInstr *LTZCNTInst = nullptr;
5511 SmallVector<std::pair<MachineInstr *, unsigned>, 4> InstsToUpdate;
5512 bool NoSignFlag = false;
5513 bool ClearsOverflowFlag = false;
5514 bool ShouldUpdateCC = false;
5515 bool IsSwapped = false;
5516 bool HasNF = Subtarget.hasNF();
5517 unsigned OpNo = 0;
5518 X86::CondCode NewCC = X86::COND_INVALID;
5519 int64_t ImmDelta = 0;
5520
5521 // Search backward from CmpInstr for the next instruction defining EFLAGS.
5522 const TargetRegisterInfo *TRI = &getRegisterInfo();
5523 MachineBasicBlock &CmpMBB = *CmpInstr.getParent();
5524 MachineBasicBlock::reverse_iterator From =
5525 std::next(x: MachineBasicBlock::reverse_iterator(CmpInstr));
5526 for (MachineBasicBlock *MBB = &CmpMBB;;) {
5527 for (MachineInstr &Inst : make_range(x: From, y: MBB->rend())) {
5528 // Try to use EFLAGS from the instruction defining %SrcReg. Example:
5529 // %eax = addl ...
5530 // ... // EFLAGS not changed
5531 // testl %eax, %eax // <-- can be removed
5532 if (&Inst == SrcRegDef) {
5533 if (IsCmpZero &&
5534 isDefConvertible(MI: Inst, NoSignFlag, ClearsOverflowFlag)) {
5535 MI = &Inst;
5536 break;
5537 }
5538
5539 // Look back for the following pattern, in which case the
5540 // test16rr/test64rr instruction could be erased.
5541 //
5542 // Example for test16rr:
5543 // %reg = and32ri %in_reg, 5
5544 // ... // EFLAGS not changed.
5545 // %src_reg = copy %reg.sub_16bit:gr32
5546 // test16rr %src_reg, %src_reg, implicit-def $eflags
5547 // Example for test64rr:
5548 // %reg = and32ri %in_reg, 5
5549 // ... // EFLAGS not changed.
5550 // %src_reg = subreg_to_reg %reg, %subreg.sub_index
5551 // test64rr %src_reg, %src_reg, implicit-def $eflags
5552 MachineInstr *AndInstr = nullptr;
5553 if (IsCmpZero &&
5554 findRedundantFlagInstr(CmpInstr, CmpValDefInstr&: Inst, MRI, AndInstr: &AndInstr, TRI,
5555 ST: Subtarget, NoSignFlag, ClearsOverflowFlag)) {
5556 assert(AndInstr != nullptr && X86::isAND(AndInstr->getOpcode()));
5557 MI = AndInstr;
5558 break;
5559 }
5560 // Cannot find other candidates before definition of SrcReg.
5561 return false;
5562 }
5563
5564 if (Inst.modifiesRegister(Reg: X86::EFLAGS, TRI)) {
5565 // Try to use EFLAGS produced by an instruction reading %SrcReg.
5566 // Example:
5567 // %eax = ...
5568 // ...
5569 // popcntl %eax
5570 // ... // EFLAGS not changed
5571 // testl %eax, %eax // <-- can be removed
5572 if (IsCmpZero) {
5573 std::tie(args&: NewCC, args&: OpNo) = isUseDefConvertible(MI: Inst);
5574 if (NewCC != X86::COND_INVALID && Inst.getOperand(i: OpNo).isReg() &&
5575 Inst.getOperand(i: OpNo).getReg() == SrcReg) {
5576 ShouldUpdateCC = true;
5577 MI = &Inst;
5578 break;
5579 }
5580 }
5581
5582 // Try to use EFLAGS from an instruction with similar flag results.
5583 // Example:
5584 // sub x, y or cmp x, y
5585 // ... // EFLAGS not changed
5586 // cmp x, y // <-- can be removed
5587 if (isRedundantFlagInstr(FlagI: CmpInstr, SrcReg, SrcReg2, ImmMask: CmpMask, ImmValue: CmpValue,
5588 OI: Inst, IsSwapped: &IsSwapped, ImmDelta: &ImmDelta)) {
5589 Sub = &Inst;
5590 break;
5591 }
5592
5593 if (isCmpRedundantAfterLTZCNT(SrcReg, SrcReg2, ImmMask: CmpMask, ImmValue: CmpValue,
5594 OI: Inst)) {
5595 LTZCNTInst = &Inst;
5596 break;
5597 }
5598
5599 // MOV32r0 is implemented with xor which clobbers condition code. It is
5600 // safe to move up, if the definition to EFLAGS is dead and earlier
5601 // instructions do not read or write EFLAGS.
5602 if (!Movr0Inst && Inst.getOpcode() == X86::MOV32r0 &&
5603 Inst.registerDefIsDead(Reg: X86::EFLAGS, TRI)) {
5604 Movr0Inst = &Inst;
5605 continue;
5606 }
5607
5608 // Try to replace non-NF with NF instructions.
5609 if (HasNF) {
5610 unsigned NewOp = X86::getNFVariantIfClobberRemovable(MI: Inst, TRI);
5611 if (!NewOp)
5612 return false;
5613
5614 InstsToUpdate.push_back(Elt: std::make_pair(x: &Inst, y&: NewOp));
5615 continue;
5616 }
5617
5618 // Cannot do anything for any other EFLAG changes.
5619 return false;
5620 }
5621 }
5622
5623 if (MI || Sub || LTZCNTInst)
5624 break;
5625
5626 // Reached the begin of the basic block. If it has exactly one predecessor,
5627 // continue the backward scan there. Otherwise (multiple predecessors), try
5628 // to reuse EFLAGS from a dominating producer (handled below).
5629 if (MBB->pred_size() != 1) {
5630 // The block has multiple predecessors. We can still reuse EFLAGS from an
5631 // equivalent flag producer that dominates CmpInstr, provided every path
5632 // from that producer to CmpInstr only clobbers EFLAGS via instructions
5633 // that have an NF (no-flags) variant (which requires APX). This handles
5634 // patterns like (CMP duplicated by CodeGenPrepare across a diamond):
5635 // entry: cmp %x, C ; br
5636 // bb1: imul ... ; clobbers EFLAGS -> {nf} imul
5637 // bb2: ...
5638 // bb3: cmp %x, C ; <-- redundant, reuse EFLAGS from entry
5639 // cmovcc ...
5640 // The helper caps the total number of NF conversions so this cannot grow
5641 // code size without bound just to delete one compare.
5642 if (HasNF)
5643 Sub = findDominatingRedundantFlagInstr(
5644 CmpInstr, SrcReg, SrcReg2, CmpMask, CmpValue, MultiPredMBB: MBB, IsSwapped,
5645 ImmDelta, InstsToUpdate);
5646 if (!Sub)
5647 return false;
5648 break;
5649 }
5650 MBB = *MBB->pred_begin();
5651 From = MBB->rbegin();
5652 }
5653
5654 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
5655 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
5656 // If we are done with the basic block, we need to check whether EFLAGS is
5657 // live-out.
5658 bool FlagsMayLiveOut = true;
5659 SmallVector<std::pair<MachineInstr *, X86::CondCode>, 4> OpsToUpdate;
5660 MachineBasicBlock::iterator AfterCmpInstr =
5661 std::next(x: MachineBasicBlock::iterator(CmpInstr));
5662 for (MachineInstr &Instr : make_range(x: AfterCmpInstr, y: CmpMBB.end())) {
5663 bool ModifyEFLAGS = Instr.modifiesRegister(Reg: X86::EFLAGS, TRI);
5664 bool UseEFLAGS = Instr.readsRegister(Reg: X86::EFLAGS, TRI);
5665 // We should check the usage if this instruction uses and updates EFLAGS.
5666 if (!UseEFLAGS && ModifyEFLAGS) {
5667 // It is safe to remove CmpInstr if EFLAGS is updated again.
5668 FlagsMayLiveOut = false;
5669 break;
5670 }
5671 if (!UseEFLAGS && !ModifyEFLAGS)
5672 continue;
5673
5674 // EFLAGS is used by this instruction.
5675 X86::CondCode OldCC = X86::getCondFromMI(MI: Instr);
5676 if ((MI || IsSwapped || ImmDelta != 0) && OldCC == X86::COND_INVALID)
5677 return false;
5678
5679 X86::CondCode ReplacementCC = X86::COND_INVALID;
5680 if (MI) {
5681 switch (OldCC) {
5682 default:
5683 break;
5684 case X86::COND_A:
5685 case X86::COND_AE:
5686 case X86::COND_B:
5687 case X86::COND_BE:
5688 // CF is used, we can't perform this optimization.
5689 return false;
5690 case X86::COND_G:
5691 case X86::COND_GE:
5692 case X86::COND_L:
5693 case X86::COND_LE:
5694 // If SF is used, but the instruction doesn't update the SF, then we
5695 // can't do the optimization.
5696 if (NoSignFlag)
5697 return false;
5698 [[fallthrough]];
5699 case X86::COND_O:
5700 case X86::COND_NO:
5701 // If OF is used, the instruction needs to clear it like CmpZero does.
5702 if (!ClearsOverflowFlag)
5703 return false;
5704 break;
5705 case X86::COND_S:
5706 case X86::COND_NS:
5707 // If SF is used, but the instruction doesn't update the SF, then we
5708 // can't do the optimization.
5709 if (NoSignFlag)
5710 return false;
5711 break;
5712 }
5713
5714 // If we're updating the condition code check if we have to reverse the
5715 // condition.
5716 if (ShouldUpdateCC)
5717 switch (OldCC) {
5718 default:
5719 return false;
5720 case X86::COND_E:
5721 ReplacementCC = NewCC;
5722 break;
5723 case X86::COND_NE:
5724 ReplacementCC = GetOppositeBranchCondition(CC: NewCC);
5725 break;
5726 }
5727 } else if (IsSwapped) {
5728 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
5729 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
5730 // We swap the condition code and synthesize the new opcode.
5731 ReplacementCC = getSwappedCondition(CC: OldCC);
5732 if (ReplacementCC == X86::COND_INVALID)
5733 return false;
5734 ShouldUpdateCC = true;
5735 } else if (ImmDelta != 0) {
5736 unsigned BitWidth = RI.getRegSizeInBits(RC: *MRI->getRegClass(Reg: SrcReg));
5737 // Shift amount for min/max constants to adjust for 8/16/32 instruction
5738 // sizes.
5739 switch (OldCC) {
5740 case X86::COND_L: // x <s (C + 1) --> x <=s C
5741 if (ImmDelta != 1 || APInt::getSignedMinValue(numBits: BitWidth) == CmpValue)
5742 return false;
5743 ReplacementCC = X86::COND_LE;
5744 break;
5745 case X86::COND_B: // x <u (C + 1) --> x <=u C
5746 if (ImmDelta != 1 || CmpValue == 0)
5747 return false;
5748 ReplacementCC = X86::COND_BE;
5749 break;
5750 case X86::COND_GE: // x >=s (C + 1) --> x >s C
5751 if (ImmDelta != 1 || APInt::getSignedMinValue(numBits: BitWidth) == CmpValue)
5752 return false;
5753 ReplacementCC = X86::COND_G;
5754 break;
5755 case X86::COND_AE: // x >=u (C + 1) --> x >u C
5756 if (ImmDelta != 1 || CmpValue == 0)
5757 return false;
5758 ReplacementCC = X86::COND_A;
5759 break;
5760 case X86::COND_G: // x >s (C - 1) --> x >=s C
5761 if (ImmDelta != -1 || APInt::getSignedMaxValue(numBits: BitWidth) == CmpValue)
5762 return false;
5763 ReplacementCC = X86::COND_GE;
5764 break;
5765 case X86::COND_A: // x >u (C - 1) --> x >=u C
5766 if (ImmDelta != -1 || APInt::getMaxValue(numBits: BitWidth) == CmpValue)
5767 return false;
5768 ReplacementCC = X86::COND_AE;
5769 break;
5770 case X86::COND_LE: // x <=s (C - 1) --> x <s C
5771 if (ImmDelta != -1 || APInt::getSignedMaxValue(numBits: BitWidth) == CmpValue)
5772 return false;
5773 ReplacementCC = X86::COND_L;
5774 break;
5775 case X86::COND_BE: // x <=u (C - 1) --> x <u C
5776 if (ImmDelta != -1 || APInt::getMaxValue(numBits: BitWidth) == CmpValue)
5777 return false;
5778 ReplacementCC = X86::COND_B;
5779 break;
5780 default:
5781 return false;
5782 }
5783 ShouldUpdateCC = true;
5784 }
5785
5786 if (LTZCNTInst) {
5787 unsigned InstCode = Instr.getOpcode();
5788 if (!X86::isADC(Opcode: InstCode) && !X86::isSBB(Opcode: InstCode) &&
5789 !X86::isRCL(Opcode: InstCode) && !X86::isRCR(Opcode: InstCode))
5790 return false;
5791
5792 MI = LTZCNTInst;
5793 }
5794
5795 if (ShouldUpdateCC && ReplacementCC != OldCC) {
5796 // Push the MachineInstr to OpsToUpdate.
5797 // If it is safe to remove CmpInstr, the condition code of these
5798 // instructions will be modified.
5799 OpsToUpdate.push_back(Elt: std::make_pair(x: &Instr, y&: ReplacementCC));
5800 }
5801 if (ModifyEFLAGS || Instr.killsRegister(Reg: X86::EFLAGS, TRI)) {
5802 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
5803 FlagsMayLiveOut = false;
5804 break;
5805 }
5806 }
5807
5808 // If we have to update users but EFLAGS is live-out abort, since we cannot
5809 // easily find all of the users.
5810 if ((MI != nullptr || ShouldUpdateCC) && FlagsMayLiveOut) {
5811 for (MachineBasicBlock *Successor : CmpMBB.successors())
5812 if (Successor->isLiveIn(Reg: X86::EFLAGS))
5813 return false;
5814 }
5815
5816 // The instruction to be updated is either Sub or MI.
5817 assert((MI == nullptr || Sub == nullptr) && "Should not have Sub and MI set");
5818 Sub = MI != nullptr ? MI : Sub;
5819 MachineBasicBlock *SubBB = Sub->getParent();
5820 // Move Movr0Inst to the appropriate place before Sub.
5821 if (Movr0Inst) {
5822 // Only move within the same block so we don't accidentally move to a
5823 // block with higher execution frequency.
5824 if (&CmpMBB != SubBB)
5825 return false;
5826 // Look backwards until we find a def that doesn't use the current EFLAGS.
5827 MachineBasicBlock::reverse_iterator InsertI = Sub,
5828 InsertE = Sub->getParent()->rend();
5829 for (; InsertI != InsertE; ++InsertI) {
5830 MachineInstr *Instr = &*InsertI;
5831 if (!Instr->readsRegister(Reg: X86::EFLAGS, TRI) &&
5832 Instr->modifiesRegister(Reg: X86::EFLAGS, TRI)) {
5833 Movr0Inst->getParent()->remove(I: Movr0Inst);
5834 Instr->getParent()->insert(I: MachineBasicBlock::iterator(Instr),
5835 MI: Movr0Inst);
5836 break;
5837 }
5838 }
5839 if (InsertI == InsertE)
5840 return false;
5841 }
5842
5843 // Replace non-NF with NF instructions.
5844 for (auto &Inst : InstsToUpdate) {
5845 Inst.first->setDesc(get(Opcode: Inst.second));
5846 Inst.first->removeOperand(
5847 OpNo: Inst.first->findRegisterDefOperandIdx(Reg: X86::EFLAGS, /*TRI=*/nullptr));
5848 }
5849
5850 // Make sure Sub instruction defines EFLAGS and mark the def live.
5851 MachineOperand *FlagDef =
5852 Sub->findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
5853 assert(FlagDef && "Unable to locate a def EFLAGS operand");
5854 FlagDef->setIsDead(false);
5855
5856 CmpInstr.eraseFromParent();
5857
5858 // Modify the condition code of instructions in OpsToUpdate.
5859 for (auto &Op : OpsToUpdate) {
5860 Op.first->getOperand(i: Op.first->getDesc().getNumOperands() - 1)
5861 .setImm(Op.second);
5862 }
5863 // Add EFLAGS to block live-ins between CmpBB and block of flags producer.
5864 // Walk the CFG backward from CmpMBB up to (but excluding) SubBB, marking
5865 // EFLAGS live-in on every block in between. SubBB dominates CmpMBB (whether
5866 // the producer was found by the single-predecessor backward walk or the
5867 // multi-predecessor dominator search), so the walk reaches SubBB on every
5868 // path and never escapes above it. A single-predecessor chain is just the
5869 // degenerate case where every block has exactly one predecessor.
5870 SmallPtrSet<MachineBasicBlock *, 8> Visited;
5871 SmallVector<MachineBasicBlock *, 8> Worklist(1, &CmpMBB);
5872 Visited.insert(Ptr: &CmpMBB);
5873 while (!Worklist.empty()) {
5874 MachineBasicBlock *MBB = Worklist.pop_back_val();
5875 // EFLAGS is produced inside SubBB, so it is not live-in there.
5876 if (MBB == SubBB)
5877 continue;
5878 if (!MBB->isLiveIn(Reg: X86::EFLAGS))
5879 MBB->addLiveIn(PhysReg: X86::EFLAGS);
5880 for (MachineBasicBlock *Pred : MBB->predecessors())
5881 if (Visited.insert(Ptr: Pred).second)
5882 Worklist.push_back(Elt: Pred);
5883 }
5884 return true;
5885}
5886
5887/// \returns true if the instruction can be changed to COPY when imm is 0.
5888static bool canConvert2Copy(unsigned Opc) {
5889 switch (Opc) {
5890 default:
5891 return false;
5892 CASE_ND(ADD64ri32)
5893 CASE_ND(SUB64ri32)
5894 CASE_ND(OR64ri32)
5895 CASE_ND(XOR64ri32)
5896 CASE_ND(ADD32ri)
5897 CASE_ND(SUB32ri)
5898 CASE_ND(OR32ri)
5899 CASE_ND(XOR32ri)
5900 return true;
5901 }
5902}
5903
5904/// Convert an ALUrr opcode to corresponding ALUri opcode. Such as
5905/// ADD32rr ==> ADD32ri
5906static unsigned convertALUrr2ALUri(unsigned Opc) {
5907 switch (Opc) {
5908 default:
5909 return 0;
5910#define FROM_TO(FROM, TO) \
5911 case X86::FROM: \
5912 return X86::TO; \
5913 case X86::FROM##_ND: \
5914 return X86::TO##_ND;
5915 FROM_TO(ADC64rr, ADC64ri32)
5916 FROM_TO(SBB64rr, SBB64ri32)
5917 FROM_TO(AND64rr, AND64ri32)
5918 FROM_TO(OR64rr, OR64ri32)
5919 FROM_TO(XOR64rr, XOR64ri32)
5920 FROM_TO(SHR64rCL, SHR64ri)
5921 FROM_TO(SHL64rCL, SHL64ri)
5922 FROM_TO(SAR64rCL, SAR64ri)
5923 FROM_TO(ROL64rCL, ROL64ri)
5924 FROM_TO(ROR64rCL, ROR64ri)
5925 FROM_TO(RCL64rCL, RCL64ri)
5926 FROM_TO(RCR64rCL, RCR64ri)
5927 FROM_TO(ADD32rr, ADD32ri)
5928 FROM_TO(ADC32rr, ADC32ri)
5929 FROM_TO(SUB32rr, SUB32ri)
5930 FROM_TO(SBB32rr, SBB32ri)
5931 FROM_TO(AND32rr, AND32ri)
5932 FROM_TO(OR32rr, OR32ri)
5933 FROM_TO(XOR32rr, XOR32ri)
5934 FROM_TO(SHR32rCL, SHR32ri)
5935 FROM_TO(SHL32rCL, SHL32ri)
5936 FROM_TO(SAR32rCL, SAR32ri)
5937 FROM_TO(ROL32rCL, ROL32ri)
5938 FROM_TO(ROR32rCL, ROR32ri)
5939 FROM_TO(RCL32rCL, RCL32ri)
5940 FROM_TO(RCR32rCL, RCR32ri)
5941#undef FROM_TO
5942#define FROM_TO(FROM, TO) \
5943 case X86::FROM: \
5944 return X86::TO;
5945 FROM_TO(ADD64rr, ADD64ri32)
5946 FROM_TO(SUB64rr, SUB64ri32)
5947 FROM_TO(TEST64rr, TEST64ri32)
5948 FROM_TO(CTEST64rr, CTEST64ri32)
5949 FROM_TO(CMP64rr, CMP64ri32)
5950 FROM_TO(CCMP64rr, CCMP64ri32)
5951 FROM_TO(TEST32rr, TEST32ri)
5952 FROM_TO(CTEST32rr, CTEST32ri)
5953 FROM_TO(CMP32rr, CMP32ri)
5954 FROM_TO(CCMP32rr, CCMP32ri)
5955#undef FROM_TO
5956 case X86::ADD64rr_ND:
5957 return X86::ADD64ri32_ND;
5958 case X86::SUB64rr_ND:
5959 return X86::SUB64ri32_ND;
5960 }
5961}
5962
5963/// Reg is assigned ImmVal in DefMI, and is used in UseMI.
5964/// If MakeChange is true, this function tries to replace Reg by ImmVal in
5965/// UseMI. If MakeChange is false, just check if folding is possible.
5966//
5967/// \returns true if folding is successful or possible.
5968bool X86InstrInfo::foldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI,
5969 Register Reg, int64_t ImmVal,
5970 MachineRegisterInfo *MRI,
5971 bool MakeChange) const {
5972 bool Modified = false;
5973
5974 // 64 bit operations accept sign extended 32 bit immediates.
5975 // 32 bit operations accept all 32 bit immediates, so we don't need to check
5976 // them.
5977 const TargetRegisterClass *RC = nullptr;
5978 if (Reg.isVirtual())
5979 RC = MRI->getRegClass(Reg);
5980 if ((Reg.isPhysical() && X86::GR64RegClass.contains(Reg)) ||
5981 (Reg.isVirtual() && X86::GR64RegClass.hasSubClassEq(RC))) {
5982 if (!isInt<32>(x: ImmVal))
5983 return false;
5984 }
5985
5986 if (UseMI.findRegisterUseOperand(Reg, /*TRI=*/nullptr)->getSubReg())
5987 return false;
5988 // Immediate has larger code size than register. So avoid folding the
5989 // immediate if it has more than 1 use and we are optimizing for size.
5990 if (UseMI.getMF()->getFunction().hasOptSize() && Reg.isVirtual() &&
5991 !MRI->hasOneNonDBGUse(RegNo: Reg))
5992 return false;
5993
5994 unsigned Opc = UseMI.getOpcode();
5995 unsigned NewOpc;
5996 if (Opc == TargetOpcode::COPY) {
5997 Register ToReg = UseMI.getOperand(i: 0).getReg();
5998 const TargetRegisterClass *RC = nullptr;
5999 if (ToReg.isVirtual())
6000 RC = MRI->getRegClass(Reg: ToReg);
6001 bool GR32Reg = (ToReg.isVirtual() && X86::GR32RegClass.hasSubClassEq(RC)) ||
6002 (ToReg.isPhysical() && X86::GR32RegClass.contains(Reg: ToReg));
6003 bool GR64Reg = (ToReg.isVirtual() && X86::GR64RegClass.hasSubClassEq(RC)) ||
6004 (ToReg.isPhysical() && X86::GR64RegClass.contains(Reg: ToReg));
6005 bool GR8Reg = (ToReg.isVirtual() && X86::GR8RegClass.hasSubClassEq(RC)) ||
6006 (ToReg.isPhysical() && X86::GR8RegClass.contains(Reg: ToReg));
6007
6008 if (ImmVal == 0) {
6009 // We have MOV32r0 only.
6010 if (!GR32Reg)
6011 return false;
6012 }
6013
6014 if (GR64Reg) {
6015 if (isUInt<32>(x: ImmVal))
6016 NewOpc = X86::MOV32ri64;
6017 else
6018 NewOpc = X86::MOV64ri;
6019 } else if (GR32Reg) {
6020 NewOpc = X86::MOV32ri;
6021 if (ImmVal == 0) {
6022 // MOV32r0 clobbers EFLAGS.
6023 const TargetRegisterInfo *TRI = &getRegisterInfo();
6024 if (UseMI.getParent()->computeRegisterLiveness(
6025 TRI, Reg: X86::EFLAGS, Before: UseMI) != MachineBasicBlock::LQR_Dead)
6026 return false;
6027
6028 // MOV32r0 is different than other cases because it doesn't encode the
6029 // immediate in the instruction. So we directly modify it here.
6030 if (!MakeChange)
6031 return true;
6032 UseMI.setDesc(get(Opcode: X86::MOV32r0));
6033 UseMI.removeOperand(
6034 OpNo: UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr));
6035 UseMI.addOperand(Op: MachineOperand::CreateReg(Reg: X86::EFLAGS, /*isDef=*/true,
6036 /*isImp=*/true,
6037 /*isKill=*/false,
6038 /*isDead=*/true));
6039 Modified = true;
6040 }
6041 } else if (GR8Reg)
6042 NewOpc = X86::MOV8ri;
6043 else
6044 return false;
6045 } else
6046 NewOpc = convertALUrr2ALUri(Opc);
6047
6048 if (!NewOpc)
6049 return false;
6050
6051 // For SUB instructions the immediate can only be the second source operand.
6052 if ((NewOpc == X86::SUB64ri32 || NewOpc == X86::SUB32ri ||
6053 NewOpc == X86::SBB64ri32 || NewOpc == X86::SBB32ri ||
6054 NewOpc == X86::SUB64ri32_ND || NewOpc == X86::SUB32ri_ND ||
6055 NewOpc == X86::SBB64ri32_ND || NewOpc == X86::SBB32ri_ND) &&
6056 UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr) != 2)
6057 return false;
6058 // For CMP instructions the immediate can only be at index 1.
6059 if (((NewOpc == X86::CMP64ri32 || NewOpc == X86::CMP32ri) ||
6060 (NewOpc == X86::CCMP64ri32 || NewOpc == X86::CCMP32ri)) &&
6061 UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr) != 1)
6062 return false;
6063
6064 using namespace X86;
6065 if (isSHL(Opcode: Opc) || isSHR(Opcode: Opc) || isSAR(Opcode: Opc) || isROL(Opcode: Opc) || isROR(Opcode: Opc) ||
6066 isRCL(Opcode: Opc) || isRCR(Opcode: Opc)) {
6067 unsigned RegIdx = UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr);
6068 if (RegIdx < 2)
6069 return false;
6070 if (!isInt<8>(x: ImmVal))
6071 return false;
6072 assert(Reg == X86::CL);
6073
6074 if (!MakeChange)
6075 return true;
6076 UseMI.setDesc(get(Opcode: NewOpc));
6077 UseMI.removeOperand(OpNo: RegIdx);
6078 UseMI.addOperand(Op: MachineOperand::CreateImm(Val: ImmVal));
6079 // Reg is physical register $cl, so we don't know if DefMI is dead through
6080 // MRI. Let the caller handle it, or pass dead-mi-elimination can delete
6081 // the dead physical register define instruction.
6082 return true;
6083 }
6084
6085 if (!MakeChange)
6086 return true;
6087
6088 if (!Modified) {
6089 // Modify the instruction.
6090 if (ImmVal == 0 && canConvert2Copy(Opc: NewOpc) &&
6091 UseMI.registerDefIsDead(Reg: X86::EFLAGS, /*TRI=*/nullptr)) {
6092 // %100 = add %101, 0
6093 // ==>
6094 // %100 = COPY %101
6095 UseMI.setDesc(get(Opcode: TargetOpcode::COPY));
6096 UseMI.removeOperand(
6097 OpNo: UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr));
6098 UseMI.removeOperand(
6099 OpNo: UseMI.findRegisterDefOperandIdx(Reg: X86::EFLAGS, /*TRI=*/nullptr));
6100 UseMI.untieRegOperand(OpIdx: 0);
6101 UseMI.clearFlag(Flag: MachineInstr::MIFlag::NoSWrap);
6102 UseMI.clearFlag(Flag: MachineInstr::MIFlag::NoUWrap);
6103 } else {
6104 unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
6105 unsigned ImmOpNum = 2;
6106 if (!UseMI.getOperand(i: 0).isDef()) {
6107 Op1 = 0; // TEST, CMP, CTEST, CCMP
6108 ImmOpNum = 1;
6109 }
6110 if (Opc == TargetOpcode::COPY)
6111 ImmOpNum = 1;
6112 if (findCommutedOpIndices(MI: UseMI, SrcOpIdx1&: Op1, SrcOpIdx2&: Op2) &&
6113 UseMI.getOperand(i: Op1).getReg() == Reg)
6114 commuteInstruction(MI&: UseMI);
6115
6116 assert(UseMI.getOperand(ImmOpNum).getReg() == Reg);
6117 UseMI.setDesc(get(Opcode: NewOpc));
6118 UseMI.getOperand(i: ImmOpNum).ChangeToImmediate(ImmVal);
6119 }
6120 }
6121
6122 if (Reg.isVirtual() && MRI->use_nodbg_empty(RegNo: Reg))
6123 DefMI->eraseFromBundle();
6124
6125 return true;
6126}
6127
6128/// foldImmediate - 'Reg' is known to be defined by a move immediate
6129/// instruction, try to fold the immediate into the use instruction.
6130bool X86InstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
6131 Register Reg, MachineRegisterInfo *MRI) const {
6132 int64_t ImmVal;
6133 if (!getConstValDefinedInReg(MI: DefMI, Reg, ImmVal))
6134 return false;
6135
6136 return foldImmediateImpl(UseMI, DefMI: &DefMI, Reg, ImmVal, MRI, MakeChange: true);
6137}
6138
6139/// Expand a single-def pseudo instruction to a two-addr
6140/// instruction with two undef reads of the register being defined.
6141/// This is used for mapping:
6142/// %xmm4 = V_SET0
6143/// to:
6144/// %xmm4 = PXORrr undef %xmm4, undef %xmm4
6145///
6146static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
6147 const MCInstrDesc &Desc) {
6148 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
6149 Register Reg = MIB.getReg(Idx: 0);
6150 MIB->setDesc(Desc);
6151
6152 // MachineInstr::addOperand() will insert explicit operands before any
6153 // implicit operands.
6154 MIB.addReg(RegNo: Reg, Flags: RegState::Undef).addReg(RegNo: Reg, Flags: RegState::Undef);
6155 // But we don't trust that.
6156 assert(MIB.getReg(1) == Reg && MIB.getReg(2) == Reg && "Misplaced operand");
6157 return true;
6158}
6159
6160/// Expand a single-def pseudo instruction to a two-addr
6161/// instruction with two %k0 reads.
6162/// This is used for mapping:
6163/// %k4 = K_SET1
6164/// to:
6165/// %k4 = KXNORrr %k0, %k0
6166static bool Expand2AddrKreg(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
6167 Register Reg) {
6168 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
6169 MIB->setDesc(Desc);
6170 MIB.addReg(RegNo: Reg, Flags: RegState::Undef).addReg(RegNo: Reg, Flags: RegState::Undef);
6171 return true;
6172}
6173
6174static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
6175 bool MinusOne) {
6176 MachineBasicBlock &MBB = *MIB->getParent();
6177 const DebugLoc &DL = MIB->getDebugLoc();
6178 Register Reg = MIB.getReg(Idx: 0);
6179
6180 // Insert the XOR.
6181 BuildMI(BB&: MBB, I: MIB.getInstr(), MIMD: DL, MCID: TII.get(Opcode: X86::XOR32rr), DestReg: Reg)
6182 .addReg(RegNo: Reg, Flags: RegState::Undef)
6183 .addReg(RegNo: Reg, Flags: RegState::Undef);
6184
6185 // Turn the pseudo into an INC or DEC.
6186 MIB->setDesc(TII.get(Opcode: MinusOne ? X86::DEC32r : X86::INC32r));
6187 MIB.addReg(RegNo: Reg);
6188
6189 return true;
6190}
6191
6192static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
6193 const TargetInstrInfo &TII,
6194 const X86Subtarget &Subtarget) {
6195 MachineBasicBlock &MBB = *MIB->getParent();
6196 const DebugLoc &DL = MIB->getDebugLoc();
6197 int64_t Imm = MIB->getOperand(i: 1).getImm();
6198 assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
6199 MachineBasicBlock::iterator I = MIB.getInstr();
6200
6201 int StackAdjustment;
6202
6203 if (Subtarget.is64Bit()) {
6204 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
6205 MIB->getOpcode() == X86::MOV32ImmSExti8);
6206
6207 // Can't use push/pop lowering if the function might write to the red zone.
6208 X86MachineFunctionInfo *X86FI =
6209 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
6210 if (X86FI->getUsesRedZone()) {
6211 MIB->setDesc(TII.get(Opcode: MIB->getOpcode() == X86::MOV32ImmSExti8
6212 ? X86::MOV32ri
6213 : X86::MOV64ri));
6214 return true;
6215 }
6216
6217 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
6218 // widen the register if necessary.
6219 StackAdjustment = 8;
6220 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII.get(Opcode: X86::PUSH64i32)).addImm(Val: Imm);
6221 MIB->setDesc(TII.get(Opcode: X86::POP64r));
6222 MIB->getOperand(i: 0).setReg(getX86SubSuperRegister(Reg: MIB.getReg(Idx: 0), Size: 64));
6223 } else {
6224 assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
6225 StackAdjustment = 4;
6226 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII.get(Opcode: X86::PUSH32i)).addImm(Val: Imm);
6227 MIB->setDesc(TII.get(Opcode: X86::POP32r));
6228 }
6229 MIB->removeOperand(OpNo: 1);
6230 MIB->addImplicitDefUseOperands(MF&: *MBB.getParent());
6231
6232 // Build CFI if necessary.
6233 MachineFunction &MF = *MBB.getParent();
6234 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
6235 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo().usesWindowsCFI();
6236 bool NeedsDwarfCFI = !IsWin64Prologue && MF.needsFrameMoves();
6237 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
6238 if (EmitCFI) {
6239 TFL->BuildCFI(
6240 MBB, MBBI: I, DL,
6241 CFIInst: MCCFIInstruction::createAdjustCfaOffset(L: nullptr, Adjustment: StackAdjustment));
6242 TFL->BuildCFI(
6243 MBB, MBBI: std::next(x: I), DL,
6244 CFIInst: MCCFIInstruction::createAdjustCfaOffset(L: nullptr, Adjustment: -StackAdjustment));
6245 }
6246
6247 return true;
6248}
6249
6250// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
6251// code sequence is needed for other targets.
6252static void expandLoadStackGuard(MachineInstrBuilder &MIB,
6253 const TargetInstrInfo &TII) {
6254 MachineBasicBlock &MBB = *MIB->getParent();
6255 const DebugLoc &DL = MIB->getDebugLoc();
6256 Register Reg = MIB.getReg(Idx: 0);
6257 const GlobalValue *GV =
6258 cast<GlobalValue>(Val: (*MIB->memoperands_begin())->getValue());
6259 auto Flags = MachineMemOperand::MOLoad |
6260 MachineMemOperand::MODereferenceable |
6261 MachineMemOperand::MOInvariant;
6262 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
6263 PtrInfo: MachinePointerInfo::getGOT(MF&: *MBB.getParent()), F: Flags, Size: 8, BaseAlignment: Align(8));
6264 MachineBasicBlock::iterator I = MIB.getInstr();
6265
6266 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII.get(Opcode: X86::MOV64rm), DestReg: Reg)
6267 .addReg(RegNo: X86::RIP)
6268 .addImm(Val: 1)
6269 .addReg(RegNo: 0)
6270 .addGlobalAddress(GV, Offset: 0, TargetFlags: X86II::MO_GOTPCREL)
6271 .addReg(RegNo: 0)
6272 .addMemOperand(MMO);
6273 MIB->setDebugLoc(DL);
6274 MIB->setDesc(TII.get(Opcode: X86::MOV64rm));
6275 MIB.addReg(RegNo: Reg, Flags: RegState::Kill).addImm(Val: 1).addReg(RegNo: 0).addImm(Val: 0).addReg(RegNo: 0);
6276}
6277
6278static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
6279 MachineBasicBlock &MBB = *MIB->getParent();
6280 MachineFunction &MF = *MBB.getParent();
6281 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
6282 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
6283 unsigned XorOp =
6284 MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
6285 MIB->setDesc(TII.get(Opcode: XorOp));
6286 MIB.addReg(RegNo: TRI->getFrameRegister(MF), Flags: RegState::Undef);
6287 return true;
6288}
6289
6290// This is used to handle spills for 128/256-bit registers when we have AVX512,
6291// but not VLX. If it uses an extended register we need to use an instruction
6292// that loads the lower 128/256-bit, but is available with only AVX512F.
6293static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
6294 const TargetRegisterInfo *TRI,
6295 const MCInstrDesc &LoadDesc,
6296 const MCInstrDesc &BroadcastDesc, unsigned SubIdx) {
6297 Register DestReg = MIB.getReg(Idx: 0);
6298 // Check if DestReg is XMM16-31 or YMM16-31.
6299 if (TRI->getEncodingValue(Reg: DestReg) < 16) {
6300 // We can use a normal VEX encoded load.
6301 MIB->setDesc(LoadDesc);
6302 } else {
6303 // Use a 128/256-bit VBROADCAST instruction.
6304 MIB->setDesc(BroadcastDesc);
6305 // Change the destination to a 512-bit register.
6306 DestReg = TRI->getMatchingSuperReg(Reg: DestReg, SubIdx, RC: &X86::VR512RegClass);
6307 MIB->getOperand(i: 0).setReg(DestReg);
6308 }
6309 return true;
6310}
6311
6312// This is used to handle spills for 128/256-bit registers when we have AVX512,
6313// but not VLX. If it uses an extended register we need to use an instruction
6314// that stores the lower 128/256-bit, but is available with only AVX512F.
6315static bool expandNOVLXStore(MachineInstrBuilder &MIB,
6316 const TargetRegisterInfo *TRI,
6317 const MCInstrDesc &StoreDesc,
6318 const MCInstrDesc &ExtractDesc, unsigned SubIdx) {
6319 Register SrcReg = MIB.getReg(Idx: X86::AddrNumOperands);
6320 // Check if DestReg is XMM16-31 or YMM16-31.
6321 if (TRI->getEncodingValue(Reg: SrcReg) < 16) {
6322 // We can use a normal VEX encoded store.
6323 MIB->setDesc(StoreDesc);
6324 } else {
6325 // Use a VEXTRACTF instruction.
6326 MIB->setDesc(ExtractDesc);
6327 // Change the destination to a 512-bit register.
6328 SrcReg = TRI->getMatchingSuperReg(Reg: SrcReg, SubIdx, RC: &X86::VR512RegClass);
6329 MIB->getOperand(i: X86::AddrNumOperands).setReg(SrcReg);
6330 MIB.addImm(Val: 0x0); // Append immediate to extract from the lower bits.
6331 }
6332
6333 return true;
6334}
6335
6336static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
6337 MIB->setDesc(Desc);
6338 int64_t ShiftAmt = MIB->getOperand(i: 2).getImm();
6339 // Temporarily remove the immediate so we can add another source register.
6340 MIB->removeOperand(OpNo: 2);
6341 // Add the register. Don't copy the kill flag if there is one.
6342 MIB.addReg(RegNo: MIB.getReg(Idx: 1), Flags: getUndefRegState(B: MIB->getOperand(i: 1).isUndef()));
6343 // Add back the immediate.
6344 MIB.addImm(Val: ShiftAmt);
6345 return true;
6346}
6347
6348static bool expandMOVSHP(MachineInstrBuilder &MIB, MachineInstr &MI,
6349 const TargetInstrInfo &TII, bool HasAVX) {
6350 unsigned NewOpc;
6351 if (MI.getOpcode() == X86::MOVSHPrm) {
6352 NewOpc = HasAVX ? X86::VMOVSSrm : X86::MOVSSrm;
6353 Register Reg = MI.getOperand(i: 0).getReg();
6354 if (Reg > X86::XMM15)
6355 NewOpc = X86::VMOVSSZrm;
6356 } else {
6357 NewOpc = HasAVX ? X86::VMOVSSmr : X86::MOVSSmr;
6358 Register Reg = MI.getOperand(i: 5).getReg();
6359 if (Reg > X86::XMM15)
6360 NewOpc = X86::VMOVSSZmr;
6361 }
6362
6363 MIB->setDesc(TII.get(Opcode: NewOpc));
6364 return true;
6365}
6366
6367bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
6368 bool HasAVX = Subtarget.hasAVX();
6369 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
6370 switch (MI.getOpcode()) {
6371 case X86::MOV32r0:
6372 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::XOR32rr));
6373 case X86::MOV32r1:
6374 return expandMOV32r1(MIB, TII: *this, /*MinusOne=*/false);
6375 case X86::MOV32r_1:
6376 return expandMOV32r1(MIB, TII: *this, /*MinusOne=*/true);
6377 case X86::MOV32ImmSExti8:
6378 case X86::MOV64ImmSExti8:
6379 return ExpandMOVImmSExti8(MIB, TII: *this, Subtarget);
6380 case X86::SETB_C32r:
6381 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::SBB32rr));
6382 case X86::SETB_C64r:
6383 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::SBB64rr));
6384 case X86::MMX_SET0:
6385 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::MMX_PXORrr));
6386 case X86::V_SET0:
6387 case X86::FsFLD0SS:
6388 case X86::FsFLD0SD:
6389 case X86::FsFLD0SH:
6390 case X86::FsFLD0F128:
6391 return Expand2AddrUndef(MIB, Desc: get(Opcode: HasAVX ? X86::VXORPSrr : X86::XORPSrr));
6392 case X86::AVX512_128_SET0:
6393 case X86::AVX512_FsFLD0SH:
6394 case X86::AVX512_FsFLD0SS:
6395 case X86::AVX512_FsFLD0SD:
6396 case X86::AVX512_FsFLD0F128: {
6397 bool HasVLX = Subtarget.hasVLX();
6398 Register SrcReg = MIB.getReg(Idx: 0);
6399 const TargetRegisterInfo *TRI = &getRegisterInfo();
6400 if (HasVLX || TRI->getEncodingValue(Reg: SrcReg) < 16)
6401 return Expand2AddrUndef(MIB,
6402 Desc: get(Opcode: HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
6403 // Extended register without VLX. Use a larger XOR.
6404 SrcReg =
6405 TRI->getMatchingSuperReg(Reg: SrcReg, SubIdx: X86::sub_xmm, RC: &X86::VR512RegClass);
6406 MIB->getOperand(i: 0).setReg(SrcReg);
6407 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::VPXORDZrr));
6408 }
6409 case X86::MOVSHPmr:
6410 case X86::MOVSHPrm:
6411 return expandMOVSHP(MIB, MI, TII: *this, HasAVX: Subtarget.hasAVX());
6412 case X86::V_SETALLONES:
6413 return Expand2AddrUndef(MIB,
6414 Desc: get(Opcode: HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
6415 case X86::AVX2_SETALLONES:
6416 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::VPCMPEQDYrr));
6417 case X86::AVX1_SETALLONES: {
6418 Register Reg = MIB.getReg(Idx: 0);
6419 // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
6420 MIB->setDesc(get(Opcode: X86::VCMPPSYrri));
6421 MIB.addReg(RegNo: Reg, Flags: RegState::Undef).addReg(RegNo: Reg, Flags: RegState::Undef).addImm(Val: 0xf);
6422 return true;
6423 }
6424 case X86::AVX512_128_SETALLONES:
6425 case X86::AVX512_256_SETALLONES:
6426 case X86::AVX512_512_SETALLONES: {
6427 Register Reg = MIB.getReg(Idx: 0);
6428 unsigned Opc;
6429 switch (MI.getOpcode()) {
6430 case X86::AVX512_128_SETALLONES: {
6431 if (X86::VR128RegClass.contains(Reg))
6432 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::VPCMPEQDrr));
6433
6434 Opc = X86::VPTERNLOGDZ128rri;
6435 break;
6436 }
6437 case X86::AVX512_256_SETALLONES: {
6438 if (X86::VR256RegClass.contains(Reg))
6439 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::VPCMPEQDYrr));
6440
6441 Opc = X86::VPTERNLOGDZ256rri;
6442 break;
6443 }
6444 case X86::AVX512_512_SETALLONES:
6445 Opc = X86::VPTERNLOGDZrri;
6446 break;
6447 }
6448 MIB->setDesc(get(Opcode: Opc));
6449 // VPTERNLOGD needs 3 register inputs and an immediate.
6450 // 0xff will return 1s for any input.
6451 MIB.addReg(RegNo: Reg, Flags: RegState::Undef)
6452 .addReg(RegNo: Reg, Flags: RegState::Undef)
6453 .addReg(RegNo: Reg, Flags: RegState::Undef)
6454 .addImm(Val: 0xff);
6455 return true;
6456 }
6457 case X86::AVX512_512_SEXT_MASK_32:
6458 case X86::AVX512_512_SEXT_MASK_64: {
6459 Register Reg = MIB.getReg(Idx: 0);
6460 Register MaskReg = MIB.getReg(Idx: 1);
6461 RegState MaskState = getRegState(RegOp: MIB->getOperand(i: 1));
6462 unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64)
6463 ? X86::VPTERNLOGQZrrikz
6464 : X86::VPTERNLOGDZrrikz;
6465 MI.removeOperand(OpNo: 1);
6466 MIB->setDesc(get(Opcode: Opc));
6467 // VPTERNLOG needs 3 register inputs and an immediate.
6468 // 0xff will return 1s for any input.
6469 MIB.addReg(RegNo: Reg, Flags: RegState::Undef)
6470 .addReg(RegNo: MaskReg, Flags: MaskState)
6471 .addReg(RegNo: Reg, Flags: RegState::Undef)
6472 .addReg(RegNo: Reg, Flags: RegState::Undef)
6473 .addImm(Val: 0xff);
6474 return true;
6475 }
6476 case X86::VMOVAPSZ128rm_NOVLX:
6477 return expandNOVLXLoad(MIB, TRI: &getRegisterInfo(), LoadDesc: get(Opcode: X86::VMOVAPSrm),
6478 BroadcastDesc: get(Opcode: X86::VBROADCASTF32X4Zrm), SubIdx: X86::sub_xmm);
6479 case X86::VMOVUPSZ128rm_NOVLX:
6480 return expandNOVLXLoad(MIB, TRI: &getRegisterInfo(), LoadDesc: get(Opcode: X86::VMOVUPSrm),
6481 BroadcastDesc: get(Opcode: X86::VBROADCASTF32X4Zrm), SubIdx: X86::sub_xmm);
6482 case X86::VMOVAPSZ256rm_NOVLX:
6483 return expandNOVLXLoad(MIB, TRI: &getRegisterInfo(), LoadDesc: get(Opcode: X86::VMOVAPSYrm),
6484 BroadcastDesc: get(Opcode: X86::VBROADCASTF64X4Zrm), SubIdx: X86::sub_ymm);
6485 case X86::VMOVUPSZ256rm_NOVLX:
6486 return expandNOVLXLoad(MIB, TRI: &getRegisterInfo(), LoadDesc: get(Opcode: X86::VMOVUPSYrm),
6487 BroadcastDesc: get(Opcode: X86::VBROADCASTF64X4Zrm), SubIdx: X86::sub_ymm);
6488 case X86::VMOVAPSZ128mr_NOVLX:
6489 return expandNOVLXStore(MIB, TRI: &getRegisterInfo(), StoreDesc: get(Opcode: X86::VMOVAPSmr),
6490 ExtractDesc: get(Opcode: X86::VEXTRACTF32X4Zmri), SubIdx: X86::sub_xmm);
6491 case X86::VMOVUPSZ128mr_NOVLX:
6492 return expandNOVLXStore(MIB, TRI: &getRegisterInfo(), StoreDesc: get(Opcode: X86::VMOVUPSmr),
6493 ExtractDesc: get(Opcode: X86::VEXTRACTF32X4Zmri), SubIdx: X86::sub_xmm);
6494 case X86::VMOVAPSZ256mr_NOVLX:
6495 return expandNOVLXStore(MIB, TRI: &getRegisterInfo(), StoreDesc: get(Opcode: X86::VMOVAPSYmr),
6496 ExtractDesc: get(Opcode: X86::VEXTRACTF64X4Zmri), SubIdx: X86::sub_ymm);
6497 case X86::VMOVUPSZ256mr_NOVLX:
6498 return expandNOVLXStore(MIB, TRI: &getRegisterInfo(), StoreDesc: get(Opcode: X86::VMOVUPSYmr),
6499 ExtractDesc: get(Opcode: X86::VEXTRACTF64X4Zmri), SubIdx: X86::sub_ymm);
6500 case X86::MOV32ri64: {
6501 Register Reg = MIB.getReg(Idx: 0);
6502 Register Reg32 = RI.getSubReg(Reg, Idx: X86::sub_32bit);
6503 MI.setDesc(get(Opcode: X86::MOV32ri));
6504 MIB->getOperand(i: 0).setReg(Reg32);
6505 MIB.addReg(RegNo: Reg, Flags: RegState::ImplicitDefine);
6506 return true;
6507 }
6508
6509 case X86::RDFLAGS32:
6510 case X86::RDFLAGS64: {
6511 unsigned Is64Bit = MI.getOpcode() == X86::RDFLAGS64;
6512 MachineBasicBlock &MBB = *MIB->getParent();
6513
6514 MachineInstr *NewMI = BuildMI(BB&: MBB, I&: MI, MIMD: MIB->getDebugLoc(),
6515 MCID: get(Opcode: Is64Bit ? X86::PUSHF64 : X86::PUSHF32))
6516 .getInstr();
6517
6518 // Permit reads of the EFLAGS and DF registers without them being defined.
6519 // This intrinsic exists to read external processor state in flags, such as
6520 // the trap flag, interrupt flag, and direction flag, none of which are
6521 // modeled by the backend.
6522 assert(NewMI->getOperand(2).getReg() == X86::EFLAGS &&
6523 "Unexpected register in operand! Should be EFLAGS.");
6524 NewMI->getOperand(i: 2).setIsUndef();
6525 assert(NewMI->getOperand(3).getReg() == X86::DF &&
6526 "Unexpected register in operand! Should be DF.");
6527 NewMI->getOperand(i: 3).setIsUndef();
6528
6529 MIB->setDesc(get(Opcode: Is64Bit ? X86::POP64r : X86::POP32r));
6530 return true;
6531 }
6532
6533 case X86::WRFLAGS32:
6534 case X86::WRFLAGS64: {
6535 unsigned Is64Bit = MI.getOpcode() == X86::WRFLAGS64;
6536 MachineBasicBlock &MBB = *MIB->getParent();
6537
6538 BuildMI(BB&: MBB, I&: MI, MIMD: MIB->getDebugLoc(),
6539 MCID: get(Opcode: Is64Bit ? X86::PUSH64r : X86::PUSH32r))
6540 .addReg(RegNo: MI.getOperand(i: 0).getReg());
6541 BuildMI(BB&: MBB, I&: MI, MIMD: MIB->getDebugLoc(),
6542 MCID: get(Opcode: Is64Bit ? X86::POPF64 : X86::POPF32));
6543 MI.eraseFromParent();
6544 return true;
6545 }
6546
6547 // KNL does not recognize dependency-breaking idioms for mask registers,
6548 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
6549 // Using %k0 as the undef input register is a performance heuristic based
6550 // on the assumption that %k0 is used less frequently than the other mask
6551 // registers, since it is not usable as a write mask.
6552 // FIXME: A more advanced approach would be to choose the best input mask
6553 // register based on context.
6554 case X86::KSET0B:
6555 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXORBkk), Reg: X86::K0);
6556 case X86::KSET0W:
6557 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXORWkk), Reg: X86::K0);
6558 case X86::KSET0D:
6559 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXORDkk), Reg: X86::K0);
6560 case X86::KSET0Q:
6561 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXORQkk), Reg: X86::K0);
6562 case X86::KSET1B:
6563 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXNORBkk), Reg: X86::K0);
6564 case X86::KSET1W:
6565 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXNORWkk), Reg: X86::K0);
6566 case X86::KSET1D:
6567 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXNORDkk), Reg: X86::K0);
6568 case X86::KSET1Q:
6569 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXNORQkk), Reg: X86::K0);
6570 case TargetOpcode::LOAD_STACK_GUARD:
6571 expandLoadStackGuard(MIB, TII: *this);
6572 return true;
6573 case X86::XOR64_FP:
6574 case X86::XOR32_FP:
6575 return expandXorFP(MIB, TII: *this);
6576 case X86::SHLDROT32ri:
6577 return expandSHXDROT(MIB, Desc: get(Opcode: X86::SHLD32rri8));
6578 case X86::SHLDROT64ri:
6579 return expandSHXDROT(MIB, Desc: get(Opcode: X86::SHLD64rri8));
6580 case X86::SHRDROT32ri:
6581 return expandSHXDROT(MIB, Desc: get(Opcode: X86::SHRD32rri8));
6582 case X86::SHRDROT64ri:
6583 return expandSHXDROT(MIB, Desc: get(Opcode: X86::SHRD64rri8));
6584 case X86::ADD8rr_DB:
6585 MIB->setDesc(get(Opcode: X86::OR8rr));
6586 break;
6587 case X86::ADD16rr_DB:
6588 MIB->setDesc(get(Opcode: X86::OR16rr));
6589 break;
6590 case X86::ADD32rr_DB:
6591 MIB->setDesc(get(Opcode: X86::OR32rr));
6592 break;
6593 case X86::ADD64rr_DB:
6594 MIB->setDesc(get(Opcode: X86::OR64rr));
6595 break;
6596 case X86::ADD8ri_DB:
6597 MIB->setDesc(get(Opcode: X86::OR8ri));
6598 break;
6599 case X86::ADD16ri_DB:
6600 MIB->setDesc(get(Opcode: X86::OR16ri));
6601 break;
6602 case X86::ADD32ri_DB:
6603 MIB->setDesc(get(Opcode: X86::OR32ri));
6604 break;
6605 case X86::ADD64ri32_DB:
6606 MIB->setDesc(get(Opcode: X86::OR64ri32));
6607 break;
6608 }
6609 return false;
6610}
6611
6612/// Return true for all instructions that only update
6613/// the first 32 or 64-bits of the destination register and leave the rest
6614/// unmodified. This can be used to avoid folding loads if the instructions
6615/// only update part of the destination register, and the non-updated part is
6616/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
6617/// instructions breaks the partial register dependency and it can improve
6618/// performance. e.g.:
6619///
6620/// movss (%rdi), %xmm0
6621/// cvtss2sd %xmm0, %xmm0
6622///
6623/// Instead of
6624/// cvtss2sd (%rdi), %xmm0
6625///
6626/// FIXME: This should be turned into a TSFlags.
6627///
6628static bool hasPartialRegUpdate(unsigned Opcode, const X86Subtarget &Subtarget,
6629 bool ForLoadFold = false) {
6630 switch (Opcode) {
6631 case X86::CVTSI2SSrr:
6632 case X86::CVTSI2SSrm:
6633 case X86::CVTSI642SSrr:
6634 case X86::CVTSI642SSrm:
6635 case X86::CVTSI2SDrr:
6636 case X86::CVTSI2SDrm:
6637 case X86::CVTSI642SDrr:
6638 case X86::CVTSI642SDrm:
6639 // Load folding won't effect the undef register update since the input is
6640 // a GPR.
6641 return !ForLoadFold;
6642 case X86::CVTSD2SSrr:
6643 case X86::CVTSD2SSrm:
6644 case X86::CVTSS2SDrr:
6645 case X86::CVTSS2SDrm:
6646 case X86::MOVHPDrm:
6647 case X86::MOVHPSrm:
6648 case X86::MOVLPDrm:
6649 case X86::MOVLPSrm:
6650 case X86::RCPSSr:
6651 case X86::RCPSSm:
6652 case X86::RCPSSr_Int:
6653 case X86::RCPSSm_Int:
6654 case X86::ROUNDSDri:
6655 case X86::ROUNDSDmi:
6656 case X86::ROUNDSSri:
6657 case X86::ROUNDSSmi:
6658 case X86::RSQRTSSr:
6659 case X86::RSQRTSSm:
6660 case X86::RSQRTSSr_Int:
6661 case X86::RSQRTSSm_Int:
6662 case X86::SQRTSSr:
6663 case X86::SQRTSSm:
6664 case X86::SQRTSSr_Int:
6665 case X86::SQRTSSm_Int:
6666 case X86::SQRTSDr:
6667 case X86::SQRTSDm:
6668 case X86::SQRTSDr_Int:
6669 case X86::SQRTSDm_Int:
6670 return true;
6671 case X86::VFCMULCPHZ128rm:
6672 case X86::VFCMULCPHZ128rmb:
6673 case X86::VFCMULCPHZ128rmbkz:
6674 case X86::VFCMULCPHZ128rmkz:
6675 case X86::VFCMULCPHZ128rr:
6676 case X86::VFCMULCPHZ128rrkz:
6677 case X86::VFCMULCPHZ256rm:
6678 case X86::VFCMULCPHZ256rmb:
6679 case X86::VFCMULCPHZ256rmbkz:
6680 case X86::VFCMULCPHZ256rmkz:
6681 case X86::VFCMULCPHZ256rr:
6682 case X86::VFCMULCPHZ256rrkz:
6683 case X86::VFCMULCPHZrm:
6684 case X86::VFCMULCPHZrmb:
6685 case X86::VFCMULCPHZrmbkz:
6686 case X86::VFCMULCPHZrmkz:
6687 case X86::VFCMULCPHZrr:
6688 case X86::VFCMULCPHZrrb:
6689 case X86::VFCMULCPHZrrbkz:
6690 case X86::VFCMULCPHZrrkz:
6691 case X86::VFMULCPHZ128rm:
6692 case X86::VFMULCPHZ128rmb:
6693 case X86::VFMULCPHZ128rmbkz:
6694 case X86::VFMULCPHZ128rmkz:
6695 case X86::VFMULCPHZ128rr:
6696 case X86::VFMULCPHZ128rrkz:
6697 case X86::VFMULCPHZ256rm:
6698 case X86::VFMULCPHZ256rmb:
6699 case X86::VFMULCPHZ256rmbkz:
6700 case X86::VFMULCPHZ256rmkz:
6701 case X86::VFMULCPHZ256rr:
6702 case X86::VFMULCPHZ256rrkz:
6703 case X86::VFMULCPHZrm:
6704 case X86::VFMULCPHZrmb:
6705 case X86::VFMULCPHZrmbkz:
6706 case X86::VFMULCPHZrmkz:
6707 case X86::VFMULCPHZrr:
6708 case X86::VFMULCPHZrrb:
6709 case X86::VFMULCPHZrrbkz:
6710 case X86::VFMULCPHZrrkz:
6711 case X86::VFCMULCSHZrm:
6712 case X86::VFCMULCSHZrmkz:
6713 case X86::VFCMULCSHZrr:
6714 case X86::VFCMULCSHZrrb:
6715 case X86::VFCMULCSHZrrbkz:
6716 case X86::VFCMULCSHZrrkz:
6717 case X86::VFMULCSHZrm:
6718 case X86::VFMULCSHZrmkz:
6719 case X86::VFMULCSHZrr:
6720 case X86::VFMULCSHZrrb:
6721 case X86::VFMULCSHZrrbkz:
6722 case X86::VFMULCSHZrrkz:
6723 return Subtarget.hasMULCFalseDeps();
6724 case X86::VPERMDYrm:
6725 case X86::VPERMDYrr:
6726 case X86::VPERMQYmi:
6727 case X86::VPERMQYri:
6728 case X86::VPERMPSYrm:
6729 case X86::VPERMPSYrr:
6730 case X86::VPERMPDYmi:
6731 case X86::VPERMPDYri:
6732 case X86::VPERMDZ256rm:
6733 case X86::VPERMDZ256rmb:
6734 case X86::VPERMDZ256rmbkz:
6735 case X86::VPERMDZ256rmkz:
6736 case X86::VPERMDZ256rr:
6737 case X86::VPERMDZ256rrkz:
6738 case X86::VPERMDZrm:
6739 case X86::VPERMDZrmb:
6740 case X86::VPERMDZrmbkz:
6741 case X86::VPERMDZrmkz:
6742 case X86::VPERMDZrr:
6743 case X86::VPERMDZrrkz:
6744 case X86::VPERMQZ256mbi:
6745 case X86::VPERMQZ256mbikz:
6746 case X86::VPERMQZ256mi:
6747 case X86::VPERMQZ256mikz:
6748 case X86::VPERMQZ256ri:
6749 case X86::VPERMQZ256rikz:
6750 case X86::VPERMQZ256rm:
6751 case X86::VPERMQZ256rmb:
6752 case X86::VPERMQZ256rmbkz:
6753 case X86::VPERMQZ256rmkz:
6754 case X86::VPERMQZ256rr:
6755 case X86::VPERMQZ256rrkz:
6756 case X86::VPERMQZmbi:
6757 case X86::VPERMQZmbikz:
6758 case X86::VPERMQZmi:
6759 case X86::VPERMQZmikz:
6760 case X86::VPERMQZri:
6761 case X86::VPERMQZrikz:
6762 case X86::VPERMQZrm:
6763 case X86::VPERMQZrmb:
6764 case X86::VPERMQZrmbkz:
6765 case X86::VPERMQZrmkz:
6766 case X86::VPERMQZrr:
6767 case X86::VPERMQZrrkz:
6768 case X86::VPERMPSZ256rm:
6769 case X86::VPERMPSZ256rmb:
6770 case X86::VPERMPSZ256rmbkz:
6771 case X86::VPERMPSZ256rmkz:
6772 case X86::VPERMPSZ256rr:
6773 case X86::VPERMPSZ256rrkz:
6774 case X86::VPERMPSZrm:
6775 case X86::VPERMPSZrmb:
6776 case X86::VPERMPSZrmbkz:
6777 case X86::VPERMPSZrmkz:
6778 case X86::VPERMPSZrr:
6779 case X86::VPERMPSZrrkz:
6780 case X86::VPERMPDZ256mbi:
6781 case X86::VPERMPDZ256mbikz:
6782 case X86::VPERMPDZ256mi:
6783 case X86::VPERMPDZ256mikz:
6784 case X86::VPERMPDZ256ri:
6785 case X86::VPERMPDZ256rikz:
6786 case X86::VPERMPDZ256rm:
6787 case X86::VPERMPDZ256rmb:
6788 case X86::VPERMPDZ256rmbkz:
6789 case X86::VPERMPDZ256rmkz:
6790 case X86::VPERMPDZ256rr:
6791 case X86::VPERMPDZ256rrkz:
6792 case X86::VPERMPDZmbi:
6793 case X86::VPERMPDZmbikz:
6794 case X86::VPERMPDZmi:
6795 case X86::VPERMPDZmikz:
6796 case X86::VPERMPDZri:
6797 case X86::VPERMPDZrikz:
6798 case X86::VPERMPDZrm:
6799 case X86::VPERMPDZrmb:
6800 case X86::VPERMPDZrmbkz:
6801 case X86::VPERMPDZrmkz:
6802 case X86::VPERMPDZrr:
6803 case X86::VPERMPDZrrkz:
6804 return Subtarget.hasPERMFalseDeps();
6805 case X86::VRANGEPDZ128rmbi:
6806 case X86::VRANGEPDZ128rmbikz:
6807 case X86::VRANGEPDZ128rmi:
6808 case X86::VRANGEPDZ128rmikz:
6809 case X86::VRANGEPDZ128rri:
6810 case X86::VRANGEPDZ128rrikz:
6811 case X86::VRANGEPDZ256rmbi:
6812 case X86::VRANGEPDZ256rmbikz:
6813 case X86::VRANGEPDZ256rmi:
6814 case X86::VRANGEPDZ256rmikz:
6815 case X86::VRANGEPDZ256rri:
6816 case X86::VRANGEPDZ256rrikz:
6817 case X86::VRANGEPDZrmbi:
6818 case X86::VRANGEPDZrmbikz:
6819 case X86::VRANGEPDZrmi:
6820 case X86::VRANGEPDZrmikz:
6821 case X86::VRANGEPDZrri:
6822 case X86::VRANGEPDZrrib:
6823 case X86::VRANGEPDZrribkz:
6824 case X86::VRANGEPDZrrikz:
6825 case X86::VRANGEPSZ128rmbi:
6826 case X86::VRANGEPSZ128rmbikz:
6827 case X86::VRANGEPSZ128rmi:
6828 case X86::VRANGEPSZ128rmikz:
6829 case X86::VRANGEPSZ128rri:
6830 case X86::VRANGEPSZ128rrikz:
6831 case X86::VRANGEPSZ256rmbi:
6832 case X86::VRANGEPSZ256rmbikz:
6833 case X86::VRANGEPSZ256rmi:
6834 case X86::VRANGEPSZ256rmikz:
6835 case X86::VRANGEPSZ256rri:
6836 case X86::VRANGEPSZ256rrikz:
6837 case X86::VRANGEPSZrmbi:
6838 case X86::VRANGEPSZrmbikz:
6839 case X86::VRANGEPSZrmi:
6840 case X86::VRANGEPSZrmikz:
6841 case X86::VRANGEPSZrri:
6842 case X86::VRANGEPSZrrib:
6843 case X86::VRANGEPSZrribkz:
6844 case X86::VRANGEPSZrrikz:
6845 case X86::VRANGESDZrmi:
6846 case X86::VRANGESDZrmikz:
6847 case X86::VRANGESDZrri:
6848 case X86::VRANGESDZrrib:
6849 case X86::VRANGESDZrribkz:
6850 case X86::VRANGESDZrrikz:
6851 case X86::VRANGESSZrmi:
6852 case X86::VRANGESSZrmikz:
6853 case X86::VRANGESSZrri:
6854 case X86::VRANGESSZrrib:
6855 case X86::VRANGESSZrribkz:
6856 case X86::VRANGESSZrrikz:
6857 return Subtarget.hasRANGEFalseDeps();
6858 case X86::VGETMANTSSZrmi:
6859 case X86::VGETMANTSSZrmikz:
6860 case X86::VGETMANTSSZrri:
6861 case X86::VGETMANTSSZrrib:
6862 case X86::VGETMANTSSZrribkz:
6863 case X86::VGETMANTSSZrrikz:
6864 case X86::VGETMANTSDZrmi:
6865 case X86::VGETMANTSDZrmikz:
6866 case X86::VGETMANTSDZrri:
6867 case X86::VGETMANTSDZrrib:
6868 case X86::VGETMANTSDZrribkz:
6869 case X86::VGETMANTSDZrrikz:
6870 case X86::VGETMANTSHZrmi:
6871 case X86::VGETMANTSHZrmikz:
6872 case X86::VGETMANTSHZrri:
6873 case X86::VGETMANTSHZrrib:
6874 case X86::VGETMANTSHZrribkz:
6875 case X86::VGETMANTSHZrrikz:
6876 case X86::VGETMANTPSZ128rmbi:
6877 case X86::VGETMANTPSZ128rmbikz:
6878 case X86::VGETMANTPSZ128rmi:
6879 case X86::VGETMANTPSZ128rmikz:
6880 case X86::VGETMANTPSZ256rmbi:
6881 case X86::VGETMANTPSZ256rmbikz:
6882 case X86::VGETMANTPSZ256rmi:
6883 case X86::VGETMANTPSZ256rmikz:
6884 case X86::VGETMANTPSZrmbi:
6885 case X86::VGETMANTPSZrmbikz:
6886 case X86::VGETMANTPSZrmi:
6887 case X86::VGETMANTPSZrmikz:
6888 case X86::VGETMANTPDZ128rmbi:
6889 case X86::VGETMANTPDZ128rmbikz:
6890 case X86::VGETMANTPDZ128rmi:
6891 case X86::VGETMANTPDZ128rmikz:
6892 case X86::VGETMANTPDZ256rmbi:
6893 case X86::VGETMANTPDZ256rmbikz:
6894 case X86::VGETMANTPDZ256rmi:
6895 case X86::VGETMANTPDZ256rmikz:
6896 case X86::VGETMANTPDZrmbi:
6897 case X86::VGETMANTPDZrmbikz:
6898 case X86::VGETMANTPDZrmi:
6899 case X86::VGETMANTPDZrmikz:
6900 return Subtarget.hasGETMANTFalseDeps();
6901 case X86::VPMULLQZ128rm:
6902 case X86::VPMULLQZ128rmb:
6903 case X86::VPMULLQZ128rmbkz:
6904 case X86::VPMULLQZ128rmkz:
6905 case X86::VPMULLQZ128rr:
6906 case X86::VPMULLQZ128rrkz:
6907 case X86::VPMULLQZ256rm:
6908 case X86::VPMULLQZ256rmb:
6909 case X86::VPMULLQZ256rmbkz:
6910 case X86::VPMULLQZ256rmkz:
6911 case X86::VPMULLQZ256rr:
6912 case X86::VPMULLQZ256rrkz:
6913 case X86::VPMULLQZrm:
6914 case X86::VPMULLQZrmb:
6915 case X86::VPMULLQZrmbkz:
6916 case X86::VPMULLQZrmkz:
6917 case X86::VPMULLQZrr:
6918 case X86::VPMULLQZrrkz:
6919 return Subtarget.hasMULLQFalseDeps();
6920 case X86::VPCOMPRESSBZ128rrkz:
6921 case X86::VPCOMPRESSBZ256rrkz:
6922 case X86::VPCOMPRESSBZrrkz:
6923 case X86::VPCOMPRESSWZ128rrkz:
6924 case X86::VPCOMPRESSWZ256rrkz:
6925 case X86::VPCOMPRESSWZrrkz:
6926 case X86::VPCOMPRESSDZ128rrkz:
6927 case X86::VPCOMPRESSDZ256rrkz:
6928 case X86::VPCOMPRESSDZrrkz:
6929 case X86::VPCOMPRESSQZ128rrkz:
6930 case X86::VPCOMPRESSQZ256rrkz:
6931 case X86::VPCOMPRESSQZrrkz:
6932 case X86::VCOMPRESSPSZ128rrkz:
6933 case X86::VCOMPRESSPSZ256rrkz:
6934 case X86::VCOMPRESSPSZrrkz:
6935 case X86::VCOMPRESSPDZ128rrkz:
6936 case X86::VCOMPRESSPDZ256rrkz:
6937 case X86::VCOMPRESSPDZrrkz:
6938 return Subtarget.hasCOMPRESSFalseDeps();
6939 case X86::VPEXPANDBZ128rmkz:
6940 case X86::VPEXPANDBZ128rrkz:
6941 case X86::VPEXPANDBZ256rmkz:
6942 case X86::VPEXPANDBZ256rrkz:
6943 case X86::VPEXPANDBZrmkz:
6944 case X86::VPEXPANDBZrrkz:
6945 case X86::VPEXPANDWZ128rmkz:
6946 case X86::VPEXPANDWZ128rrkz:
6947 case X86::VPEXPANDWZ256rmkz:
6948 case X86::VPEXPANDWZ256rrkz:
6949 case X86::VPEXPANDWZrmkz:
6950 case X86::VPEXPANDWZrrkz:
6951 case X86::VPEXPANDDZ128rmkz:
6952 case X86::VPEXPANDDZ128rrkz:
6953 case X86::VPEXPANDDZ256rmkz:
6954 case X86::VPEXPANDDZ256rrkz:
6955 case X86::VPEXPANDDZrmkz:
6956 case X86::VPEXPANDDZrrkz:
6957 case X86::VPEXPANDQZ128rmkz:
6958 case X86::VPEXPANDQZ128rrkz:
6959 case X86::VPEXPANDQZ256rmkz:
6960 case X86::VPEXPANDQZ256rrkz:
6961 case X86::VPEXPANDQZrmkz:
6962 case X86::VPEXPANDQZrrkz:
6963 case X86::VEXPANDPSZ128rmkz:
6964 case X86::VEXPANDPSZ128rrkz:
6965 case X86::VEXPANDPSZ256rmkz:
6966 case X86::VEXPANDPSZ256rrkz:
6967 case X86::VEXPANDPSZrmkz:
6968 case X86::VEXPANDPSZrrkz:
6969 case X86::VEXPANDPDZ128rmkz:
6970 case X86::VEXPANDPDZ128rrkz:
6971 case X86::VEXPANDPDZ256rmkz:
6972 case X86::VEXPANDPDZ256rrkz:
6973 case X86::VEXPANDPDZrmkz:
6974 case X86::VEXPANDPDZrrkz:
6975 return Subtarget.hasEXPANDFalseDeps();
6976 // GPR
6977 case X86::POPCNT32rm:
6978 case X86::POPCNT32rr:
6979 case X86::POPCNT64rm:
6980 case X86::POPCNT64rr:
6981 return Subtarget.hasPOPCNTFalseDeps();
6982 case X86::LZCNT32rm:
6983 case X86::LZCNT32rr:
6984 case X86::LZCNT64rm:
6985 case X86::LZCNT64rr:
6986 return Subtarget.hasLZCNTFalseDeps();
6987 case X86::TZCNT32rm:
6988 case X86::TZCNT32rr:
6989 case X86::TZCNT64rm:
6990 case X86::TZCNT64rr:
6991 return Subtarget.hasTZCNTFalseDeps();
6992 case X86::BLSR32rr:
6993 case X86::BLSR32rm:
6994 case X86::BLSR64rr:
6995 case X86::BLSR64rm:
6996 case X86::BLSI32rr:
6997 case X86::BLSI32rm:
6998 case X86::BLSI64rr:
6999 case X86::BLSI64rm:
7000 case X86::BLSMSK32rr:
7001 case X86::BLSMSK32rm:
7002 case X86::BLSMSK64rr:
7003 case X86::BLSMSK64rm:
7004 return Subtarget.hasBLSFalseDeps() && !ForLoadFold; // Preserve load folding
7005 }
7006
7007 return false;
7008}
7009
7010/// Inform the BreakFalseDeps pass how many idle
7011/// instructions we would like before a partial register update.
7012unsigned X86InstrInfo::getPartialRegUpdateClearance(
7013 const MachineInstr &MI, unsigned OpNum,
7014 const TargetRegisterInfo *TRI) const {
7015
7016 if (OpNum != 0)
7017 return 0;
7018
7019 // NDD ops with 8/16b results may appear to be partial register
7020 // updates after register allocation.
7021 bool HasNDDPartialWrite = false;
7022 if (X86II::hasNewDataDest(TSFlags: MI.getDesc().TSFlags)) {
7023 Register Reg = MI.getOperand(i: 0).getReg();
7024 if (!Reg.isVirtual())
7025 HasNDDPartialWrite =
7026 X86::GR8RegClass.contains(Reg) || X86::GR16RegClass.contains(Reg);
7027 }
7028
7029 if (!(HasNDDPartialWrite || hasPartialRegUpdate(Opcode: MI.getOpcode(), Subtarget)))
7030 return 0;
7031
7032 // Check if the result register is also used as a source.
7033 // For non-NDD ops, this means a partial update is wanted, hence we return 0.
7034 // For NDD ops, this means it is possible to compress the instruction
7035 // to a legacy form in CompressEVEX, which would create an unwanted partial
7036 // update, so we return the clearance.
7037 const MachineOperand &MO = MI.getOperand(i: 0);
7038 Register Reg = MO.getReg();
7039 bool ReadsReg = false;
7040 if (Reg.isVirtual())
7041 ReadsReg = (MO.readsReg() || MI.readsVirtualRegister(Reg));
7042 else
7043 ReadsReg = MI.readsRegister(Reg, TRI);
7044 if (ReadsReg != HasNDDPartialWrite)
7045 return 0;
7046
7047 // If any instructions in the clearance range are reading Reg, insert a
7048 // dependency breaking instruction, which is inexpensive and is likely to
7049 // be hidden in other instruction's cycles.
7050 return PartialRegUpdateClearance;
7051}
7052
7053// Return true for any instruction the copies the high bits of the first source
7054// operand into the unused high bits of the destination operand.
7055// Also returns true for instructions that have two inputs where one may
7056// be undef and we want it to use the same register as the other input.
7057static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
7058 bool ForLoadFold = false) {
7059 // Set the OpNum parameter to the first source operand.
7060 switch (Opcode) {
7061 case X86::MMX_PUNPCKHBWrr:
7062 case X86::MMX_PUNPCKHWDrr:
7063 case X86::MMX_PUNPCKHDQrr:
7064 case X86::MMX_PUNPCKLBWrr:
7065 case X86::MMX_PUNPCKLWDrr:
7066 case X86::MMX_PUNPCKLDQrr:
7067 case X86::MOVHLPSrr:
7068 case X86::PACKSSWBrr:
7069 case X86::PACKUSWBrr:
7070 case X86::PACKSSDWrr:
7071 case X86::PACKUSDWrr:
7072 case X86::PUNPCKHBWrr:
7073 case X86::PUNPCKLBWrr:
7074 case X86::PUNPCKHWDrr:
7075 case X86::PUNPCKLWDrr:
7076 case X86::PUNPCKHDQrr:
7077 case X86::PUNPCKLDQrr:
7078 case X86::PUNPCKHQDQrr:
7079 case X86::PUNPCKLQDQrr:
7080 case X86::SHUFPDrri:
7081 case X86::SHUFPSrri:
7082 // These instructions are sometimes used with an undef first or second
7083 // source. Return true here so BreakFalseDeps will assign this source to the
7084 // same register as the first source to avoid a false dependency.
7085 // Operand 1 of these instructions is tied so they're separate from their
7086 // VEX counterparts.
7087 return OpNum == 2 && !ForLoadFold;
7088
7089 case X86::VMOVLHPSrr:
7090 case X86::VMOVLHPSZrr:
7091 case X86::VPACKSSWBrr:
7092 case X86::VPACKUSWBrr:
7093 case X86::VPACKSSDWrr:
7094 case X86::VPACKUSDWrr:
7095 case X86::VPACKSSWBZ128rr:
7096 case X86::VPACKUSWBZ128rr:
7097 case X86::VPACKSSDWZ128rr:
7098 case X86::VPACKUSDWZ128rr:
7099 case X86::VPERM2F128rri:
7100 case X86::VPERM2I128rri:
7101 case X86::VSHUFF32X4Z256rri:
7102 case X86::VSHUFF32X4Zrri:
7103 case X86::VSHUFF64X2Z256rri:
7104 case X86::VSHUFF64X2Zrri:
7105 case X86::VSHUFI32X4Z256rri:
7106 case X86::VSHUFI32X4Zrri:
7107 case X86::VSHUFI64X2Z256rri:
7108 case X86::VSHUFI64X2Zrri:
7109 case X86::VPUNPCKHBWrr:
7110 case X86::VPUNPCKLBWrr:
7111 case X86::VPUNPCKHBWYrr:
7112 case X86::VPUNPCKLBWYrr:
7113 case X86::VPUNPCKHBWZ128rr:
7114 case X86::VPUNPCKLBWZ128rr:
7115 case X86::VPUNPCKHBWZ256rr:
7116 case X86::VPUNPCKLBWZ256rr:
7117 case X86::VPUNPCKHBWZrr:
7118 case X86::VPUNPCKLBWZrr:
7119 case X86::VPUNPCKHWDrr:
7120 case X86::VPUNPCKLWDrr:
7121 case X86::VPUNPCKHWDYrr:
7122 case X86::VPUNPCKLWDYrr:
7123 case X86::VPUNPCKHWDZ128rr:
7124 case X86::VPUNPCKLWDZ128rr:
7125 case X86::VPUNPCKHWDZ256rr:
7126 case X86::VPUNPCKLWDZ256rr:
7127 case X86::VPUNPCKHWDZrr:
7128 case X86::VPUNPCKLWDZrr:
7129 case X86::VPUNPCKHDQrr:
7130 case X86::VPUNPCKLDQrr:
7131 case X86::VPUNPCKHDQYrr:
7132 case X86::VPUNPCKLDQYrr:
7133 case X86::VPUNPCKHDQZ128rr:
7134 case X86::VPUNPCKLDQZ128rr:
7135 case X86::VPUNPCKHDQZ256rr:
7136 case X86::VPUNPCKLDQZ256rr:
7137 case X86::VPUNPCKHDQZrr:
7138 case X86::VPUNPCKLDQZrr:
7139 case X86::VPUNPCKHQDQrr:
7140 case X86::VPUNPCKLQDQrr:
7141 case X86::VPUNPCKHQDQYrr:
7142 case X86::VPUNPCKLQDQYrr:
7143 case X86::VPUNPCKHQDQZ128rr:
7144 case X86::VPUNPCKLQDQZ128rr:
7145 case X86::VPUNPCKHQDQZ256rr:
7146 case X86::VPUNPCKLQDQZ256rr:
7147 case X86::VPUNPCKHQDQZrr:
7148 case X86::VPUNPCKLQDQZrr:
7149 // These instructions are sometimes used with an undef first or second
7150 // source. Return true here so BreakFalseDeps will assign this source to the
7151 // same register as the first source to avoid a false dependency.
7152 return (OpNum == 1 || OpNum == 2) && !ForLoadFold;
7153
7154 case X86::VCVTSI2SSrr:
7155 case X86::VCVTSI2SSrm:
7156 case X86::VCVTSI2SSrr_Int:
7157 case X86::VCVTSI2SSrm_Int:
7158 case X86::VCVTSI642SSrr:
7159 case X86::VCVTSI642SSrm:
7160 case X86::VCVTSI642SSrr_Int:
7161 case X86::VCVTSI642SSrm_Int:
7162 case X86::VCVTSI2SDrr:
7163 case X86::VCVTSI2SDrm:
7164 case X86::VCVTSI2SDrr_Int:
7165 case X86::VCVTSI2SDrm_Int:
7166 case X86::VCVTSI642SDrr:
7167 case X86::VCVTSI642SDrm:
7168 case X86::VCVTSI642SDrr_Int:
7169 case X86::VCVTSI642SDrm_Int:
7170 // AVX-512
7171 case X86::VCVTSI2SSZrr:
7172 case X86::VCVTSI2SSZrm:
7173 case X86::VCVTSI2SSZrr_Int:
7174 case X86::VCVTSI2SSZrrb_Int:
7175 case X86::VCVTSI2SSZrm_Int:
7176 case X86::VCVTSI642SSZrr:
7177 case X86::VCVTSI642SSZrm:
7178 case X86::VCVTSI642SSZrr_Int:
7179 case X86::VCVTSI642SSZrrb_Int:
7180 case X86::VCVTSI642SSZrm_Int:
7181 case X86::VCVTSI2SDZrr:
7182 case X86::VCVTSI2SDZrm:
7183 case X86::VCVTSI2SDZrr_Int:
7184 case X86::VCVTSI2SDZrm_Int:
7185 case X86::VCVTSI642SDZrr:
7186 case X86::VCVTSI642SDZrm:
7187 case X86::VCVTSI642SDZrr_Int:
7188 case X86::VCVTSI642SDZrrb_Int:
7189 case X86::VCVTSI642SDZrm_Int:
7190 case X86::VCVTUSI2SSZrr:
7191 case X86::VCVTUSI2SSZrm:
7192 case X86::VCVTUSI2SSZrr_Int:
7193 case X86::VCVTUSI2SSZrrb_Int:
7194 case X86::VCVTUSI2SSZrm_Int:
7195 case X86::VCVTUSI642SSZrr:
7196 case X86::VCVTUSI642SSZrm:
7197 case X86::VCVTUSI642SSZrr_Int:
7198 case X86::VCVTUSI642SSZrrb_Int:
7199 case X86::VCVTUSI642SSZrm_Int:
7200 case X86::VCVTUSI2SDZrr:
7201 case X86::VCVTUSI2SDZrm:
7202 case X86::VCVTUSI2SDZrr_Int:
7203 case X86::VCVTUSI2SDZrm_Int:
7204 case X86::VCVTUSI642SDZrr:
7205 case X86::VCVTUSI642SDZrm:
7206 case X86::VCVTUSI642SDZrr_Int:
7207 case X86::VCVTUSI642SDZrrb_Int:
7208 case X86::VCVTUSI642SDZrm_Int:
7209 case X86::VCVTSI2SHZrr:
7210 case X86::VCVTSI2SHZrm:
7211 case X86::VCVTSI2SHZrr_Int:
7212 case X86::VCVTSI2SHZrrb_Int:
7213 case X86::VCVTSI2SHZrm_Int:
7214 case X86::VCVTSI642SHZrr:
7215 case X86::VCVTSI642SHZrm:
7216 case X86::VCVTSI642SHZrr_Int:
7217 case X86::VCVTSI642SHZrrb_Int:
7218 case X86::VCVTSI642SHZrm_Int:
7219 case X86::VCVTUSI2SHZrr:
7220 case X86::VCVTUSI2SHZrm:
7221 case X86::VCVTUSI2SHZrr_Int:
7222 case X86::VCVTUSI2SHZrrb_Int:
7223 case X86::VCVTUSI2SHZrm_Int:
7224 case X86::VCVTUSI642SHZrr:
7225 case X86::VCVTUSI642SHZrm:
7226 case X86::VCVTUSI642SHZrr_Int:
7227 case X86::VCVTUSI642SHZrrb_Int:
7228 case X86::VCVTUSI642SHZrm_Int:
7229 // Load folding won't effect the undef register update since the input is
7230 // a GPR.
7231 return OpNum == 1 && !ForLoadFold;
7232 case X86::VCVTSD2SSrr:
7233 case X86::VCVTSD2SSrm:
7234 case X86::VCVTSD2SSrr_Int:
7235 case X86::VCVTSD2SSrm_Int:
7236 case X86::VCVTSS2SDrr:
7237 case X86::VCVTSS2SDrm:
7238 case X86::VCVTSS2SDrr_Int:
7239 case X86::VCVTSS2SDrm_Int:
7240 case X86::VRCPSSr:
7241 case X86::VRCPSSr_Int:
7242 case X86::VRCPSSm:
7243 case X86::VRCPSSm_Int:
7244 case X86::VROUNDSDri:
7245 case X86::VROUNDSDmi:
7246 case X86::VROUNDSDri_Int:
7247 case X86::VROUNDSDmi_Int:
7248 case X86::VROUNDSSri:
7249 case X86::VROUNDSSmi:
7250 case X86::VROUNDSSri_Int:
7251 case X86::VROUNDSSmi_Int:
7252 case X86::VRSQRTSSr:
7253 case X86::VRSQRTSSr_Int:
7254 case X86::VRSQRTSSm:
7255 case X86::VRSQRTSSm_Int:
7256 case X86::VSQRTSSr:
7257 case X86::VSQRTSSr_Int:
7258 case X86::VSQRTSSm:
7259 case X86::VSQRTSSm_Int:
7260 case X86::VSQRTSDr:
7261 case X86::VSQRTSDr_Int:
7262 case X86::VSQRTSDm:
7263 case X86::VSQRTSDm_Int:
7264 // AVX-512
7265 case X86::VCVTSD2SSZrr:
7266 case X86::VCVTSD2SSZrr_Int:
7267 case X86::VCVTSD2SSZrrb_Int:
7268 case X86::VCVTSD2SSZrm:
7269 case X86::VCVTSD2SSZrm_Int:
7270 case X86::VCVTSS2SDZrr:
7271 case X86::VCVTSS2SDZrr_Int:
7272 case X86::VCVTSS2SDZrrb_Int:
7273 case X86::VCVTSS2SDZrm:
7274 case X86::VCVTSS2SDZrm_Int:
7275 case X86::VGETEXPSDZr:
7276 case X86::VGETEXPSDZrb:
7277 case X86::VGETEXPSDZm:
7278 case X86::VGETEXPSSZr:
7279 case X86::VGETEXPSSZrb:
7280 case X86::VGETEXPSSZm:
7281 case X86::VGETMANTSDZrri:
7282 case X86::VGETMANTSDZrrib:
7283 case X86::VGETMANTSDZrmi:
7284 case X86::VGETMANTSSZrri:
7285 case X86::VGETMANTSSZrrib:
7286 case X86::VGETMANTSSZrmi:
7287 case X86::VRNDSCALESDZrri:
7288 case X86::VRNDSCALESDZrri_Int:
7289 case X86::VRNDSCALESDZrrib_Int:
7290 case X86::VRNDSCALESDZrmi:
7291 case X86::VRNDSCALESDZrmi_Int:
7292 case X86::VRNDSCALESSZrri:
7293 case X86::VRNDSCALESSZrri_Int:
7294 case X86::VRNDSCALESSZrrib_Int:
7295 case X86::VRNDSCALESSZrmi:
7296 case X86::VRNDSCALESSZrmi_Int:
7297 case X86::VRCP14SDZrr:
7298 case X86::VRCP14SDZrm:
7299 case X86::VRCP14SSZrr:
7300 case X86::VRCP14SSZrm:
7301 case X86::VRCPSHZrr:
7302 case X86::VRCPSHZrm:
7303 case X86::VRSQRTSHZrr:
7304 case X86::VRSQRTSHZrm:
7305 case X86::VREDUCESHZrmi:
7306 case X86::VREDUCESHZrri:
7307 case X86::VREDUCESHZrrib:
7308 case X86::VGETEXPSHZr:
7309 case X86::VGETEXPSHZrb:
7310 case X86::VGETEXPSHZm:
7311 case X86::VGETMANTSHZrri:
7312 case X86::VGETMANTSHZrrib:
7313 case X86::VGETMANTSHZrmi:
7314 case X86::VRNDSCALESHZrri:
7315 case X86::VRNDSCALESHZrri_Int:
7316 case X86::VRNDSCALESHZrrib_Int:
7317 case X86::VRNDSCALESHZrmi:
7318 case X86::VRNDSCALESHZrmi_Int:
7319 case X86::VSQRTSHZr:
7320 case X86::VSQRTSHZr_Int:
7321 case X86::VSQRTSHZrb_Int:
7322 case X86::VSQRTSHZm:
7323 case X86::VSQRTSHZm_Int:
7324 case X86::VRCP28SDZr:
7325 case X86::VRCP28SDZrb:
7326 case X86::VRCP28SDZm:
7327 case X86::VRCP28SSZr:
7328 case X86::VRCP28SSZrb:
7329 case X86::VRCP28SSZm:
7330 case X86::VREDUCESSZrmi:
7331 case X86::VREDUCESSZrri:
7332 case X86::VREDUCESSZrrib:
7333 case X86::VRSQRT14SDZrr:
7334 case X86::VRSQRT14SDZrm:
7335 case X86::VRSQRT14SSZrr:
7336 case X86::VRSQRT14SSZrm:
7337 case X86::VRSQRT28SDZr:
7338 case X86::VRSQRT28SDZrb:
7339 case X86::VRSQRT28SDZm:
7340 case X86::VRSQRT28SSZr:
7341 case X86::VRSQRT28SSZrb:
7342 case X86::VRSQRT28SSZm:
7343 case X86::VSQRTSSZr:
7344 case X86::VSQRTSSZr_Int:
7345 case X86::VSQRTSSZrb_Int:
7346 case X86::VSQRTSSZm:
7347 case X86::VSQRTSSZm_Int:
7348 case X86::VSQRTSDZr:
7349 case X86::VSQRTSDZr_Int:
7350 case X86::VSQRTSDZrb_Int:
7351 case X86::VSQRTSDZm:
7352 case X86::VSQRTSDZm_Int:
7353 case X86::VCVTSD2SHZrr:
7354 case X86::VCVTSD2SHZrr_Int:
7355 case X86::VCVTSD2SHZrrb_Int:
7356 case X86::VCVTSD2SHZrm:
7357 case X86::VCVTSD2SHZrm_Int:
7358 case X86::VCVTSS2SHZrr:
7359 case X86::VCVTSS2SHZrr_Int:
7360 case X86::VCVTSS2SHZrrb_Int:
7361 case X86::VCVTSS2SHZrm:
7362 case X86::VCVTSS2SHZrm_Int:
7363 case X86::VCVTSH2SDZrr:
7364 case X86::VCVTSH2SDZrr_Int:
7365 case X86::VCVTSH2SDZrrb_Int:
7366 case X86::VCVTSH2SDZrm:
7367 case X86::VCVTSH2SDZrm_Int:
7368 case X86::VCVTSH2SSZrr:
7369 case X86::VCVTSH2SSZrr_Int:
7370 case X86::VCVTSH2SSZrrb_Int:
7371 case X86::VCVTSH2SSZrm:
7372 case X86::VCVTSH2SSZrm_Int:
7373 return OpNum == 1;
7374 case X86::VMOVSSZrrk:
7375 case X86::VMOVSDZrrk:
7376 return OpNum == 3 && !ForLoadFold;
7377 case X86::VMOVSSZrrkz:
7378 case X86::VMOVSDZrrkz:
7379 return OpNum == 2 && !ForLoadFold;
7380 }
7381
7382 return false;
7383}
7384
7385/// Inform the BreakFalseDeps pass how many idle instructions we would like
7386/// before certain undef register reads.
7387///
7388/// This catches the VCVTSI2SD family of instructions:
7389///
7390/// vcvtsi2sdq %rax, undef %xmm0, %xmm14
7391///
7392/// We should to be careful *not* to catch VXOR idioms which are presumably
7393/// handled specially in the pipeline:
7394///
7395/// vxorps undef %xmm1, undef %xmm1, %xmm1
7396///
7397/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
7398/// high bits that are passed-through are not live.
7399unsigned
7400X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
7401 const TargetRegisterInfo *TRI) const {
7402 const MachineOperand &MO = MI.getOperand(i: OpNum);
7403 if (MO.getReg().isPhysical() && hasUndefRegUpdate(Opcode: MI.getOpcode(), OpNum))
7404 return UndefRegClearance;
7405
7406 return 0;
7407}
7408
7409void X86InstrInfo::breakPartialRegDependency(
7410 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
7411 Register Reg = MI.getOperand(i: OpNum).getReg();
7412 // If MI kills this register, the false dependence is already broken.
7413 if (MI.killsRegister(Reg, TRI))
7414 return;
7415
7416 if (X86::VR128RegClass.contains(Reg)) {
7417 // These instructions are all floating point domain, so xorps is the best
7418 // choice.
7419 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
7420 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc), DestReg: Reg)
7421 .addReg(RegNo: Reg, Flags: RegState::Undef)
7422 .addReg(RegNo: Reg, Flags: RegState::Undef);
7423 MI.addRegisterKilled(IncomingReg: Reg, RegInfo: TRI, AddIfNotFound: true);
7424 } else if (X86::VR256RegClass.contains(Reg)) {
7425 // Use vxorps to clear the full ymm register.
7426 // It wants to read and write the xmm sub-register.
7427 Register XReg = TRI->getSubReg(Reg, Idx: X86::sub_xmm);
7428 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::VXORPSrr), DestReg: XReg)
7429 .addReg(RegNo: XReg, Flags: RegState::Undef)
7430 .addReg(RegNo: XReg, Flags: RegState::Undef)
7431 .addReg(RegNo: Reg, Flags: RegState::ImplicitDefine);
7432 MI.addRegisterKilled(IncomingReg: Reg, RegInfo: TRI, AddIfNotFound: true);
7433 } else if (X86::VR128XRegClass.contains(Reg)) {
7434 // Only handle VLX targets.
7435 if (!Subtarget.hasVLX())
7436 return;
7437 // Since vxorps requires AVX512DQ, vpxord should be the best choice.
7438 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::VPXORDZ128rr), DestReg: Reg)
7439 .addReg(RegNo: Reg, Flags: RegState::Undef)
7440 .addReg(RegNo: Reg, Flags: RegState::Undef);
7441 MI.addRegisterKilled(IncomingReg: Reg, RegInfo: TRI, AddIfNotFound: true);
7442 } else if (X86::VR256XRegClass.contains(Reg) ||
7443 X86::VR512RegClass.contains(Reg)) {
7444 // Only handle VLX targets.
7445 if (!Subtarget.hasVLX())
7446 return;
7447 // Use vpxord to clear the full ymm/zmm register.
7448 // It wants to read and write the xmm sub-register.
7449 Register XReg = TRI->getSubReg(Reg, Idx: X86::sub_xmm);
7450 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::VPXORDZ128rr), DestReg: XReg)
7451 .addReg(RegNo: XReg, Flags: RegState::Undef)
7452 .addReg(RegNo: XReg, Flags: RegState::Undef)
7453 .addReg(RegNo: Reg, Flags: RegState::ImplicitDefine);
7454 MI.addRegisterKilled(IncomingReg: Reg, RegInfo: TRI, AddIfNotFound: true);
7455 } else if (X86::GR64RegClass.contains(Reg)) {
7456 // Using XOR32rr because it has shorter encoding and zeros up the upper bits
7457 // as well.
7458 Register XReg = TRI->getSubReg(Reg, Idx: X86::sub_32bit);
7459 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::XOR32rr), DestReg: XReg)
7460 .addReg(RegNo: XReg, Flags: RegState::Undef)
7461 .addReg(RegNo: XReg, Flags: RegState::Undef)
7462 .addReg(RegNo: Reg, Flags: RegState::ImplicitDefine);
7463 MI.addRegisterKilled(IncomingReg: Reg, RegInfo: TRI, AddIfNotFound: true);
7464 } else if (X86::GR32RegClass.contains(Reg)) {
7465 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::XOR32rr), DestReg: Reg)
7466 .addReg(RegNo: Reg, Flags: RegState::Undef)
7467 .addReg(RegNo: Reg, Flags: RegState::Undef);
7468 MI.addRegisterKilled(IncomingReg: Reg, RegInfo: TRI, AddIfNotFound: true);
7469 } else if ((X86::GR16RegClass.contains(Reg) ||
7470 X86::GR8RegClass.contains(Reg)) &&
7471 X86II::hasNewDataDest(TSFlags: MI.getDesc().TSFlags)) {
7472 // This case is only expected for NDD ops which appear to be partial
7473 // writes, but are not due to the zeroing of the upper part. Here
7474 // we add an implicit def of the superegister, which prevents
7475 // CompressEVEX from converting this to a legacy form.
7476 Register SuperReg = getX86SubSuperRegister(Reg, Size: 64);
7477 MachineInstrBuilder BuildMI(*MI.getParent()->getParent(), &MI);
7478 if (!MI.definesRegister(Reg: SuperReg, /*TRI=*/nullptr))
7479 BuildMI.addReg(RegNo: SuperReg, Flags: RegState::ImplicitDefine);
7480 }
7481}
7482
7483static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
7484 int PtrOffset = 0) {
7485 unsigned NumAddrOps = MOs.size();
7486
7487 if (NumAddrOps < 4) {
7488 // FrameIndex only - add an immediate offset (whether its zero or not).
7489 for (unsigned i = 0; i != NumAddrOps; ++i)
7490 MIB.add(MO: MOs[i]);
7491 addOffset(MIB, Offset: PtrOffset);
7492 } else {
7493 // General Memory Addressing - we need to add any offset to an existing
7494 // offset.
7495 assert(MOs.size() == 5 && "Unexpected memory operand list length");
7496 for (unsigned i = 0; i != NumAddrOps; ++i) {
7497 const MachineOperand &MO = MOs[i];
7498 if (i == 3 && PtrOffset != 0) {
7499 MIB.addDisp(Disp: MO, off: PtrOffset);
7500 } else {
7501 MIB.add(MO);
7502 }
7503 }
7504 }
7505}
7506
7507static void updateOperandRegConstraints(MachineFunction &MF,
7508 MachineInstr &NewMI,
7509 const TargetInstrInfo &TII) {
7510 MachineRegisterInfo &MRI = MF.getRegInfo();
7511
7512 for (int Idx : llvm::seq<int>(Begin: 0, End: NewMI.getNumOperands())) {
7513 MachineOperand &MO = NewMI.getOperand(i: Idx);
7514 // We only need to update constraints on virtual register operands.
7515 if (!MO.isReg())
7516 continue;
7517 Register Reg = MO.getReg();
7518 if (!Reg.isVirtual())
7519 continue;
7520
7521 auto *NewRC =
7522 MRI.constrainRegClass(Reg, RC: TII.getRegClass(MCID: NewMI.getDesc(), OpNum: Idx));
7523 if (!NewRC) {
7524 LLVM_DEBUG(
7525 dbgs() << "WARNING: Unable to update register constraint for operand "
7526 << Idx << " of instruction:\n";
7527 NewMI.dump(); dbgs() << "\n");
7528 }
7529 }
7530}
7531
7532static MachineInstr *fuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
7533 ArrayRef<MachineOperand> MOs,
7534 MachineBasicBlock::iterator InsertPt,
7535 MachineInstr &MI,
7536 const TargetInstrInfo &TII) {
7537 // Create the base instruction with the memory operand as the first part.
7538 // Omit the implicit operands, something BuildMI can't do.
7539 MachineInstr *NewMI =
7540 MF.CreateMachineInstr(MCID: TII.get(Opcode), DL: MI.getDebugLoc(), NoImplicit: true);
7541 MachineInstrBuilder MIB(MF, NewMI);
7542 addOperands(MIB, MOs);
7543
7544 // Loop over the rest of the ri operands, converting them over.
7545 unsigned NumOps = MI.getDesc().getNumOperands() - 2;
7546 for (unsigned i = 0; i != NumOps; ++i) {
7547 MachineOperand &MO = MI.getOperand(i: i + 2);
7548 MIB.add(MO);
7549 }
7550 for (const MachineOperand &MO : llvm::drop_begin(RangeOrContainer: MI.operands(), N: NumOps + 2))
7551 MIB.add(MO);
7552
7553 updateOperandRegConstraints(MF, NewMI&: *NewMI, TII);
7554
7555 MachineBasicBlock *MBB = InsertPt->getParent();
7556 MBB->insert(I: InsertPt, MI: NewMI);
7557
7558 return MIB;
7559}
7560
7561static MachineInstr *fuseInst(MachineFunction &MF, unsigned Opcode,
7562 unsigned OpNo, ArrayRef<MachineOperand> MOs,
7563 MachineBasicBlock::iterator InsertPt,
7564 MachineInstr &MI, const TargetInstrInfo &TII,
7565 int PtrOffset = 0) {
7566 // Omit the implicit operands, something BuildMI can't do.
7567 MachineInstr *NewMI =
7568 MF.CreateMachineInstr(MCID: TII.get(Opcode), DL: MI.getDebugLoc(), NoImplicit: true);
7569 MachineInstrBuilder MIB(MF, NewMI);
7570
7571 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
7572 MachineOperand &MO = MI.getOperand(i);
7573 if (i == OpNo) {
7574 assert(MO.isReg() && "Expected to fold into reg operand!");
7575 addOperands(MIB, MOs, PtrOffset);
7576 } else {
7577 MIB.add(MO);
7578 }
7579 }
7580
7581 updateOperandRegConstraints(MF, NewMI&: *NewMI, TII);
7582
7583 // Copy the NoFPExcept flag from the instruction we're fusing.
7584 if (MI.getFlag(Flag: MachineInstr::MIFlag::NoFPExcept))
7585 NewMI->setFlag(MachineInstr::MIFlag::NoFPExcept);
7586
7587 MachineBasicBlock *MBB = InsertPt->getParent();
7588 MBB->insert(I: InsertPt, MI: NewMI);
7589
7590 return MIB;
7591}
7592
7593static MachineInstr *makeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
7594 ArrayRef<MachineOperand> MOs,
7595 MachineBasicBlock::iterator InsertPt,
7596 MachineInstr &MI) {
7597 MachineInstrBuilder MIB = BuildMI(BB&: *InsertPt->getParent(), I: InsertPt,
7598 MIMD: MI.getDebugLoc(), MCID: TII.get(Opcode));
7599 addOperands(MIB, MOs);
7600 return MIB.addImm(Val: 0);
7601}
7602
7603MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
7604 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
7605 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
7606 unsigned Size, Align Alignment) const {
7607 switch (MI.getOpcode()) {
7608 case X86::INSERTPSrri:
7609 case X86::VINSERTPSrri:
7610 case X86::VINSERTPSZrri:
7611 // Attempt to convert the load of inserted vector into a fold load
7612 // of a single float.
7613 if (OpNum == 2) {
7614 unsigned Imm = MI.getOperand(i: MI.getNumOperands() - 1).getImm();
7615 unsigned ZMask = Imm & 15;
7616 unsigned DstIdx = (Imm >> 4) & 3;
7617 unsigned SrcIdx = (Imm >> 6) & 3;
7618
7619 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7620 const TargetRegisterClass *RC = getRegClass(MCID: MI.getDesc(), OpNum);
7621 unsigned RCSize = TRI.getRegSizeInBits(RC: *RC) / 8;
7622 if ((Size == 0 || Size >= 16) && RCSize >= 16 &&
7623 (MI.getOpcode() != X86::INSERTPSrri || Alignment >= Align(4))) {
7624 int PtrOffset = SrcIdx * 4;
7625 unsigned NewImm = (DstIdx << 4) | ZMask;
7626 unsigned NewOpCode =
7627 (MI.getOpcode() == X86::VINSERTPSZrri) ? X86::VINSERTPSZrmi
7628 : (MI.getOpcode() == X86::VINSERTPSrri) ? X86::VINSERTPSrmi
7629 : X86::INSERTPSrmi;
7630 MachineInstr *NewMI =
7631 fuseInst(MF, Opcode: NewOpCode, OpNo: OpNum, MOs, InsertPt, MI, TII: *this, PtrOffset);
7632 NewMI->getOperand(i: NewMI->getNumOperands() - 1).setImm(NewImm);
7633 return NewMI;
7634 }
7635 }
7636 break;
7637 case X86::MOVHLPSrr:
7638 case X86::VMOVHLPSrr:
7639 case X86::VMOVHLPSZrr:
7640 // Move the upper 64-bits of the second operand to the lower 64-bits.
7641 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
7642 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
7643 if (OpNum == 2) {
7644 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7645 const TargetRegisterClass *RC = getRegClass(MCID: MI.getDesc(), OpNum);
7646 unsigned RCSize = TRI.getRegSizeInBits(RC: *RC) / 8;
7647 if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(8)) {
7648 unsigned NewOpCode =
7649 (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm
7650 : (MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm
7651 : X86::MOVLPSrm;
7652 MachineInstr *NewMI =
7653 fuseInst(MF, Opcode: NewOpCode, OpNo: OpNum, MOs, InsertPt, MI, TII: *this, PtrOffset: 8);
7654 return NewMI;
7655 }
7656 }
7657 break;
7658 case X86::UNPCKLPDrr:
7659 // If we won't be able to fold this to the memory form of UNPCKL, use
7660 // MOVHPD instead. Done as custom because we can't have this in the load
7661 // table twice.
7662 if (OpNum == 2) {
7663 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7664 const TargetRegisterClass *RC = getRegClass(MCID: MI.getDesc(), OpNum);
7665 unsigned RCSize = TRI.getRegSizeInBits(RC: *RC) / 8;
7666 if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment < Align(16)) {
7667 MachineInstr *NewMI =
7668 fuseInst(MF, Opcode: X86::MOVHPDrm, OpNo: OpNum, MOs, InsertPt, MI, TII: *this);
7669 return NewMI;
7670 }
7671 }
7672 break;
7673 case X86::MOV32r0:
7674 if (auto *NewMI =
7675 makeM0Inst(TII: *this, Opcode: (Size == 4) ? X86::MOV32mi : X86::MOV64mi32, MOs,
7676 InsertPt, MI))
7677 return NewMI;
7678 break;
7679 }
7680
7681 return nullptr;
7682}
7683
7684static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
7685 MachineInstr &MI) {
7686 if (!hasUndefRegUpdate(Opcode: MI.getOpcode(), OpNum: 1, /*ForLoadFold*/ true) ||
7687 !MI.getOperand(i: 1).isReg())
7688 return false;
7689
7690 // The are two cases we need to handle depending on where in the pipeline
7691 // the folding attempt is being made.
7692 // -Register has the undef flag set.
7693 // -Register is produced by the IMPLICIT_DEF instruction.
7694
7695 if (MI.getOperand(i: 1).isUndef())
7696 return true;
7697
7698 MachineRegisterInfo &RegInfo = MF.getRegInfo();
7699 MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(Reg: MI.getOperand(i: 1).getReg());
7700 return VRegDef && VRegDef->isImplicitDef();
7701}
7702
7703unsigned X86InstrInfo::commuteOperandsForFold(MachineInstr &MI,
7704 unsigned Idx1) const {
7705 unsigned Idx2 = CommuteAnyOperandIndex;
7706 if (!findCommutedOpIndices(MI, SrcOpIdx1&: Idx1, SrcOpIdx2&: Idx2))
7707 return Idx1;
7708
7709 bool HasDef = MI.getDesc().getNumDefs();
7710 Register Reg0 = HasDef ? MI.getOperand(i: 0).getReg() : Register();
7711 Register Reg1 = MI.getOperand(i: Idx1).getReg();
7712 Register Reg2 = MI.getOperand(i: Idx2).getReg();
7713 bool Tied1 = 0 == MI.getDesc().getOperandConstraint(OpNum: Idx1, Constraint: MCOI::TIED_TO);
7714 bool Tied2 = 0 == MI.getDesc().getOperandConstraint(OpNum: Idx2, Constraint: MCOI::TIED_TO);
7715
7716 // If either of the commutable operands are tied to the destination
7717 // then we can not commute + fold.
7718 if ((HasDef && Reg0 == Reg1 && Tied1) || (HasDef && Reg0 == Reg2 && Tied2))
7719 return Idx1;
7720
7721 return commuteInstruction(MI, NewMI: false, OpIdx1: Idx1, OpIdx2: Idx2) ? Idx2 : Idx1;
7722}
7723
7724static void printFailMsgforFold(const MachineInstr &MI, unsigned Idx) {
7725 if (PrintFailedFusing && !MI.isCopy())
7726 dbgs() << "We failed to fuse operand " << Idx << " in " << MI;
7727}
7728
7729MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
7730 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
7731 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
7732 unsigned Size, Align Alignment, bool AllowCommute, MachineInstr *&CopyMI,
7733 VirtRegMap *VRM) const {
7734 bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
7735 bool isSlowIndirectCall = Subtarget.slowIndirectCall();
7736 unsigned Opc = MI.getOpcode();
7737
7738 // For CPUs that favor the register form of a call,
7739 // do not fold loads into calls, unless optimizing for size aggressively.
7740 if ((isSlowTwoMemOps || isSlowIndirectCall) &&
7741 !MF.getFunction().hasMinSize() &&
7742 (Opc == X86::CALL32r || Opc == X86::CALL64r ||
7743 Opc == X86::CALL64r_ImpCall))
7744 return nullptr;
7745
7746 // For CPUs that favor the register form of a push,
7747 // do not fold loads into pushes, unless optimizing for size aggressively.
7748 if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
7749 (Opc == X86::PUSH16r || Opc == X86::PUSH32r || Opc == X86::PUSH64r))
7750 return nullptr;
7751
7752 // Avoid partial and undef register update stalls unless optimizing for size.
7753 if (!MF.getFunction().hasOptSize() &&
7754 (hasPartialRegUpdate(Opcode: Opc, Subtarget, /*ForLoadFold*/ true) ||
7755 shouldPreventUndefRegUpdateMemFold(MF, MI)))
7756 return nullptr;
7757
7758 unsigned NumOps = MI.getDesc().getNumOperands();
7759 bool IsTwoAddr = NumOps > 1 && OpNum < 2 && MI.getOperand(i: 0).isReg() &&
7760 MI.getOperand(i: 1).isReg() &&
7761 MI.getOperand(i: 0).getReg() == MI.getOperand(i: 1).getReg();
7762
7763 // FIXME: AsmPrinter doesn't know how to handle
7764 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
7765 if (Opc == X86::ADD32ri &&
7766 MI.getOperand(i: 2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
7767 return nullptr;
7768
7769 // GOTTPOFF relocation loads can only be folded into add instructions.
7770 // FIXME: Need to exclude other relocations that only support specific
7771 // instructions.
7772 if (MOs.size() == X86::AddrNumOperands &&
7773 MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
7774 Opc != X86::ADD64rr)
7775 return nullptr;
7776
7777 // Don't fold loads into indirect calls that need a KCFI check as we'll
7778 // have to unfold these in X86TargetLowering::EmitKCFICheck anyway.
7779 if (MI.isCall() && MI.getCFIType())
7780 return nullptr;
7781
7782 // Attempt to fold any custom cases we have.
7783 if (auto *CustomMI = foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt,
7784 Size, Alignment))
7785 return CustomMI;
7786
7787 // Folding a memory location into the two-address part of a two-address
7788 // instruction is different than folding it other places. It requires
7789 // replacing the *two* registers with the memory location.
7790 //
7791 // Utilize the mapping NonNDD -> RMW for the NDD variant.
7792 unsigned NonNDOpc = Subtarget.hasNDD() ? X86::getNonNDVariant(Opc) : 0U;
7793 // Utilize the mapping NonNDD if NDD memory variant is not preferred.
7794 bool NoNDDM = NonNDOpc && !Subtarget.hasNDDM();
7795
7796 MachineRegisterInfo &MRI = MF.getRegInfo();
7797 if (NoNDDM && !IsTwoAddr && !MRI.isSSA()) {
7798 // Bail out if dst has subreg. It happens during register-coalescer from
7799 // 704B %19:gr32 = SUB32rr_ND killed %0:gr32, killed %7:gr32, ...
7800 // 752B undef %23.sub_32bit:gr64 = COPY killed %19:gr32
7801 // 768B %25:gr32 = LEA64_32r killed %23:gr64, 1, killed %21:gr64_nosp, ...
7802 // to
7803 // 704B undef %23.sub_32bit:gr64_with_sub_8bit = SUB32rr_ND %0:gr32, ...
7804 // 768B %25:gr32 = LEA64_32r %23:gr64_with_sub_8bit, 1, %21:gr64_nosp, ...
7805 // Machine verifier fails if we try to tie %23 to the source.
7806 if (MI.getOperand(i: 0).getSubReg())
7807 return nullptr;
7808
7809 // Bail out if dst has been assigned a physical register. Otherwise, we
7810 // cannot update LiveRegMatrix properly.
7811 Register Dst = MI.getOperand(i: 0).getReg();
7812 if (VRM && Dst != MI.getOperand(i: 1).getReg() &&
7813 (!Dst.isVirtual() || VRM->getPhys(virtReg: Dst)))
7814 return nullptr;
7815 }
7816
7817 const X86FoldTableEntry *I =
7818 IsTwoAddr ? lookupTwoAddrFoldTable(RegOp: NonNDOpc ? NonNDOpc : Opc)
7819 : lookupFoldTable(RegOp: NoNDDM ? NonNDOpc : Opc, OpNum);
7820
7821 MachineInstr *NewMI = nullptr;
7822 if (I) {
7823 unsigned Opcode = I->DstOp;
7824 if (Alignment <
7825 Align(1ULL << ((I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT)))
7826 return nullptr;
7827 bool NarrowToMOV32rm = false;
7828 if (Size) {
7829 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7830 const TargetRegisterClass *RC = getRegClass(MCID: MI.getDesc(), OpNum);
7831 unsigned RCSize = TRI.getRegSizeInBits(RC: *RC) / 8;
7832 // Check if it's safe to fold the load. If the size of the object is
7833 // narrower than the load width, then it's not.
7834 // FIXME: Allow scalar intrinsic instructions like ADDSSrm_Int.
7835 if ((I->Flags & TB_FOLDED_LOAD) && Size < RCSize) {
7836 // If this is a 64-bit load, but the spill slot is 32, then we can do
7837 // a 32-bit load which is implicitly zero-extended. This likely is
7838 // due to live interval analysis remat'ing a load from stack slot.
7839 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
7840 return nullptr;
7841 if (MI.getOperand(i: 0).getSubReg() || MI.getOperand(i: 1).getSubReg())
7842 return nullptr;
7843 Opcode = X86::MOV32rm;
7844 NarrowToMOV32rm = true;
7845 }
7846 // For stores, make sure the size of the object is equal to the size of
7847 // the store. If the object is larger, the extra bits would be garbage. If
7848 // the object is smaller we might overwrite another object or fault.
7849 if ((I->Flags & TB_FOLDED_STORE) && Size != RCSize)
7850 return nullptr;
7851 }
7852
7853 NewMI = IsTwoAddr ? fuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, TII: *this)
7854 : fuseInst(MF, Opcode, OpNo: OpNum, MOs, InsertPt, MI, TII: *this);
7855
7856 if (NarrowToMOV32rm) {
7857 // If this is the special case where we use a MOV32rm to load a 32-bit
7858 // value and zero-extend the top bits. Change the destination register
7859 // to a 32-bit one.
7860 Register DstReg = NewMI->getOperand(i: 0).getReg();
7861 if (DstReg.isPhysical())
7862 NewMI->getOperand(i: 0).setReg(RI.getSubReg(Reg: DstReg, Idx: X86::sub_32bit));
7863 else
7864 NewMI->getOperand(i: 0).setSubReg(X86::sub_32bit);
7865 }
7866
7867 if (NoNDDM && !IsTwoAddr) {
7868 Register SrcReg = MI.getOperand(i: 1).getReg();
7869 unsigned SrcSub = MI.getOperand(i: 1).getSubReg();
7870 if (MI.killsRegister(Reg: SrcReg, /*TRI=*/nullptr) ||
7871 MI.getOperand(i: 0).getReg() == SrcReg)
7872 return NewMI;
7873
7874 Register NewSrc = MI.getOperand(i: 0).getReg();
7875 if (MRI.isSSA())
7876 NewSrc = MRI.createVirtualRegister(RegClass: getRegClass(MCID: NewMI->getDesc(), OpNum: 1));
7877
7878 CopyMI = BuildMI(BB&: *NewMI->getParent(), I&: *NewMI, MIMD: MI.getDebugLoc(),
7879 MCID: get(Opcode: TargetOpcode::COPY))
7880 .addDef(RegNo: NewSrc)
7881 .addReg(RegNo: SrcReg, Flags: {}, SubReg: SrcSub);
7882 NewMI->getOperand(i: 1).setReg(NewSrc);
7883 NewMI->getOperand(i: 1).setSubReg(0);
7884 }
7885 return NewMI;
7886 }
7887
7888 if (AllowCommute) {
7889 // If the instruction and target operand are commutable, commute the
7890 // instruction and try again.
7891 unsigned CommuteOpIdx2 = commuteOperandsForFold(MI, Idx1: OpNum);
7892 if (CommuteOpIdx2 == OpNum) {
7893 printFailMsgforFold(MI, Idx: OpNum);
7894 return nullptr;
7895 }
7896 // Attempt to fold with the commuted version of the instruction.
7897 NewMI = foldMemoryOperandImpl(MF, MI, OpNum: CommuteOpIdx2, MOs, InsertPt, Size,
7898 Alignment, /*AllowCommute=*/false, CopyMI);
7899 if (NewMI)
7900 return NewMI;
7901 // Folding failed again - undo the commute before returning.
7902 commuteInstruction(MI, NewMI: false, OpIdx1: OpNum, OpIdx2: CommuteOpIdx2);
7903 }
7904
7905 printFailMsgforFold(MI, Idx: OpNum);
7906 return nullptr;
7907}
7908
7909MachineInstr *
7910X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
7911 ArrayRef<unsigned> Ops, int FrameIndex,
7912 MachineInstr *&CopyMI, LiveIntervals *LIS,
7913 VirtRegMap *VRM) const {
7914 MachineBasicBlock::iterator InsertPt = MI;
7915 // Check switch flag
7916 if (NoFusing)
7917 return nullptr;
7918
7919 // Avoid partial and undef register update stalls unless optimizing for size.
7920 if (!MF.getFunction().hasOptSize() &&
7921 (hasPartialRegUpdate(Opcode: MI.getOpcode(), Subtarget, /*ForLoadFold*/ true) ||
7922 shouldPreventUndefRegUpdateMemFold(MF, MI)))
7923 return nullptr;
7924
7925 // Don't fold subreg spills, or reloads that use a high subreg.
7926 for (auto Op : Ops) {
7927 MachineOperand &MO = MI.getOperand(i: Op);
7928 auto SubReg = MO.getSubReg();
7929 // MOV32r0 is special b/c it's used to clear a 64-bit register too.
7930 // (See patterns for MOV32r0 in TD files).
7931 if (MI.getOpcode() == X86::MOV32r0 && SubReg == X86::sub_32bit)
7932 continue;
7933 if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
7934 return nullptr;
7935 }
7936
7937 const MachineFrameInfo &MFI = MF.getFrameInfo();
7938 unsigned Size = MFI.getObjectSize(ObjectIdx: FrameIndex);
7939 Align Alignment = MFI.getObjectAlign(ObjectIdx: FrameIndex);
7940 // If the function stack isn't realigned we don't want to fold instructions
7941 // that need increased alignment.
7942 if (!RI.hasStackRealignment(MF))
7943 Alignment =
7944 std::min(a: Alignment, b: Subtarget.getFrameLowering()->getStackAlign());
7945
7946 auto Impl = [&]() {
7947 return foldMemoryOperandImpl(
7948 MF, MI, OpNum: Ops[0], MOs: MachineOperand::CreateFI(Idx: FrameIndex), InsertPt, Size,
7949 Alignment, /*AllowCommute=*/true, CopyMI, VRM);
7950 };
7951 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
7952 unsigned NewOpc = 0;
7953 unsigned RCSize = 0;
7954 unsigned Opc = MI.getOpcode();
7955 switch (Opc) {
7956 default:
7957 // NDD can be folded into RMW though its Op0 and Op1 are not tied.
7958 return (Subtarget.hasNDD() ? X86::getNonNDVariant(Opc) : 0U) ? Impl()
7959 : nullptr;
7960 case X86::TEST8rr:
7961 NewOpc = X86::CMP8ri;
7962 RCSize = 1;
7963 break;
7964 case X86::TEST16rr:
7965 NewOpc = X86::CMP16ri;
7966 RCSize = 2;
7967 break;
7968 case X86::TEST32rr:
7969 NewOpc = X86::CMP32ri;
7970 RCSize = 4;
7971 break;
7972 case X86::TEST64rr:
7973 NewOpc = X86::CMP64ri32;
7974 RCSize = 8;
7975 break;
7976 }
7977 // Check if it's safe to fold the load. If the size of the object is
7978 // narrower than the load width, then it's not.
7979 if (Size < RCSize)
7980 return nullptr;
7981 // Change to CMPXXri r, 0 first.
7982 MI.setDesc(get(Opcode: NewOpc));
7983 MI.getOperand(i: 1).ChangeToImmediate(ImmVal: 0);
7984 } else if (Ops.size() != 1)
7985 return nullptr;
7986
7987 return Impl();
7988}
7989
7990/// Check if \p LoadMI is a partial register load that we can't fold into \p MI
7991/// because the latter uses contents that wouldn't be defined in the folded
7992/// version. For instance, this transformation isn't legal:
7993/// movss (%rdi), %xmm0
7994/// addps %xmm0, %xmm0
7995/// ->
7996/// addps (%rdi), %xmm0
7997///
7998/// But this one is:
7999/// movss (%rdi), %xmm0
8000/// addss %xmm0, %xmm0
8001/// ->
8002/// addss (%rdi), %xmm0
8003///
8004static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
8005 const MachineInstr &UserMI,
8006 const MachineFunction &MF) {
8007 unsigned Opc = LoadMI.getOpcode();
8008 unsigned UserOpc = UserMI.getOpcode();
8009 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
8010 const TargetRegisterClass *RC =
8011 MF.getRegInfo().getRegClass(Reg: LoadMI.getOperand(i: 0).getReg());
8012 unsigned RegSize = TRI.getRegSizeInBits(RC: *RC);
8013
8014 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm ||
8015 Opc == X86::MOVSSrm_alt || Opc == X86::VMOVSSrm_alt ||
8016 Opc == X86::VMOVSSZrm_alt) &&
8017 RegSize > 32) {
8018 // These instructions only load 32 bits, we can't fold them if the
8019 // destination register is wider than 32 bits (4 bytes), and its user
8020 // instruction isn't scalar (SS).
8021 switch (UserOpc) {
8022 case X86::CVTSS2SDrr_Int:
8023 case X86::VCVTSS2SDrr_Int:
8024 case X86::VCVTSS2SDZrr_Int:
8025 case X86::VCVTSS2SDZrrk_Int:
8026 case X86::VCVTSS2SDZrrkz_Int:
8027 case X86::CVTSS2SIrr_Int:
8028 case X86::CVTSS2SI64rr_Int:
8029 case X86::VCVTSS2SIrr_Int:
8030 case X86::VCVTSS2SI64rr_Int:
8031 case X86::VCVTSS2SIZrr_Int:
8032 case X86::VCVTSS2SI64Zrr_Int:
8033 case X86::CVTTSS2SIrr_Int:
8034 case X86::CVTTSS2SI64rr_Int:
8035 case X86::VCVTTSS2SIrr_Int:
8036 case X86::VCVTTSS2SI64rr_Int:
8037 case X86::VCVTTSS2SIZrr_Int:
8038 case X86::VCVTTSS2SI64Zrr_Int:
8039 case X86::VCVTSS2USIZrr_Int:
8040 case X86::VCVTSS2USI64Zrr_Int:
8041 case X86::VCVTTSS2USIZrr_Int:
8042 case X86::VCVTTSS2USI64Zrr_Int:
8043 case X86::RCPSSr_Int:
8044 case X86::VRCPSSr_Int:
8045 case X86::RSQRTSSr_Int:
8046 case X86::VRSQRTSSr_Int:
8047 case X86::ROUNDSSri_Int:
8048 case X86::VROUNDSSri_Int:
8049 case X86::COMISSrr_Int:
8050 case X86::VCOMISSrr_Int:
8051 case X86::VCOMISSZrr_Int:
8052 case X86::UCOMISSrr_Int:
8053 case X86::VUCOMISSrr_Int:
8054 case X86::VUCOMISSZrr_Int:
8055 case X86::ADDSSrr_Int:
8056 case X86::VADDSSrr_Int:
8057 case X86::VADDSSZrr_Int:
8058 case X86::CMPSSrri_Int:
8059 case X86::VCMPSSrri_Int:
8060 case X86::VCMPSSZrri_Int:
8061 case X86::DIVSSrr_Int:
8062 case X86::VDIVSSrr_Int:
8063 case X86::VDIVSSZrr_Int:
8064 case X86::MAXSSrr_Int:
8065 case X86::VMAXSSrr_Int:
8066 case X86::VMAXSSZrr_Int:
8067 case X86::MINSSrr_Int:
8068 case X86::VMINSSrr_Int:
8069 case X86::VMINSSZrr_Int:
8070 case X86::MULSSrr_Int:
8071 case X86::VMULSSrr_Int:
8072 case X86::VMULSSZrr_Int:
8073 case X86::SQRTSSr_Int:
8074 case X86::VSQRTSSr_Int:
8075 case X86::VSQRTSSZr_Int:
8076 case X86::SUBSSrr_Int:
8077 case X86::VSUBSSrr_Int:
8078 case X86::VSUBSSZrr_Int:
8079 case X86::VADDSSZrrk_Int:
8080 case X86::VADDSSZrrkz_Int:
8081 case X86::VCMPSSZrrik_Int:
8082 case X86::VDIVSSZrrk_Int:
8083 case X86::VDIVSSZrrkz_Int:
8084 case X86::VMAXSSZrrk_Int:
8085 case X86::VMAXSSZrrkz_Int:
8086 case X86::VMINSSZrrk_Int:
8087 case X86::VMINSSZrrkz_Int:
8088 case X86::VMULSSZrrk_Int:
8089 case X86::VMULSSZrrkz_Int:
8090 case X86::VSQRTSSZrk_Int:
8091 case X86::VSQRTSSZrkz_Int:
8092 case X86::VSUBSSZrrk_Int:
8093 case X86::VSUBSSZrrkz_Int:
8094 case X86::VFMADDSS4rr_Int:
8095 case X86::VFNMADDSS4rr_Int:
8096 case X86::VFMSUBSS4rr_Int:
8097 case X86::VFNMSUBSS4rr_Int:
8098 case X86::VFMADD132SSr_Int:
8099 case X86::VFNMADD132SSr_Int:
8100 case X86::VFMADD213SSr_Int:
8101 case X86::VFNMADD213SSr_Int:
8102 case X86::VFMADD231SSr_Int:
8103 case X86::VFNMADD231SSr_Int:
8104 case X86::VFMSUB132SSr_Int:
8105 case X86::VFNMSUB132SSr_Int:
8106 case X86::VFMSUB213SSr_Int:
8107 case X86::VFNMSUB213SSr_Int:
8108 case X86::VFMSUB231SSr_Int:
8109 case X86::VFNMSUB231SSr_Int:
8110 case X86::VFMADD132SSZr_Int:
8111 case X86::VFNMADD132SSZr_Int:
8112 case X86::VFMADD213SSZr_Int:
8113 case X86::VFNMADD213SSZr_Int:
8114 case X86::VFMADD231SSZr_Int:
8115 case X86::VFNMADD231SSZr_Int:
8116 case X86::VFMSUB132SSZr_Int:
8117 case X86::VFNMSUB132SSZr_Int:
8118 case X86::VFMSUB213SSZr_Int:
8119 case X86::VFNMSUB213SSZr_Int:
8120 case X86::VFMSUB231SSZr_Int:
8121 case X86::VFNMSUB231SSZr_Int:
8122 case X86::VFMADD132SSZrk_Int:
8123 case X86::VFNMADD132SSZrk_Int:
8124 case X86::VFMADD213SSZrk_Int:
8125 case X86::VFNMADD213SSZrk_Int:
8126 case X86::VFMADD231SSZrk_Int:
8127 case X86::VFNMADD231SSZrk_Int:
8128 case X86::VFMSUB132SSZrk_Int:
8129 case X86::VFNMSUB132SSZrk_Int:
8130 case X86::VFMSUB213SSZrk_Int:
8131 case X86::VFNMSUB213SSZrk_Int:
8132 case X86::VFMSUB231SSZrk_Int:
8133 case X86::VFNMSUB231SSZrk_Int:
8134 case X86::VFMADD132SSZrkz_Int:
8135 case X86::VFNMADD132SSZrkz_Int:
8136 case X86::VFMADD213SSZrkz_Int:
8137 case X86::VFNMADD213SSZrkz_Int:
8138 case X86::VFMADD231SSZrkz_Int:
8139 case X86::VFNMADD231SSZrkz_Int:
8140 case X86::VFMSUB132SSZrkz_Int:
8141 case X86::VFNMSUB132SSZrkz_Int:
8142 case X86::VFMSUB213SSZrkz_Int:
8143 case X86::VFNMSUB213SSZrkz_Int:
8144 case X86::VFMSUB231SSZrkz_Int:
8145 case X86::VFNMSUB231SSZrkz_Int:
8146 case X86::VFIXUPIMMSSZrri:
8147 case X86::VFIXUPIMMSSZrrik:
8148 case X86::VFIXUPIMMSSZrrikz:
8149 case X86::VFPCLASSSSZri:
8150 case X86::VFPCLASSSSZrik:
8151 case X86::VGETEXPSSZr:
8152 case X86::VGETEXPSSZrk:
8153 case X86::VGETEXPSSZrkz:
8154 case X86::VGETMANTSSZrri:
8155 case X86::VGETMANTSSZrrik:
8156 case X86::VGETMANTSSZrrikz:
8157 case X86::VRANGESSZrri:
8158 case X86::VRANGESSZrrik:
8159 case X86::VRANGESSZrrikz:
8160 case X86::VRCP14SSZrr:
8161 case X86::VRCP14SSZrrk:
8162 case X86::VRCP14SSZrrkz:
8163 case X86::VRCP28SSZr:
8164 case X86::VRCP28SSZrk:
8165 case X86::VRCP28SSZrkz:
8166 case X86::VREDUCESSZrri:
8167 case X86::VREDUCESSZrrik:
8168 case X86::VREDUCESSZrrikz:
8169 case X86::VRNDSCALESSZrri_Int:
8170 case X86::VRNDSCALESSZrrik_Int:
8171 case X86::VRNDSCALESSZrrikz_Int:
8172 case X86::VRSQRT14SSZrr:
8173 case X86::VRSQRT14SSZrrk:
8174 case X86::VRSQRT14SSZrrkz:
8175 case X86::VRSQRT28SSZr:
8176 case X86::VRSQRT28SSZrk:
8177 case X86::VRSQRT28SSZrkz:
8178 case X86::VSCALEFSSZrr:
8179 case X86::VSCALEFSSZrrk:
8180 case X86::VSCALEFSSZrrkz:
8181 return false;
8182 default:
8183 return true;
8184 }
8185 }
8186
8187 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm ||
8188 Opc == X86::MOVSDrm_alt || Opc == X86::VMOVSDrm_alt ||
8189 Opc == X86::VMOVSDZrm_alt) &&
8190 RegSize > 64) {
8191 // These instructions only load 64 bits, we can't fold them if the
8192 // destination register is wider than 64 bits (8 bytes), and its user
8193 // instruction isn't scalar (SD).
8194 switch (UserOpc) {
8195 case X86::CVTSD2SSrr_Int:
8196 case X86::VCVTSD2SSrr_Int:
8197 case X86::VCVTSD2SSZrr_Int:
8198 case X86::VCVTSD2SSZrrk_Int:
8199 case X86::VCVTSD2SSZrrkz_Int:
8200 case X86::CVTSD2SIrr_Int:
8201 case X86::CVTSD2SI64rr_Int:
8202 case X86::VCVTSD2SIrr_Int:
8203 case X86::VCVTSD2SI64rr_Int:
8204 case X86::VCVTSD2SIZrr_Int:
8205 case X86::VCVTSD2SI64Zrr_Int:
8206 case X86::CVTTSD2SIrr_Int:
8207 case X86::CVTTSD2SI64rr_Int:
8208 case X86::VCVTTSD2SIrr_Int:
8209 case X86::VCVTTSD2SI64rr_Int:
8210 case X86::VCVTTSD2SIZrr_Int:
8211 case X86::VCVTTSD2SI64Zrr_Int:
8212 case X86::VCVTSD2USIZrr_Int:
8213 case X86::VCVTSD2USI64Zrr_Int:
8214 case X86::VCVTTSD2USIZrr_Int:
8215 case X86::VCVTTSD2USI64Zrr_Int:
8216 case X86::ROUNDSDri_Int:
8217 case X86::VROUNDSDri_Int:
8218 case X86::COMISDrr_Int:
8219 case X86::VCOMISDrr_Int:
8220 case X86::VCOMISDZrr_Int:
8221 case X86::UCOMISDrr_Int:
8222 case X86::VUCOMISDrr_Int:
8223 case X86::VUCOMISDZrr_Int:
8224 case X86::ADDSDrr_Int:
8225 case X86::VADDSDrr_Int:
8226 case X86::VADDSDZrr_Int:
8227 case X86::CMPSDrri_Int:
8228 case X86::VCMPSDrri_Int:
8229 case X86::VCMPSDZrri_Int:
8230 case X86::DIVSDrr_Int:
8231 case X86::VDIVSDrr_Int:
8232 case X86::VDIVSDZrr_Int:
8233 case X86::MAXSDrr_Int:
8234 case X86::VMAXSDrr_Int:
8235 case X86::VMAXSDZrr_Int:
8236 case X86::MINSDrr_Int:
8237 case X86::VMINSDrr_Int:
8238 case X86::VMINSDZrr_Int:
8239 case X86::MULSDrr_Int:
8240 case X86::VMULSDrr_Int:
8241 case X86::VMULSDZrr_Int:
8242 case X86::SQRTSDr_Int:
8243 case X86::VSQRTSDr_Int:
8244 case X86::VSQRTSDZr_Int:
8245 case X86::SUBSDrr_Int:
8246 case X86::VSUBSDrr_Int:
8247 case X86::VSUBSDZrr_Int:
8248 case X86::VADDSDZrrk_Int:
8249 case X86::VADDSDZrrkz_Int:
8250 case X86::VCMPSDZrrik_Int:
8251 case X86::VDIVSDZrrk_Int:
8252 case X86::VDIVSDZrrkz_Int:
8253 case X86::VMAXSDZrrk_Int:
8254 case X86::VMAXSDZrrkz_Int:
8255 case X86::VMINSDZrrk_Int:
8256 case X86::VMINSDZrrkz_Int:
8257 case X86::VMULSDZrrk_Int:
8258 case X86::VMULSDZrrkz_Int:
8259 case X86::VSQRTSDZrk_Int:
8260 case X86::VSQRTSDZrkz_Int:
8261 case X86::VSUBSDZrrk_Int:
8262 case X86::VSUBSDZrrkz_Int:
8263 case X86::VFMADDSD4rr_Int:
8264 case X86::VFNMADDSD4rr_Int:
8265 case X86::VFMSUBSD4rr_Int:
8266 case X86::VFNMSUBSD4rr_Int:
8267 case X86::VFMADD132SDr_Int:
8268 case X86::VFNMADD132SDr_Int:
8269 case X86::VFMADD213SDr_Int:
8270 case X86::VFNMADD213SDr_Int:
8271 case X86::VFMADD231SDr_Int:
8272 case X86::VFNMADD231SDr_Int:
8273 case X86::VFMSUB132SDr_Int:
8274 case X86::VFNMSUB132SDr_Int:
8275 case X86::VFMSUB213SDr_Int:
8276 case X86::VFNMSUB213SDr_Int:
8277 case X86::VFMSUB231SDr_Int:
8278 case X86::VFNMSUB231SDr_Int:
8279 case X86::VFMADD132SDZr_Int:
8280 case X86::VFNMADD132SDZr_Int:
8281 case X86::VFMADD213SDZr_Int:
8282 case X86::VFNMADD213SDZr_Int:
8283 case X86::VFMADD231SDZr_Int:
8284 case X86::VFNMADD231SDZr_Int:
8285 case X86::VFMSUB132SDZr_Int:
8286 case X86::VFNMSUB132SDZr_Int:
8287 case X86::VFMSUB213SDZr_Int:
8288 case X86::VFNMSUB213SDZr_Int:
8289 case X86::VFMSUB231SDZr_Int:
8290 case X86::VFNMSUB231SDZr_Int:
8291 case X86::VFMADD132SDZrk_Int:
8292 case X86::VFNMADD132SDZrk_Int:
8293 case X86::VFMADD213SDZrk_Int:
8294 case X86::VFNMADD213SDZrk_Int:
8295 case X86::VFMADD231SDZrk_Int:
8296 case X86::VFNMADD231SDZrk_Int:
8297 case X86::VFMSUB132SDZrk_Int:
8298 case X86::VFNMSUB132SDZrk_Int:
8299 case X86::VFMSUB213SDZrk_Int:
8300 case X86::VFNMSUB213SDZrk_Int:
8301 case X86::VFMSUB231SDZrk_Int:
8302 case X86::VFNMSUB231SDZrk_Int:
8303 case X86::VFMADD132SDZrkz_Int:
8304 case X86::VFNMADD132SDZrkz_Int:
8305 case X86::VFMADD213SDZrkz_Int:
8306 case X86::VFNMADD213SDZrkz_Int:
8307 case X86::VFMADD231SDZrkz_Int:
8308 case X86::VFNMADD231SDZrkz_Int:
8309 case X86::VFMSUB132SDZrkz_Int:
8310 case X86::VFNMSUB132SDZrkz_Int:
8311 case X86::VFMSUB213SDZrkz_Int:
8312 case X86::VFNMSUB213SDZrkz_Int:
8313 case X86::VFMSUB231SDZrkz_Int:
8314 case X86::VFNMSUB231SDZrkz_Int:
8315 case X86::VFIXUPIMMSDZrri:
8316 case X86::VFIXUPIMMSDZrrik:
8317 case X86::VFIXUPIMMSDZrrikz:
8318 case X86::VFPCLASSSDZri:
8319 case X86::VFPCLASSSDZrik:
8320 case X86::VGETEXPSDZr:
8321 case X86::VGETEXPSDZrk:
8322 case X86::VGETEXPSDZrkz:
8323 case X86::VGETMANTSDZrri:
8324 case X86::VGETMANTSDZrrik:
8325 case X86::VGETMANTSDZrrikz:
8326 case X86::VRANGESDZrri:
8327 case X86::VRANGESDZrrik:
8328 case X86::VRANGESDZrrikz:
8329 case X86::VRCP14SDZrr:
8330 case X86::VRCP14SDZrrk:
8331 case X86::VRCP14SDZrrkz:
8332 case X86::VRCP28SDZr:
8333 case X86::VRCP28SDZrk:
8334 case X86::VRCP28SDZrkz:
8335 case X86::VREDUCESDZrri:
8336 case X86::VREDUCESDZrrik:
8337 case X86::VREDUCESDZrrikz:
8338 case X86::VRNDSCALESDZrri_Int:
8339 case X86::VRNDSCALESDZrrik_Int:
8340 case X86::VRNDSCALESDZrrikz_Int:
8341 case X86::VRSQRT14SDZrr:
8342 case X86::VRSQRT14SDZrrk:
8343 case X86::VRSQRT14SDZrrkz:
8344 case X86::VRSQRT28SDZr:
8345 case X86::VRSQRT28SDZrk:
8346 case X86::VRSQRT28SDZrkz:
8347 case X86::VSCALEFSDZrr:
8348 case X86::VSCALEFSDZrrk:
8349 case X86::VSCALEFSDZrrkz:
8350 return false;
8351 default:
8352 return true;
8353 }
8354 }
8355
8356 if ((Opc == X86::VMOVSHZrm || Opc == X86::VMOVSHZrm_alt) && RegSize > 16) {
8357 // These instructions only load 16 bits, we can't fold them if the
8358 // destination register is wider than 16 bits (2 bytes), and its user
8359 // instruction isn't scalar (SH).
8360 switch (UserOpc) {
8361 case X86::VADDSHZrr_Int:
8362 case X86::VCMPSHZrri_Int:
8363 case X86::VDIVSHZrr_Int:
8364 case X86::VMAXSHZrr_Int:
8365 case X86::VMINSHZrr_Int:
8366 case X86::VMULSHZrr_Int:
8367 case X86::VSUBSHZrr_Int:
8368 case X86::VADDSHZrrk_Int:
8369 case X86::VADDSHZrrkz_Int:
8370 case X86::VCMPSHZrrik_Int:
8371 case X86::VDIVSHZrrk_Int:
8372 case X86::VDIVSHZrrkz_Int:
8373 case X86::VMAXSHZrrk_Int:
8374 case X86::VMAXSHZrrkz_Int:
8375 case X86::VMINSHZrrk_Int:
8376 case X86::VMINSHZrrkz_Int:
8377 case X86::VMULSHZrrk_Int:
8378 case X86::VMULSHZrrkz_Int:
8379 case X86::VSUBSHZrrk_Int:
8380 case X86::VSUBSHZrrkz_Int:
8381 case X86::VFMADD132SHZr_Int:
8382 case X86::VFNMADD132SHZr_Int:
8383 case X86::VFMADD213SHZr_Int:
8384 case X86::VFNMADD213SHZr_Int:
8385 case X86::VFMADD231SHZr_Int:
8386 case X86::VFNMADD231SHZr_Int:
8387 case X86::VFMSUB132SHZr_Int:
8388 case X86::VFNMSUB132SHZr_Int:
8389 case X86::VFMSUB213SHZr_Int:
8390 case X86::VFNMSUB213SHZr_Int:
8391 case X86::VFMSUB231SHZr_Int:
8392 case X86::VFNMSUB231SHZr_Int:
8393 case X86::VFMADD132SHZrk_Int:
8394 case X86::VFNMADD132SHZrk_Int:
8395 case X86::VFMADD213SHZrk_Int:
8396 case X86::VFNMADD213SHZrk_Int:
8397 case X86::VFMADD231SHZrk_Int:
8398 case X86::VFNMADD231SHZrk_Int:
8399 case X86::VFMSUB132SHZrk_Int:
8400 case X86::VFNMSUB132SHZrk_Int:
8401 case X86::VFMSUB213SHZrk_Int:
8402 case X86::VFNMSUB213SHZrk_Int:
8403 case X86::VFMSUB231SHZrk_Int:
8404 case X86::VFNMSUB231SHZrk_Int:
8405 case X86::VFMADD132SHZrkz_Int:
8406 case X86::VFNMADD132SHZrkz_Int:
8407 case X86::VFMADD213SHZrkz_Int:
8408 case X86::VFNMADD213SHZrkz_Int:
8409 case X86::VFMADD231SHZrkz_Int:
8410 case X86::VFNMADD231SHZrkz_Int:
8411 case X86::VFMSUB132SHZrkz_Int:
8412 case X86::VFNMSUB132SHZrkz_Int:
8413 case X86::VFMSUB213SHZrkz_Int:
8414 case X86::VFNMSUB213SHZrkz_Int:
8415 case X86::VFMSUB231SHZrkz_Int:
8416 case X86::VFNMSUB231SHZrkz_Int:
8417 return false;
8418 default:
8419 return true;
8420 }
8421 }
8422
8423 return false;
8424}
8425
8426MachineInstr *
8427X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
8428 ArrayRef<unsigned> Ops,
8429 MachineInstr &LoadMI, MachineInstr *&CopyMI,
8430 LiveIntervals *LIS, VirtRegMap *VRM) const {
8431 MachineBasicBlock::iterator InsertPt = MI;
8432
8433 // If LoadMI is a masked load, check MI having the same mask.
8434 const MCInstrDesc &MCID = get(Opcode: LoadMI.getOpcode());
8435 unsigned NumOps = MCID.getNumOperands();
8436 if (NumOps >= 3) {
8437 Register MaskReg;
8438 const MachineOperand &Op1 = LoadMI.getOperand(i: 1);
8439 const MachineOperand &Op2 = LoadMI.getOperand(i: 2);
8440
8441 auto IsVKWMClass = [](const TargetRegisterClass *RC) {
8442 return RC == &X86::VK2WMRegClass || RC == &X86::VK4WMRegClass ||
8443 RC == &X86::VK8WMRegClass || RC == &X86::VK16WMRegClass ||
8444 RC == &X86::VK32WMRegClass || RC == &X86::VK64WMRegClass;
8445 };
8446
8447 if (Op1.isReg() && IsVKWMClass(getRegClass(MCID, OpNum: 1)))
8448 MaskReg = Op1.getReg();
8449 else if (Op2.isReg() && IsVKWMClass(getRegClass(MCID, OpNum: 2)))
8450 MaskReg = Op2.getReg();
8451
8452 if (MaskReg) {
8453 // Some instructions are invalid to fold into even with the same mask.
8454 // Folding is unsafe if an active destination element may read from a
8455 // source element that is masked off.
8456 if (isNonFoldableWithSameMask(RegOp: MI.getOpcode()))
8457 return nullptr;
8458 bool HasSameMask = false;
8459 for (unsigned I = 1, E = MI.getDesc().getNumOperands(); I < E; ++I) {
8460 const MachineOperand &Op = MI.getOperand(i: I);
8461 if (Op.isReg() && Op.getReg() == MaskReg) {
8462 HasSameMask = true;
8463 break;
8464 }
8465 }
8466 if (!HasSameMask)
8467 return nullptr;
8468 }
8469 }
8470
8471 // TODO: Support the case where LoadMI loads a wide register, but MI
8472 // only uses a subreg.
8473 for (auto Op : Ops) {
8474 if (MI.getOperand(i: Op).getSubReg())
8475 return nullptr;
8476 }
8477
8478 // If loading from a FrameIndex, fold directly from the FrameIndex.
8479 int FrameIndex;
8480 if (isLoadFromStackSlot(MI: LoadMI, FrameIndex)) {
8481 if (isNonFoldablePartialRegisterLoad(LoadMI, UserMI: MI, MF))
8482 return nullptr;
8483 return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex, CopyMI, LIS, VRM);
8484 }
8485
8486 // Check switch flag
8487 if (NoFusing)
8488 return nullptr;
8489
8490 // Avoid partial and undef register update stalls unless optimizing for size.
8491 if (!MF.getFunction().hasOptSize() &&
8492 (hasPartialRegUpdate(Opcode: MI.getOpcode(), Subtarget, /*ForLoadFold*/ true) ||
8493 shouldPreventUndefRegUpdateMemFold(MF, MI)))
8494 return nullptr;
8495
8496 // Do not fold a NDD instruction and a memory instruction with relocation to
8497 // avoid emit APX relocation when the flag is disabled for backward
8498 // compatibility.
8499 uint64_t TSFlags = MI.getDesc().TSFlags;
8500 if (!X86EnableAPXForRelocation && isMemInstrWithGOTPCREL(MI: LoadMI) &&
8501 X86II::hasNewDataDest(TSFlags))
8502 return nullptr;
8503
8504 // Determine the alignment of the load.
8505 Align Alignment;
8506 unsigned LoadOpc = LoadMI.getOpcode();
8507 if (LoadMI.hasOneMemOperand())
8508 Alignment = (*LoadMI.memoperands_begin())->getAlign();
8509 else
8510 switch (LoadOpc) {
8511 case X86::AVX512_512_SETALLONES:
8512 Alignment = Align(64);
8513 break;
8514 case X86::AVX2_SETALLONES:
8515 case X86::AVX1_SETALLONES:
8516 case X86::AVX512_256_SETALLONES:
8517 Alignment = Align(32);
8518 break;
8519 case X86::V_SET0:
8520 case X86::V_SETALLONES:
8521 case X86::AVX512_128_SET0:
8522 case X86::FsFLD0F128:
8523 case X86::AVX512_FsFLD0F128:
8524 case X86::AVX512_128_SETALLONES:
8525 Alignment = Align(16);
8526 break;
8527 case X86::MMX_SET0:
8528 case X86::FsFLD0SD:
8529 case X86::AVX512_FsFLD0SD:
8530 Alignment = Align(8);
8531 break;
8532 case X86::FsFLD0SS:
8533 case X86::AVX512_FsFLD0SS:
8534 Alignment = Align(4);
8535 break;
8536 case X86::FsFLD0SH:
8537 case X86::AVX512_FsFLD0SH:
8538 Alignment = Align(2);
8539 break;
8540 default:
8541 return nullptr;
8542 }
8543 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
8544 unsigned NewOpc = 0;
8545 switch (MI.getOpcode()) {
8546 default:
8547 return nullptr;
8548 case X86::TEST8rr:
8549 NewOpc = X86::CMP8ri;
8550 break;
8551 case X86::TEST16rr:
8552 NewOpc = X86::CMP16ri;
8553 break;
8554 case X86::TEST32rr:
8555 NewOpc = X86::CMP32ri;
8556 break;
8557 case X86::TEST64rr:
8558 NewOpc = X86::CMP64ri32;
8559 break;
8560 }
8561 // Change to CMPXXri r, 0 first.
8562 MI.setDesc(get(Opcode: NewOpc));
8563 MI.getOperand(i: 1).ChangeToImmediate(ImmVal: 0);
8564 } else if (Ops.size() != 1)
8565 return nullptr;
8566
8567 // Make sure the subregisters match.
8568 // Otherwise we risk changing the size of the load.
8569 if (LoadMI.getOperand(i: 0).getSubReg() != MI.getOperand(i: Ops[0]).getSubReg())
8570 return nullptr;
8571
8572 SmallVector<MachineOperand, X86::AddrNumOperands> MOs;
8573 switch (LoadOpc) {
8574 case X86::MMX_SET0:
8575 case X86::V_SET0:
8576 case X86::V_SETALLONES:
8577 case X86::AVX2_SETALLONES:
8578 case X86::AVX1_SETALLONES:
8579 case X86::AVX512_128_SET0:
8580 case X86::AVX512_128_SETALLONES:
8581 case X86::AVX512_256_SETALLONES:
8582 case X86::AVX512_512_SETALLONES:
8583 case X86::FsFLD0SH:
8584 case X86::AVX512_FsFLD0SH:
8585 case X86::FsFLD0SD:
8586 case X86::AVX512_FsFLD0SD:
8587 case X86::FsFLD0SS:
8588 case X86::AVX512_FsFLD0SS:
8589 case X86::FsFLD0F128:
8590 case X86::AVX512_FsFLD0F128: {
8591 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
8592 // Create a constant-pool entry and operands to load from it.
8593
8594 // Large code model can't fold loads this way.
8595 if (MF.getTarget().getCodeModel() == CodeModel::Large)
8596 return nullptr;
8597
8598 // x86-32 PIC requires a PIC base register for constant pools.
8599 unsigned PICBase = 0;
8600 // Since we're using Small or Kernel code model, we can always use
8601 // RIP-relative addressing for a smaller encoding.
8602 if (Subtarget.is64Bit()) {
8603 PICBase = X86::RIP;
8604 } else if (MF.getTarget().isPositionIndependent()) {
8605 // FIXME: PICBase = getGlobalBaseReg(&MF);
8606 // This doesn't work for several reasons.
8607 // 1. GlobalBaseReg may have been spilled.
8608 // 2. It may not be live at MI.
8609 return nullptr;
8610 }
8611
8612 // Create a constant-pool entry.
8613 MachineConstantPool &MCP = *MF.getConstantPool();
8614 Type *Ty;
8615 bool IsAllOnes = false;
8616 switch (LoadOpc) {
8617 case X86::FsFLD0SS:
8618 case X86::AVX512_FsFLD0SS:
8619 Ty = Type::getFloatTy(C&: MF.getFunction().getContext());
8620 break;
8621 case X86::FsFLD0SD:
8622 case X86::AVX512_FsFLD0SD:
8623 Ty = Type::getDoubleTy(C&: MF.getFunction().getContext());
8624 break;
8625 case X86::FsFLD0F128:
8626 case X86::AVX512_FsFLD0F128:
8627 Ty = Type::getFP128Ty(C&: MF.getFunction().getContext());
8628 break;
8629 case X86::FsFLD0SH:
8630 case X86::AVX512_FsFLD0SH:
8631 Ty = Type::getHalfTy(C&: MF.getFunction().getContext());
8632 break;
8633 case X86::AVX512_512_SETALLONES:
8634 IsAllOnes = true;
8635 Ty = FixedVectorType::get(ElementType: Type::getInt32Ty(C&: MF.getFunction().getContext()),
8636 NumElts: 16);
8637 break;
8638 case X86::AVX1_SETALLONES:
8639 case X86::AVX2_SETALLONES:
8640 case X86::AVX512_256_SETALLONES:
8641 IsAllOnes = true;
8642 Ty = FixedVectorType::get(ElementType: Type::getInt32Ty(C&: MF.getFunction().getContext()),
8643 NumElts: 8);
8644
8645 break;
8646 case X86::MMX_SET0:
8647 Ty = FixedVectorType::get(ElementType: Type::getInt32Ty(C&: MF.getFunction().getContext()),
8648 NumElts: 2);
8649 break;
8650 case X86::V_SETALLONES:
8651 case X86::AVX512_128_SETALLONES:
8652 IsAllOnes = true;
8653 [[fallthrough]];
8654 case X86::V_SET0:
8655 case X86::AVX512_128_SET0:
8656 Ty = FixedVectorType::get(ElementType: Type::getInt32Ty(C&: MF.getFunction().getContext()),
8657 NumElts: 4);
8658 break;
8659 }
8660
8661 const Constant *C =
8662 IsAllOnes ? Constant::getAllOnesValue(Ty) : Constant::getNullValue(Ty);
8663 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
8664
8665 // Create operands to load from the constant pool entry.
8666 MOs.push_back(Elt: MachineOperand::CreateReg(Reg: PICBase, isDef: false));
8667 MOs.push_back(Elt: MachineOperand::CreateImm(Val: 1));
8668 MOs.push_back(Elt: MachineOperand::CreateReg(Reg: 0, isDef: false));
8669 MOs.push_back(Elt: MachineOperand::CreateCPI(Idx: CPI, Offset: 0));
8670 MOs.push_back(Elt: MachineOperand::CreateReg(Reg: 0, isDef: false));
8671 break;
8672 }
8673 case X86::VPBROADCASTBZ128rm:
8674 case X86::VPBROADCASTBZ256rm:
8675 case X86::VPBROADCASTBZrm:
8676 case X86::VBROADCASTF32X2Z256rm:
8677 case X86::VBROADCASTF32X2Zrm:
8678 case X86::VBROADCASTI32X2Z128rm:
8679 case X86::VBROADCASTI32X2Z256rm:
8680 case X86::VBROADCASTI32X2Zrm:
8681 // No instructions currently fuse with 8bits or 32bits x 2.
8682 return nullptr;
8683
8684#define FOLD_BROADCAST(SIZE) \
8685 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands, \
8686 LoadMI.operands_begin() + NumOps); \
8687 return foldMemoryBroadcast(MF, MI, Ops[0], MOs, InsertPt, /*Size=*/SIZE, \
8688 /*AllowCommute=*/true);
8689 case X86::VPBROADCASTWZ128rm:
8690 case X86::VPBROADCASTWZ256rm:
8691 case X86::VPBROADCASTWZrm:
8692 FOLD_BROADCAST(16);
8693 case X86::VPBROADCASTDZ128rm:
8694 case X86::VPBROADCASTDZ256rm:
8695 case X86::VPBROADCASTDZrm:
8696 case X86::VBROADCASTSSZ128rm:
8697 case X86::VBROADCASTSSZ256rm:
8698 case X86::VBROADCASTSSZrm:
8699 FOLD_BROADCAST(32);
8700 case X86::VPBROADCASTQZ128rm:
8701 case X86::VPBROADCASTQZ256rm:
8702 case X86::VPBROADCASTQZrm:
8703 case X86::VBROADCASTSDZ256rm:
8704 case X86::VBROADCASTSDZrm:
8705 FOLD_BROADCAST(64);
8706 default: {
8707 if (isNonFoldablePartialRegisterLoad(LoadMI, UserMI: MI, MF))
8708 return nullptr;
8709
8710 // Folding a normal load. Just copy the load's address operands.
8711 MOs.append(in_start: LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
8712 in_end: LoadMI.operands_begin() + NumOps);
8713 break;
8714 }
8715 }
8716 return foldMemoryOperandImpl(MF, MI, OpNum: Ops[0], MOs, InsertPt,
8717 /*Size=*/0, Alignment, /*AllowCommute=*/true,
8718 CopyMI, VRM);
8719}
8720
8721MachineInstr *
8722X86InstrInfo::foldMemoryBroadcast(MachineFunction &MF, MachineInstr &MI,
8723 unsigned OpNum, ArrayRef<MachineOperand> MOs,
8724 MachineBasicBlock::iterator InsertPt,
8725 unsigned BitsSize, bool AllowCommute) const {
8726
8727 if (auto *I = lookupBroadcastFoldTable(RegOp: MI.getOpcode(), OpNum))
8728 return matchBroadcastSize(Entry: *I, BroadcastBits: BitsSize)
8729 ? fuseInst(MF, Opcode: I->DstOp, OpNo: OpNum, MOs, InsertPt, MI, TII: *this)
8730 : nullptr;
8731
8732 if (AllowCommute) {
8733 // If the instruction and target operand are commutable, commute the
8734 // instruction and try again.
8735 unsigned CommuteOpIdx2 = commuteOperandsForFold(MI, Idx1: OpNum);
8736 if (CommuteOpIdx2 == OpNum) {
8737 printFailMsgforFold(MI, Idx: OpNum);
8738 return nullptr;
8739 }
8740 MachineInstr *NewMI =
8741 foldMemoryBroadcast(MF, MI, OpNum: CommuteOpIdx2, MOs, InsertPt, BitsSize,
8742 /*AllowCommute=*/false);
8743 if (NewMI)
8744 return NewMI;
8745 // Folding failed again - undo the commute before returning.
8746 commuteInstruction(MI, NewMI: false, OpIdx1: OpNum, OpIdx2: CommuteOpIdx2);
8747 }
8748
8749 printFailMsgforFold(MI, Idx: OpNum);
8750 return nullptr;
8751}
8752
8753static SmallVector<MachineMemOperand *, 2>
8754extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
8755 SmallVector<MachineMemOperand *, 2> LoadMMOs;
8756
8757 for (MachineMemOperand *MMO : MMOs) {
8758 if (!MMO->isLoad())
8759 continue;
8760
8761 if (!MMO->isStore()) {
8762 // Reuse the MMO.
8763 LoadMMOs.push_back(Elt: MMO);
8764 } else {
8765 // Clone the MMO and unset the store flag.
8766 LoadMMOs.push_back(Elt: MF.getMachineMemOperand(
8767 MMO, Flags: MMO->getFlags() & ~MachineMemOperand::MOStore));
8768 }
8769 }
8770
8771 return LoadMMOs;
8772}
8773
8774static SmallVector<MachineMemOperand *, 2>
8775extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
8776 SmallVector<MachineMemOperand *, 2> StoreMMOs;
8777
8778 for (MachineMemOperand *MMO : MMOs) {
8779 if (!MMO->isStore())
8780 continue;
8781
8782 if (!MMO->isLoad()) {
8783 // Reuse the MMO.
8784 StoreMMOs.push_back(Elt: MMO);
8785 } else {
8786 // Clone the MMO and unset the load flag.
8787 StoreMMOs.push_back(Elt: MF.getMachineMemOperand(
8788 MMO, Flags: MMO->getFlags() & ~MachineMemOperand::MOLoad));
8789 }
8790 }
8791
8792 return StoreMMOs;
8793}
8794
8795static unsigned getBroadcastOpcode(const X86FoldTableEntry *I,
8796 const TargetRegisterClass *RC,
8797 const X86Subtarget &STI) {
8798 assert(STI.hasAVX512() && "Expected at least AVX512!");
8799 unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(RC: *RC);
8800 assert((SpillSize == 64 || STI.hasVLX()) &&
8801 "Can't broadcast less than 64 bytes without AVX512VL!");
8802
8803#define CASE_BCAST_TYPE_OPC(TYPE, OP16, OP32, OP64) \
8804 case TYPE: \
8805 switch (SpillSize) { \
8806 default: \
8807 llvm_unreachable("Unknown spill size"); \
8808 case 16: \
8809 return X86::OP16; \
8810 case 32: \
8811 return X86::OP32; \
8812 case 64: \
8813 return X86::OP64; \
8814 } \
8815 break;
8816
8817 switch (I->Flags & TB_BCAST_MASK) {
8818 default:
8819 llvm_unreachable("Unexpected broadcast type!");
8820 CASE_BCAST_TYPE_OPC(TB_BCAST_W, VPBROADCASTWZ128rm, VPBROADCASTWZ256rm,
8821 VPBROADCASTWZrm)
8822 CASE_BCAST_TYPE_OPC(TB_BCAST_D, VPBROADCASTDZ128rm, VPBROADCASTDZ256rm,
8823 VPBROADCASTDZrm)
8824 CASE_BCAST_TYPE_OPC(TB_BCAST_Q, VPBROADCASTQZ128rm, VPBROADCASTQZ256rm,
8825 VPBROADCASTQZrm)
8826 CASE_BCAST_TYPE_OPC(TB_BCAST_SH, VPBROADCASTWZ128rm, VPBROADCASTWZ256rm,
8827 VPBROADCASTWZrm)
8828 CASE_BCAST_TYPE_OPC(TB_BCAST_SS, VBROADCASTSSZ128rm, VBROADCASTSSZ256rm,
8829 VBROADCASTSSZrm)
8830 CASE_BCAST_TYPE_OPC(TB_BCAST_SD, VMOVDDUPZ128rm, VBROADCASTSDZ256rm,
8831 VBROADCASTSDZrm)
8832 }
8833}
8834
8835bool X86InstrInfo::unfoldMemoryOperand(
8836 MachineFunction &MF, MachineInstr &MI, Register Reg, bool UnfoldLoad,
8837 bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
8838 const X86FoldTableEntry *I = lookupUnfoldTable(MemOp: MI.getOpcode());
8839 if (I == nullptr)
8840 return false;
8841 unsigned Opc = I->DstOp;
8842 unsigned Index = I->Flags & TB_INDEX_MASK;
8843 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
8844 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
8845 if (UnfoldLoad && !FoldedLoad)
8846 return false;
8847 UnfoldLoad &= FoldedLoad;
8848 if (UnfoldStore && !FoldedStore)
8849 return false;
8850 UnfoldStore &= FoldedStore;
8851
8852 const MCInstrDesc &MCID = get(Opcode: Opc);
8853
8854 const TargetRegisterClass *RC = getRegClass(MCID, OpNum: Index);
8855 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
8856 // TODO: Check if 32-byte or greater accesses are slow too?
8857 if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
8858 Subtarget.isUnalignedMem16Slow())
8859 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
8860 // conservatively assume the address is unaligned. That's bad for
8861 // performance.
8862 return false;
8863 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
8864 SmallVector<MachineOperand, 2> BeforeOps;
8865 SmallVector<MachineOperand, 2> AfterOps;
8866 SmallVector<MachineOperand, 4> ImpOps;
8867 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
8868 MachineOperand &Op = MI.getOperand(i);
8869 if (i >= Index && i < Index + X86::AddrNumOperands)
8870 AddrOps.push_back(Elt: Op);
8871 else if (Op.isReg() && Op.isImplicit())
8872 ImpOps.push_back(Elt: Op);
8873 else if (i < Index)
8874 BeforeOps.push_back(Elt: Op);
8875 else if (i > Index)
8876 AfterOps.push_back(Elt: Op);
8877 }
8878
8879 // Emit the load or broadcast instruction.
8880 if (UnfoldLoad) {
8881 auto MMOs = extractLoadMMOs(MMOs: MI.memoperands(), MF);
8882
8883 unsigned Opc;
8884 if (I->Flags & TB_BCAST_MASK) {
8885 Opc = getBroadcastOpcode(I, RC, STI: Subtarget);
8886 } else {
8887 unsigned Alignment = std::max<uint32_t>(a: TRI.getSpillSize(RC: *RC), b: 16);
8888 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
8889 Opc = getLoadRegOpcode(DestReg: Reg, RC, IsStackAligned: isAligned, STI: Subtarget);
8890 }
8891
8892 DebugLoc DL;
8893 MachineInstrBuilder MIB = BuildMI(MF, MIMD: DL, MCID: get(Opcode: Opc), DestReg: Reg);
8894 for (const MachineOperand &AddrOp : AddrOps)
8895 MIB.add(MO: AddrOp);
8896 MIB.setMemRefs(MMOs);
8897 NewMIs.push_back(Elt: MIB);
8898
8899 if (UnfoldStore) {
8900 // Address operands cannot be marked isKill.
8901 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
8902 MachineOperand &MO = NewMIs[0]->getOperand(i);
8903 if (MO.isReg())
8904 MO.setIsKill(false);
8905 }
8906 }
8907 }
8908
8909 // Emit the data processing instruction.
8910 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, DL: MI.getDebugLoc(), NoImplicit: true);
8911 MachineInstrBuilder MIB(MF, DataMI);
8912
8913 if (FoldedStore)
8914 MIB.addReg(RegNo: Reg, Flags: RegState::Define);
8915 for (MachineOperand &BeforeOp : BeforeOps)
8916 MIB.add(MO: BeforeOp);
8917 if (FoldedLoad)
8918 MIB.addReg(RegNo: Reg);
8919 for (MachineOperand &AfterOp : AfterOps)
8920 MIB.add(MO: AfterOp);
8921 for (MachineOperand &ImpOp : ImpOps) {
8922 MIB.addReg(RegNo: ImpOp.getReg(), Flags: getDefRegState(B: ImpOp.isDef()) |
8923 RegState::Implicit |
8924 getKillRegState(B: ImpOp.isKill()) |
8925 getDeadRegState(B: ImpOp.isDead()) |
8926 getUndefRegState(B: ImpOp.isUndef()));
8927 }
8928 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
8929 switch (DataMI->getOpcode()) {
8930 default:
8931 break;
8932 case X86::CMP64ri32:
8933 case X86::CMP32ri:
8934 case X86::CMP16ri:
8935 case X86::CMP8ri: {
8936 MachineOperand &MO0 = DataMI->getOperand(i: 0);
8937 MachineOperand &MO1 = DataMI->getOperand(i: 1);
8938 if (MO1.isImm() && MO1.getImm() == 0) {
8939 unsigned NewOpc;
8940 switch (DataMI->getOpcode()) {
8941 default:
8942 llvm_unreachable("Unreachable!");
8943 case X86::CMP64ri32:
8944 NewOpc = X86::TEST64rr;
8945 break;
8946 case X86::CMP32ri:
8947 NewOpc = X86::TEST32rr;
8948 break;
8949 case X86::CMP16ri:
8950 NewOpc = X86::TEST16rr;
8951 break;
8952 case X86::CMP8ri:
8953 NewOpc = X86::TEST8rr;
8954 break;
8955 }
8956 DataMI->setDesc(get(Opcode: NewOpc));
8957 MO1.ChangeToRegister(Reg: MO0.getReg(), isDef: false);
8958 }
8959 }
8960 }
8961 NewMIs.push_back(Elt: DataMI);
8962
8963 // Emit the store instruction.
8964 if (UnfoldStore) {
8965 const TargetRegisterClass *DstRC = getRegClass(MCID, OpNum: 0);
8966 auto MMOs = extractStoreMMOs(MMOs: MI.memoperands(), MF);
8967 unsigned Alignment = std::max<uint32_t>(a: TRI.getSpillSize(RC: *DstRC), b: 16);
8968 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
8969 unsigned Opc = getStoreRegOpcode(SrcReg: Reg, RC: DstRC, IsStackAligned: isAligned, STI: Subtarget);
8970 DebugLoc DL;
8971 MachineInstrBuilder MIB = BuildMI(MF, MIMD: DL, MCID: get(Opcode: Opc));
8972 for (const MachineOperand &AddrOp : AddrOps)
8973 MIB.add(MO: AddrOp);
8974 MIB.addReg(RegNo: Reg, Flags: RegState::Kill);
8975 MIB.setMemRefs(MMOs);
8976 NewMIs.push_back(Elt: MIB);
8977 }
8978
8979 return true;
8980}
8981
8982bool X86InstrInfo::unfoldMemoryOperand(
8983 SelectionDAG &DAG, SDNode *N, SmallVectorImpl<SDNode *> &NewNodes) const {
8984 if (!N->isMachineOpcode())
8985 return false;
8986
8987 const X86FoldTableEntry *I = lookupUnfoldTable(MemOp: N->getMachineOpcode());
8988 if (I == nullptr)
8989 return false;
8990 unsigned Opc = I->DstOp;
8991 unsigned Index = I->Flags & TB_INDEX_MASK;
8992 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
8993 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
8994 const MCInstrDesc &MCID = get(Opcode: Opc);
8995 MachineFunction &MF = DAG.getMachineFunction();
8996 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
8997 const TargetRegisterClass *RC = getRegClass(MCID, OpNum: Index);
8998 unsigned NumDefs = MCID.NumDefs;
8999 std::vector<SDValue> AddrOps;
9000 std::vector<SDValue> BeforeOps;
9001 std::vector<SDValue> AfterOps;
9002 SDLoc dl(N);
9003 unsigned NumOps = N->getNumOperands();
9004 for (unsigned i = 0; i != NumOps - 1; ++i) {
9005 SDValue Op = N->getOperand(Num: i);
9006 if (i >= Index - NumDefs && i < Index - NumDefs + X86::AddrNumOperands)
9007 AddrOps.push_back(x: Op);
9008 else if (i < Index - NumDefs)
9009 BeforeOps.push_back(x: Op);
9010 else if (i > Index - NumDefs)
9011 AfterOps.push_back(x: Op);
9012 }
9013 SDValue Chain = N->getOperand(Num: NumOps - 1);
9014 AddrOps.push_back(x: Chain);
9015
9016 // Emit the load instruction.
9017 SDNode *Load = nullptr;
9018 if (FoldedLoad) {
9019 EVT VT = *TRI.legalclasstypes_begin(RC: *RC);
9020 auto MMOs = extractLoadMMOs(MMOs: cast<MachineSDNode>(Val: N)->memoperands(), MF);
9021 if (MMOs.empty() && RC == &X86::VR128RegClass &&
9022 Subtarget.isUnalignedMem16Slow())
9023 // Do not introduce a slow unaligned load.
9024 return false;
9025 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
9026 // memory access is slow above.
9027
9028 unsigned Opc;
9029 if (I->Flags & TB_BCAST_MASK) {
9030 Opc = getBroadcastOpcode(I, RC, STI: Subtarget);
9031 } else {
9032 unsigned Alignment = std::max<uint32_t>(a: TRI.getSpillSize(RC: *RC), b: 16);
9033 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
9034 Opc = getLoadRegOpcode(DestReg: 0, RC, IsStackAligned: isAligned, STI: Subtarget);
9035 }
9036
9037 Load = DAG.getMachineNode(Opcode: Opc, dl, VT1: VT, VT2: MVT::Other, Ops: AddrOps);
9038 NewNodes.push_back(Elt: Load);
9039
9040 // Preserve memory reference information.
9041 DAG.setNodeMemRefs(N: cast<MachineSDNode>(Val: Load), NewMemRefs: MMOs);
9042 }
9043
9044 // Emit the data processing instruction.
9045 std::vector<EVT> VTs;
9046 const TargetRegisterClass *DstRC = nullptr;
9047 if (MCID.getNumDefs() > 0) {
9048 DstRC = getRegClass(MCID, OpNum: 0);
9049 VTs.push_back(x: *TRI.legalclasstypes_begin(RC: *DstRC));
9050 }
9051 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
9052 EVT VT = N->getValueType(ResNo: i);
9053 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
9054 VTs.push_back(x: VT);
9055 }
9056 if (Load)
9057 BeforeOps.push_back(x: SDValue(Load, 0));
9058 llvm::append_range(C&: BeforeOps, R&: AfterOps);
9059 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
9060 switch (Opc) {
9061 default:
9062 break;
9063 case X86::CMP64ri32:
9064 case X86::CMP32ri:
9065 case X86::CMP16ri:
9066 case X86::CMP8ri:
9067 if (isNullConstant(V: BeforeOps[1])) {
9068 switch (Opc) {
9069 default:
9070 llvm_unreachable("Unreachable!");
9071 case X86::CMP64ri32:
9072 Opc = X86::TEST64rr;
9073 break;
9074 case X86::CMP32ri:
9075 Opc = X86::TEST32rr;
9076 break;
9077 case X86::CMP16ri:
9078 Opc = X86::TEST16rr;
9079 break;
9080 case X86::CMP8ri:
9081 Opc = X86::TEST8rr;
9082 break;
9083 }
9084 BeforeOps[1] = BeforeOps[0];
9085 }
9086 }
9087 SDNode *NewNode = DAG.getMachineNode(Opcode: Opc, dl, ResultTys: VTs, Ops: BeforeOps);
9088 NewNodes.push_back(Elt: NewNode);
9089
9090 // Emit the store instruction.
9091 if (FoldedStore) {
9092 AddrOps.pop_back();
9093 AddrOps.push_back(x: SDValue(NewNode, 0));
9094 AddrOps.push_back(x: Chain);
9095 auto MMOs = extractStoreMMOs(MMOs: cast<MachineSDNode>(Val: N)->memoperands(), MF);
9096 if (MMOs.empty() && RC == &X86::VR128RegClass &&
9097 Subtarget.isUnalignedMem16Slow())
9098 // Do not introduce a slow unaligned store.
9099 return false;
9100 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
9101 // memory access is slow above.
9102 unsigned Alignment = std::max<uint32_t>(a: TRI.getSpillSize(RC: *RC), b: 16);
9103 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
9104 SDNode *Store =
9105 DAG.getMachineNode(Opcode: getStoreRegOpcode(SrcReg: 0, RC: DstRC, IsStackAligned: isAligned, STI: Subtarget),
9106 dl, VT: MVT::Other, Ops: AddrOps);
9107 NewNodes.push_back(Elt: Store);
9108
9109 // Preserve memory reference information.
9110 DAG.setNodeMemRefs(N: cast<MachineSDNode>(Val: Store), NewMemRefs: MMOs);
9111 }
9112
9113 return true;
9114}
9115
9116unsigned
9117X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad,
9118 bool UnfoldStore,
9119 unsigned *LoadRegIndex) const {
9120 const X86FoldTableEntry *I = lookupUnfoldTable(MemOp: Opc);
9121 if (I == nullptr)
9122 return 0;
9123 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
9124 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
9125 if (UnfoldLoad && !FoldedLoad)
9126 return 0;
9127 if (UnfoldStore && !FoldedStore)
9128 return 0;
9129 if (LoadRegIndex)
9130 *LoadRegIndex = I->Flags & TB_INDEX_MASK;
9131 return I->DstOp;
9132}
9133
9134bool X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
9135 int64_t &Offset1,
9136 int64_t &Offset2) const {
9137 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
9138 return false;
9139
9140 auto IsLoadOpcode = [&](unsigned Opcode) {
9141 switch (Opcode) {
9142 default:
9143 return false;
9144 case X86::MOV8rm:
9145 case X86::MOV16rm:
9146 case X86::MOV32rm:
9147 case X86::MOV64rm:
9148 case X86::LD_Fp32m:
9149 case X86::LD_Fp64m:
9150 case X86::LD_Fp80m:
9151 case X86::MOVSSrm:
9152 case X86::MOVSSrm_alt:
9153 case X86::MOVSDrm:
9154 case X86::MOVSDrm_alt:
9155 case X86::MMX_MOVD64rm:
9156 case X86::MMX_MOVQ64rm:
9157 case X86::MOVAPSrm:
9158 case X86::MOVUPSrm:
9159 case X86::MOVAPDrm:
9160 case X86::MOVUPDrm:
9161 case X86::MOVDQArm:
9162 case X86::MOVDQUrm:
9163 // AVX load instructions
9164 case X86::VMOVSSrm:
9165 case X86::VMOVSSrm_alt:
9166 case X86::VMOVSDrm:
9167 case X86::VMOVSDrm_alt:
9168 case X86::VMOVAPSrm:
9169 case X86::VMOVUPSrm:
9170 case X86::VMOVAPDrm:
9171 case X86::VMOVUPDrm:
9172 case X86::VMOVDQArm:
9173 case X86::VMOVDQUrm:
9174 case X86::VMOVAPSYrm:
9175 case X86::VMOVUPSYrm:
9176 case X86::VMOVAPDYrm:
9177 case X86::VMOVUPDYrm:
9178 case X86::VMOVDQAYrm:
9179 case X86::VMOVDQUYrm:
9180 // AVX512 load instructions
9181 case X86::VMOVSSZrm:
9182 case X86::VMOVSSZrm_alt:
9183 case X86::VMOVSDZrm:
9184 case X86::VMOVSDZrm_alt:
9185 case X86::VMOVAPSZ128rm:
9186 case X86::VMOVUPSZ128rm:
9187 case X86::VMOVAPSZ128rm_NOVLX:
9188 case X86::VMOVUPSZ128rm_NOVLX:
9189 case X86::VMOVAPDZ128rm:
9190 case X86::VMOVUPDZ128rm:
9191 case X86::VMOVDQU8Z128rm:
9192 case X86::VMOVDQU16Z128rm:
9193 case X86::VMOVDQA32Z128rm:
9194 case X86::VMOVDQU32Z128rm:
9195 case X86::VMOVDQA64Z128rm:
9196 case X86::VMOVDQU64Z128rm:
9197 case X86::VMOVAPSZ256rm:
9198 case X86::VMOVUPSZ256rm:
9199 case X86::VMOVAPSZ256rm_NOVLX:
9200 case X86::VMOVUPSZ256rm_NOVLX:
9201 case X86::VMOVAPDZ256rm:
9202 case X86::VMOVUPDZ256rm:
9203 case X86::VMOVDQU8Z256rm:
9204 case X86::VMOVDQU16Z256rm:
9205 case X86::VMOVDQA32Z256rm:
9206 case X86::VMOVDQU32Z256rm:
9207 case X86::VMOVDQA64Z256rm:
9208 case X86::VMOVDQU64Z256rm:
9209 case X86::VMOVAPSZrm:
9210 case X86::VMOVUPSZrm:
9211 case X86::VMOVAPDZrm:
9212 case X86::VMOVUPDZrm:
9213 case X86::VMOVDQU8Zrm:
9214 case X86::VMOVDQU16Zrm:
9215 case X86::VMOVDQA32Zrm:
9216 case X86::VMOVDQU32Zrm:
9217 case X86::VMOVDQA64Zrm:
9218 case X86::VMOVDQU64Zrm:
9219 case X86::KMOVBkm:
9220 case X86::KMOVBkm_EVEX:
9221 case X86::KMOVWkm:
9222 case X86::KMOVWkm_EVEX:
9223 case X86::KMOVDkm:
9224 case X86::KMOVDkm_EVEX:
9225 case X86::KMOVQkm:
9226 case X86::KMOVQkm_EVEX:
9227 return true;
9228 }
9229 };
9230
9231 if (!IsLoadOpcode(Load1->getMachineOpcode()) ||
9232 !IsLoadOpcode(Load2->getMachineOpcode()))
9233 return false;
9234
9235 // Lambda to check if both the loads have the same value for an operand index.
9236 auto HasSameOp = [&](int I) {
9237 return Load1->getOperand(Num: I) == Load2->getOperand(Num: I);
9238 };
9239
9240 // All operands except the displacement should match.
9241 if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
9242 !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
9243 return false;
9244
9245 // Chain Operand must be the same.
9246 if (!HasSameOp(5))
9247 return false;
9248
9249 // Now let's examine if the displacements are constants.
9250 auto Disp1 = dyn_cast<ConstantSDNode>(Val: Load1->getOperand(Num: X86::AddrDisp));
9251 auto Disp2 = dyn_cast<ConstantSDNode>(Val: Load2->getOperand(Num: X86::AddrDisp));
9252 if (!Disp1 || !Disp2)
9253 return false;
9254
9255 Offset1 = Disp1->getSExtValue();
9256 Offset2 = Disp2->getSExtValue();
9257 return true;
9258}
9259
9260bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
9261 int64_t Offset1, int64_t Offset2,
9262 unsigned NumLoads) const {
9263 assert(Offset2 > Offset1);
9264 if ((Offset2 - Offset1) / 8 > 64)
9265 return false;
9266
9267 unsigned Opc1 = Load1->getMachineOpcode();
9268 unsigned Opc2 = Load2->getMachineOpcode();
9269 if (Opc1 != Opc2)
9270 return false; // FIXME: overly conservative?
9271
9272 switch (Opc1) {
9273 default:
9274 break;
9275 case X86::LD_Fp32m:
9276 case X86::LD_Fp64m:
9277 case X86::LD_Fp80m:
9278 case X86::MMX_MOVD64rm:
9279 case X86::MMX_MOVQ64rm:
9280 return false;
9281 }
9282
9283 EVT VT = Load1->getValueType(ResNo: 0);
9284 switch (VT.getSimpleVT().SimpleTy) {
9285 default:
9286 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
9287 // have 16 of them to play with.
9288 if (Subtarget.is64Bit()) {
9289 if (NumLoads >= 3)
9290 return false;
9291 } else if (NumLoads) {
9292 return false;
9293 }
9294 break;
9295 case MVT::i8:
9296 case MVT::i16:
9297 case MVT::i32:
9298 case MVT::i64:
9299 case MVT::f32:
9300 case MVT::f64:
9301 if (NumLoads)
9302 return false;
9303 break;
9304 }
9305
9306 return true;
9307}
9308
9309bool X86InstrInfo::isSchedulingBoundary(const MachineInstr &MI,
9310 const MachineBasicBlock *MBB,
9311 const MachineFunction &MF) const {
9312
9313 // ENDBR instructions should not be scheduled around.
9314 unsigned Opcode = MI.getOpcode();
9315 if (Opcode == X86::ENDBR64 || Opcode == X86::ENDBR32 ||
9316 Opcode == X86::PLDTILECFGV)
9317 return true;
9318
9319 // Frame setup and destroy can't be scheduled around.
9320 if (MI.getFlag(Flag: MachineInstr::FrameSetup) ||
9321 MI.getFlag(Flag: MachineInstr::FrameDestroy))
9322 return true;
9323
9324 return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF);
9325}
9326
9327bool X86InstrInfo::reverseBranchCondition(
9328 SmallVectorImpl<MachineOperand> &Cond) const {
9329 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
9330 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
9331 Cond[0].setImm(GetOppositeBranchCondition(CC));
9332 return false;
9333}
9334
9335bool X86InstrInfo::isSafeToMoveRegClassDefs(
9336 const TargetRegisterClass *RC) const {
9337 // FIXME: Return false for x87 stack register classes for now. We can't
9338 // allow any loads of these registers before FpGet_ST0_80.
9339 return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
9340 RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
9341 RC == &X86::RFP80RegClass);
9342}
9343
9344/// Return a virtual register initialized with the
9345/// the global base register value. Output instructions required to
9346/// initialize the register in the function entry block, if necessary.
9347///
9348/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
9349///
9350Register X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
9351 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
9352 Register GlobalBaseReg = X86FI->getGlobalBaseReg();
9353 if (GlobalBaseReg)
9354 return GlobalBaseReg;
9355
9356 // Create the register. The code to initialize it is inserted
9357 // later, by the CGBR pass (below).
9358 MachineRegisterInfo &RegInfo = MF->getRegInfo();
9359 GlobalBaseReg = RegInfo.createVirtualRegister(
9360 RegClass: Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
9361 X86FI->setGlobalBaseReg(GlobalBaseReg);
9362 return GlobalBaseReg;
9363}
9364
9365// FIXME: Some shuffle and unpack instructions have equivalents in different
9366// domains, but they require a bit more work than just switching opcodes.
9367
9368static const uint16_t *lookup(unsigned opcode, unsigned domain,
9369 ArrayRef<uint16_t[3]> Table) {
9370 for (const uint16_t(&Row)[3] : Table)
9371 if (Row[domain - 1] == opcode)
9372 return Row;
9373 return nullptr;
9374}
9375
9376static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
9377 ArrayRef<uint16_t[4]> Table) {
9378 // If this is the integer domain make sure to check both integer columns.
9379 for (const uint16_t(&Row)[4] : Table)
9380 if (Row[domain - 1] == opcode || (domain == 3 && Row[3] == opcode))
9381 return Row;
9382 return nullptr;
9383}
9384
9385// Helper to attempt to widen/narrow blend masks.
9386static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
9387 unsigned NewWidth, unsigned *pNewMask = nullptr) {
9388 assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
9389 "Illegal blend mask scale");
9390 unsigned NewMask = 0;
9391
9392 if ((OldWidth % NewWidth) == 0) {
9393 unsigned Scale = OldWidth / NewWidth;
9394 unsigned SubMask = (1u << Scale) - 1;
9395 for (unsigned i = 0; i != NewWidth; ++i) {
9396 unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
9397 if (Sub == SubMask)
9398 NewMask |= (1u << i);
9399 else if (Sub != 0x0)
9400 return false;
9401 }
9402 } else {
9403 unsigned Scale = NewWidth / OldWidth;
9404 unsigned SubMask = (1u << Scale) - 1;
9405 for (unsigned i = 0; i != OldWidth; ++i) {
9406 if (OldMask & (1 << i)) {
9407 NewMask |= (SubMask << (i * Scale));
9408 }
9409 }
9410 }
9411
9412 if (pNewMask)
9413 *pNewMask = NewMask;
9414 return true;
9415}
9416
9417uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
9418 unsigned Opcode = MI.getOpcode();
9419 unsigned NumOperands = MI.getDesc().getNumOperands();
9420
9421 auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
9422 uint16_t validDomains = 0;
9423 if (MI.getOperand(i: NumOperands - 1).isImm()) {
9424 unsigned Imm = MI.getOperand(i: NumOperands - 1).getImm();
9425 if (AdjustBlendMask(OldMask: Imm, OldWidth: ImmWidth, NewWidth: Is256 ? 8 : 4))
9426 validDomains |= 0x2; // PackedSingle
9427 if (AdjustBlendMask(OldMask: Imm, OldWidth: ImmWidth, NewWidth: Is256 ? 4 : 2))
9428 validDomains |= 0x4; // PackedDouble
9429 if (!Is256 || Subtarget.hasAVX2())
9430 validDomains |= 0x8; // PackedInt
9431 }
9432 return validDomains;
9433 };
9434
9435 switch (Opcode) {
9436 case X86::BLENDPDrmi:
9437 case X86::BLENDPDrri:
9438 case X86::VBLENDPDrmi:
9439 case X86::VBLENDPDrri:
9440 return GetBlendDomains(2, false);
9441 case X86::VBLENDPDYrmi:
9442 case X86::VBLENDPDYrri:
9443 return GetBlendDomains(4, true);
9444 case X86::BLENDPSrmi:
9445 case X86::BLENDPSrri:
9446 case X86::VBLENDPSrmi:
9447 case X86::VBLENDPSrri:
9448 case X86::VPBLENDDrmi:
9449 case X86::VPBLENDDrri:
9450 return GetBlendDomains(4, false);
9451 case X86::VBLENDPSYrmi:
9452 case X86::VBLENDPSYrri:
9453 case X86::VPBLENDDYrmi:
9454 case X86::VPBLENDDYrri:
9455 return GetBlendDomains(8, true);
9456 case X86::PBLENDWrmi:
9457 case X86::PBLENDWrri:
9458 case X86::VPBLENDWrmi:
9459 case X86::VPBLENDWrri:
9460 // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
9461 case X86::VPBLENDWYrmi:
9462 case X86::VPBLENDWYrri:
9463 return GetBlendDomains(8, false);
9464 case X86::VPANDDZ128rr:
9465 case X86::VPANDDZ128rm:
9466 case X86::VPANDDZ256rr:
9467 case X86::VPANDDZ256rm:
9468 case X86::VPANDQZ128rr:
9469 case X86::VPANDQZ128rm:
9470 case X86::VPANDQZ256rr:
9471 case X86::VPANDQZ256rm:
9472 case X86::VPANDNDZ128rr:
9473 case X86::VPANDNDZ128rm:
9474 case X86::VPANDNDZ256rr:
9475 case X86::VPANDNDZ256rm:
9476 case X86::VPANDNQZ128rr:
9477 case X86::VPANDNQZ128rm:
9478 case X86::VPANDNQZ256rr:
9479 case X86::VPANDNQZ256rm:
9480 case X86::VPORDZ128rr:
9481 case X86::VPORDZ128rm:
9482 case X86::VPORDZ256rr:
9483 case X86::VPORDZ256rm:
9484 case X86::VPORQZ128rr:
9485 case X86::VPORQZ128rm:
9486 case X86::VPORQZ256rr:
9487 case X86::VPORQZ256rm:
9488 case X86::VPXORDZ128rr:
9489 case X86::VPXORDZ128rm:
9490 case X86::VPXORDZ256rr:
9491 case X86::VPXORDZ256rm:
9492 case X86::VPXORQZ128rr:
9493 case X86::VPXORQZ128rm:
9494 case X86::VPXORQZ256rr:
9495 case X86::VPXORQZ256rm:
9496 // If we don't have DQI see if we can still switch from an EVEX integer
9497 // instruction to a VEX floating point instruction.
9498 if (Subtarget.hasDQI())
9499 return 0;
9500
9501 if (RI.getEncodingValue(Reg: MI.getOperand(i: 0).getReg()) >= 16)
9502 return 0;
9503 if (RI.getEncodingValue(Reg: MI.getOperand(i: 1).getReg()) >= 16)
9504 return 0;
9505 // Register forms will have 3 operands. Memory form will have more.
9506 if (NumOperands == 3 &&
9507 RI.getEncodingValue(Reg: MI.getOperand(i: 2).getReg()) >= 16)
9508 return 0;
9509
9510 // All domains are valid.
9511 return 0xe;
9512 case X86::MOVHLPSrr:
9513 // We can swap domains when both inputs are the same register.
9514 // FIXME: This doesn't catch all the cases we would like. If the input
9515 // register isn't KILLed by the instruction, the two address instruction
9516 // pass puts a COPY on one input. The other input uses the original
9517 // register. This prevents the same physical register from being used by
9518 // both inputs.
9519 if (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 2).getReg() &&
9520 MI.getOperand(i: 0).getSubReg() == 0 &&
9521 MI.getOperand(i: 1).getSubReg() == 0 && MI.getOperand(i: 2).getSubReg() == 0)
9522 return 0x6;
9523 return 0;
9524 case X86::SHUFPDrri:
9525 return 0x6;
9526 }
9527 return 0;
9528}
9529
9530#include "X86ReplaceableInstrs.def"
9531
9532bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
9533 unsigned Domain) const {
9534 assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
9535 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
9536 assert(dom && "Not an SSE instruction");
9537
9538 unsigned Opcode = MI.getOpcode();
9539 unsigned NumOperands = MI.getDesc().getNumOperands();
9540
9541 auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
9542 if (MI.getOperand(i: NumOperands - 1).isImm()) {
9543 unsigned Imm = MI.getOperand(i: NumOperands - 1).getImm() & 255;
9544 Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
9545 unsigned NewImm = Imm;
9546
9547 const uint16_t *table = lookup(opcode: Opcode, domain: dom, Table: ReplaceableBlendInstrs);
9548 if (!table)
9549 table = lookup(opcode: Opcode, domain: dom, Table: ReplaceableBlendAVX2Instrs);
9550
9551 if (Domain == 1) { // PackedSingle
9552 AdjustBlendMask(OldMask: Imm, OldWidth: ImmWidth, NewWidth: Is256 ? 8 : 4, pNewMask: &NewImm);
9553 } else if (Domain == 2) { // PackedDouble
9554 AdjustBlendMask(OldMask: Imm, OldWidth: ImmWidth, NewWidth: Is256 ? 4 : 2, pNewMask: &NewImm);
9555 } else if (Domain == 3) { // PackedInt
9556 if (Subtarget.hasAVX2()) {
9557 // If we are already VPBLENDW use that, else use VPBLENDD.
9558 if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
9559 table = lookup(opcode: Opcode, domain: dom, Table: ReplaceableBlendAVX2Instrs);
9560 AdjustBlendMask(OldMask: Imm, OldWidth: ImmWidth, NewWidth: Is256 ? 8 : 4, pNewMask: &NewImm);
9561 }
9562 } else {
9563 assert(!Is256 && "128-bit vector expected");
9564 AdjustBlendMask(OldMask: Imm, OldWidth: ImmWidth, NewWidth: 8, pNewMask: &NewImm);
9565 }
9566 }
9567
9568 assert(table && table[Domain - 1] && "Unknown domain op");
9569 MI.setDesc(get(Opcode: table[Domain - 1]));
9570 MI.getOperand(i: NumOperands - 1).setImm(NewImm & 255);
9571 }
9572 return true;
9573 };
9574
9575 switch (Opcode) {
9576 case X86::BLENDPDrmi:
9577 case X86::BLENDPDrri:
9578 case X86::VBLENDPDrmi:
9579 case X86::VBLENDPDrri:
9580 return SetBlendDomain(2, false);
9581 case X86::VBLENDPDYrmi:
9582 case X86::VBLENDPDYrri:
9583 return SetBlendDomain(4, true);
9584 case X86::BLENDPSrmi:
9585 case X86::BLENDPSrri:
9586 case X86::VBLENDPSrmi:
9587 case X86::VBLENDPSrri:
9588 case X86::VPBLENDDrmi:
9589 case X86::VPBLENDDrri:
9590 return SetBlendDomain(4, false);
9591 case X86::VBLENDPSYrmi:
9592 case X86::VBLENDPSYrri:
9593 case X86::VPBLENDDYrmi:
9594 case X86::VPBLENDDYrri:
9595 return SetBlendDomain(8, true);
9596 case X86::PBLENDWrmi:
9597 case X86::PBLENDWrri:
9598 case X86::VPBLENDWrmi:
9599 case X86::VPBLENDWrri:
9600 return SetBlendDomain(8, false);
9601 case X86::VPBLENDWYrmi:
9602 case X86::VPBLENDWYrri:
9603 return SetBlendDomain(16, true);
9604 case X86::VPANDDZ128rr:
9605 case X86::VPANDDZ128rm:
9606 case X86::VPANDDZ256rr:
9607 case X86::VPANDDZ256rm:
9608 case X86::VPANDQZ128rr:
9609 case X86::VPANDQZ128rm:
9610 case X86::VPANDQZ256rr:
9611 case X86::VPANDQZ256rm:
9612 case X86::VPANDNDZ128rr:
9613 case X86::VPANDNDZ128rm:
9614 case X86::VPANDNDZ256rr:
9615 case X86::VPANDNDZ256rm:
9616 case X86::VPANDNQZ128rr:
9617 case X86::VPANDNQZ128rm:
9618 case X86::VPANDNQZ256rr:
9619 case X86::VPANDNQZ256rm:
9620 case X86::VPORDZ128rr:
9621 case X86::VPORDZ128rm:
9622 case X86::VPORDZ256rr:
9623 case X86::VPORDZ256rm:
9624 case X86::VPORQZ128rr:
9625 case X86::VPORQZ128rm:
9626 case X86::VPORQZ256rr:
9627 case X86::VPORQZ256rm:
9628 case X86::VPXORDZ128rr:
9629 case X86::VPXORDZ128rm:
9630 case X86::VPXORDZ256rr:
9631 case X86::VPXORDZ256rm:
9632 case X86::VPXORQZ128rr:
9633 case X86::VPXORQZ128rm:
9634 case X86::VPXORQZ256rr:
9635 case X86::VPXORQZ256rm: {
9636 // Without DQI, convert EVEX instructions to VEX instructions.
9637 if (Subtarget.hasDQI())
9638 return false;
9639
9640 const uint16_t *table =
9641 lookupAVX512(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableCustomAVX512LogicInstrs);
9642 assert(table && "Instruction not found in table?");
9643 // Don't change integer Q instructions to D instructions and
9644 // use D intructions if we started with a PS instruction.
9645 if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
9646 Domain = 4;
9647 MI.setDesc(get(Opcode: table[Domain - 1]));
9648 return true;
9649 }
9650 case X86::UNPCKHPDrr:
9651 case X86::MOVHLPSrr:
9652 // We just need to commute the instruction which will switch the domains.
9653 if (Domain != dom && Domain != 3 &&
9654 MI.getOperand(i: 1).getReg() == MI.getOperand(i: 2).getReg() &&
9655 MI.getOperand(i: 0).getSubReg() == 0 &&
9656 MI.getOperand(i: 1).getSubReg() == 0 &&
9657 MI.getOperand(i: 2).getSubReg() == 0) {
9658 commuteInstruction(MI, NewMI: false);
9659 return true;
9660 }
9661 // We must always return true for MOVHLPSrr.
9662 if (Opcode == X86::MOVHLPSrr)
9663 return true;
9664 break;
9665 case X86::SHUFPDrri: {
9666 if (Domain == 1) {
9667 unsigned Imm = MI.getOperand(i: 3).getImm();
9668 unsigned NewImm = 0x44;
9669 if (Imm & 1)
9670 NewImm |= 0x0a;
9671 if (Imm & 2)
9672 NewImm |= 0xa0;
9673 MI.getOperand(i: 3).setImm(NewImm);
9674 MI.setDesc(get(Opcode: X86::SHUFPSrri));
9675 }
9676 return true;
9677 }
9678 }
9679 return false;
9680}
9681
9682std::pair<uint16_t, uint16_t>
9683X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
9684 uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
9685 unsigned opcode = MI.getOpcode();
9686 uint16_t validDomains = 0;
9687 if (domain) {
9688 // Attempt to match for custom instructions.
9689 validDomains = getExecutionDomainCustom(MI);
9690 if (validDomains)
9691 return std::make_pair(x&: domain, y&: validDomains);
9692
9693 if (lookup(opcode, domain, Table: ReplaceableInstrs)) {
9694 validDomains = 0xe;
9695 } else if (lookup(opcode, domain, Table: ReplaceableInstrsAVX2)) {
9696 validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
9697 } else if (lookup(opcode, domain, Table: ReplaceableInstrsFP)) {
9698 validDomains = 0x6;
9699 } else if (lookup(opcode, domain, Table: ReplaceableInstrsAVX2InsertExtract)) {
9700 // Insert/extract instructions should only effect domain if AVX2
9701 // is enabled.
9702 if (!Subtarget.hasAVX2())
9703 return std::make_pair(x: 0, y: 0);
9704 validDomains = 0xe;
9705 } else if (lookupAVX512(opcode, domain, Table: ReplaceableInstrsAVX512)) {
9706 validDomains = 0xe;
9707 } else if (Subtarget.hasDQI() &&
9708 lookupAVX512(opcode, domain, Table: ReplaceableInstrsAVX512DQ)) {
9709 validDomains = 0xe;
9710 } else if (Subtarget.hasDQI()) {
9711 if (const uint16_t *table =
9712 lookupAVX512(opcode, domain, Table: ReplaceableInstrsAVX512DQMasked)) {
9713 if (domain == 1 || (domain == 3 && table[3] == opcode))
9714 validDomains = 0xa;
9715 else
9716 validDomains = 0xc;
9717 }
9718 }
9719 }
9720 return std::make_pair(x&: domain, y&: validDomains);
9721}
9722
9723void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
9724 assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
9725 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
9726 assert(dom && "Not an SSE instruction");
9727
9728 // Attempt to match for custom instructions.
9729 if (setExecutionDomainCustom(MI, Domain))
9730 return;
9731
9732 const uint16_t *table = lookup(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrs);
9733 if (!table) { // try the other table
9734 assert((Subtarget.hasAVX2() || Domain < 3) &&
9735 "256-bit vector operations only available in AVX2");
9736 table = lookup(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrsAVX2);
9737 }
9738 if (!table) { // try the FP table
9739 table = lookup(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrsFP);
9740 assert((!table || Domain < 3) &&
9741 "Can only select PackedSingle or PackedDouble");
9742 }
9743 if (!table) { // try the other table
9744 assert(Subtarget.hasAVX2() &&
9745 "256-bit insert/extract only available in AVX2");
9746 table = lookup(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrsAVX2InsertExtract);
9747 }
9748 if (!table) { // try the AVX512 table
9749 assert(Subtarget.hasAVX512() && "Requires AVX-512");
9750 table = lookupAVX512(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrsAVX512);
9751 // Don't change integer Q instructions to D instructions.
9752 if (table && Domain == 3 && table[3] == MI.getOpcode())
9753 Domain = 4;
9754 }
9755 if (!table) { // try the AVX512DQ table
9756 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
9757 table = lookupAVX512(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrsAVX512DQ);
9758 // Don't change integer Q instructions to D instructions and
9759 // use D instructions if we started with a PS instruction.
9760 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
9761 Domain = 4;
9762 }
9763 if (!table) { // try the AVX512DQMasked table
9764 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
9765 table = lookupAVX512(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrsAVX512DQMasked);
9766 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
9767 Domain = 4;
9768 }
9769 assert(table && "Cannot change domain");
9770 MI.setDesc(get(Opcode: table[Domain - 1]));
9771}
9772
9773void X86InstrInfo::insertNoop(MachineBasicBlock &MBB,
9774 MachineBasicBlock::iterator MI) const {
9775 DebugLoc DL;
9776 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: get(Opcode: X86::NOOP));
9777}
9778
9779/// Return the noop instruction to use for a noop.
9780MCInst X86InstrInfo::getNop() const {
9781 MCInst Nop;
9782 Nop.setOpcode(X86::NOOP);
9783 return Nop;
9784}
9785
9786bool X86InstrInfo::isHighLatencyDef(int opc) const {
9787 switch (opc) {
9788 default:
9789 return false;
9790 case X86::DIVPDrm:
9791 case X86::DIVPDrr:
9792 case X86::DIVPSrm:
9793 case X86::DIVPSrr:
9794 case X86::DIVSDrm:
9795 case X86::DIVSDrm_Int:
9796 case X86::DIVSDrr:
9797 case X86::DIVSDrr_Int:
9798 case X86::DIVSSrm:
9799 case X86::DIVSSrm_Int:
9800 case X86::DIVSSrr:
9801 case X86::DIVSSrr_Int:
9802 case X86::SQRTPDm:
9803 case X86::SQRTPDr:
9804 case X86::SQRTPSm:
9805 case X86::SQRTPSr:
9806 case X86::SQRTSDm:
9807 case X86::SQRTSDm_Int:
9808 case X86::SQRTSDr:
9809 case X86::SQRTSDr_Int:
9810 case X86::SQRTSSm:
9811 case X86::SQRTSSm_Int:
9812 case X86::SQRTSSr:
9813 case X86::SQRTSSr_Int:
9814 // AVX instructions with high latency
9815 case X86::VDIVPDrm:
9816 case X86::VDIVPDrr:
9817 case X86::VDIVPDYrm:
9818 case X86::VDIVPDYrr:
9819 case X86::VDIVPSrm:
9820 case X86::VDIVPSrr:
9821 case X86::VDIVPSYrm:
9822 case X86::VDIVPSYrr:
9823 case X86::VDIVSDrm:
9824 case X86::VDIVSDrm_Int:
9825 case X86::VDIVSDrr:
9826 case X86::VDIVSDrr_Int:
9827 case X86::VDIVSSrm:
9828 case X86::VDIVSSrm_Int:
9829 case X86::VDIVSSrr:
9830 case X86::VDIVSSrr_Int:
9831 case X86::VSQRTPDm:
9832 case X86::VSQRTPDr:
9833 case X86::VSQRTPDYm:
9834 case X86::VSQRTPDYr:
9835 case X86::VSQRTPSm:
9836 case X86::VSQRTPSr:
9837 case X86::VSQRTPSYm:
9838 case X86::VSQRTPSYr:
9839 case X86::VSQRTSDm:
9840 case X86::VSQRTSDm_Int:
9841 case X86::VSQRTSDr:
9842 case X86::VSQRTSDr_Int:
9843 case X86::VSQRTSSm:
9844 case X86::VSQRTSSm_Int:
9845 case X86::VSQRTSSr:
9846 case X86::VSQRTSSr_Int:
9847 // AVX512 instructions with high latency
9848 case X86::VDIVPDZ128rm:
9849 case X86::VDIVPDZ128rmb:
9850 case X86::VDIVPDZ128rmbk:
9851 case X86::VDIVPDZ128rmbkz:
9852 case X86::VDIVPDZ128rmk:
9853 case X86::VDIVPDZ128rmkz:
9854 case X86::VDIVPDZ128rr:
9855 case X86::VDIVPDZ128rrk:
9856 case X86::VDIVPDZ128rrkz:
9857 case X86::VDIVPDZ256rm:
9858 case X86::VDIVPDZ256rmb:
9859 case X86::VDIVPDZ256rmbk:
9860 case X86::VDIVPDZ256rmbkz:
9861 case X86::VDIVPDZ256rmk:
9862 case X86::VDIVPDZ256rmkz:
9863 case X86::VDIVPDZ256rr:
9864 case X86::VDIVPDZ256rrk:
9865 case X86::VDIVPDZ256rrkz:
9866 case X86::VDIVPDZrrb:
9867 case X86::VDIVPDZrrbk:
9868 case X86::VDIVPDZrrbkz:
9869 case X86::VDIVPDZrm:
9870 case X86::VDIVPDZrmb:
9871 case X86::VDIVPDZrmbk:
9872 case X86::VDIVPDZrmbkz:
9873 case X86::VDIVPDZrmk:
9874 case X86::VDIVPDZrmkz:
9875 case X86::VDIVPDZrr:
9876 case X86::VDIVPDZrrk:
9877 case X86::VDIVPDZrrkz:
9878 case X86::VDIVPSZ128rm:
9879 case X86::VDIVPSZ128rmb:
9880 case X86::VDIVPSZ128rmbk:
9881 case X86::VDIVPSZ128rmbkz:
9882 case X86::VDIVPSZ128rmk:
9883 case X86::VDIVPSZ128rmkz:
9884 case X86::VDIVPSZ128rr:
9885 case X86::VDIVPSZ128rrk:
9886 case X86::VDIVPSZ128rrkz:
9887 case X86::VDIVPSZ256rm:
9888 case X86::VDIVPSZ256rmb:
9889 case X86::VDIVPSZ256rmbk:
9890 case X86::VDIVPSZ256rmbkz:
9891 case X86::VDIVPSZ256rmk:
9892 case X86::VDIVPSZ256rmkz:
9893 case X86::VDIVPSZ256rr:
9894 case X86::VDIVPSZ256rrk:
9895 case X86::VDIVPSZ256rrkz:
9896 case X86::VDIVPSZrrb:
9897 case X86::VDIVPSZrrbk:
9898 case X86::VDIVPSZrrbkz:
9899 case X86::VDIVPSZrm:
9900 case X86::VDIVPSZrmb:
9901 case X86::VDIVPSZrmbk:
9902 case X86::VDIVPSZrmbkz:
9903 case X86::VDIVPSZrmk:
9904 case X86::VDIVPSZrmkz:
9905 case X86::VDIVPSZrr:
9906 case X86::VDIVPSZrrk:
9907 case X86::VDIVPSZrrkz:
9908 case X86::VDIVSDZrm:
9909 case X86::VDIVSDZrr:
9910 case X86::VDIVSDZrm_Int:
9911 case X86::VDIVSDZrmk_Int:
9912 case X86::VDIVSDZrmkz_Int:
9913 case X86::VDIVSDZrr_Int:
9914 case X86::VDIVSDZrrk_Int:
9915 case X86::VDIVSDZrrkz_Int:
9916 case X86::VDIVSDZrrb_Int:
9917 case X86::VDIVSDZrrbk_Int:
9918 case X86::VDIVSDZrrbkz_Int:
9919 case X86::VDIVSSZrm:
9920 case X86::VDIVSSZrr:
9921 case X86::VDIVSSZrm_Int:
9922 case X86::VDIVSSZrmk_Int:
9923 case X86::VDIVSSZrmkz_Int:
9924 case X86::VDIVSSZrr_Int:
9925 case X86::VDIVSSZrrk_Int:
9926 case X86::VDIVSSZrrkz_Int:
9927 case X86::VDIVSSZrrb_Int:
9928 case X86::VDIVSSZrrbk_Int:
9929 case X86::VDIVSSZrrbkz_Int:
9930 case X86::VSQRTPDZ128m:
9931 case X86::VSQRTPDZ128mb:
9932 case X86::VSQRTPDZ128mbk:
9933 case X86::VSQRTPDZ128mbkz:
9934 case X86::VSQRTPDZ128mk:
9935 case X86::VSQRTPDZ128mkz:
9936 case X86::VSQRTPDZ128r:
9937 case X86::VSQRTPDZ128rk:
9938 case X86::VSQRTPDZ128rkz:
9939 case X86::VSQRTPDZ256m:
9940 case X86::VSQRTPDZ256mb:
9941 case X86::VSQRTPDZ256mbk:
9942 case X86::VSQRTPDZ256mbkz:
9943 case X86::VSQRTPDZ256mk:
9944 case X86::VSQRTPDZ256mkz:
9945 case X86::VSQRTPDZ256r:
9946 case X86::VSQRTPDZ256rk:
9947 case X86::VSQRTPDZ256rkz:
9948 case X86::VSQRTPDZm:
9949 case X86::VSQRTPDZmb:
9950 case X86::VSQRTPDZmbk:
9951 case X86::VSQRTPDZmbkz:
9952 case X86::VSQRTPDZmk:
9953 case X86::VSQRTPDZmkz:
9954 case X86::VSQRTPDZr:
9955 case X86::VSQRTPDZrb:
9956 case X86::VSQRTPDZrbk:
9957 case X86::VSQRTPDZrbkz:
9958 case X86::VSQRTPDZrk:
9959 case X86::VSQRTPDZrkz:
9960 case X86::VSQRTPSZ128m:
9961 case X86::VSQRTPSZ128mb:
9962 case X86::VSQRTPSZ128mbk:
9963 case X86::VSQRTPSZ128mbkz:
9964 case X86::VSQRTPSZ128mk:
9965 case X86::VSQRTPSZ128mkz:
9966 case X86::VSQRTPSZ128r:
9967 case X86::VSQRTPSZ128rk:
9968 case X86::VSQRTPSZ128rkz:
9969 case X86::VSQRTPSZ256m:
9970 case X86::VSQRTPSZ256mb:
9971 case X86::VSQRTPSZ256mbk:
9972 case X86::VSQRTPSZ256mbkz:
9973 case X86::VSQRTPSZ256mk:
9974 case X86::VSQRTPSZ256mkz:
9975 case X86::VSQRTPSZ256r:
9976 case X86::VSQRTPSZ256rk:
9977 case X86::VSQRTPSZ256rkz:
9978 case X86::VSQRTPSZm:
9979 case X86::VSQRTPSZmb:
9980 case X86::VSQRTPSZmbk:
9981 case X86::VSQRTPSZmbkz:
9982 case X86::VSQRTPSZmk:
9983 case X86::VSQRTPSZmkz:
9984 case X86::VSQRTPSZr:
9985 case X86::VSQRTPSZrb:
9986 case X86::VSQRTPSZrbk:
9987 case X86::VSQRTPSZrbkz:
9988 case X86::VSQRTPSZrk:
9989 case X86::VSQRTPSZrkz:
9990 case X86::VSQRTSDZm:
9991 case X86::VSQRTSDZm_Int:
9992 case X86::VSQRTSDZmk_Int:
9993 case X86::VSQRTSDZmkz_Int:
9994 case X86::VSQRTSDZr:
9995 case X86::VSQRTSDZr_Int:
9996 case X86::VSQRTSDZrk_Int:
9997 case X86::VSQRTSDZrkz_Int:
9998 case X86::VSQRTSDZrb_Int:
9999 case X86::VSQRTSDZrbk_Int:
10000 case X86::VSQRTSDZrbkz_Int:
10001 case X86::VSQRTSSZm:
10002 case X86::VSQRTSSZm_Int:
10003 case X86::VSQRTSSZmk_Int:
10004 case X86::VSQRTSSZmkz_Int:
10005 case X86::VSQRTSSZr:
10006 case X86::VSQRTSSZr_Int:
10007 case X86::VSQRTSSZrk_Int:
10008 case X86::VSQRTSSZrkz_Int:
10009 case X86::VSQRTSSZrb_Int:
10010 case X86::VSQRTSSZrbk_Int:
10011 case X86::VSQRTSSZrbkz_Int:
10012
10013 case X86::VGATHERDPDYrm:
10014 case X86::VGATHERDPDZ128rm:
10015 case X86::VGATHERDPDZ256rm:
10016 case X86::VGATHERDPDZrm:
10017 case X86::VGATHERDPDrm:
10018 case X86::VGATHERDPSYrm:
10019 case X86::VGATHERDPSZ128rm:
10020 case X86::VGATHERDPSZ256rm:
10021 case X86::VGATHERDPSZrm:
10022 case X86::VGATHERDPSrm:
10023 case X86::VGATHERPF0DPDm:
10024 case X86::VGATHERPF0DPSm:
10025 case X86::VGATHERPF0QPDm:
10026 case X86::VGATHERPF0QPSm:
10027 case X86::VGATHERPF1DPDm:
10028 case X86::VGATHERPF1DPSm:
10029 case X86::VGATHERPF1QPDm:
10030 case X86::VGATHERPF1QPSm:
10031 case X86::VGATHERQPDYrm:
10032 case X86::VGATHERQPDZ128rm:
10033 case X86::VGATHERQPDZ256rm:
10034 case X86::VGATHERQPDZrm:
10035 case X86::VGATHERQPDrm:
10036 case X86::VGATHERQPSYrm:
10037 case X86::VGATHERQPSZ128rm:
10038 case X86::VGATHERQPSZ256rm:
10039 case X86::VGATHERQPSZrm:
10040 case X86::VGATHERQPSrm:
10041 case X86::VPGATHERDDYrm:
10042 case X86::VPGATHERDDZ128rm:
10043 case X86::VPGATHERDDZ256rm:
10044 case X86::VPGATHERDDZrm:
10045 case X86::VPGATHERDDrm:
10046 case X86::VPGATHERDQYrm:
10047 case X86::VPGATHERDQZ128rm:
10048 case X86::VPGATHERDQZ256rm:
10049 case X86::VPGATHERDQZrm:
10050 case X86::VPGATHERDQrm:
10051 case X86::VPGATHERQDYrm:
10052 case X86::VPGATHERQDZ128rm:
10053 case X86::VPGATHERQDZ256rm:
10054 case X86::VPGATHERQDZrm:
10055 case X86::VPGATHERQDrm:
10056 case X86::VPGATHERQQYrm:
10057 case X86::VPGATHERQQZ128rm:
10058 case X86::VPGATHERQQZ256rm:
10059 case X86::VPGATHERQQZrm:
10060 case X86::VPGATHERQQrm:
10061 case X86::VSCATTERDPDZ128mr:
10062 case X86::VSCATTERDPDZ256mr:
10063 case X86::VSCATTERDPDZmr:
10064 case X86::VSCATTERDPSZ128mr:
10065 case X86::VSCATTERDPSZ256mr:
10066 case X86::VSCATTERDPSZmr:
10067 case X86::VSCATTERPF0DPDm:
10068 case X86::VSCATTERPF0DPSm:
10069 case X86::VSCATTERPF0QPDm:
10070 case X86::VSCATTERPF0QPSm:
10071 case X86::VSCATTERPF1DPDm:
10072 case X86::VSCATTERPF1DPSm:
10073 case X86::VSCATTERPF1QPDm:
10074 case X86::VSCATTERPF1QPSm:
10075 case X86::VSCATTERQPDZ128mr:
10076 case X86::VSCATTERQPDZ256mr:
10077 case X86::VSCATTERQPDZmr:
10078 case X86::VSCATTERQPSZ128mr:
10079 case X86::VSCATTERQPSZ256mr:
10080 case X86::VSCATTERQPSZmr:
10081 case X86::VPSCATTERDDZ128mr:
10082 case X86::VPSCATTERDDZ256mr:
10083 case X86::VPSCATTERDDZmr:
10084 case X86::VPSCATTERDQZ128mr:
10085 case X86::VPSCATTERDQZ256mr:
10086 case X86::VPSCATTERDQZmr:
10087 case X86::VPSCATTERQDZ128mr:
10088 case X86::VPSCATTERQDZ256mr:
10089 case X86::VPSCATTERQDZmr:
10090 case X86::VPSCATTERQQZ128mr:
10091 case X86::VPSCATTERQQZ256mr:
10092 case X86::VPSCATTERQQZmr:
10093 return true;
10094 }
10095}
10096
10097bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
10098 const MachineRegisterInfo *MRI,
10099 const MachineInstr &DefMI,
10100 unsigned DefIdx,
10101 const MachineInstr &UseMI,
10102 unsigned UseIdx) const {
10103 return isHighLatencyDef(opc: DefMI.getOpcode());
10104}
10105
10106bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
10107 const MachineBasicBlock *MBB) const {
10108 assert(Inst.getNumExplicitOperands() == 3 && Inst.getNumExplicitDefs() == 1 &&
10109 Inst.getNumDefs() <= 2 && "Reassociation needs binary operators");
10110
10111 // Integer binary math/logic instructions have a third source operand:
10112 // the EFLAGS register. That operand must be both defined here and never
10113 // used; ie, it must be dead. If the EFLAGS operand is live, then we can
10114 // not change anything because rearranging the operands could affect other
10115 // instructions that depend on the exact status flags (zero, sign, etc.)
10116 // that are set by using these particular operands with this operation.
10117 const MachineOperand *FlagDef =
10118 Inst.findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
10119 assert((Inst.getNumDefs() == 1 || FlagDef) && "Implicit def isn't flags?");
10120 if (FlagDef && !FlagDef->isDead())
10121 return false;
10122
10123 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
10124}
10125
10126// TODO: There are many more machine instruction opcodes to match:
10127// 1. Other data types (integer, vectors)
10128// 2. Other math / logic operations (xor, or)
10129// 3. Other forms of the same operation (intrinsics and other variants)
10130bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
10131 bool Invert) const {
10132 if (Invert)
10133 return false;
10134 switch (Inst.getOpcode()) {
10135 CASE_ND(ADD8rr)
10136 CASE_ND(ADD16rr)
10137 CASE_ND(ADD32rr)
10138 CASE_ND(ADD64rr)
10139 CASE_ND(AND8rr)
10140 CASE_ND(AND16rr)
10141 CASE_ND(AND32rr)
10142 CASE_ND(AND64rr)
10143 CASE_ND(OR8rr)
10144 CASE_ND(OR16rr)
10145 CASE_ND(OR32rr)
10146 CASE_ND(OR64rr)
10147 CASE_ND(XOR8rr)
10148 CASE_ND(XOR16rr)
10149 CASE_ND(XOR32rr)
10150 CASE_ND(XOR64rr)
10151 CASE_ND(IMUL16rr)
10152 CASE_ND(IMUL32rr)
10153 CASE_ND(IMUL64rr)
10154 case X86::PANDrr:
10155 case X86::PORrr:
10156 case X86::PXORrr:
10157 case X86::ANDPDrr:
10158 case X86::ANDPSrr:
10159 case X86::ORPDrr:
10160 case X86::ORPSrr:
10161 case X86::XORPDrr:
10162 case X86::XORPSrr:
10163 case X86::PADDBrr:
10164 case X86::PADDWrr:
10165 case X86::PADDDrr:
10166 case X86::PADDQrr:
10167 case X86::PMULLWrr:
10168 case X86::PMULLDrr:
10169 case X86::PMAXSBrr:
10170 case X86::PMAXSDrr:
10171 case X86::PMAXSWrr:
10172 case X86::PMAXUBrr:
10173 case X86::PMAXUDrr:
10174 case X86::PMAXUWrr:
10175 case X86::PMINSBrr:
10176 case X86::PMINSDrr:
10177 case X86::PMINSWrr:
10178 case X86::PMINUBrr:
10179 case X86::PMINUDrr:
10180 case X86::PMINUWrr:
10181 case X86::VPANDrr:
10182 case X86::VPANDYrr:
10183 case X86::VPANDDZ128rr:
10184 case X86::VPANDDZ256rr:
10185 case X86::VPANDDZrr:
10186 case X86::VPANDQZ128rr:
10187 case X86::VPANDQZ256rr:
10188 case X86::VPANDQZrr:
10189 case X86::VPORrr:
10190 case X86::VPORYrr:
10191 case X86::VPORDZ128rr:
10192 case X86::VPORDZ256rr:
10193 case X86::VPORDZrr:
10194 case X86::VPORQZ128rr:
10195 case X86::VPORQZ256rr:
10196 case X86::VPORQZrr:
10197 case X86::VPXORrr:
10198 case X86::VPXORYrr:
10199 case X86::VPXORDZ128rr:
10200 case X86::VPXORDZ256rr:
10201 case X86::VPXORDZrr:
10202 case X86::VPXORQZ128rr:
10203 case X86::VPXORQZ256rr:
10204 case X86::VPXORQZrr:
10205 case X86::VANDPDrr:
10206 case X86::VANDPSrr:
10207 case X86::VANDPDYrr:
10208 case X86::VANDPSYrr:
10209 case X86::VANDPDZ128rr:
10210 case X86::VANDPSZ128rr:
10211 case X86::VANDPDZ256rr:
10212 case X86::VANDPSZ256rr:
10213 case X86::VANDPDZrr:
10214 case X86::VANDPSZrr:
10215 case X86::VORPDrr:
10216 case X86::VORPSrr:
10217 case X86::VORPDYrr:
10218 case X86::VORPSYrr:
10219 case X86::VORPDZ128rr:
10220 case X86::VORPSZ128rr:
10221 case X86::VORPDZ256rr:
10222 case X86::VORPSZ256rr:
10223 case X86::VORPDZrr:
10224 case X86::VORPSZrr:
10225 case X86::VXORPDrr:
10226 case X86::VXORPSrr:
10227 case X86::VXORPDYrr:
10228 case X86::VXORPSYrr:
10229 case X86::VXORPDZ128rr:
10230 case X86::VXORPSZ128rr:
10231 case X86::VXORPDZ256rr:
10232 case X86::VXORPSZ256rr:
10233 case X86::VXORPDZrr:
10234 case X86::VXORPSZrr:
10235 case X86::KADDBkk:
10236 case X86::KADDWkk:
10237 case X86::KADDDkk:
10238 case X86::KADDQkk:
10239 case X86::KANDBkk:
10240 case X86::KANDWkk:
10241 case X86::KANDDkk:
10242 case X86::KANDQkk:
10243 case X86::KORBkk:
10244 case X86::KORWkk:
10245 case X86::KORDkk:
10246 case X86::KORQkk:
10247 case X86::KXORBkk:
10248 case X86::KXORWkk:
10249 case X86::KXORDkk:
10250 case X86::KXORQkk:
10251 case X86::VPADDBrr:
10252 case X86::VPADDWrr:
10253 case X86::VPADDDrr:
10254 case X86::VPADDQrr:
10255 case X86::VPADDBYrr:
10256 case X86::VPADDWYrr:
10257 case X86::VPADDDYrr:
10258 case X86::VPADDQYrr:
10259 case X86::VPADDBZ128rr:
10260 case X86::VPADDWZ128rr:
10261 case X86::VPADDDZ128rr:
10262 case X86::VPADDQZ128rr:
10263 case X86::VPADDBZ256rr:
10264 case X86::VPADDWZ256rr:
10265 case X86::VPADDDZ256rr:
10266 case X86::VPADDQZ256rr:
10267 case X86::VPADDBZrr:
10268 case X86::VPADDWZrr:
10269 case X86::VPADDDZrr:
10270 case X86::VPADDQZrr:
10271 case X86::VPMULLWrr:
10272 case X86::VPMULLWYrr:
10273 case X86::VPMULLWZ128rr:
10274 case X86::VPMULLWZ256rr:
10275 case X86::VPMULLWZrr:
10276 case X86::VPMULLDrr:
10277 case X86::VPMULLDYrr:
10278 case X86::VPMULLDZ128rr:
10279 case X86::VPMULLDZ256rr:
10280 case X86::VPMULLDZrr:
10281 case X86::VPMULLQZ128rr:
10282 case X86::VPMULLQZ256rr:
10283 case X86::VPMULLQZrr:
10284 case X86::VPMAXSBrr:
10285 case X86::VPMAXSBYrr:
10286 case X86::VPMAXSBZ128rr:
10287 case X86::VPMAXSBZ256rr:
10288 case X86::VPMAXSBZrr:
10289 case X86::VPMAXSDrr:
10290 case X86::VPMAXSDYrr:
10291 case X86::VPMAXSDZ128rr:
10292 case X86::VPMAXSDZ256rr:
10293 case X86::VPMAXSDZrr:
10294 case X86::VPMAXSQZ128rr:
10295 case X86::VPMAXSQZ256rr:
10296 case X86::VPMAXSQZrr:
10297 case X86::VPMAXSWrr:
10298 case X86::VPMAXSWYrr:
10299 case X86::VPMAXSWZ128rr:
10300 case X86::VPMAXSWZ256rr:
10301 case X86::VPMAXSWZrr:
10302 case X86::VPMAXUBrr:
10303 case X86::VPMAXUBYrr:
10304 case X86::VPMAXUBZ128rr:
10305 case X86::VPMAXUBZ256rr:
10306 case X86::VPMAXUBZrr:
10307 case X86::VPMAXUDrr:
10308 case X86::VPMAXUDYrr:
10309 case X86::VPMAXUDZ128rr:
10310 case X86::VPMAXUDZ256rr:
10311 case X86::VPMAXUDZrr:
10312 case X86::VPMAXUQZ128rr:
10313 case X86::VPMAXUQZ256rr:
10314 case X86::VPMAXUQZrr:
10315 case X86::VPMAXUWrr:
10316 case X86::VPMAXUWYrr:
10317 case X86::VPMAXUWZ128rr:
10318 case X86::VPMAXUWZ256rr:
10319 case X86::VPMAXUWZrr:
10320 case X86::VPMINSBrr:
10321 case X86::VPMINSBYrr:
10322 case X86::VPMINSBZ128rr:
10323 case X86::VPMINSBZ256rr:
10324 case X86::VPMINSBZrr:
10325 case X86::VPMINSDrr:
10326 case X86::VPMINSDYrr:
10327 case X86::VPMINSDZ128rr:
10328 case X86::VPMINSDZ256rr:
10329 case X86::VPMINSDZrr:
10330 case X86::VPMINSQZ128rr:
10331 case X86::VPMINSQZ256rr:
10332 case X86::VPMINSQZrr:
10333 case X86::VPMINSWrr:
10334 case X86::VPMINSWYrr:
10335 case X86::VPMINSWZ128rr:
10336 case X86::VPMINSWZ256rr:
10337 case X86::VPMINSWZrr:
10338 case X86::VPMINUBrr:
10339 case X86::VPMINUBYrr:
10340 case X86::VPMINUBZ128rr:
10341 case X86::VPMINUBZ256rr:
10342 case X86::VPMINUBZrr:
10343 case X86::VPMINUDrr:
10344 case X86::VPMINUDYrr:
10345 case X86::VPMINUDZ128rr:
10346 case X86::VPMINUDZ256rr:
10347 case X86::VPMINUDZrr:
10348 case X86::VPMINUQZ128rr:
10349 case X86::VPMINUQZ256rr:
10350 case X86::VPMINUQZrr:
10351 case X86::VPMINUWrr:
10352 case X86::VPMINUWYrr:
10353 case X86::VPMINUWZ128rr:
10354 case X86::VPMINUWZ256rr:
10355 case X86::VPMINUWZrr:
10356 // Normal min/max instructions are not commutative because of NaN and signed
10357 // zero semantics, but these are. Thus, there's no need to check for global
10358 // relaxed math; the instructions themselves have the properties we need.
10359 case X86::MAXCPDrr:
10360 case X86::MAXCPSrr:
10361 case X86::MAXCSDrr:
10362 case X86::MAXCSSrr:
10363 case X86::MINCPDrr:
10364 case X86::MINCPSrr:
10365 case X86::MINCSDrr:
10366 case X86::MINCSSrr:
10367 case X86::VMAXCPDrr:
10368 case X86::VMAXCPSrr:
10369 case X86::VMAXCPDYrr:
10370 case X86::VMAXCPSYrr:
10371 case X86::VMAXCPDZ128rr:
10372 case X86::VMAXCPSZ128rr:
10373 case X86::VMAXCPDZ256rr:
10374 case X86::VMAXCPSZ256rr:
10375 case X86::VMAXCPDZrr:
10376 case X86::VMAXCPSZrr:
10377 case X86::VMAXCSDrr:
10378 case X86::VMAXCSSrr:
10379 case X86::VMAXCSDZrr:
10380 case X86::VMAXCSSZrr:
10381 case X86::VMINCPDrr:
10382 case X86::VMINCPSrr:
10383 case X86::VMINCPDYrr:
10384 case X86::VMINCPSYrr:
10385 case X86::VMINCPDZ128rr:
10386 case X86::VMINCPSZ128rr:
10387 case X86::VMINCPDZ256rr:
10388 case X86::VMINCPSZ256rr:
10389 case X86::VMINCPDZrr:
10390 case X86::VMINCPSZrr:
10391 case X86::VMINCSDrr:
10392 case X86::VMINCSSrr:
10393 case X86::VMINCSDZrr:
10394 case X86::VMINCSSZrr:
10395 case X86::VMAXCPHZ128rr:
10396 case X86::VMAXCPHZ256rr:
10397 case X86::VMAXCPHZrr:
10398 case X86::VMAXCSHZrr:
10399 case X86::VMINCPHZ128rr:
10400 case X86::VMINCPHZ256rr:
10401 case X86::VMINCPHZrr:
10402 case X86::VMINCSHZrr:
10403 return true;
10404 case X86::ADDPDrr:
10405 case X86::ADDPSrr:
10406 case X86::ADDSDrr:
10407 case X86::ADDSSrr:
10408 case X86::MULPDrr:
10409 case X86::MULPSrr:
10410 case X86::MULSDrr:
10411 case X86::MULSSrr:
10412 case X86::VADDPDrr:
10413 case X86::VADDPSrr:
10414 case X86::VADDPDYrr:
10415 case X86::VADDPSYrr:
10416 case X86::VADDPDZ128rr:
10417 case X86::VADDPSZ128rr:
10418 case X86::VADDPDZ256rr:
10419 case X86::VADDPSZ256rr:
10420 case X86::VADDPDZrr:
10421 case X86::VADDPSZrr:
10422 case X86::VADDSDrr:
10423 case X86::VADDSSrr:
10424 case X86::VADDSDZrr:
10425 case X86::VADDSSZrr:
10426 case X86::VMULPDrr:
10427 case X86::VMULPSrr:
10428 case X86::VMULPDYrr:
10429 case X86::VMULPSYrr:
10430 case X86::VMULPDZ128rr:
10431 case X86::VMULPSZ128rr:
10432 case X86::VMULPDZ256rr:
10433 case X86::VMULPSZ256rr:
10434 case X86::VMULPDZrr:
10435 case X86::VMULPSZrr:
10436 case X86::VMULSDrr:
10437 case X86::VMULSSrr:
10438 case X86::VMULSDZrr:
10439 case X86::VMULSSZrr:
10440 case X86::VADDPHZ128rr:
10441 case X86::VADDPHZ256rr:
10442 case X86::VADDPHZrr:
10443 case X86::VADDSHZrr:
10444 case X86::VMULPHZ128rr:
10445 case X86::VMULPHZ256rr:
10446 case X86::VMULPHZrr:
10447 case X86::VMULSHZrr:
10448 return Inst.getFlag(Flag: MachineInstr::MIFlag::FmReassoc) &&
10449 Inst.getFlag(Flag: MachineInstr::MIFlag::FmNsz);
10450 default:
10451 return false;
10452 }
10453}
10454
10455/// If \p DescribedReg overlaps with the MOVrr instruction's destination
10456/// register then, if possible, describe the value in terms of the source
10457/// register.
10458static std::optional<ParamLoadedValue>
10459describeMOVrrLoadedValue(const MachineInstr &MI, Register DescribedReg,
10460 const TargetRegisterInfo *TRI) {
10461 Register DestReg = MI.getOperand(i: 0).getReg();
10462 Register SrcReg = MI.getOperand(i: 1).getReg();
10463
10464 auto Expr = DIExpression::get(Context&: MI.getMF()->getFunction().getContext(), Elements: {});
10465
10466 // If the described register is the destination, just return the source.
10467 if (DestReg == DescribedReg)
10468 return ParamLoadedValue(MachineOperand::CreateReg(Reg: SrcReg, isDef: false), Expr);
10469
10470 // If the described register is a sub-register of the destination register,
10471 // then pick out the source register's corresponding sub-register.
10472 if (unsigned SubRegIdx = TRI->getSubRegIndex(RegNo: DestReg, SubRegNo: DescribedReg)) {
10473 Register SrcSubReg = TRI->getSubReg(Reg: SrcReg, Idx: SubRegIdx);
10474 return ParamLoadedValue(MachineOperand::CreateReg(Reg: SrcSubReg, isDef: false), Expr);
10475 }
10476
10477 // The remaining case to consider is when the described register is a
10478 // super-register of the destination register. MOV8rr and MOV16rr does not
10479 // write to any of the other bytes in the register, meaning that we'd have to
10480 // describe the value using a combination of the source register and the
10481 // non-overlapping bits in the described register, which is not currently
10482 // possible.
10483 if (MI.getOpcode() == X86::MOV8rr || MI.getOpcode() == X86::MOV16rr ||
10484 !TRI->isSuperRegister(RegA: DestReg, RegB: DescribedReg))
10485 return std::nullopt;
10486
10487 assert(MI.getOpcode() == X86::MOV32rr && "Unexpected super-register case");
10488 return ParamLoadedValue(MachineOperand::CreateReg(Reg: SrcReg, isDef: false), Expr);
10489}
10490
10491std::optional<ParamLoadedValue>
10492X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
10493 const MachineOperand *Op = nullptr;
10494 DIExpression *Expr = nullptr;
10495
10496 const TargetRegisterInfo *TRI = &getRegisterInfo();
10497
10498 switch (MI.getOpcode()) {
10499 case X86::LEA32r:
10500 case X86::LEA64r:
10501 case X86::LEA64_32r: {
10502 // We may need to describe a 64-bit parameter with a 32-bit LEA.
10503 if (!TRI->isSuperRegisterEq(RegA: MI.getOperand(i: 0).getReg(), RegB: Reg))
10504 return std::nullopt;
10505
10506 // Operand 4 could be global address. For now we do not support
10507 // such situation.
10508 if (!MI.getOperand(i: 4).isImm() || !MI.getOperand(i: 2).isImm())
10509 return std::nullopt;
10510
10511 const MachineOperand &Op1 = MI.getOperand(i: 1);
10512 const MachineOperand &Op2 = MI.getOperand(i: 3);
10513 assert(Op2.isReg() &&
10514 (Op2.getReg() == X86::NoRegister || Op2.getReg().isPhysical()));
10515
10516 // Omit situations like:
10517 // %rsi = lea %rsi, 4, ...
10518 if ((Op1.isReg() && Op1.getReg() == MI.getOperand(i: 0).getReg()) ||
10519 Op2.getReg() == MI.getOperand(i: 0).getReg())
10520 return std::nullopt;
10521 else if ((Op1.isReg() && Op1.getReg() != X86::NoRegister &&
10522 TRI->regsOverlap(RegA: Op1.getReg(), RegB: MI.getOperand(i: 0).getReg())) ||
10523 (Op2.getReg() != X86::NoRegister &&
10524 TRI->regsOverlap(RegA: Op2.getReg(), RegB: MI.getOperand(i: 0).getReg())))
10525 return std::nullopt;
10526
10527 int64_t Coef = MI.getOperand(i: 2).getImm();
10528 int64_t Offset = MI.getOperand(i: 4).getImm();
10529 SmallVector<uint64_t, 8> Ops;
10530
10531 if ((Op1.isReg() && Op1.getReg() != X86::NoRegister)) {
10532 Op = &Op1;
10533 } else if (Op1.isFI())
10534 Op = &Op1;
10535
10536 if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) {
10537 Ops.push_back(Elt: dwarf::DW_OP_constu);
10538 Ops.push_back(Elt: Coef + 1);
10539 Ops.push_back(Elt: dwarf::DW_OP_mul);
10540 } else {
10541 if (Op && Op2.getReg() != X86::NoRegister) {
10542 int dwarfReg = TRI->getDwarfRegNum(Reg: Op2.getReg(), isEH: false);
10543 if (dwarfReg < 0)
10544 return std::nullopt;
10545 else if (dwarfReg < 32) {
10546 Ops.push_back(Elt: dwarf::DW_OP_breg0 + dwarfReg);
10547 Ops.push_back(Elt: 0);
10548 } else {
10549 Ops.push_back(Elt: dwarf::DW_OP_bregx);
10550 Ops.push_back(Elt: dwarfReg);
10551 Ops.push_back(Elt: 0);
10552 }
10553 } else if (!Op) {
10554 assert(Op2.getReg() != X86::NoRegister);
10555 Op = &Op2;
10556 }
10557
10558 if (Coef > 1) {
10559 assert(Op2.getReg() != X86::NoRegister);
10560 Ops.push_back(Elt: dwarf::DW_OP_constu);
10561 Ops.push_back(Elt: Coef);
10562 Ops.push_back(Elt: dwarf::DW_OP_mul);
10563 }
10564
10565 if (((Op1.isReg() && Op1.getReg() != X86::NoRegister) || Op1.isFI()) &&
10566 Op2.getReg() != X86::NoRegister) {
10567 Ops.push_back(Elt: dwarf::DW_OP_plus);
10568 }
10569 }
10570
10571 DIExpression::appendOffset(Ops, Offset);
10572 Expr = DIExpression::get(Context&: MI.getMF()->getFunction().getContext(), Elements: Ops);
10573
10574 return ParamLoadedValue(*Op, Expr);
10575 }
10576 case X86::MOV8ri:
10577 case X86::MOV16ri:
10578 // TODO: Handle MOV8ri and MOV16ri.
10579 return std::nullopt;
10580 case X86::MOV32ri:
10581 case X86::MOV64ri:
10582 case X86::MOV64ri32:
10583 // MOV32ri may be used for producing zero-extended 32-bit immediates in
10584 // 64-bit parameters, so we need to consider super-registers.
10585 if (!TRI->isSuperRegisterEq(RegA: MI.getOperand(i: 0).getReg(), RegB: Reg))
10586 return std::nullopt;
10587 return ParamLoadedValue(MI.getOperand(i: 1), Expr);
10588 case X86::MOV8rr:
10589 case X86::MOV16rr:
10590 case X86::MOV32rr:
10591 case X86::MOV64rr:
10592 return describeMOVrrLoadedValue(MI, DescribedReg: Reg, TRI);
10593 case X86::XOR32rr: {
10594 // 64-bit parameters are zero-materialized using XOR32rr, so also consider
10595 // super-registers.
10596 if (!TRI->isSuperRegisterEq(RegA: MI.getOperand(i: 0).getReg(), RegB: Reg))
10597 return std::nullopt;
10598 if (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 2).getReg())
10599 return ParamLoadedValue(MachineOperand::CreateImm(Val: 0), Expr);
10600 return std::nullopt;
10601 }
10602 case X86::MOVSX64rr32: {
10603 // We may need to describe the lower 32 bits of the MOVSX; for example, in
10604 // cases like this:
10605 //
10606 // $ebx = [...]
10607 // $rdi = MOVSX64rr32 $ebx
10608 // $esi = MOV32rr $edi
10609 if (!TRI->isSubRegisterEq(RegA: MI.getOperand(i: 0).getReg(), RegB: Reg))
10610 return std::nullopt;
10611
10612 Expr = DIExpression::get(Context&: MI.getMF()->getFunction().getContext(), Elements: {});
10613
10614 // If the described register is the destination register we need to
10615 // sign-extend the source register from 32 bits. The other case we handle
10616 // is when the described register is the 32-bit sub-register of the
10617 // destination register, in case we just need to return the source
10618 // register.
10619 if (Reg == MI.getOperand(i: 0).getReg())
10620 Expr = DIExpression::appendExt(Expr, FromSize: 32, ToSize: 64, Signed: true);
10621 else
10622 assert(getX86MCRegisterClass(X86::GR32RegClassID).contains(Reg) &&
10623 "Unhandled sub-register case for MOVSX64rr32");
10624
10625 return ParamLoadedValue(MI.getOperand(i: 1), Expr);
10626 }
10627 default:
10628 assert(!MI.isMoveImmediate() && "Unexpected MoveImm instruction");
10629 return TargetInstrInfo::describeLoadedValue(MI, Reg);
10630 }
10631}
10632
10633/// This is an architecture-specific helper function of reassociateOps.
10634/// Set special operand attributes for new instructions after reassociation.
10635void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
10636 MachineInstr &OldMI2,
10637 MachineInstr &NewMI1,
10638 MachineInstr &NewMI2) const {
10639 // Integer instructions may define an implicit EFLAGS dest register operand.
10640 MachineOperand *OldFlagDef1 =
10641 OldMI1.findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
10642 MachineOperand *OldFlagDef2 =
10643 OldMI2.findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
10644
10645 assert(!OldFlagDef1 == !OldFlagDef2 &&
10646 "Unexpected instruction type for reassociation");
10647
10648 if (!OldFlagDef1 || !OldFlagDef2)
10649 return;
10650
10651 assert(OldFlagDef1->isDead() && OldFlagDef2->isDead() &&
10652 "Must have dead EFLAGS operand in reassociable instruction");
10653
10654 MachineOperand *NewFlagDef1 =
10655 NewMI1.findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
10656 MachineOperand *NewFlagDef2 =
10657 NewMI2.findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
10658
10659 assert(NewFlagDef1 && NewFlagDef2 &&
10660 "Unexpected operand in reassociable instruction");
10661
10662 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
10663 // of this pass or other passes. The EFLAGS operands must be dead in these new
10664 // instructions because the EFLAGS operands in the original instructions must
10665 // be dead in order for reassociation to occur.
10666 NewFlagDef1->setIsDead();
10667 NewFlagDef2->setIsDead();
10668}
10669
10670std::pair<unsigned, unsigned>
10671X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
10672 return std::make_pair(x&: TF, y: 0u);
10673}
10674
10675ArrayRef<std::pair<unsigned, const char *>>
10676X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
10677 using namespace X86II;
10678 static const std::pair<unsigned, const char *> TargetFlags[] = {
10679 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
10680 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
10681 {MO_GOT, "x86-got"},
10682 {MO_GOTOFF, "x86-gotoff"},
10683 {MO_GOTPCREL, "x86-gotpcrel"},
10684 {MO_GOTPCREL_NORELAX, "x86-gotpcrel-norelax"},
10685 {MO_PLT, "x86-plt"},
10686 {MO_TLSGD, "x86-tlsgd"},
10687 {MO_TLSLD, "x86-tlsld"},
10688 {MO_TLSLDM, "x86-tlsldm"},
10689 {MO_GOTTPOFF, "x86-gottpoff"},
10690 {MO_INDNTPOFF, "x86-indntpoff"},
10691 {MO_TPOFF, "x86-tpoff"},
10692 {MO_DTPOFF, "x86-dtpoff"},
10693 {MO_NTPOFF, "x86-ntpoff"},
10694 {MO_GOTNTPOFF, "x86-gotntpoff"},
10695 {MO_DLLIMPORT, "x86-dllimport"},
10696 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
10697 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
10698 {MO_TLVP, "x86-tlvp"},
10699 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
10700 {MO_SECREL, "x86-secrel"},
10701 {MO_COFFSTUB, "x86-coffstub"}};
10702 return ArrayRef(TargetFlags);
10703}
10704
10705/// Constants defining how certain sequences should be outlined.
10706///
10707/// \p MachineOutlinerDefault implies that the function is called with a call
10708/// instruction, and a return must be emitted for the outlined function frame.
10709///
10710/// That is,
10711///
10712/// I1 OUTLINED_FUNCTION:
10713/// I2 --> call OUTLINED_FUNCTION I1
10714/// I3 I2
10715/// I3
10716/// ret
10717///
10718/// * Call construction overhead: 1 (call instruction)
10719/// * Frame construction overhead: 1 (return instruction)
10720///
10721/// \p MachineOutlinerTailCall implies that the function is being tail called.
10722/// A jump is emitted instead of a call, and the return is already present in
10723/// the outlined sequence. That is,
10724///
10725/// I1 OUTLINED_FUNCTION:
10726/// I2 --> jmp OUTLINED_FUNCTION I1
10727/// ret I2
10728/// ret
10729///
10730/// * Call construction overhead: 1 (jump instruction)
10731/// * Frame construction overhead: 0 (don't need to return)
10732///
10733enum MachineOutlinerClass { MachineOutlinerDefault, MachineOutlinerTailCall };
10734
10735std::optional<std::unique_ptr<outliner::OutlinedFunction>>
10736X86InstrInfo::getOutliningCandidateInfo(
10737 const MachineModuleInfo &MMI,
10738 std::vector<outliner::Candidate> &RepeatedSequenceLocs,
10739 unsigned MinRepeats) const {
10740 unsigned SequenceSize = 0;
10741 for (auto &MI : RepeatedSequenceLocs[0]) {
10742 // FIXME: x86 doesn't implement getInstSizeInBytes, so
10743 // we can't tell the cost. Just assume each instruction
10744 // is one byte.
10745 if (MI.isDebugInstr() || MI.isKill())
10746 continue;
10747 SequenceSize += 1;
10748 }
10749
10750 // We check to see if CFI Instructions are present, and if they are
10751 // we find the number of CFI Instructions in the candidates.
10752 unsigned CFICount = 0;
10753 for (auto &I : RepeatedSequenceLocs[0]) {
10754 if (I.isCFIInstruction())
10755 CFICount++;
10756 }
10757
10758 // We compare the number of found CFI Instructions to the number of CFI
10759 // instructions in the parent function for each candidate. We must check this
10760 // since if we outline one of the CFI instructions in a function, we have to
10761 // outline them all for correctness. If we do not, the address offsets will be
10762 // incorrect between the two sections of the program.
10763 for (outliner::Candidate &C : RepeatedSequenceLocs) {
10764 std::vector<MCCFIInstruction> CFIInstructions =
10765 C.getMF()->getFrameInstructions();
10766
10767 if (CFICount > 0 && CFICount != CFIInstructions.size())
10768 return std::nullopt;
10769 }
10770
10771 // FIXME: Use real size in bytes for call and ret instructions.
10772 if (RepeatedSequenceLocs[0].back().isTerminator()) {
10773 for (outliner::Candidate &C : RepeatedSequenceLocs)
10774 C.setCallInfo(CID: MachineOutlinerTailCall, CO: 1);
10775
10776 return std::make_unique<outliner::OutlinedFunction>(
10777 args&: RepeatedSequenceLocs, args&: SequenceSize,
10778 args: 0, // Number of bytes to emit frame.
10779 args: MachineOutlinerTailCall // Type of frame.
10780 );
10781 }
10782
10783 if (CFICount > 0)
10784 return std::nullopt;
10785
10786 for (outliner::Candidate &C : RepeatedSequenceLocs)
10787 C.setCallInfo(CID: MachineOutlinerDefault, CO: 1);
10788
10789 return std::make_unique<outliner::OutlinedFunction>(
10790 args&: RepeatedSequenceLocs, args&: SequenceSize, args: 1, args: MachineOutlinerDefault);
10791}
10792
10793bool X86InstrInfo::isFunctionSafeToOutlineFrom(
10794 MachineFunction &MF, bool OutlineFromLinkOnceODRs) const {
10795 const Function &F = MF.getFunction();
10796
10797 // Does the function use a red zone? If it does, then we can't risk messing
10798 // with the stack.
10799 if (Subtarget.getFrameLowering()->has128ByteRedZone(MF)) {
10800 // It could have a red zone. If it does, then we don't want to touch it.
10801 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
10802 if (!X86FI || X86FI->getUsesRedZone())
10803 return false;
10804 }
10805
10806 // If we *don't* want to outline from things that could potentially be deduped
10807 // then return false.
10808 if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
10809 return false;
10810
10811 // This function is viable for outlining, so return true.
10812 return true;
10813}
10814
10815outliner::InstrType
10816X86InstrInfo::getOutliningTypeImpl(const MachineModuleInfo &MMI,
10817 MachineBasicBlock::iterator &MIT,
10818 unsigned Flags) const {
10819 MachineInstr &MI = *MIT;
10820
10821 // Is this a terminator for a basic block?
10822 if (MI.isTerminator())
10823 // TargetInstrInfo::getOutliningType has already filtered out anything
10824 // that would break this, so we can allow it here.
10825 return outliner::InstrType::Legal;
10826
10827 // Don't outline anything that modifies or reads from the stack pointer.
10828 //
10829 // FIXME: There are instructions which are being manually built without
10830 // explicit uses/defs so we also have to check the MCInstrDesc. We should be
10831 // able to remove the extra checks once those are fixed up. For example,
10832 // sometimes we might get something like %rax = POP64r 1. This won't be
10833 // caught by modifiesRegister or readsRegister even though the instruction
10834 // really ought to be formed so that modifiesRegister/readsRegister would
10835 // catch it.
10836 if (MI.modifiesRegister(Reg: X86::RSP, TRI: &RI) || MI.readsRegister(Reg: X86::RSP, TRI: &RI) ||
10837 MI.getDesc().hasImplicitUseOfPhysReg(Reg: X86::RSP) ||
10838 MI.getDesc().hasImplicitDefOfPhysReg(Reg: X86::RSP))
10839 return outliner::InstrType::Illegal;
10840
10841 // Outlined calls change the instruction pointer, so don't read from it.
10842 if (MI.readsRegister(Reg: X86::RIP, TRI: &RI) ||
10843 MI.getDesc().hasImplicitUseOfPhysReg(Reg: X86::RIP) ||
10844 MI.getDesc().hasImplicitDefOfPhysReg(Reg: X86::RIP))
10845 return outliner::InstrType::Illegal;
10846
10847 // Don't outline CFI instructions.
10848 if (MI.isCFIInstruction())
10849 return outliner::InstrType::Illegal;
10850
10851 return outliner::InstrType::Legal;
10852}
10853
10854void X86InstrInfo::buildOutlinedFrame(
10855 MachineBasicBlock &MBB, MachineFunction &MF,
10856 const outliner::OutlinedFunction &OF) const {
10857 // If we're a tail call, we already have a return, so don't do anything.
10858 if (OF.FrameConstructionID == MachineOutlinerTailCall)
10859 return;
10860
10861 // We're a normal call, so our sequence doesn't have a return instruction.
10862 // Add it in.
10863 MachineInstr *retq = BuildMI(MF, MIMD: DebugLoc(), MCID: get(Opcode: X86::RET64));
10864 MBB.insert(I: MBB.end(), MI: retq);
10865}
10866
10867MachineBasicBlock::iterator X86InstrInfo::insertOutlinedCall(
10868 Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It,
10869 MachineFunction &MF, outliner::Candidate &C) const {
10870 // Is it a tail call?
10871 if (C.CallConstructionID == MachineOutlinerTailCall) {
10872 // Yes, just insert a JMP.
10873 It = MBB.insert(I: It, MI: BuildMI(MF, MIMD: DebugLoc(), MCID: get(Opcode: X86::TAILJMPd64))
10874 .addGlobalAddress(GV: M.getNamedValue(Name: MF.getName())));
10875 } else {
10876 // No, insert a call.
10877 It = MBB.insert(I: It, MI: BuildMI(MF, MIMD: DebugLoc(), MCID: get(Opcode: X86::CALL64pcrel32))
10878 .addGlobalAddress(GV: M.getNamedValue(Name: MF.getName())));
10879 }
10880
10881 return It;
10882}
10883
10884void X86InstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB,
10885 MachineBasicBlock::iterator Iter,
10886 DebugLoc &DL,
10887 bool AllowSideEffects) const {
10888 const MachineFunction &MF = *MBB.getParent();
10889 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
10890 const TargetRegisterInfo &TRI = getRegisterInfo();
10891
10892 if (ST.hasMMX() && X86::VR64RegClass.contains(Reg))
10893 // FIXME: Should we ignore MMX registers?
10894 return;
10895
10896 if (TRI.isGeneralPurposeRegister(MF, PhysReg: Reg)) {
10897 // Convert register to the 32-bit version. Both 'movl' and 'xorl' clear the
10898 // upper bits of a 64-bit register automagically.
10899 Reg = getX86SubSuperRegister(Reg, Size: 32);
10900
10901 if (!AllowSideEffects)
10902 // XOR affects flags, so use a MOV instead.
10903 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: X86::MOV32ri), DestReg: Reg).addImm(Val: 0);
10904 else
10905 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: X86::XOR32rr), DestReg: Reg)
10906 .addReg(RegNo: Reg, Flags: RegState::Undef)
10907 .addReg(RegNo: Reg, Flags: RegState::Undef);
10908 } else if (X86::VR128RegClass.contains(Reg)) {
10909 // XMM#
10910 if (!ST.hasSSE1())
10911 return;
10912
10913 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: X86::V_SET0), DestReg: Reg);
10914 } else if (X86::VR256RegClass.contains(Reg)) {
10915 // YMM#
10916 if (!ST.hasAVX())
10917 return;
10918
10919 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: X86::V_SET0), DestReg: TRI.getSubReg(Reg, Idx: X86::sub_xmm));
10920 } else if (X86::VR512RegClass.contains(Reg)) {
10921 // ZMM#
10922 if (!ST.hasAVX512())
10923 return;
10924
10925 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: X86::AVX512_128_SET0),
10926 DestReg: TRI.getSubReg(Reg, Idx: X86::sub_xmm));
10927 } else if (X86::VK1RegClass.contains(Reg) || X86::VK2RegClass.contains(Reg) ||
10928 X86::VK4RegClass.contains(Reg) || X86::VK8RegClass.contains(Reg) ||
10929 X86::VK16RegClass.contains(Reg)) {
10930 if (!ST.hasVLX())
10931 return;
10932
10933 unsigned Op = ST.hasBWI() ? X86::KSET0Q : X86::KSET0W;
10934 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: Op), DestReg: Reg);
10935 }
10936}
10937
10938bool X86InstrInfo::getMachineCombinerPatterns(
10939 MachineInstr &Root, SmallVectorImpl<unsigned> &Patterns,
10940 bool DoRegPressureReduce) const {
10941 unsigned Opc = Root.getOpcode();
10942 switch (Opc) {
10943 case X86::VPDPWSSDrr:
10944 case X86::VPDPWSSDrm:
10945 case X86::VPDPWSSDYrr:
10946 case X86::VPDPWSSDYrm: {
10947 if (!Subtarget.hasFastDPWSSD()) {
10948 Patterns.push_back(Elt: X86MachineCombinerPattern::DPWSSD);
10949 return true;
10950 }
10951 break;
10952 }
10953 case X86::VPDPWSSDZ128rr:
10954 case X86::VPDPWSSDZ128rm:
10955 case X86::VPDPWSSDZ256rr:
10956 case X86::VPDPWSSDZ256rm:
10957 case X86::VPDPWSSDZrr:
10958 case X86::VPDPWSSDZrm: {
10959 if (Subtarget.hasBWI() && !Subtarget.hasFastDPWSSD()) {
10960 Patterns.push_back(Elt: X86MachineCombinerPattern::DPWSSD);
10961 return true;
10962 }
10963 break;
10964 }
10965 }
10966 return TargetInstrInfo::getMachineCombinerPatterns(Root,
10967 Patterns, DoRegPressureReduce);
10968}
10969
10970static void
10971genAlternativeDpCodeSequence(MachineInstr &Root, const TargetInstrInfo &TII,
10972 SmallVectorImpl<MachineInstr *> &InsInstrs,
10973 SmallVectorImpl<MachineInstr *> &DelInstrs,
10974 DenseMap<Register, unsigned> &InstrIdxForVirtReg) {
10975 MachineFunction *MF = Root.getMF();
10976 MachineRegisterInfo &RegInfo = MF->getRegInfo();
10977
10978 unsigned Opc = Root.getOpcode();
10979 unsigned AddOpc = 0;
10980 unsigned MaddOpc = 0;
10981 switch (Opc) {
10982 default:
10983 assert(false && "It should not reach here");
10984 break;
10985 // vpdpwssd xmm2,xmm3,xmm1
10986 // -->
10987 // vpmaddwd xmm3,xmm3,xmm1
10988 // vpaddd xmm2,xmm2,xmm3
10989 case X86::VPDPWSSDrr:
10990 MaddOpc = X86::VPMADDWDrr;
10991 AddOpc = X86::VPADDDrr;
10992 break;
10993 case X86::VPDPWSSDrm:
10994 MaddOpc = X86::VPMADDWDrm;
10995 AddOpc = X86::VPADDDrr;
10996 break;
10997 case X86::VPDPWSSDZ128rr:
10998 MaddOpc = X86::VPMADDWDZ128rr;
10999 AddOpc = X86::VPADDDZ128rr;
11000 break;
11001 case X86::VPDPWSSDZ128rm:
11002 MaddOpc = X86::VPMADDWDZ128rm;
11003 AddOpc = X86::VPADDDZ128rr;
11004 break;
11005 // vpdpwssd ymm2,ymm3,ymm1
11006 // -->
11007 // vpmaddwd ymm3,ymm3,ymm1
11008 // vpaddd ymm2,ymm2,ymm3
11009 case X86::VPDPWSSDYrr:
11010 MaddOpc = X86::VPMADDWDYrr;
11011 AddOpc = X86::VPADDDYrr;
11012 break;
11013 case X86::VPDPWSSDYrm:
11014 MaddOpc = X86::VPMADDWDYrm;
11015 AddOpc = X86::VPADDDYrr;
11016 break;
11017 case X86::VPDPWSSDZ256rr:
11018 MaddOpc = X86::VPMADDWDZ256rr;
11019 AddOpc = X86::VPADDDZ256rr;
11020 break;
11021 case X86::VPDPWSSDZ256rm:
11022 MaddOpc = X86::VPMADDWDZ256rm;
11023 AddOpc = X86::VPADDDZ256rr;
11024 break;
11025 // vpdpwssd zmm2,zmm3,zmm1
11026 // -->
11027 // vpmaddwd zmm3,zmm3,zmm1
11028 // vpaddd zmm2,zmm2,zmm3
11029 case X86::VPDPWSSDZrr:
11030 MaddOpc = X86::VPMADDWDZrr;
11031 AddOpc = X86::VPADDDZrr;
11032 break;
11033 case X86::VPDPWSSDZrm:
11034 MaddOpc = X86::VPMADDWDZrm;
11035 AddOpc = X86::VPADDDZrr;
11036 break;
11037 }
11038 // Create vpmaddwd.
11039 const TargetRegisterClass *RC =
11040 RegInfo.getRegClass(Reg: Root.getOperand(i: 0).getReg());
11041 Register NewReg = RegInfo.createVirtualRegister(RegClass: RC);
11042 MachineInstr *Madd = Root.getMF()->CloneMachineInstr(Orig: &Root);
11043 Madd->setDesc(TII.get(Opcode: MaddOpc));
11044 Madd->untieRegOperand(OpIdx: 1);
11045 Madd->removeOperand(OpNo: 1);
11046 Madd->getOperand(i: 0).setReg(NewReg);
11047 InstrIdxForVirtReg.insert(KV: std::make_pair(x&: NewReg, y: 0));
11048 // Create vpaddd.
11049 Register DstReg = Root.getOperand(i: 0).getReg();
11050 bool IsKill = Root.getOperand(i: 1).isKill();
11051 MachineInstr *Add =
11052 BuildMI(MF&: *MF, MIMD: MIMetadata(Root), MCID: TII.get(Opcode: AddOpc), DestReg: DstReg)
11053 .addReg(RegNo: Root.getOperand(i: 1).getReg(), Flags: getKillRegState(B: IsKill))
11054 .addReg(RegNo: Madd->getOperand(i: 0).getReg(), Flags: getKillRegState(B: true));
11055 InsInstrs.push_back(Elt: Madd);
11056 InsInstrs.push_back(Elt: Add);
11057 DelInstrs.push_back(Elt: &Root);
11058}
11059
11060void X86InstrInfo::genAlternativeCodeSequence(
11061 MachineInstr &Root, unsigned Pattern,
11062 SmallVectorImpl<MachineInstr *> &InsInstrs,
11063 SmallVectorImpl<MachineInstr *> &DelInstrs,
11064 DenseMap<Register, unsigned> &InstrIdxForVirtReg) const {
11065 switch (Pattern) {
11066 default:
11067 // Reassociate instructions.
11068 TargetInstrInfo::genAlternativeCodeSequence(Root, Pattern, InsInstrs,
11069 DelInstrs, InstIdxForVirtReg&: InstrIdxForVirtReg);
11070 return;
11071 case X86MachineCombinerPattern::DPWSSD:
11072 genAlternativeDpCodeSequence(Root, TII: *this, InsInstrs, DelInstrs,
11073 InstrIdxForVirtReg);
11074 return;
11075 }
11076}
11077
11078// See also: X86DAGToDAGISel::SelectInlineAsmMemoryOperand().
11079void X86InstrInfo::getFrameIndexOperands(SmallVectorImpl<MachineOperand> &Ops,
11080 int FI) const {
11081 X86AddressMode M;
11082 M.BaseType = X86AddressMode::FrameIndexBase;
11083 M.Base.FrameIndex = FI;
11084 M.getFullAddress(MO&: Ops);
11085}
11086
11087MachineInstr *
11088X86InstrInfo::insertCodePrefetchInstr(MachineBasicBlock &MBB,
11089 MachineBasicBlock::iterator InsertBefore,
11090 const GlobalValue *GV) const {
11091 MachineFunction &MF = *MBB.getParent();
11092 MachineInstr *PrefetchInstr = MF.CreateMachineInstr(
11093 MCID: get(Opcode: X86::PREFETCHIT1),
11094 DL: InsertBefore == MBB.instr_end() ? MBB.findPrevDebugLoc(MBBI: InsertBefore)
11095 : InsertBefore->getDebugLoc(),
11096 NoImplicit: true);
11097 MachineInstrBuilder MIB(MF, PrefetchInstr);
11098 MIB.addMemOperand(MMO: MF.getMachineMemOperand(PtrInfo: MachinePointerInfo(GV),
11099 F: MachineMemOperand::MOLoad, /*s=*/Size: 8,
11100 /*base_alignment=*/BaseAlignment: llvm::Align(1)));
11101 MIB.addReg(RegNo: X86::RIP).addImm(Val: 1).addReg(RegNo: X86::NoRegister);
11102 MIB.addGlobalAddress(GV);
11103 MIB.addReg(RegNo: X86::NoRegister);
11104 MBB.insert(I: InsertBefore, MI: PrefetchInstr);
11105 return PrefetchInstr;
11106}
11107
11108#define GET_INSTRINFO_HELPERS
11109#include "X86GenInstrInfo.inc"
11110