1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the X86 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86InstrInfo.h"
14#include "X86.h"
15#include "X86InstrBuilder.h"
16#include "X86InstrFoldTables.h"
17#include "X86MachineFunctionInfo.h"
18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/Sequence.h"
22#include "llvm/CodeGen/LiveIntervals.h"
23#include "llvm/CodeGen/LivePhysRegs.h"
24#include "llvm/CodeGen/LiveVariables.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineDominators.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineInstr.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineModuleInfo.h"
31#include "llvm/CodeGen/MachineOperand.h"
32#include "llvm/CodeGen/MachineRegisterInfo.h"
33#include "llvm/CodeGen/StackMaps.h"
34#include "llvm/IR/DebugInfoMetadata.h"
35#include "llvm/IR/DerivedTypes.h"
36#include "llvm/IR/Function.h"
37#include "llvm/IR/InstrTypes.h"
38#include "llvm/IR/Module.h"
39#include "llvm/MC/MCAsmInfo.h"
40#include "llvm/MC/MCExpr.h"
41#include "llvm/MC/MCInst.h"
42#include "llvm/Support/CommandLine.h"
43#include "llvm/Support/Debug.h"
44#include "llvm/Support/ErrorHandling.h"
45#include "llvm/Support/raw_ostream.h"
46#include "llvm/Target/TargetOptions.h"
47#include <atomic>
48#include <optional>
49
50using namespace llvm;
51
52#define DEBUG_TYPE "x86-instr-info"
53
54#define GET_INSTRINFO_CTOR_DTOR
55#include "X86GenInstrInfo.inc"
56
57extern cl::opt<bool> X86EnableAPXForRelocation;
58
59static cl::opt<bool>
60 NoFusing("disable-spill-fusing",
61 cl::desc("Disable fusing of spill code into instructions"),
62 cl::Hidden);
63static cl::opt<bool>
64 PrintFailedFusing("print-failed-fuse-candidates",
65 cl::desc("Print instructions that the allocator wants to"
66 " fuse, but the X86 backend currently can't"),
67 cl::Hidden);
68static cl::opt<bool>
69 ReMatPICStubLoad("remat-pic-stub-load",
70 cl::desc("Re-materialize load from stub in PIC mode"),
71 cl::init(Val: false), cl::Hidden);
72static cl::opt<unsigned>
73 PartialRegUpdateClearance("partial-reg-update-clearance",
74 cl::desc("Clearance between two register writes "
75 "for inserting XOR to avoid partial "
76 "register update"),
77 cl::init(Val: 64), cl::Hidden);
78static cl::opt<unsigned> UndefRegClearance(
79 "undef-reg-clearance",
80 cl::desc("How many idle instructions we would like before "
81 "certain undef register reads"),
82 cl::init(Val: 128), cl::Hidden);
83
84// Pin the vtable to this file.
85void X86InstrInfo::anchor() {}
86
87X86InstrInfo::X86InstrInfo(const X86Subtarget &STI)
88 : X86GenInstrInfo(STI, RI,
89 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
90 : X86::ADJCALLSTACKDOWN32),
91 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
92 : X86::ADJCALLSTACKUP32),
93 X86::CATCHRET, (STI.is64Bit() ? X86::RET64 : X86::RET32)),
94 Subtarget(STI), RI(STI.getTargetTriple()) {}
95
96const TargetRegisterClass *X86InstrInfo::getRegClass(const MCInstrDesc &MCID,
97 unsigned OpNum) const {
98 auto *RC = TargetInstrInfo::getRegClass(MCID, OpNum);
99 // If the target does not have egpr, then r16-r31 will be resereved for all
100 // instructions.
101 if (!RC || !Subtarget.hasEGPR())
102 return RC;
103
104 if (X86II::canUseApxExtendedReg(Desc: MCID))
105 return RC;
106
107 const X86RegisterInfo *RI = Subtarget.getRegisterInfo();
108 return RI->constrainRegClassToNonRex2(RC);
109}
110
111bool X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
112 Register &SrcReg, Register &DstReg,
113 unsigned &SubIdx) const {
114 switch (MI.getOpcode()) {
115 default:
116 break;
117 case X86::MOVSX16rr8:
118 case X86::MOVZX16rr8:
119 case X86::MOVSX32rr8:
120 case X86::MOVZX32rr8:
121 case X86::MOVSX64rr8:
122 if (!Subtarget.is64Bit())
123 // It's not always legal to reference the low 8-bit of the larger
124 // register in 32-bit mode.
125 return false;
126 [[fallthrough]];
127 case X86::MOVSX32rr16:
128 case X86::MOVZX32rr16:
129 case X86::MOVSX64rr16:
130 case X86::MOVSX64rr32: {
131 if (MI.getOperand(i: 0).getSubReg() || MI.getOperand(i: 1).getSubReg())
132 // Be conservative.
133 return false;
134 SrcReg = MI.getOperand(i: 1).getReg();
135 DstReg = MI.getOperand(i: 0).getReg();
136 switch (MI.getOpcode()) {
137 default:
138 llvm_unreachable("Unreachable!");
139 case X86::MOVSX16rr8:
140 case X86::MOVZX16rr8:
141 case X86::MOVSX32rr8:
142 case X86::MOVZX32rr8:
143 case X86::MOVSX64rr8:
144 SubIdx = X86::sub_8bit;
145 break;
146 case X86::MOVSX32rr16:
147 case X86::MOVZX32rr16:
148 case X86::MOVSX64rr16:
149 SubIdx = X86::sub_16bit;
150 break;
151 case X86::MOVSX64rr32:
152 SubIdx = X86::sub_32bit;
153 break;
154 }
155 return true;
156 }
157 }
158 return false;
159}
160
161bool X86InstrInfo::isDataInvariant(MachineInstr &MI) {
162 if (MI.mayLoad() || MI.mayStore())
163 return false;
164
165 // Some target-independent operations that trivially lower to data-invariant
166 // instructions.
167 if (MI.isCopyLike() || MI.isInsertSubreg())
168 return true;
169
170 unsigned Opcode = MI.getOpcode();
171 using namespace X86;
172 // On x86 it is believed that imul is constant time w.r.t. the loaded data.
173 // However, they set flags and are perhaps the most surprisingly constant
174 // time operations so we call them out here separately.
175 if (isIMUL(Opcode))
176 return true;
177 // Bit scanning and counting instructions that are somewhat surprisingly
178 // constant time as they scan across bits and do other fairly complex
179 // operations like popcnt, but are believed to be constant time on x86.
180 // However, these set flags.
181 if (isBSF(Opcode) || isBSR(Opcode) || isLZCNT(Opcode) || isPOPCNT(Opcode) ||
182 isTZCNT(Opcode))
183 return true;
184 // Bit manipulation instructions are effectively combinations of basic
185 // arithmetic ops, and should still execute in constant time. These also
186 // set flags.
187 if (isBLCFILL(Opcode) || isBLCI(Opcode) || isBLCIC(Opcode) ||
188 isBLCMSK(Opcode) || isBLCS(Opcode) || isBLSFILL(Opcode) ||
189 isBLSI(Opcode) || isBLSIC(Opcode) || isBLSMSK(Opcode) || isBLSR(Opcode) ||
190 isTZMSK(Opcode))
191 return true;
192 // Bit extracting and clearing instructions should execute in constant time,
193 // and set flags.
194 if (isBEXTR(Opcode) || isBZHI(Opcode))
195 return true;
196 // Shift and rotate.
197 if (isROL(Opcode) || isROR(Opcode) || isSAR(Opcode) || isSHL(Opcode) ||
198 isSHR(Opcode) || isSHLD(Opcode) || isSHRD(Opcode))
199 return true;
200 // Basic arithmetic is constant time on the input but does set flags.
201 if (isADC(Opcode) || isADD(Opcode) || isAND(Opcode) || isOR(Opcode) ||
202 isSBB(Opcode) || isSUB(Opcode) || isXOR(Opcode))
203 return true;
204 // Arithmetic with just 32-bit and 64-bit variants and no immediates.
205 if (isANDN(Opcode))
206 return true;
207 // Unary arithmetic operations.
208 if (isDEC(Opcode) || isINC(Opcode) || isNEG(Opcode))
209 return true;
210 // Unlike other arithmetic, NOT doesn't set EFLAGS.
211 if (isNOT(Opcode))
212 return true;
213 // Various move instructions used to zero or sign extend things. Note that we
214 // intentionally don't support the _NOREX variants as we can't handle that
215 // register constraint anyways.
216 if (isMOVSX(Opcode) || isMOVZX(Opcode) || isMOVSXD(Opcode) || isMOV(Opcode))
217 return true;
218 // Arithmetic instructions that are both constant time and don't set flags.
219 if (isRORX(Opcode) || isSARX(Opcode) || isSHLX(Opcode) || isSHRX(Opcode))
220 return true;
221 // LEA doesn't actually access memory, and its arithmetic is constant time.
222 if (isLEA(Opcode))
223 return true;
224 // By default, assume that the instruction is not data invariant.
225 return false;
226}
227
228bool X86InstrInfo::isDataInvariantLoad(MachineInstr &MI) {
229 switch (MI.getOpcode()) {
230 default:
231 // By default, assume that the load will immediately leak.
232 return false;
233
234 // On x86 it is believed that imul is constant time w.r.t. the loaded data.
235 // However, they set flags and are perhaps the most surprisingly constant
236 // time operations so we call them out here separately.
237 case X86::IMUL16rm:
238 case X86::IMUL16rmi:
239 case X86::IMUL32rm:
240 case X86::IMUL32rmi:
241 case X86::IMUL64rm:
242 case X86::IMUL64rmi32:
243
244 // Bit scanning and counting instructions that are somewhat surprisingly
245 // constant time as they scan across bits and do other fairly complex
246 // operations like popcnt, but are believed to be constant time on x86.
247 // However, these set flags.
248 case X86::BSF16rm:
249 case X86::BSF32rm:
250 case X86::BSF64rm:
251 case X86::BSR16rm:
252 case X86::BSR32rm:
253 case X86::BSR64rm:
254 case X86::LZCNT16rm:
255 case X86::LZCNT32rm:
256 case X86::LZCNT64rm:
257 case X86::POPCNT16rm:
258 case X86::POPCNT32rm:
259 case X86::POPCNT64rm:
260 case X86::TZCNT16rm:
261 case X86::TZCNT32rm:
262 case X86::TZCNT64rm:
263
264 // Bit manipulation instructions are effectively combinations of basic
265 // arithmetic ops, and should still execute in constant time. These also
266 // set flags.
267 case X86::BLCFILL32rm:
268 case X86::BLCFILL64rm:
269 case X86::BLCI32rm:
270 case X86::BLCI64rm:
271 case X86::BLCIC32rm:
272 case X86::BLCIC64rm:
273 case X86::BLCMSK32rm:
274 case X86::BLCMSK64rm:
275 case X86::BLCS32rm:
276 case X86::BLCS64rm:
277 case X86::BLSFILL32rm:
278 case X86::BLSFILL64rm:
279 case X86::BLSI32rm:
280 case X86::BLSI64rm:
281 case X86::BLSIC32rm:
282 case X86::BLSIC64rm:
283 case X86::BLSMSK32rm:
284 case X86::BLSMSK64rm:
285 case X86::BLSR32rm:
286 case X86::BLSR64rm:
287 case X86::TZMSK32rm:
288 case X86::TZMSK64rm:
289
290 // Bit extracting and clearing instructions should execute in constant time,
291 // and set flags.
292 case X86::BEXTR32rm:
293 case X86::BEXTR64rm:
294 case X86::BEXTRI32mi:
295 case X86::BEXTRI64mi:
296 case X86::BZHI32rm:
297 case X86::BZHI64rm:
298
299 // Basic arithmetic is constant time on the input but does set flags.
300 case X86::ADC8rm:
301 case X86::ADC16rm:
302 case X86::ADC32rm:
303 case X86::ADC64rm:
304 case X86::ADD8rm:
305 case X86::ADD16rm:
306 case X86::ADD32rm:
307 case X86::ADD64rm:
308 case X86::AND8rm:
309 case X86::AND16rm:
310 case X86::AND32rm:
311 case X86::AND64rm:
312 case X86::ANDN32rm:
313 case X86::ANDN64rm:
314 case X86::OR8rm:
315 case X86::OR16rm:
316 case X86::OR32rm:
317 case X86::OR64rm:
318 case X86::SBB8rm:
319 case X86::SBB16rm:
320 case X86::SBB32rm:
321 case X86::SBB64rm:
322 case X86::SUB8rm:
323 case X86::SUB16rm:
324 case X86::SUB32rm:
325 case X86::SUB64rm:
326 case X86::XOR8rm:
327 case X86::XOR16rm:
328 case X86::XOR32rm:
329 case X86::XOR64rm:
330
331 // Integer multiply w/o affecting flags is still believed to be constant
332 // time on x86. Called out separately as this is among the most surprising
333 // instructions to exhibit that behavior.
334 case X86::MULX32rm:
335 case X86::MULX64rm:
336
337 // Arithmetic instructions that are both constant time and don't set flags.
338 case X86::RORX32mi:
339 case X86::RORX64mi:
340 case X86::SARX32rm:
341 case X86::SARX64rm:
342 case X86::SHLX32rm:
343 case X86::SHLX64rm:
344 case X86::SHRX32rm:
345 case X86::SHRX64rm:
346
347 // Conversions are believed to be constant time and don't set flags.
348 case X86::CVTTSD2SI64rm:
349 case X86::VCVTTSD2SI64rm:
350 case X86::VCVTTSD2SI64Zrm:
351 case X86::CVTTSD2SIrm:
352 case X86::VCVTTSD2SIrm:
353 case X86::VCVTTSD2SIZrm:
354 case X86::CVTTSS2SI64rm:
355 case X86::VCVTTSS2SI64rm:
356 case X86::VCVTTSS2SI64Zrm:
357 case X86::CVTTSS2SIrm:
358 case X86::VCVTTSS2SIrm:
359 case X86::VCVTTSS2SIZrm:
360 case X86::CVTSI2SDrm:
361 case X86::VCVTSI2SDrm:
362 case X86::VCVTSI2SDZrm:
363 case X86::CVTSI2SSrm:
364 case X86::VCVTSI2SSrm:
365 case X86::VCVTSI2SSZrm:
366 case X86::CVTSI642SDrm:
367 case X86::VCVTSI642SDrm:
368 case X86::VCVTSI642SDZrm:
369 case X86::CVTSI642SSrm:
370 case X86::VCVTSI642SSrm:
371 case X86::VCVTSI642SSZrm:
372 case X86::CVTSS2SDrm:
373 case X86::VCVTSS2SDrm:
374 case X86::VCVTSS2SDZrm:
375 case X86::CVTSD2SSrm:
376 case X86::VCVTSD2SSrm:
377 case X86::VCVTSD2SSZrm:
378 // AVX512 added unsigned integer conversions.
379 case X86::VCVTTSD2USI64Zrm:
380 case X86::VCVTTSD2USIZrm:
381 case X86::VCVTTSS2USI64Zrm:
382 case X86::VCVTTSS2USIZrm:
383 case X86::VCVTUSI2SDZrm:
384 case X86::VCVTUSI642SDZrm:
385 case X86::VCVTUSI2SSZrm:
386 case X86::VCVTUSI642SSZrm:
387
388 // Loads to register don't set flags.
389 case X86::MOV8rm:
390 case X86::MOV8rm_NOREX:
391 case X86::MOV16rm:
392 case X86::MOV32rm:
393 case X86::MOV64rm:
394 case X86::MOVSX16rm8:
395 case X86::MOVSX32rm16:
396 case X86::MOVSX32rm8:
397 case X86::MOVSX32rm8_NOREX:
398 case X86::MOVSX64rm16:
399 case X86::MOVSX64rm32:
400 case X86::MOVSX64rm8:
401 case X86::MOVZX16rm8:
402 case X86::MOVZX32rm16:
403 case X86::MOVZX32rm8:
404 case X86::MOVZX32rm8_NOREX:
405 case X86::MOVZX64rm16:
406 case X86::MOVZX64rm8:
407 return true;
408 }
409}
410
411int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
412 const MachineFunction *MF = MI.getParent()->getParent();
413 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
414
415 if (isFrameInstr(I: MI)) {
416 int SPAdj = alignTo(Size: getFrameSize(I: MI), A: TFI->getStackAlign());
417 SPAdj -= getFrameAdjustment(I: MI);
418 if (!isFrameSetup(I: MI))
419 SPAdj = -SPAdj;
420 return SPAdj;
421 }
422
423 // To know whether a call adjusts the stack, we need information
424 // that is bound to the following ADJCALLSTACKUP pseudo.
425 // Look for the next ADJCALLSTACKUP that follows the call.
426 if (MI.isCall()) {
427 const MachineBasicBlock *MBB = MI.getParent();
428 auto I = ++MachineBasicBlock::const_iterator(MI);
429 for (auto E = MBB->end(); I != E; ++I) {
430 if (I->getOpcode() == getCallFrameDestroyOpcode() || I->isCall())
431 break;
432 }
433
434 // If we could not find a frame destroy opcode, then it has already
435 // been simplified, so we don't care.
436 if (I->getOpcode() != getCallFrameDestroyOpcode())
437 return 0;
438
439 return -(I->getOperand(i: 1).getImm());
440 }
441
442 // Currently handle only PUSHes we can reasonably expect to see
443 // in call sequences
444 switch (MI.getOpcode()) {
445 default:
446 return 0;
447 case X86::PUSH32r:
448 case X86::PUSH32rmm:
449 case X86::PUSH32rmr:
450 case X86::PUSH32i:
451 return 4;
452 case X86::PUSH64r:
453 case X86::PUSH64rmm:
454 case X86::PUSH64rmr:
455 case X86::PUSH64i32:
456 return 8;
457 }
458}
459
460/// Return true and the FrameIndex if the specified
461/// operand and follow operands form a reference to the stack frame.
462bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
463 int &FrameIndex) const {
464 if (MI.getOperand(i: Op + X86::AddrBaseReg).isFI() &&
465 MI.getOperand(i: Op + X86::AddrScaleAmt).isImm() &&
466 MI.getOperand(i: Op + X86::AddrIndexReg).isReg() &&
467 MI.getOperand(i: Op + X86::AddrDisp).isImm() &&
468 MI.getOperand(i: Op + X86::AddrScaleAmt).getImm() == 1 &&
469 MI.getOperand(i: Op + X86::AddrIndexReg).getReg() == 0 &&
470 MI.getOperand(i: Op + X86::AddrDisp).getImm() == 0) {
471 FrameIndex = MI.getOperand(i: Op + X86::AddrBaseReg).getIndex();
472 return true;
473 }
474 return false;
475}
476
477static bool isFrameLoadOpcode(int Opcode, TypeSize &MemBytes) {
478 switch (Opcode) {
479 default:
480 return false;
481 case X86::MOV8rm:
482 case X86::KMOVBkm:
483 case X86::KMOVBkm_EVEX:
484 MemBytes = TypeSize::getFixed(ExactSize: 1);
485 return true;
486 case X86::MOV16rm:
487 case X86::KMOVWkm:
488 case X86::KMOVWkm_EVEX:
489 case X86::VMOVSHZrm:
490 case X86::VMOVSHZrm_alt:
491 MemBytes = TypeSize::getFixed(ExactSize: 2);
492 return true;
493 case X86::MOV32rm:
494 case X86::MOVSSrm:
495 case X86::MOVSSrm_alt:
496 case X86::VMOVSSrm:
497 case X86::VMOVSSrm_alt:
498 case X86::VMOVSSZrm:
499 case X86::VMOVSSZrm_alt:
500 case X86::KMOVDkm:
501 case X86::KMOVDkm_EVEX:
502 MemBytes = TypeSize::getFixed(ExactSize: 4);
503 return true;
504 case X86::MOV64rm:
505 case X86::LD_Fp64m:
506 case X86::MOVSDrm:
507 case X86::MOVSDrm_alt:
508 case X86::VMOVSDrm:
509 case X86::VMOVSDrm_alt:
510 case X86::VMOVSDZrm:
511 case X86::VMOVSDZrm_alt:
512 case X86::MMX_MOVD64rm:
513 case X86::MMX_MOVQ64rm:
514 case X86::KMOVQkm:
515 case X86::KMOVQkm_EVEX:
516 MemBytes = TypeSize::getFixed(ExactSize: 8);
517 return true;
518 case X86::MOVAPSrm:
519 case X86::MOVUPSrm:
520 case X86::MOVAPDrm:
521 case X86::MOVUPDrm:
522 case X86::MOVDQArm:
523 case X86::MOVDQUrm:
524 case X86::VMOVAPSrm:
525 case X86::VMOVUPSrm:
526 case X86::VMOVAPDrm:
527 case X86::VMOVUPDrm:
528 case X86::VMOVDQArm:
529 case X86::VMOVDQUrm:
530 case X86::VMOVAPSZ128rm:
531 case X86::VMOVUPSZ128rm:
532 case X86::VMOVAPSZ128rm_NOVLX:
533 case X86::VMOVUPSZ128rm_NOVLX:
534 case X86::VMOVAPDZ128rm:
535 case X86::VMOVUPDZ128rm:
536 case X86::VMOVDQU8Z128rm:
537 case X86::VMOVDQU16Z128rm:
538 case X86::VMOVDQA32Z128rm:
539 case X86::VMOVDQU32Z128rm:
540 case X86::VMOVDQA64Z128rm:
541 case X86::VMOVDQU64Z128rm:
542 MemBytes = TypeSize::getFixed(ExactSize: 16);
543 return true;
544 case X86::VMOVAPSYrm:
545 case X86::VMOVUPSYrm:
546 case X86::VMOVAPDYrm:
547 case X86::VMOVUPDYrm:
548 case X86::VMOVDQAYrm:
549 case X86::VMOVDQUYrm:
550 case X86::VMOVAPSZ256rm:
551 case X86::VMOVUPSZ256rm:
552 case X86::VMOVAPSZ256rm_NOVLX:
553 case X86::VMOVUPSZ256rm_NOVLX:
554 case X86::VMOVAPDZ256rm:
555 case X86::VMOVUPDZ256rm:
556 case X86::VMOVDQU8Z256rm:
557 case X86::VMOVDQU16Z256rm:
558 case X86::VMOVDQA32Z256rm:
559 case X86::VMOVDQU32Z256rm:
560 case X86::VMOVDQA64Z256rm:
561 case X86::VMOVDQU64Z256rm:
562 MemBytes = TypeSize::getFixed(ExactSize: 32);
563 return true;
564 case X86::VMOVAPSZrm:
565 case X86::VMOVUPSZrm:
566 case X86::VMOVAPDZrm:
567 case X86::VMOVUPDZrm:
568 case X86::VMOVDQU8Zrm:
569 case X86::VMOVDQU16Zrm:
570 case X86::VMOVDQA32Zrm:
571 case X86::VMOVDQU32Zrm:
572 case X86::VMOVDQA64Zrm:
573 case X86::VMOVDQU64Zrm:
574 MemBytes = TypeSize::getFixed(ExactSize: 64);
575 return true;
576 }
577}
578
579static bool isFrameStoreOpcode(int Opcode, TypeSize &MemBytes) {
580 switch (Opcode) {
581 default:
582 return false;
583 case X86::MOV8mr:
584 case X86::KMOVBmk:
585 case X86::KMOVBmk_EVEX:
586 MemBytes = TypeSize::getFixed(ExactSize: 1);
587 return true;
588 case X86::MOV16mr:
589 case X86::KMOVWmk:
590 case X86::KMOVWmk_EVEX:
591 case X86::VMOVSHZmr:
592 MemBytes = TypeSize::getFixed(ExactSize: 2);
593 return true;
594 case X86::MOV32mr:
595 case X86::MOVSSmr:
596 case X86::VMOVSSmr:
597 case X86::VMOVSSZmr:
598 case X86::KMOVDmk:
599 case X86::KMOVDmk_EVEX:
600 MemBytes = TypeSize::getFixed(ExactSize: 4);
601 return true;
602 case X86::MOV64mr:
603 case X86::ST_FpP64m:
604 case X86::MOVSDmr:
605 case X86::VMOVSDmr:
606 case X86::VMOVSDZmr:
607 case X86::MMX_MOVD64mr:
608 case X86::MMX_MOVQ64mr:
609 case X86::MMX_MOVNTQmr:
610 case X86::KMOVQmk:
611 case X86::KMOVQmk_EVEX:
612 MemBytes = TypeSize::getFixed(ExactSize: 8);
613 return true;
614 case X86::MOVAPSmr:
615 case X86::MOVUPSmr:
616 case X86::MOVAPDmr:
617 case X86::MOVUPDmr:
618 case X86::MOVDQAmr:
619 case X86::MOVDQUmr:
620 case X86::VMOVAPSmr:
621 case X86::VMOVUPSmr:
622 case X86::VMOVAPDmr:
623 case X86::VMOVUPDmr:
624 case X86::VMOVDQAmr:
625 case X86::VMOVDQUmr:
626 case X86::VMOVUPSZ128mr:
627 case X86::VMOVAPSZ128mr:
628 case X86::VMOVUPSZ128mr_NOVLX:
629 case X86::VMOVAPSZ128mr_NOVLX:
630 case X86::VMOVUPDZ128mr:
631 case X86::VMOVAPDZ128mr:
632 case X86::VMOVDQA32Z128mr:
633 case X86::VMOVDQU32Z128mr:
634 case X86::VMOVDQA64Z128mr:
635 case X86::VMOVDQU64Z128mr:
636 case X86::VMOVDQU8Z128mr:
637 case X86::VMOVDQU16Z128mr:
638 MemBytes = TypeSize::getFixed(ExactSize: 16);
639 return true;
640 case X86::VMOVUPSYmr:
641 case X86::VMOVAPSYmr:
642 case X86::VMOVUPDYmr:
643 case X86::VMOVAPDYmr:
644 case X86::VMOVDQUYmr:
645 case X86::VMOVDQAYmr:
646 case X86::VMOVUPSZ256mr:
647 case X86::VMOVAPSZ256mr:
648 case X86::VMOVUPSZ256mr_NOVLX:
649 case X86::VMOVAPSZ256mr_NOVLX:
650 case X86::VMOVUPDZ256mr:
651 case X86::VMOVAPDZ256mr:
652 case X86::VMOVDQU8Z256mr:
653 case X86::VMOVDQU16Z256mr:
654 case X86::VMOVDQA32Z256mr:
655 case X86::VMOVDQU32Z256mr:
656 case X86::VMOVDQA64Z256mr:
657 case X86::VMOVDQU64Z256mr:
658 MemBytes = TypeSize::getFixed(ExactSize: 32);
659 return true;
660 case X86::VMOVUPSZmr:
661 case X86::VMOVAPSZmr:
662 case X86::VMOVUPDZmr:
663 case X86::VMOVAPDZmr:
664 case X86::VMOVDQU8Zmr:
665 case X86::VMOVDQU16Zmr:
666 case X86::VMOVDQA32Zmr:
667 case X86::VMOVDQU32Zmr:
668 case X86::VMOVDQA64Zmr:
669 case X86::VMOVDQU64Zmr:
670 MemBytes = TypeSize::getFixed(ExactSize: 64);
671 return true;
672 }
673 return false;
674}
675
676Register X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
677 int &FrameIndex) const {
678 TypeSize Dummy = TypeSize::getZero();
679 return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, MemBytes&: Dummy);
680}
681
682Register X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
683 int &FrameIndex,
684 TypeSize &MemBytes) const {
685 if (isFrameLoadOpcode(Opcode: MI.getOpcode(), MemBytes))
686 if (MI.getOperand(i: 0).getSubReg() == 0 && isFrameOperand(MI, Op: 1, FrameIndex))
687 return MI.getOperand(i: 0).getReg();
688 return Register();
689}
690
691Register X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
692 int &FrameIndex) const {
693 TypeSize Dummy = TypeSize::getZero();
694 if (isFrameLoadOpcode(Opcode: MI.getOpcode(), MemBytes&: Dummy)) {
695 if (Register Reg = isLoadFromStackSlot(MI, FrameIndex))
696 return Reg;
697 // Check for post-frame index elimination operations
698 SmallVector<const MachineMemOperand *, 1> Accesses;
699 if (hasLoadFromStackSlot(MI, Accesses)) {
700 FrameIndex =
701 cast<FixedStackPseudoSourceValue>(Val: Accesses.front()->getPseudoValue())
702 ->getFrameIndex();
703 return MI.getOperand(i: 0).getReg();
704 }
705 }
706 return Register();
707}
708
709Register X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
710 int &FrameIndex) const {
711 TypeSize Dummy = TypeSize::getZero();
712 return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, MemBytes&: Dummy);
713}
714
715Register X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
716 int &FrameIndex,
717 TypeSize &MemBytes) const {
718 if (isFrameStoreOpcode(Opcode: MI.getOpcode(), MemBytes))
719 if (MI.getOperand(i: X86::AddrNumOperands).getSubReg() == 0 &&
720 isFrameOperand(MI, Op: 0, FrameIndex))
721 return MI.getOperand(i: X86::AddrNumOperands).getReg();
722 return Register();
723}
724
725Register X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
726 int &FrameIndex) const {
727 TypeSize Dummy = TypeSize::getZero();
728 if (isFrameStoreOpcode(Opcode: MI.getOpcode(), MemBytes&: Dummy)) {
729 if (Register Reg = isStoreToStackSlot(MI, FrameIndex))
730 return Reg;
731 // Check for post-frame index elimination operations
732 SmallVector<const MachineMemOperand *, 1> Accesses;
733 if (hasStoreToStackSlot(MI, Accesses)) {
734 FrameIndex =
735 cast<FixedStackPseudoSourceValue>(Val: Accesses.front()->getPseudoValue())
736 ->getFrameIndex();
737 return MI.getOperand(i: X86::AddrNumOperands).getReg();
738 }
739 }
740 return Register();
741}
742
743/// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
744static bool regIsPICBase(Register BaseReg, const MachineRegisterInfo &MRI) {
745 // Don't waste compile time scanning use-def chains of physregs.
746 if (!BaseReg.isVirtual())
747 return false;
748 bool isPICBase = false;
749 for (const MachineInstr &DefMI : MRI.def_instructions(Reg: BaseReg)) {
750 if (DefMI.getOpcode() != X86::MOVPC32r)
751 return false;
752 assert(!isPICBase && "More than one PIC base?");
753 isPICBase = true;
754 }
755 return isPICBase;
756}
757
758bool X86InstrInfo::isReMaterializableImpl(
759 const MachineInstr &MI) const {
760 switch (MI.getOpcode()) {
761 default:
762 // This function should only be called for opcodes with the ReMaterializable
763 // flag set.
764 llvm_unreachable("Unknown rematerializable operation!");
765 break;
766 case X86::IMPLICIT_DEF:
767 // Defer to generic logic.
768 break;
769 case X86::LOAD_STACK_GUARD:
770 case X86::LD_Fp032:
771 case X86::LD_Fp064:
772 case X86::LD_Fp080:
773 case X86::LD_Fp132:
774 case X86::LD_Fp164:
775 case X86::LD_Fp180:
776 case X86::AVX1_SETALLONES:
777 case X86::AVX2_SETALLONES:
778 case X86::AVX512_128_SET0:
779 case X86::AVX512_256_SET0:
780 case X86::AVX512_512_SET0:
781 case X86::AVX512_128_SETALLONES:
782 case X86::AVX512_256_SETALLONES:
783 case X86::AVX512_512_SETALLONES:
784 case X86::AVX512_FsFLD0SD:
785 case X86::AVX512_FsFLD0SH:
786 case X86::AVX512_FsFLD0SS:
787 case X86::AVX512_FsFLD0F128:
788 case X86::AVX_SET0:
789 case X86::FsFLD0SD:
790 case X86::FsFLD0SS:
791 case X86::FsFLD0SH:
792 case X86::FsFLD0F128:
793 case X86::KSET0B:
794 case X86::KSET0D:
795 case X86::KSET0Q:
796 case X86::KSET0W:
797 case X86::KSET1B:
798 case X86::KSET1D:
799 case X86::KSET1Q:
800 case X86::KSET1W:
801 case X86::MMX_SET0:
802 case X86::MOV32ImmSExti8:
803 case X86::MOV32r0:
804 case X86::MOV32r1:
805 case X86::MOV32r_1:
806 case X86::MOV32ri64:
807 case X86::MOV64ImmSExti8:
808 case X86::V_SET0:
809 case X86::V_SETALLONES:
810 case X86::MOV16ri:
811 case X86::MOV32ri:
812 case X86::MOV64ri:
813 case X86::MOV64ri32:
814 case X86::MOV8ri:
815 case X86::PTILEZEROV:
816 return true;
817
818 case X86::MOV8rm:
819 case X86::MOV8rm_NOREX:
820 case X86::MOV16rm:
821 case X86::MOV32rm:
822 case X86::MOV64rm:
823 case X86::MOVSSrm:
824 case X86::MOVSSrm_alt:
825 case X86::MOVSDrm:
826 case X86::MOVSDrm_alt:
827 case X86::MOVAPSrm:
828 case X86::MOVUPSrm:
829 case X86::MOVAPDrm:
830 case X86::MOVUPDrm:
831 case X86::MOVDQArm:
832 case X86::MOVDQUrm:
833 case X86::VMOVSSrm:
834 case X86::VMOVSSrm_alt:
835 case X86::VMOVSDrm:
836 case X86::VMOVSDrm_alt:
837 case X86::VMOVAPSrm:
838 case X86::VMOVUPSrm:
839 case X86::VMOVAPDrm:
840 case X86::VMOVUPDrm:
841 case X86::VMOVDQArm:
842 case X86::VMOVDQUrm:
843 case X86::VMOVAPSYrm:
844 case X86::VMOVUPSYrm:
845 case X86::VMOVAPDYrm:
846 case X86::VMOVUPDYrm:
847 case X86::VMOVDQAYrm:
848 case X86::VMOVDQUYrm:
849 case X86::MMX_MOVD64rm:
850 case X86::MMX_MOVQ64rm:
851 case X86::VBROADCASTSSrm:
852 case X86::VBROADCASTSSYrm:
853 case X86::VBROADCASTSDYrm:
854 // AVX-512
855 case X86::VPBROADCASTBZ128rm:
856 case X86::VPBROADCASTBZ256rm:
857 case X86::VPBROADCASTBZrm:
858 case X86::VBROADCASTF32X2Z256rm:
859 case X86::VBROADCASTF32X2Zrm:
860 case X86::VBROADCASTI32X2Z128rm:
861 case X86::VBROADCASTI32X2Z256rm:
862 case X86::VBROADCASTI32X2Zrm:
863 case X86::VPBROADCASTWZ128rm:
864 case X86::VPBROADCASTWZ256rm:
865 case X86::VPBROADCASTWZrm:
866 case X86::VPBROADCASTDZ128rm:
867 case X86::VPBROADCASTDZ256rm:
868 case X86::VPBROADCASTDZrm:
869 case X86::VBROADCASTSSZ128rm:
870 case X86::VBROADCASTSSZ256rm:
871 case X86::VBROADCASTSSZrm:
872 case X86::VPBROADCASTQZ128rm:
873 case X86::VPBROADCASTQZ256rm:
874 case X86::VPBROADCASTQZrm:
875 case X86::VBROADCASTSDZ256rm:
876 case X86::VBROADCASTSDZrm:
877 case X86::VMOVSSZrm:
878 case X86::VMOVSSZrm_alt:
879 case X86::VMOVSDZrm:
880 case X86::VMOVSDZrm_alt:
881 case X86::VMOVSHZrm:
882 case X86::VMOVSHZrm_alt:
883 case X86::VMOVAPDZ128rm:
884 case X86::VMOVAPDZ256rm:
885 case X86::VMOVAPDZrm:
886 case X86::VMOVAPSZ128rm:
887 case X86::VMOVAPSZ256rm:
888 case X86::VMOVAPSZ128rm_NOVLX:
889 case X86::VMOVAPSZ256rm_NOVLX:
890 case X86::VMOVAPSZrm:
891 case X86::VMOVDQA32Z128rm:
892 case X86::VMOVDQA32Z256rm:
893 case X86::VMOVDQA32Zrm:
894 case X86::VMOVDQA64Z128rm:
895 case X86::VMOVDQA64Z256rm:
896 case X86::VMOVDQA64Zrm:
897 case X86::VMOVDQU16Z128rm:
898 case X86::VMOVDQU16Z256rm:
899 case X86::VMOVDQU16Zrm:
900 case X86::VMOVDQU32Z128rm:
901 case X86::VMOVDQU32Z256rm:
902 case X86::VMOVDQU32Zrm:
903 case X86::VMOVDQU64Z128rm:
904 case X86::VMOVDQU64Z256rm:
905 case X86::VMOVDQU64Zrm:
906 case X86::VMOVDQU8Z128rm:
907 case X86::VMOVDQU8Z256rm:
908 case X86::VMOVDQU8Zrm:
909 case X86::VMOVUPDZ128rm:
910 case X86::VMOVUPDZ256rm:
911 case X86::VMOVUPDZrm:
912 case X86::VMOVUPSZ128rm:
913 case X86::VMOVUPSZ256rm:
914 case X86::VMOVUPSZ128rm_NOVLX:
915 case X86::VMOVUPSZ256rm_NOVLX:
916 case X86::VMOVUPSZrm: {
917 // Loads from constant pools are trivially rematerializable.
918 if (MI.getOperand(i: 1 + X86::AddrBaseReg).isReg() &&
919 MI.getOperand(i: 1 + X86::AddrScaleAmt).isImm() &&
920 MI.getOperand(i: 1 + X86::AddrIndexReg).isReg() &&
921 MI.getOperand(i: 1 + X86::AddrIndexReg).getReg() == 0 &&
922 MI.isDereferenceableInvariantLoad()) {
923 Register BaseReg = MI.getOperand(i: 1 + X86::AddrBaseReg).getReg();
924 if (BaseReg == 0 || BaseReg == X86::RIP)
925 return true;
926 // Allow re-materialization of PIC load.
927 if (!(!ReMatPICStubLoad && MI.getOperand(i: 1 + X86::AddrDisp).isGlobal())) {
928 const MachineFunction &MF = *MI.getParent()->getParent();
929 const MachineRegisterInfo &MRI = MF.getRegInfo();
930 if (regIsPICBase(BaseReg, MRI))
931 return true;
932 }
933 }
934 break;
935 }
936
937 case X86::LEA32r:
938 case X86::LEA64r: {
939 if (MI.getOperand(i: 1 + X86::AddrScaleAmt).isImm() &&
940 MI.getOperand(i: 1 + X86::AddrIndexReg).isReg() &&
941 MI.getOperand(i: 1 + X86::AddrIndexReg).getReg() == 0 &&
942 !MI.getOperand(i: 1 + X86::AddrDisp).isReg()) {
943 // lea fi#, lea GV, etc. are all rematerializable.
944 if (!MI.getOperand(i: 1 + X86::AddrBaseReg).isReg())
945 return true;
946 Register BaseReg = MI.getOperand(i: 1 + X86::AddrBaseReg).getReg();
947 if (BaseReg == 0)
948 return true;
949 // Allow re-materialization of lea PICBase + x.
950 const MachineFunction &MF = *MI.getParent()->getParent();
951 const MachineRegisterInfo &MRI = MF.getRegInfo();
952 if (regIsPICBase(BaseReg, MRI))
953 return true;
954 }
955 break;
956 }
957 }
958 return TargetInstrInfo::isReMaterializableImpl(MI);
959}
960
961void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
962 MachineBasicBlock::iterator I,
963 Register DestReg, unsigned SubIdx,
964 const MachineInstr &Orig) const {
965 bool ClobbersEFLAGS = Orig.modifiesRegister(Reg: X86::EFLAGS, TRI: &TRI);
966 if (ClobbersEFLAGS && MBB.computeRegisterLiveness(TRI: &TRI, Reg: X86::EFLAGS, Before: I) !=
967 MachineBasicBlock::LQR_Dead) {
968 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
969 // effects.
970 int Value;
971 switch (Orig.getOpcode()) {
972 case X86::MOV32r0:
973 Value = 0;
974 break;
975 case X86::MOV32r1:
976 Value = 1;
977 break;
978 case X86::MOV32r_1:
979 Value = -1;
980 break;
981 default:
982 llvm_unreachable("Unexpected instruction!");
983 }
984
985 const DebugLoc &DL = Orig.getDebugLoc();
986 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: X86::MOV32ri))
987 .add(MO: Orig.getOperand(i: 0))
988 .addImm(Val: Value);
989 } else {
990 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig: &Orig);
991 MBB.insert(I, MI);
992 }
993
994 MachineInstr &NewMI = *std::prev(x: I);
995 NewMI.substituteRegister(FromReg: Orig.getOperand(i: 0).getReg(), ToReg: DestReg, SubIdx, RegInfo: TRI);
996}
997
998/// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
999bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
1000 for (const MachineOperand &MO : MI.operands()) {
1001 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS &&
1002 !MO.isDead()) {
1003 return true;
1004 }
1005 }
1006 return false;
1007}
1008
1009/// Check whether the shift count for a machine operand is non-zero.
1010inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
1011 unsigned ShiftAmtOperandIdx) {
1012 // The shift count is six bits with the REX.W prefix and five bits without.
1013 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1014 unsigned Imm = MI.getOperand(i: ShiftAmtOperandIdx).getImm();
1015 return Imm & ShiftCountMask;
1016}
1017
1018/// Check whether the given shift count is appropriate
1019/// can be represented by a LEA instruction.
1020inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1021 // Left shift instructions can be transformed into load-effective-address
1022 // instructions if we can encode them appropriately.
1023 // A LEA instruction utilizes a SIB byte to encode its scale factor.
1024 // The SIB.scale field is two bits wide which means that we can encode any
1025 // shift amount less than 4.
1026 return ShAmt < 4 && ShAmt > 0;
1027}
1028
1029static bool
1030findRedundantFlagInstr(MachineInstr &CmpInstr, MachineInstr &CmpValDefInstr,
1031 const MachineRegisterInfo *MRI, MachineInstr **AndInstr,
1032 const TargetRegisterInfo *TRI, const X86Subtarget &ST,
1033 bool &NoSignFlag, bool &ClearsOverflowFlag) {
1034 if (!(CmpValDefInstr.getOpcode() == X86::SUBREG_TO_REG &&
1035 CmpInstr.getOpcode() == X86::TEST64rr) &&
1036 !(CmpValDefInstr.getOpcode() == X86::COPY &&
1037 CmpInstr.getOpcode() == X86::TEST16rr))
1038 return false;
1039
1040 // CmpInstr is a TEST16rr/TEST64rr instruction, and
1041 // `X86InstrInfo::analyzeCompare` guarantees that it's analyzable only if two
1042 // registers are identical.
1043 assert((CmpInstr.getOperand(0).getReg() == CmpInstr.getOperand(1).getReg()) &&
1044 "CmpInstr is an analyzable TEST16rr/TEST64rr, and "
1045 "`X86InstrInfo::analyzeCompare` requires two reg operands are the"
1046 "same.");
1047
1048 // Caller (`X86InstrInfo::optimizeCompareInstr`) guarantees that
1049 // `CmpValDefInstr` defines the value that's used by `CmpInstr`; in this case
1050 // if `CmpValDefInstr` sets the EFLAGS, it is likely that `CmpInstr` is
1051 // redundant.
1052 assert(
1053 (MRI->getVRegDef(CmpInstr.getOperand(0).getReg()) == &CmpValDefInstr) &&
1054 "Caller guarantees that TEST64rr is a user of SUBREG_TO_REG or TEST16rr "
1055 "is a user of COPY sub16bit.");
1056 MachineInstr *VregDefInstr = nullptr;
1057 if (CmpInstr.getOpcode() == X86::TEST16rr) {
1058 if (!CmpValDefInstr.getOperand(i: 1).getReg().isVirtual())
1059 return false;
1060 VregDefInstr = MRI->getVRegDef(Reg: CmpValDefInstr.getOperand(i: 1).getReg());
1061 if (!VregDefInstr)
1062 return false;
1063 // We can only remove test when AND32ri or AND64ri32 whose imm can fit 16bit
1064 // size, others 32/64 bit ops would test higher bits which test16rr don't
1065 // want to.
1066 if (!((VregDefInstr->getOpcode() == X86::AND32ri ||
1067 VregDefInstr->getOpcode() == X86::AND64ri32) &&
1068 isUInt<16>(x: VregDefInstr->getOperand(i: 2).getImm())))
1069 return false;
1070 }
1071
1072 if (CmpInstr.getOpcode() == X86::TEST64rr) {
1073 // As seen in X86 td files, CmpValDefInstr.getOperand(3) is typically
1074 // sub_32bit or sub_xmm.
1075 if (CmpValDefInstr.getOperand(i: 2).getImm() != X86::sub_32bit)
1076 return false;
1077
1078 VregDefInstr = MRI->getVRegDef(Reg: CmpValDefInstr.getOperand(i: 1).getReg());
1079 }
1080
1081 assert(VregDefInstr && "Must have a definition (SSA)");
1082
1083 // Requires `CmpValDefInstr` and `VregDefInstr` are from the same MBB
1084 // to simplify the subsequent analysis.
1085 //
1086 // FIXME: If `VregDefInstr->getParent()` is the only predecessor of
1087 // `CmpValDefInstr.getParent()`, this could be handled.
1088 if (VregDefInstr->getParent() != CmpValDefInstr.getParent())
1089 return false;
1090
1091 if (X86::isAND(Opcode: VregDefInstr->getOpcode()) &&
1092 (!ST.hasNF() || VregDefInstr->modifiesRegister(Reg: X86::EFLAGS, TRI))) {
1093 // Get a sequence of instructions like
1094 // %reg = and* ... // Set EFLAGS
1095 // ... // EFLAGS not changed
1096 // %extended_reg = subreg_to_reg %reg, %subreg.sub_32bit
1097 // test64rr %extended_reg, %extended_reg, implicit-def $eflags
1098 // or
1099 // %reg = and32* ...
1100 // ... // EFLAGS not changed.
1101 // %src_reg = copy %reg.sub_16bit:gr32
1102 // test16rr %src_reg, %src_reg, implicit-def $eflags
1103 //
1104 // If subsequent readers use a subset of bits that don't change
1105 // after `and*` instructions, it's likely that the test64rr could
1106 // be optimized away.
1107 for (const MachineInstr &Instr :
1108 make_range(x: std::next(x: MachineBasicBlock::iterator(VregDefInstr)),
1109 y: MachineBasicBlock::iterator(CmpValDefInstr))) {
1110 // There are instructions between 'VregDefInstr' and
1111 // 'CmpValDefInstr' that modifies EFLAGS.
1112 if (Instr.modifiesRegister(Reg: X86::EFLAGS, TRI))
1113 return false;
1114 }
1115
1116 *AndInstr = VregDefInstr;
1117
1118 // AND instruction will essentially update SF and clear OF, so
1119 // NoSignFlag should be false in the sense that SF is modified by `AND`.
1120 //
1121 // However, the implementation artifically sets `NoSignFlag` to true
1122 // to poison the SF bit; that is to say, if SF is looked at later, the
1123 // optimization (to erase TEST64rr) will be disabled.
1124 //
1125 // The reason to poison SF bit is that SF bit value could be different
1126 // in the `AND` and `TEST` operation; signed bit is not known for `AND`,
1127 // and is known to be 0 as a result of `TEST64rr`.
1128 //
1129 // FIXME: As opposed to poisoning the SF bit directly, consider peeking into
1130 // the AND instruction and using the static information to guide peephole
1131 // optimization if possible. For example, it's possible to fold a
1132 // conditional move into a copy if the relevant EFLAG bits could be deduced
1133 // from an immediate operand of and operation.
1134 //
1135 NoSignFlag = true;
1136 // ClearsOverflowFlag is true for AND operation (no surprise).
1137 ClearsOverflowFlag = true;
1138 return true;
1139 }
1140 return false;
1141}
1142
1143bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
1144 unsigned Opc, bool AllowSP, Register &NewSrc,
1145 unsigned &NewSrcSubReg, bool &isKill,
1146 MachineOperand &ImplicitOp, LiveVariables *LV,
1147 LiveIntervals *LIS) const {
1148 MachineFunction &MF = *MI.getParent()->getParent();
1149 const TargetRegisterClass *RC;
1150 if (AllowSP) {
1151 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1152 } else {
1153 RC = Opc != X86::LEA32r ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1154 }
1155 Register SrcReg = Src.getReg();
1156 unsigned SubReg = Src.getSubReg();
1157 isKill = MI.killsRegister(Reg: SrcReg, /*TRI=*/nullptr);
1158
1159 NewSrcSubReg = X86::NoSubRegister;
1160
1161 // For both LEA64 and LEA32 the register already has essentially the right
1162 // type (32-bit or 64-bit) we may just need to forbid SP.
1163 if (Opc != X86::LEA64_32r) {
1164 NewSrc = SrcReg;
1165 NewSrcSubReg = SubReg;
1166 assert(!Src.isUndef() && "Undef op doesn't need optimization");
1167
1168 if (NewSrc.isVirtual() && !MF.getRegInfo().constrainRegClass(Reg: NewSrc, RC))
1169 return false;
1170
1171 return true;
1172 }
1173
1174 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1175 // another we need to add 64-bit registers to the final MI.
1176 if (SrcReg.isPhysical()) {
1177 ImplicitOp = Src;
1178 ImplicitOp.setImplicit();
1179
1180 NewSrc = getX86SubSuperRegister(Reg: SrcReg, Size: 64);
1181 assert(!SubReg && "no superregister for source");
1182 assert(NewSrc.isValid() && "Invalid Operand");
1183 assert(!Src.isUndef() && "Undef op doesn't need optimization");
1184 } else {
1185 // Virtual register of the wrong class, we have to create a temporary 64-bit
1186 // vreg to feed into the LEA.
1187 NewSrc = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1188 NewSrcSubReg = X86::NoSubRegister;
1189 MachineInstr *Copy =
1190 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: TargetOpcode::COPY))
1191 .addReg(RegNo: NewSrc, Flags: RegState::Define | RegState::Undef, SubReg: X86::sub_32bit)
1192 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill), SubReg);
1193
1194 // Which is obviously going to be dead after we're done with it.
1195 isKill = true;
1196
1197 if (LV)
1198 LV->replaceKillInstruction(Reg: SrcReg, OldMI&: MI, NewMI&: *Copy);
1199
1200 if (LIS) {
1201 SlotIndex CopyIdx = LIS->InsertMachineInstrInMaps(MI&: *Copy);
1202 SlotIndex Idx = LIS->getInstructionIndex(Instr: MI);
1203 LiveInterval &LI = LIS->getInterval(Reg: SrcReg);
1204 LiveRange::Segment *S = LI.getSegmentContaining(Idx);
1205 if (S->end.getBaseIndex() == Idx)
1206 S->end = CopyIdx.getRegSlot();
1207 }
1208 }
1209
1210 // We've set all the parameters without issue.
1211 return true;
1212}
1213
1214MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1215 MachineInstr &MI,
1216 LiveVariables *LV,
1217 LiveIntervals *LIS,
1218 bool Is8BitOp) const {
1219 // We handle 8-bit adds and various 16-bit opcodes in the switch below.
1220 MachineBasicBlock &MBB = *MI.getParent();
1221 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
1222 assert((Is8BitOp ||
1223 RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
1224 *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
1225 "Unexpected type for LEA transform");
1226
1227 // TODO: For a 32-bit target, we need to adjust the LEA variables with
1228 // something like this:
1229 // Opcode = X86::LEA32r;
1230 // InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1231 // OutRegLEA =
1232 // Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
1233 // : RegInfo.createVirtualRegister(&X86::GR32RegClass);
1234 if (!Subtarget.is64Bit())
1235 return nullptr;
1236
1237 unsigned Opcode = X86::LEA64_32r;
1238 Register InRegLEA = RegInfo.createVirtualRegister(RegClass: &X86::GR64_NOSPRegClass);
1239 Register OutRegLEA = RegInfo.createVirtualRegister(RegClass: &X86::GR32RegClass);
1240 Register InRegLEA2;
1241
1242 // Build and insert into an implicit UNDEF value. This is OK because
1243 // we will be shifting and then extracting the lower 8/16-bits.
1244 // This has the potential to cause partial register stall. e.g.
1245 // movw (%rbp,%rcx,2), %dx
1246 // leal -65(%rdx), %esi
1247 // But testing has shown this *does* help performance in 64-bit mode (at
1248 // least on modern x86 machines).
1249 MachineBasicBlock::iterator MBBI = MI.getIterator();
1250 Register Dest = MI.getOperand(i: 0).getReg();
1251 Register Src = MI.getOperand(i: 1).getReg();
1252 unsigned SrcSubReg = MI.getOperand(i: 1).getSubReg();
1253 Register Src2;
1254 unsigned Src2SubReg;
1255 bool IsDead = MI.getOperand(i: 0).isDead();
1256 bool IsKill = MI.getOperand(i: 1).isKill();
1257 unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
1258 assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
1259 MachineInstr *ImpDef =
1260 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::IMPLICIT_DEF), DestReg: InRegLEA);
1261 MachineInstr *InsMI =
1262 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: TargetOpcode::COPY))
1263 .addReg(RegNo: InRegLEA, Flags: RegState::Define, SubReg)
1264 .addReg(RegNo: Src, Flags: getKillRegState(B: IsKill), SubReg: SrcSubReg);
1265 MachineInstr *ImpDef2 = nullptr;
1266 MachineInstr *InsMI2 = nullptr;
1267
1268 MachineInstrBuilder MIB =
1269 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: get(Opcode), DestReg: OutRegLEA);
1270#define CASE_NF(OP) \
1271 case X86::OP: \
1272 case X86::OP##_NF:
1273 switch (MIOpc) {
1274 default:
1275 llvm_unreachable("Unreachable!");
1276 CASE_NF(SHL8ri)
1277 CASE_NF(SHL16ri) {
1278 unsigned ShAmt = MI.getOperand(i: 2).getImm();
1279 MIB.addReg(RegNo: 0)
1280 .addImm(Val: 1LL << ShAmt)
1281 .addReg(RegNo: InRegLEA, Flags: RegState::Kill)
1282 .addImm(Val: 0)
1283 .addReg(RegNo: 0);
1284 break;
1285 }
1286 CASE_NF(INC8r)
1287 CASE_NF(INC16r)
1288 addRegOffset(MIB, Reg: InRegLEA, isKill: true, Offset: 1);
1289 break;
1290 CASE_NF(DEC8r)
1291 CASE_NF(DEC16r)
1292 addRegOffset(MIB, Reg: InRegLEA, isKill: true, Offset: -1);
1293 break;
1294 CASE_NF(ADD8ri)
1295 CASE_NF(ADD16ri)
1296 case X86::ADD8ri_DB:
1297 case X86::ADD16ri_DB:
1298 addRegOffset(MIB, Reg: InRegLEA, isKill: true, Offset: MI.getOperand(i: 2).getImm());
1299 break;
1300 CASE_NF(ADD8rr)
1301 CASE_NF(ADD16rr)
1302 case X86::ADD8rr_DB:
1303 case X86::ADD16rr_DB: {
1304 Src2 = MI.getOperand(i: 2).getReg();
1305 Src2SubReg = MI.getOperand(i: 2).getSubReg();
1306 bool IsKill2 = MI.getOperand(i: 2).isKill();
1307 assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
1308 if (Src == Src2) {
1309 // ADD8rr/ADD16rr killed %reg1028, %reg1028
1310 // just a single insert_subreg.
1311 addRegReg(MIB, Reg1: InRegLEA, isKill1: true, SubReg1: X86::NoSubRegister, Reg2: InRegLEA, isKill2: false,
1312 SubReg2: X86::NoSubRegister);
1313 } else {
1314 if (Subtarget.is64Bit())
1315 InRegLEA2 = RegInfo.createVirtualRegister(RegClass: &X86::GR64_NOSPRegClass);
1316 else
1317 InRegLEA2 = RegInfo.createVirtualRegister(RegClass: &X86::GR32_NOSPRegClass);
1318 // Build and insert into an implicit UNDEF value. This is OK because
1319 // we will be shifting and then extracting the lower 8/16-bits.
1320 ImpDef2 = BuildMI(BB&: MBB, I: &*MIB, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::IMPLICIT_DEF),
1321 DestReg: InRegLEA2);
1322 InsMI2 = BuildMI(BB&: MBB, I: &*MIB, MIMD: MI.getDebugLoc(), MCID: get(Opcode: TargetOpcode::COPY))
1323 .addReg(RegNo: InRegLEA2, Flags: RegState::Define, SubReg)
1324 .addReg(RegNo: Src2, Flags: getKillRegState(B: IsKill2), SubReg: Src2SubReg);
1325 addRegReg(MIB, Reg1: InRegLEA, isKill1: true, SubReg1: X86::NoSubRegister, Reg2: InRegLEA2, isKill2: true,
1326 SubReg2: X86::NoSubRegister);
1327 }
1328 if (LV && IsKill2 && InsMI2)
1329 LV->replaceKillInstruction(Reg: Src2, OldMI&: MI, NewMI&: *InsMI2);
1330 break;
1331 }
1332 }
1333
1334 MachineInstr *NewMI = MIB;
1335 MachineInstr *ExtMI =
1336 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: TargetOpcode::COPY))
1337 .addReg(RegNo: Dest, Flags: RegState::Define | getDeadRegState(B: IsDead))
1338 .addReg(RegNo: OutRegLEA, Flags: RegState::Kill, SubReg);
1339
1340 if (LV) {
1341 // Update live variables.
1342 LV->getVarInfo(Reg: InRegLEA).Kills.push_back(x: NewMI);
1343 if (InRegLEA2)
1344 LV->getVarInfo(Reg: InRegLEA2).Kills.push_back(x: NewMI);
1345 LV->getVarInfo(Reg: OutRegLEA).Kills.push_back(x: ExtMI);
1346 if (IsKill)
1347 LV->replaceKillInstruction(Reg: Src, OldMI&: MI, NewMI&: *InsMI);
1348 if (IsDead)
1349 LV->replaceKillInstruction(Reg: Dest, OldMI&: MI, NewMI&: *ExtMI);
1350 }
1351
1352 if (LIS) {
1353 LIS->InsertMachineInstrInMaps(MI&: *ImpDef);
1354 SlotIndex InsIdx = LIS->InsertMachineInstrInMaps(MI&: *InsMI);
1355 if (ImpDef2)
1356 LIS->InsertMachineInstrInMaps(MI&: *ImpDef2);
1357 SlotIndex Ins2Idx;
1358 if (InsMI2)
1359 Ins2Idx = LIS->InsertMachineInstrInMaps(MI&: *InsMI2);
1360 SlotIndex NewIdx = LIS->ReplaceMachineInstrInMaps(MI, NewMI&: *NewMI);
1361 SlotIndex ExtIdx = LIS->InsertMachineInstrInMaps(MI&: *ExtMI);
1362 LIS->getInterval(Reg: InRegLEA);
1363 LIS->getInterval(Reg: OutRegLEA);
1364 if (InRegLEA2)
1365 LIS->getInterval(Reg: InRegLEA2);
1366
1367 // Move the use of Src up to InsMI.
1368 LiveInterval &SrcLI = LIS->getInterval(Reg: Src);
1369 LiveRange::Segment *SrcSeg = SrcLI.getSegmentContaining(Idx: NewIdx);
1370 if (SrcSeg->end == NewIdx.getRegSlot())
1371 SrcSeg->end = InsIdx.getRegSlot();
1372
1373 if (InsMI2) {
1374 // Move the use of Src2 up to InsMI2.
1375 LiveInterval &Src2LI = LIS->getInterval(Reg: Src2);
1376 LiveRange::Segment *Src2Seg = Src2LI.getSegmentContaining(Idx: NewIdx);
1377 if (Src2Seg->end == NewIdx.getRegSlot())
1378 Src2Seg->end = Ins2Idx.getRegSlot();
1379 }
1380
1381 // Move the definition of Dest down to ExtMI.
1382 LiveInterval &DestLI = LIS->getInterval(Reg: Dest);
1383 LiveRange::Segment *DestSeg =
1384 DestLI.getSegmentContaining(Idx: NewIdx.getRegSlot());
1385 assert(DestSeg->start == NewIdx.getRegSlot() &&
1386 DestSeg->valno->def == NewIdx.getRegSlot());
1387 DestSeg->start = ExtIdx.getRegSlot();
1388 DestSeg->valno->def = ExtIdx.getRegSlot();
1389 }
1390
1391 return ExtMI;
1392}
1393
1394/// This method must be implemented by targets that
1395/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1396/// may be able to convert a two-address instruction into a true
1397/// three-address instruction on demand. This allows the X86 target (for
1398/// example) to convert ADD and SHL instructions into LEA instructions if they
1399/// would require register copies due to two-addressness.
1400///
1401/// This method returns a null pointer if the transformation cannot be
1402/// performed, otherwise it returns the new instruction.
1403///
1404MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
1405 LiveVariables *LV,
1406 LiveIntervals *LIS) const {
1407 // The following opcodes also sets the condition code register(s). Only
1408 // convert them to equivalent lea if the condition code register def's
1409 // are dead!
1410 if (hasLiveCondCodeDef(MI))
1411 return nullptr;
1412
1413 MachineFunction &MF = *MI.getParent()->getParent();
1414 // All instructions input are two-addr instructions. Get the known operands.
1415 const MachineOperand &Dest = MI.getOperand(i: 0);
1416 const MachineOperand &Src = MI.getOperand(i: 1);
1417
1418 // Ideally, operations with undef should be folded before we get here, but we
1419 // can't guarantee it. Bail out because optimizing undefs is a waste of time.
1420 // Without this, we have to forward undef state to new register operands to
1421 // avoid machine verifier errors.
1422 if (Src.isUndef())
1423 return nullptr;
1424 if (MI.getNumOperands() > 2)
1425 if (MI.getOperand(i: 2).isReg() && MI.getOperand(i: 2).isUndef())
1426 return nullptr;
1427
1428 MachineInstr *NewMI = nullptr;
1429 Register SrcReg, SrcReg2;
1430 unsigned SrcSubReg, SrcSubReg2;
1431 bool Is64Bit = Subtarget.is64Bit();
1432
1433 bool Is8BitOp = false;
1434 unsigned NumRegOperands = 2;
1435 unsigned MIOpc = MI.getOpcode();
1436 switch (MIOpc) {
1437 default:
1438 llvm_unreachable("Unreachable!");
1439 CASE_NF(SHL64ri) {
1440 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1441 unsigned ShAmt = getTruncatedShiftCount(MI, ShiftAmtOperandIdx: 2);
1442 if (!isTruncatedShiftCountForLEA(ShAmt))
1443 return nullptr;
1444
1445 // LEA can't handle RSP.
1446 if (Src.getReg().isVirtual() && !MF.getRegInfo().constrainRegClass(
1447 Reg: Src.getReg(), RC: &X86::GR64_NOSPRegClass))
1448 return nullptr;
1449
1450 NewMI = BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::LEA64r))
1451 .add(MO: Dest)
1452 .addReg(RegNo: 0)
1453 .addImm(Val: 1LL << ShAmt)
1454 .add(MO: Src)
1455 .addImm(Val: 0)
1456 .addReg(RegNo: 0);
1457 break;
1458 }
1459 CASE_NF(SHL32ri) {
1460 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1461 unsigned ShAmt = getTruncatedShiftCount(MI, ShiftAmtOperandIdx: 2);
1462 if (!isTruncatedShiftCountForLEA(ShAmt))
1463 return nullptr;
1464
1465 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1466
1467 // LEA can't handle ESP.
1468 bool isKill;
1469 MachineOperand ImplicitOp = MachineOperand::CreateReg(Reg: 0, isDef: false);
1470 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, NewSrc&: SrcReg, NewSrcSubReg&: SrcSubReg,
1471 isKill, ImplicitOp, LV, LIS))
1472 return nullptr;
1473
1474 MachineInstrBuilder MIB =
1475 BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
1476 .add(MO: Dest)
1477 .addReg(RegNo: 0)
1478 .addImm(Val: 1LL << ShAmt)
1479 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill), SubReg: SrcSubReg)
1480 .addImm(Val: 0)
1481 .addReg(RegNo: 0);
1482 if (ImplicitOp.getReg() != 0)
1483 MIB.add(MO: ImplicitOp);
1484 NewMI = MIB;
1485
1486 // Add kills if classifyLEAReg created a new register.
1487 if (LV && SrcReg != Src.getReg())
1488 LV->getVarInfo(Reg: SrcReg).Kills.push_back(x: NewMI);
1489 break;
1490 }
1491 CASE_NF(SHL8ri)
1492 Is8BitOp = true;
1493 [[fallthrough]];
1494 CASE_NF(SHL16ri) {
1495 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1496 unsigned ShAmt = getTruncatedShiftCount(MI, ShiftAmtOperandIdx: 2);
1497 if (!isTruncatedShiftCountForLEA(ShAmt))
1498 return nullptr;
1499 return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1500 }
1501 CASE_NF(INC64r)
1502 CASE_NF(INC32r) {
1503 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
1504 unsigned Opc = (MIOpc == X86::INC64r || MIOpc == X86::INC64r_NF)
1505 ? X86::LEA64r
1506 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1507 bool isKill;
1508 MachineOperand ImplicitOp = MachineOperand::CreateReg(Reg: 0, isDef: false);
1509 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, NewSrc&: SrcReg, NewSrcSubReg&: SrcSubReg,
1510 isKill, ImplicitOp, LV, LIS))
1511 return nullptr;
1512
1513 MachineInstrBuilder MIB = BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
1514 .add(MO: Dest)
1515 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill));
1516 if (ImplicitOp.getReg() != 0)
1517 MIB.add(MO: ImplicitOp);
1518
1519 NewMI = addOffset(MIB, Offset: 1);
1520
1521 // Add kills if classifyLEAReg created a new register.
1522 if (LV && SrcReg != Src.getReg())
1523 LV->getVarInfo(Reg: SrcReg).Kills.push_back(x: NewMI);
1524 break;
1525 }
1526 CASE_NF(DEC64r)
1527 CASE_NF(DEC32r) {
1528 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
1529 unsigned Opc = (MIOpc == X86::DEC64r || MIOpc == X86::DEC64r_NF)
1530 ? X86::LEA64r
1531 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1532
1533 bool isKill;
1534 MachineOperand ImplicitOp = MachineOperand::CreateReg(Reg: 0, isDef: false);
1535 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, NewSrc&: SrcReg, NewSrcSubReg&: SrcSubReg,
1536 isKill, ImplicitOp, LV, LIS))
1537 return nullptr;
1538
1539 MachineInstrBuilder MIB = BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
1540 .add(MO: Dest)
1541 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill));
1542 if (ImplicitOp.getReg() != 0)
1543 MIB.add(MO: ImplicitOp);
1544
1545 NewMI = addOffset(MIB, Offset: -1);
1546
1547 // Add kills if classifyLEAReg created a new register.
1548 if (LV && SrcReg != Src.getReg())
1549 LV->getVarInfo(Reg: SrcReg).Kills.push_back(x: NewMI);
1550 break;
1551 }
1552 CASE_NF(DEC8r)
1553 CASE_NF(INC8r)
1554 Is8BitOp = true;
1555 [[fallthrough]];
1556 CASE_NF(DEC16r)
1557 CASE_NF(INC16r)
1558 return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1559 CASE_NF(ADD64rr)
1560 CASE_NF(ADD32rr)
1561 case X86::ADD64rr_DB:
1562 case X86::ADD32rr_DB: {
1563 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1564 unsigned Opc;
1565 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_NF ||
1566 MIOpc == X86::ADD64rr_DB)
1567 Opc = X86::LEA64r;
1568 else
1569 Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1570
1571 const MachineOperand &Src2 = MI.getOperand(i: 2);
1572 bool isKill2;
1573 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(Reg: 0, isDef: false);
1574 if (!classifyLEAReg(MI, Src: Src2, Opc, /*AllowSP=*/false, NewSrc&: SrcReg2, NewSrcSubReg&: SrcSubReg2,
1575 isKill&: isKill2, ImplicitOp&: ImplicitOp2, LV, LIS))
1576 return nullptr;
1577
1578 bool isKill;
1579 MachineOperand ImplicitOp = MachineOperand::CreateReg(Reg: 0, isDef: false);
1580 if (Src.getReg() == Src2.getReg()) {
1581 // Don't call classify LEAReg a second time on the same register, in case
1582 // the first call inserted a COPY from Src2 and marked it as killed.
1583 isKill = isKill2;
1584 SrcReg = SrcReg2;
1585 SrcSubReg = SrcSubReg2;
1586 } else {
1587 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, NewSrc&: SrcReg, NewSrcSubReg&: SrcSubReg,
1588 isKill, ImplicitOp, LV, LIS))
1589 return nullptr;
1590 }
1591
1592 MachineInstrBuilder MIB = BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc)).add(MO: Dest);
1593 if (ImplicitOp.getReg() != 0)
1594 MIB.add(MO: ImplicitOp);
1595 if (ImplicitOp2.getReg() != 0)
1596 MIB.add(MO: ImplicitOp2);
1597
1598 NewMI =
1599 addRegReg(MIB, Reg1: SrcReg, isKill1: isKill, SubReg1: SrcSubReg, Reg2: SrcReg2, isKill2, SubReg2: SrcSubReg2);
1600
1601 // Add kills if classifyLEAReg created a new register.
1602 if (LV) {
1603 if (SrcReg2 != Src2.getReg())
1604 LV->getVarInfo(Reg: SrcReg2).Kills.push_back(x: NewMI);
1605 if (SrcReg != SrcReg2 && SrcReg != Src.getReg())
1606 LV->getVarInfo(Reg: SrcReg).Kills.push_back(x: NewMI);
1607 }
1608 NumRegOperands = 3;
1609 break;
1610 }
1611 CASE_NF(ADD8rr)
1612 case X86::ADD8rr_DB:
1613 Is8BitOp = true;
1614 [[fallthrough]];
1615 CASE_NF(ADD16rr)
1616 case X86::ADD16rr_DB:
1617 return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1618 CASE_NF(ADD64ri32)
1619 case X86::ADD64ri32_DB:
1620 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1621 NewMI = addOffset(
1622 MIB: BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::LEA64r)).add(MO: Dest).add(MO: Src),
1623 Offset: MI.getOperand(i: 2));
1624 break;
1625 CASE_NF(ADD32ri)
1626 case X86::ADD32ri_DB: {
1627 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1628 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1629
1630 bool isKill;
1631 MachineOperand ImplicitOp = MachineOperand::CreateReg(Reg: 0, isDef: false);
1632 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, NewSrc&: SrcReg, NewSrcSubReg&: SrcSubReg,
1633 isKill, ImplicitOp, LV, LIS))
1634 return nullptr;
1635
1636 MachineInstrBuilder MIB =
1637 BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
1638 .add(MO: Dest)
1639 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill), SubReg: SrcSubReg);
1640 if (ImplicitOp.getReg() != 0)
1641 MIB.add(MO: ImplicitOp);
1642
1643 NewMI = addOffset(MIB, Offset: MI.getOperand(i: 2));
1644
1645 // Add kills if classifyLEAReg created a new register.
1646 if (LV && SrcReg != Src.getReg())
1647 LV->getVarInfo(Reg: SrcReg).Kills.push_back(x: NewMI);
1648 break;
1649 }
1650 CASE_NF(ADD8ri)
1651 case X86::ADD8ri_DB:
1652 Is8BitOp = true;
1653 [[fallthrough]];
1654 CASE_NF(ADD16ri)
1655 case X86::ADD16ri_DB:
1656 return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1657 CASE_NF(SUB8ri)
1658 CASE_NF(SUB16ri)
1659 /// FIXME: Support these similar to ADD8ri/ADD16ri*.
1660 return nullptr;
1661 CASE_NF(SUB32ri) {
1662 if (!MI.getOperand(i: 2).isImm())
1663 return nullptr;
1664 int64_t Imm = MI.getOperand(i: 2).getImm();
1665 if (!isInt<32>(x: -Imm))
1666 return nullptr;
1667
1668 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1669 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1670
1671 bool isKill;
1672 MachineOperand ImplicitOp = MachineOperand::CreateReg(Reg: 0, isDef: false);
1673 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, NewSrc&: SrcReg, NewSrcSubReg&: SrcSubReg,
1674 isKill, ImplicitOp, LV, LIS))
1675 return nullptr;
1676
1677 MachineInstrBuilder MIB =
1678 BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
1679 .add(MO: Dest)
1680 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill), SubReg: SrcSubReg);
1681 if (ImplicitOp.getReg() != 0)
1682 MIB.add(MO: ImplicitOp);
1683
1684 NewMI = addOffset(MIB, Offset: -Imm);
1685
1686 // Add kills if classifyLEAReg created a new register.
1687 if (LV && SrcReg != Src.getReg())
1688 LV->getVarInfo(Reg: SrcReg).Kills.push_back(x: NewMI);
1689 break;
1690 }
1691
1692 CASE_NF(SUB64ri32) {
1693 if (!MI.getOperand(i: 2).isImm())
1694 return nullptr;
1695 int64_t Imm = MI.getOperand(i: 2).getImm();
1696 if (!isInt<32>(x: -Imm))
1697 return nullptr;
1698
1699 assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!");
1700
1701 MachineInstrBuilder MIB =
1702 BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::LEA64r)).add(MO: Dest).add(MO: Src);
1703 NewMI = addOffset(MIB, Offset: -Imm);
1704 break;
1705 }
1706
1707 case X86::VMOVDQU8Z128rmk:
1708 case X86::VMOVDQU8Z256rmk:
1709 case X86::VMOVDQU8Zrmk:
1710 case X86::VMOVDQU16Z128rmk:
1711 case X86::VMOVDQU16Z256rmk:
1712 case X86::VMOVDQU16Zrmk:
1713 case X86::VMOVDQU32Z128rmk:
1714 case X86::VMOVDQA32Z128rmk:
1715 case X86::VMOVDQU32Z256rmk:
1716 case X86::VMOVDQA32Z256rmk:
1717 case X86::VMOVDQU32Zrmk:
1718 case X86::VMOVDQA32Zrmk:
1719 case X86::VMOVDQU64Z128rmk:
1720 case X86::VMOVDQA64Z128rmk:
1721 case X86::VMOVDQU64Z256rmk:
1722 case X86::VMOVDQA64Z256rmk:
1723 case X86::VMOVDQU64Zrmk:
1724 case X86::VMOVDQA64Zrmk:
1725 case X86::VMOVUPDZ128rmk:
1726 case X86::VMOVAPDZ128rmk:
1727 case X86::VMOVUPDZ256rmk:
1728 case X86::VMOVAPDZ256rmk:
1729 case X86::VMOVUPDZrmk:
1730 case X86::VMOVAPDZrmk:
1731 case X86::VMOVUPSZ128rmk:
1732 case X86::VMOVAPSZ128rmk:
1733 case X86::VMOVUPSZ256rmk:
1734 case X86::VMOVAPSZ256rmk:
1735 case X86::VMOVUPSZrmk:
1736 case X86::VMOVAPSZrmk:
1737 case X86::VBROADCASTSDZ256rmk:
1738 case X86::VBROADCASTSDZrmk:
1739 case X86::VBROADCASTSSZ128rmk:
1740 case X86::VBROADCASTSSZ256rmk:
1741 case X86::VBROADCASTSSZrmk:
1742 case X86::VPBROADCASTDZ128rmk:
1743 case X86::VPBROADCASTDZ256rmk:
1744 case X86::VPBROADCASTDZrmk:
1745 case X86::VPBROADCASTQZ128rmk:
1746 case X86::VPBROADCASTQZ256rmk:
1747 case X86::VPBROADCASTQZrmk: {
1748 unsigned Opc;
1749 switch (MIOpc) {
1750 default:
1751 llvm_unreachable("Unreachable!");
1752 case X86::VMOVDQU8Z128rmk:
1753 Opc = X86::VPBLENDMBZ128rmk;
1754 break;
1755 case X86::VMOVDQU8Z256rmk:
1756 Opc = X86::VPBLENDMBZ256rmk;
1757 break;
1758 case X86::VMOVDQU8Zrmk:
1759 Opc = X86::VPBLENDMBZrmk;
1760 break;
1761 case X86::VMOVDQU16Z128rmk:
1762 Opc = X86::VPBLENDMWZ128rmk;
1763 break;
1764 case X86::VMOVDQU16Z256rmk:
1765 Opc = X86::VPBLENDMWZ256rmk;
1766 break;
1767 case X86::VMOVDQU16Zrmk:
1768 Opc = X86::VPBLENDMWZrmk;
1769 break;
1770 case X86::VMOVDQU32Z128rmk:
1771 Opc = X86::VPBLENDMDZ128rmk;
1772 break;
1773 case X86::VMOVDQU32Z256rmk:
1774 Opc = X86::VPBLENDMDZ256rmk;
1775 break;
1776 case X86::VMOVDQU32Zrmk:
1777 Opc = X86::VPBLENDMDZrmk;
1778 break;
1779 case X86::VMOVDQU64Z128rmk:
1780 Opc = X86::VPBLENDMQZ128rmk;
1781 break;
1782 case X86::VMOVDQU64Z256rmk:
1783 Opc = X86::VPBLENDMQZ256rmk;
1784 break;
1785 case X86::VMOVDQU64Zrmk:
1786 Opc = X86::VPBLENDMQZrmk;
1787 break;
1788 case X86::VMOVUPDZ128rmk:
1789 Opc = X86::VBLENDMPDZ128rmk;
1790 break;
1791 case X86::VMOVUPDZ256rmk:
1792 Opc = X86::VBLENDMPDZ256rmk;
1793 break;
1794 case X86::VMOVUPDZrmk:
1795 Opc = X86::VBLENDMPDZrmk;
1796 break;
1797 case X86::VMOVUPSZ128rmk:
1798 Opc = X86::VBLENDMPSZ128rmk;
1799 break;
1800 case X86::VMOVUPSZ256rmk:
1801 Opc = X86::VBLENDMPSZ256rmk;
1802 break;
1803 case X86::VMOVUPSZrmk:
1804 Opc = X86::VBLENDMPSZrmk;
1805 break;
1806 case X86::VMOVDQA32Z128rmk:
1807 Opc = X86::VPBLENDMDZ128rmk;
1808 break;
1809 case X86::VMOVDQA32Z256rmk:
1810 Opc = X86::VPBLENDMDZ256rmk;
1811 break;
1812 case X86::VMOVDQA32Zrmk:
1813 Opc = X86::VPBLENDMDZrmk;
1814 break;
1815 case X86::VMOVDQA64Z128rmk:
1816 Opc = X86::VPBLENDMQZ128rmk;
1817 break;
1818 case X86::VMOVDQA64Z256rmk:
1819 Opc = X86::VPBLENDMQZ256rmk;
1820 break;
1821 case X86::VMOVDQA64Zrmk:
1822 Opc = X86::VPBLENDMQZrmk;
1823 break;
1824 case X86::VMOVAPDZ128rmk:
1825 Opc = X86::VBLENDMPDZ128rmk;
1826 break;
1827 case X86::VMOVAPDZ256rmk:
1828 Opc = X86::VBLENDMPDZ256rmk;
1829 break;
1830 case X86::VMOVAPDZrmk:
1831 Opc = X86::VBLENDMPDZrmk;
1832 break;
1833 case X86::VMOVAPSZ128rmk:
1834 Opc = X86::VBLENDMPSZ128rmk;
1835 break;
1836 case X86::VMOVAPSZ256rmk:
1837 Opc = X86::VBLENDMPSZ256rmk;
1838 break;
1839 case X86::VMOVAPSZrmk:
1840 Opc = X86::VBLENDMPSZrmk;
1841 break;
1842 case X86::VBROADCASTSDZ256rmk:
1843 Opc = X86::VBLENDMPDZ256rmbk;
1844 break;
1845 case X86::VBROADCASTSDZrmk:
1846 Opc = X86::VBLENDMPDZrmbk;
1847 break;
1848 case X86::VBROADCASTSSZ128rmk:
1849 Opc = X86::VBLENDMPSZ128rmbk;
1850 break;
1851 case X86::VBROADCASTSSZ256rmk:
1852 Opc = X86::VBLENDMPSZ256rmbk;
1853 break;
1854 case X86::VBROADCASTSSZrmk:
1855 Opc = X86::VBLENDMPSZrmbk;
1856 break;
1857 case X86::VPBROADCASTDZ128rmk:
1858 Opc = X86::VPBLENDMDZ128rmbk;
1859 break;
1860 case X86::VPBROADCASTDZ256rmk:
1861 Opc = X86::VPBLENDMDZ256rmbk;
1862 break;
1863 case X86::VPBROADCASTDZrmk:
1864 Opc = X86::VPBLENDMDZrmbk;
1865 break;
1866 case X86::VPBROADCASTQZ128rmk:
1867 Opc = X86::VPBLENDMQZ128rmbk;
1868 break;
1869 case X86::VPBROADCASTQZ256rmk:
1870 Opc = X86::VPBLENDMQZ256rmbk;
1871 break;
1872 case X86::VPBROADCASTQZrmk:
1873 Opc = X86::VPBLENDMQZrmbk;
1874 break;
1875 }
1876
1877 NewMI = BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
1878 .add(MO: Dest)
1879 .add(MO: MI.getOperand(i: 2))
1880 .add(MO: Src)
1881 .add(MO: MI.getOperand(i: 3))
1882 .add(MO: MI.getOperand(i: 4))
1883 .add(MO: MI.getOperand(i: 5))
1884 .add(MO: MI.getOperand(i: 6))
1885 .add(MO: MI.getOperand(i: 7));
1886 NumRegOperands = 4;
1887 break;
1888 }
1889
1890 case X86::VMOVDQU8Z128rrk:
1891 case X86::VMOVDQU8Z256rrk:
1892 case X86::VMOVDQU8Zrrk:
1893 case X86::VMOVDQU16Z128rrk:
1894 case X86::VMOVDQU16Z256rrk:
1895 case X86::VMOVDQU16Zrrk:
1896 case X86::VMOVDQU32Z128rrk:
1897 case X86::VMOVDQA32Z128rrk:
1898 case X86::VMOVDQU32Z256rrk:
1899 case X86::VMOVDQA32Z256rrk:
1900 case X86::VMOVDQU32Zrrk:
1901 case X86::VMOVDQA32Zrrk:
1902 case X86::VMOVDQU64Z128rrk:
1903 case X86::VMOVDQA64Z128rrk:
1904 case X86::VMOVDQU64Z256rrk:
1905 case X86::VMOVDQA64Z256rrk:
1906 case X86::VMOVDQU64Zrrk:
1907 case X86::VMOVDQA64Zrrk:
1908 case X86::VMOVUPDZ128rrk:
1909 case X86::VMOVAPDZ128rrk:
1910 case X86::VMOVUPDZ256rrk:
1911 case X86::VMOVAPDZ256rrk:
1912 case X86::VMOVUPDZrrk:
1913 case X86::VMOVAPDZrrk:
1914 case X86::VMOVUPSZ128rrk:
1915 case X86::VMOVAPSZ128rrk:
1916 case X86::VMOVUPSZ256rrk:
1917 case X86::VMOVAPSZ256rrk:
1918 case X86::VMOVUPSZrrk:
1919 case X86::VMOVAPSZrrk: {
1920 unsigned Opc;
1921 switch (MIOpc) {
1922 default:
1923 llvm_unreachable("Unreachable!");
1924 case X86::VMOVDQU8Z128rrk:
1925 Opc = X86::VPBLENDMBZ128rrk;
1926 break;
1927 case X86::VMOVDQU8Z256rrk:
1928 Opc = X86::VPBLENDMBZ256rrk;
1929 break;
1930 case X86::VMOVDQU8Zrrk:
1931 Opc = X86::VPBLENDMBZrrk;
1932 break;
1933 case X86::VMOVDQU16Z128rrk:
1934 Opc = X86::VPBLENDMWZ128rrk;
1935 break;
1936 case X86::VMOVDQU16Z256rrk:
1937 Opc = X86::VPBLENDMWZ256rrk;
1938 break;
1939 case X86::VMOVDQU16Zrrk:
1940 Opc = X86::VPBLENDMWZrrk;
1941 break;
1942 case X86::VMOVDQU32Z128rrk:
1943 Opc = X86::VPBLENDMDZ128rrk;
1944 break;
1945 case X86::VMOVDQU32Z256rrk:
1946 Opc = X86::VPBLENDMDZ256rrk;
1947 break;
1948 case X86::VMOVDQU32Zrrk:
1949 Opc = X86::VPBLENDMDZrrk;
1950 break;
1951 case X86::VMOVDQU64Z128rrk:
1952 Opc = X86::VPBLENDMQZ128rrk;
1953 break;
1954 case X86::VMOVDQU64Z256rrk:
1955 Opc = X86::VPBLENDMQZ256rrk;
1956 break;
1957 case X86::VMOVDQU64Zrrk:
1958 Opc = X86::VPBLENDMQZrrk;
1959 break;
1960 case X86::VMOVUPDZ128rrk:
1961 Opc = X86::VBLENDMPDZ128rrk;
1962 break;
1963 case X86::VMOVUPDZ256rrk:
1964 Opc = X86::VBLENDMPDZ256rrk;
1965 break;
1966 case X86::VMOVUPDZrrk:
1967 Opc = X86::VBLENDMPDZrrk;
1968 break;
1969 case X86::VMOVUPSZ128rrk:
1970 Opc = X86::VBLENDMPSZ128rrk;
1971 break;
1972 case X86::VMOVUPSZ256rrk:
1973 Opc = X86::VBLENDMPSZ256rrk;
1974 break;
1975 case X86::VMOVUPSZrrk:
1976 Opc = X86::VBLENDMPSZrrk;
1977 break;
1978 case X86::VMOVDQA32Z128rrk:
1979 Opc = X86::VPBLENDMDZ128rrk;
1980 break;
1981 case X86::VMOVDQA32Z256rrk:
1982 Opc = X86::VPBLENDMDZ256rrk;
1983 break;
1984 case X86::VMOVDQA32Zrrk:
1985 Opc = X86::VPBLENDMDZrrk;
1986 break;
1987 case X86::VMOVDQA64Z128rrk:
1988 Opc = X86::VPBLENDMQZ128rrk;
1989 break;
1990 case X86::VMOVDQA64Z256rrk:
1991 Opc = X86::VPBLENDMQZ256rrk;
1992 break;
1993 case X86::VMOVDQA64Zrrk:
1994 Opc = X86::VPBLENDMQZrrk;
1995 break;
1996 case X86::VMOVAPDZ128rrk:
1997 Opc = X86::VBLENDMPDZ128rrk;
1998 break;
1999 case X86::VMOVAPDZ256rrk:
2000 Opc = X86::VBLENDMPDZ256rrk;
2001 break;
2002 case X86::VMOVAPDZrrk:
2003 Opc = X86::VBLENDMPDZrrk;
2004 break;
2005 case X86::VMOVAPSZ128rrk:
2006 Opc = X86::VBLENDMPSZ128rrk;
2007 break;
2008 case X86::VMOVAPSZ256rrk:
2009 Opc = X86::VBLENDMPSZ256rrk;
2010 break;
2011 case X86::VMOVAPSZrrk:
2012 Opc = X86::VBLENDMPSZrrk;
2013 break;
2014 }
2015
2016 NewMI = BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
2017 .add(MO: Dest)
2018 .add(MO: MI.getOperand(i: 2))
2019 .add(MO: Src)
2020 .add(MO: MI.getOperand(i: 3));
2021 NumRegOperands = 4;
2022 break;
2023 }
2024 }
2025#undef CASE_NF
2026
2027 if (!NewMI)
2028 return nullptr;
2029
2030 if (LV) { // Update live variables
2031 for (unsigned I = 0; I < NumRegOperands; ++I) {
2032 MachineOperand &Op = MI.getOperand(i: I);
2033 if (Op.isReg() && (Op.isDead() || Op.isKill()))
2034 LV->replaceKillInstruction(Reg: Op.getReg(), OldMI&: MI, NewMI&: *NewMI);
2035 }
2036 }
2037
2038 MachineBasicBlock &MBB = *MI.getParent();
2039 MBB.insert(I: MI.getIterator(), M: NewMI); // Insert the new inst
2040
2041 if (LIS) {
2042 LIS->ReplaceMachineInstrInMaps(MI, NewMI&: *NewMI);
2043 if (SrcReg)
2044 LIS->getInterval(Reg: SrcReg);
2045 if (SrcReg2)
2046 LIS->getInterval(Reg: SrcReg2);
2047 }
2048
2049 return NewMI;
2050}
2051
2052/// This determines which of three possible cases of a three source commute
2053/// the source indexes correspond to taking into account any mask operands.
2054/// All prevents commuting a passthru operand. Returns -1 if the commute isn't
2055/// possible.
2056/// Case 0 - Possible to commute the first and second operands.
2057/// Case 1 - Possible to commute the first and third operands.
2058/// Case 2 - Possible to commute the second and third operands.
2059static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
2060 unsigned SrcOpIdx2) {
2061 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
2062 if (SrcOpIdx1 > SrcOpIdx2)
2063 std::swap(a&: SrcOpIdx1, b&: SrcOpIdx2);
2064
2065 unsigned Op1 = 1, Op2 = 2, Op3 = 3;
2066 if (X86II::isKMasked(TSFlags)) {
2067 Op2++;
2068 Op3++;
2069 }
2070
2071 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
2072 return 0;
2073 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
2074 return 1;
2075 if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
2076 return 2;
2077 llvm_unreachable("Unknown three src commute case.");
2078}
2079
2080unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
2081 const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
2082 const X86InstrFMA3Group &FMA3Group) const {
2083
2084 unsigned Opc = MI.getOpcode();
2085
2086 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
2087 // analysis. The commute optimization is legal only if all users of FMA*_Int
2088 // use only the lowest element of the FMA*_Int instruction. Such analysis are
2089 // not implemented yet. So, just return 0 in that case.
2090 // When such analysis are available this place will be the right place for
2091 // calling it.
2092 assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
2093 "Intrinsic instructions can't commute operand 1");
2094
2095 // Determine which case this commute is or if it can't be done.
2096 unsigned Case =
2097 getThreeSrcCommuteCase(TSFlags: MI.getDesc().TSFlags, SrcOpIdx1, SrcOpIdx2);
2098 assert(Case < 3 && "Unexpected case number!");
2099
2100 // Define the FMA forms mapping array that helps to map input FMA form
2101 // to output FMA form to preserve the operation semantics after
2102 // commuting the operands.
2103 const unsigned Form132Index = 0;
2104 const unsigned Form213Index = 1;
2105 const unsigned Form231Index = 2;
2106 static const unsigned FormMapping[][3] = {
2107 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
2108 // FMA132 A, C, b; ==> FMA231 C, A, b;
2109 // FMA213 B, A, c; ==> FMA213 A, B, c;
2110 // FMA231 C, A, b; ==> FMA132 A, C, b;
2111 {Form231Index, Form213Index, Form132Index},
2112 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
2113 // FMA132 A, c, B; ==> FMA132 B, c, A;
2114 // FMA213 B, a, C; ==> FMA231 C, a, B;
2115 // FMA231 C, a, B; ==> FMA213 B, a, C;
2116 {Form132Index, Form231Index, Form213Index},
2117 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
2118 // FMA132 a, C, B; ==> FMA213 a, B, C;
2119 // FMA213 b, A, C; ==> FMA132 b, C, A;
2120 // FMA231 c, A, B; ==> FMA231 c, B, A;
2121 {Form213Index, Form132Index, Form231Index}};
2122
2123 unsigned FMAForms[3];
2124 FMAForms[0] = FMA3Group.get132Opcode();
2125 FMAForms[1] = FMA3Group.get213Opcode();
2126 FMAForms[2] = FMA3Group.get231Opcode();
2127
2128 // Everything is ready, just adjust the FMA opcode and return it.
2129 for (unsigned FormIndex = 0; FormIndex < 3; FormIndex++)
2130 if (Opc == FMAForms[FormIndex])
2131 return FMAForms[FormMapping[Case][FormIndex]];
2132
2133 llvm_unreachable("Illegal FMA3 format");
2134}
2135
2136static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
2137 unsigned SrcOpIdx2) {
2138 // Determine which case this commute is or if it can't be done.
2139 unsigned Case =
2140 getThreeSrcCommuteCase(TSFlags: MI.getDesc().TSFlags, SrcOpIdx1, SrcOpIdx2);
2141 assert(Case < 3 && "Unexpected case value!");
2142
2143 // For each case we need to swap two pairs of bits in the final immediate.
2144 static const uint8_t SwapMasks[3][4] = {
2145 {0x04, 0x10, 0x08, 0x20}, // Swap bits 2/4 and 3/5.
2146 {0x02, 0x10, 0x08, 0x40}, // Swap bits 1/4 and 3/6.
2147 {0x02, 0x04, 0x20, 0x40}, // Swap bits 1/2 and 5/6.
2148 };
2149
2150 uint8_t Imm = MI.getOperand(i: MI.getNumOperands() - 1).getImm();
2151 // Clear out the bits we are swapping.
2152 uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
2153 SwapMasks[Case][2] | SwapMasks[Case][3]);
2154 // If the immediate had a bit of the pair set, then set the opposite bit.
2155 if (Imm & SwapMasks[Case][0])
2156 NewImm |= SwapMasks[Case][1];
2157 if (Imm & SwapMasks[Case][1])
2158 NewImm |= SwapMasks[Case][0];
2159 if (Imm & SwapMasks[Case][2])
2160 NewImm |= SwapMasks[Case][3];
2161 if (Imm & SwapMasks[Case][3])
2162 NewImm |= SwapMasks[Case][2];
2163 MI.getOperand(i: MI.getNumOperands() - 1).setImm(NewImm);
2164}
2165
2166// Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
2167// commuted.
2168static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
2169#define VPERM_CASES(Suffix) \
2170 case X86::VPERMI2##Suffix##Z128rr: \
2171 case X86::VPERMT2##Suffix##Z128rr: \
2172 case X86::VPERMI2##Suffix##Z256rr: \
2173 case X86::VPERMT2##Suffix##Z256rr: \
2174 case X86::VPERMI2##Suffix##Zrr: \
2175 case X86::VPERMT2##Suffix##Zrr: \
2176 case X86::VPERMI2##Suffix##Z128rm: \
2177 case X86::VPERMT2##Suffix##Z128rm: \
2178 case X86::VPERMI2##Suffix##Z256rm: \
2179 case X86::VPERMT2##Suffix##Z256rm: \
2180 case X86::VPERMI2##Suffix##Zrm: \
2181 case X86::VPERMT2##Suffix##Zrm: \
2182 case X86::VPERMI2##Suffix##Z128rrkz: \
2183 case X86::VPERMT2##Suffix##Z128rrkz: \
2184 case X86::VPERMI2##Suffix##Z256rrkz: \
2185 case X86::VPERMT2##Suffix##Z256rrkz: \
2186 case X86::VPERMI2##Suffix##Zrrkz: \
2187 case X86::VPERMT2##Suffix##Zrrkz: \
2188 case X86::VPERMI2##Suffix##Z128rmkz: \
2189 case X86::VPERMT2##Suffix##Z128rmkz: \
2190 case X86::VPERMI2##Suffix##Z256rmkz: \
2191 case X86::VPERMT2##Suffix##Z256rmkz: \
2192 case X86::VPERMI2##Suffix##Zrmkz: \
2193 case X86::VPERMT2##Suffix##Zrmkz:
2194
2195#define VPERM_CASES_BROADCAST(Suffix) \
2196 VPERM_CASES(Suffix) \
2197 case X86::VPERMI2##Suffix##Z128rmb: \
2198 case X86::VPERMT2##Suffix##Z128rmb: \
2199 case X86::VPERMI2##Suffix##Z256rmb: \
2200 case X86::VPERMT2##Suffix##Z256rmb: \
2201 case X86::VPERMI2##Suffix##Zrmb: \
2202 case X86::VPERMT2##Suffix##Zrmb: \
2203 case X86::VPERMI2##Suffix##Z128rmbkz: \
2204 case X86::VPERMT2##Suffix##Z128rmbkz: \
2205 case X86::VPERMI2##Suffix##Z256rmbkz: \
2206 case X86::VPERMT2##Suffix##Z256rmbkz: \
2207 case X86::VPERMI2##Suffix##Zrmbkz: \
2208 case X86::VPERMT2##Suffix##Zrmbkz:
2209
2210 switch (Opcode) {
2211 default:
2212 return false;
2213 VPERM_CASES(B)
2214 VPERM_CASES_BROADCAST(D)
2215 VPERM_CASES_BROADCAST(PD)
2216 VPERM_CASES_BROADCAST(PS)
2217 VPERM_CASES_BROADCAST(Q)
2218 VPERM_CASES(W)
2219 return true;
2220 }
2221#undef VPERM_CASES_BROADCAST
2222#undef VPERM_CASES
2223}
2224
2225// Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
2226// from the I opcode to the T opcode and vice versa.
2227static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
2228#define VPERM_CASES(Orig, New) \
2229 case X86::Orig##Z128rr: \
2230 return X86::New##Z128rr; \
2231 case X86::Orig##Z128rrkz: \
2232 return X86::New##Z128rrkz; \
2233 case X86::Orig##Z128rm: \
2234 return X86::New##Z128rm; \
2235 case X86::Orig##Z128rmkz: \
2236 return X86::New##Z128rmkz; \
2237 case X86::Orig##Z256rr: \
2238 return X86::New##Z256rr; \
2239 case X86::Orig##Z256rrkz: \
2240 return X86::New##Z256rrkz; \
2241 case X86::Orig##Z256rm: \
2242 return X86::New##Z256rm; \
2243 case X86::Orig##Z256rmkz: \
2244 return X86::New##Z256rmkz; \
2245 case X86::Orig##Zrr: \
2246 return X86::New##Zrr; \
2247 case X86::Orig##Zrrkz: \
2248 return X86::New##Zrrkz; \
2249 case X86::Orig##Zrm: \
2250 return X86::New##Zrm; \
2251 case X86::Orig##Zrmkz: \
2252 return X86::New##Zrmkz;
2253
2254#define VPERM_CASES_BROADCAST(Orig, New) \
2255 VPERM_CASES(Orig, New) \
2256 case X86::Orig##Z128rmb: \
2257 return X86::New##Z128rmb; \
2258 case X86::Orig##Z128rmbkz: \
2259 return X86::New##Z128rmbkz; \
2260 case X86::Orig##Z256rmb: \
2261 return X86::New##Z256rmb; \
2262 case X86::Orig##Z256rmbkz: \
2263 return X86::New##Z256rmbkz; \
2264 case X86::Orig##Zrmb: \
2265 return X86::New##Zrmb; \
2266 case X86::Orig##Zrmbkz: \
2267 return X86::New##Zrmbkz;
2268
2269 switch (Opcode) {
2270 VPERM_CASES(VPERMI2B, VPERMT2B)
2271 VPERM_CASES_BROADCAST(VPERMI2D, VPERMT2D)
2272 VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
2273 VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
2274 VPERM_CASES_BROADCAST(VPERMI2Q, VPERMT2Q)
2275 VPERM_CASES(VPERMI2W, VPERMT2W)
2276 VPERM_CASES(VPERMT2B, VPERMI2B)
2277 VPERM_CASES_BROADCAST(VPERMT2D, VPERMI2D)
2278 VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
2279 VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
2280 VPERM_CASES_BROADCAST(VPERMT2Q, VPERMI2Q)
2281 VPERM_CASES(VPERMT2W, VPERMI2W)
2282 }
2283
2284 llvm_unreachable("Unreachable!");
2285#undef VPERM_CASES_BROADCAST
2286#undef VPERM_CASES
2287}
2288
2289MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
2290 unsigned OpIdx1,
2291 unsigned OpIdx2) const {
2292 auto CloneIfNew = [&](MachineInstr &MI) {
2293 return std::exchange(obj&: NewMI, new_val: false)
2294 ? MI.getParent()->getParent()->CloneMachineInstr(Orig: &MI)
2295 : &MI;
2296 };
2297 MachineInstr *WorkingMI = nullptr;
2298 unsigned Opc = MI.getOpcode();
2299
2300#define CASE_ND(OP) \
2301 case X86::OP: \
2302 case X86::OP##_ND:
2303
2304 switch (Opc) {
2305 // SHLD B, C, I <-> SHRD C, B, (BitWidth - I)
2306 CASE_ND(SHRD16rri8)
2307 CASE_ND(SHLD16rri8)
2308 CASE_ND(SHRD32rri8)
2309 CASE_ND(SHLD32rri8)
2310 CASE_ND(SHRD64rri8)
2311 CASE_ND(SHLD64rri8) {
2312 unsigned Size;
2313 switch (Opc) {
2314 default:
2315 llvm_unreachable("Unreachable!");
2316#define FROM_TO_SIZE(A, B, S) \
2317 case X86::A: \
2318 Opc = X86::B; \
2319 Size = S; \
2320 break; \
2321 case X86::A##_ND: \
2322 Opc = X86::B##_ND; \
2323 Size = S; \
2324 break; \
2325 case X86::B: \
2326 Opc = X86::A; \
2327 Size = S; \
2328 break; \
2329 case X86::B##_ND: \
2330 Opc = X86::A##_ND; \
2331 Size = S; \
2332 break;
2333
2334 FROM_TO_SIZE(SHRD16rri8, SHLD16rri8, 16)
2335 FROM_TO_SIZE(SHRD32rri8, SHLD32rri8, 32)
2336 FROM_TO_SIZE(SHRD64rri8, SHLD64rri8, 64)
2337#undef FROM_TO_SIZE
2338 }
2339 WorkingMI = CloneIfNew(MI);
2340 WorkingMI->setDesc(get(Opcode: Opc));
2341 WorkingMI->getOperand(i: 3).setImm(Size - MI.getOperand(i: 3).getImm());
2342 break;
2343 }
2344 case X86::PFSUBrr:
2345 case X86::PFSUBRrr:
2346 // PFSUB x, y: x = x - y
2347 // PFSUBR x, y: x = y - x
2348 WorkingMI = CloneIfNew(MI);
2349 WorkingMI->setDesc(
2350 get(Opcode: X86::PFSUBRrr == Opc ? X86::PFSUBrr : X86::PFSUBRrr));
2351 break;
2352 case X86::BLENDPDrri:
2353 case X86::BLENDPSrri:
2354 case X86::PBLENDWrri:
2355 case X86::VBLENDPDrri:
2356 case X86::VBLENDPSrri:
2357 case X86::VBLENDPDYrri:
2358 case X86::VBLENDPSYrri:
2359 case X86::VPBLENDDrri:
2360 case X86::VPBLENDWrri:
2361 case X86::VPBLENDDYrri:
2362 case X86::VPBLENDWYrri: {
2363 int8_t Mask;
2364 switch (Opc) {
2365 default:
2366 llvm_unreachable("Unreachable!");
2367 case X86::BLENDPDrri:
2368 Mask = (int8_t)0x03;
2369 break;
2370 case X86::BLENDPSrri:
2371 Mask = (int8_t)0x0F;
2372 break;
2373 case X86::PBLENDWrri:
2374 Mask = (int8_t)0xFF;
2375 break;
2376 case X86::VBLENDPDrri:
2377 Mask = (int8_t)0x03;
2378 break;
2379 case X86::VBLENDPSrri:
2380 Mask = (int8_t)0x0F;
2381 break;
2382 case X86::VBLENDPDYrri:
2383 Mask = (int8_t)0x0F;
2384 break;
2385 case X86::VBLENDPSYrri:
2386 Mask = (int8_t)0xFF;
2387 break;
2388 case X86::VPBLENDDrri:
2389 Mask = (int8_t)0x0F;
2390 break;
2391 case X86::VPBLENDWrri:
2392 Mask = (int8_t)0xFF;
2393 break;
2394 case X86::VPBLENDDYrri:
2395 Mask = (int8_t)0xFF;
2396 break;
2397 case X86::VPBLENDWYrri:
2398 Mask = (int8_t)0xFF;
2399 break;
2400 }
2401 // Only the least significant bits of Imm are used.
2402 // Using int8_t to ensure it will be sign extended to the int64_t that
2403 // setImm takes in order to match isel behavior.
2404 int8_t Imm = MI.getOperand(i: 3).getImm() & Mask;
2405 WorkingMI = CloneIfNew(MI);
2406 WorkingMI->getOperand(i: 3).setImm(Mask ^ Imm);
2407 break;
2408 }
2409 case X86::INSERTPSrri:
2410 case X86::VINSERTPSrri:
2411 case X86::VINSERTPSZrri: {
2412 unsigned Imm = MI.getOperand(i: MI.getNumOperands() - 1).getImm();
2413 unsigned ZMask = Imm & 15;
2414 unsigned DstIdx = (Imm >> 4) & 3;
2415 unsigned SrcIdx = (Imm >> 6) & 3;
2416
2417 // We can commute insertps if we zero 2 of the elements, the insertion is
2418 // "inline" and we don't override the insertion with a zero.
2419 if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
2420 llvm::popcount(Value: ZMask) == 2) {
2421 unsigned AltIdx = llvm::countr_zero(Val: (ZMask | (1 << DstIdx)) ^ 15);
2422 assert(AltIdx < 4 && "Illegal insertion index");
2423 unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
2424 WorkingMI = CloneIfNew(MI);
2425 WorkingMI->getOperand(i: MI.getNumOperands() - 1).setImm(AltImm);
2426 break;
2427 }
2428 return nullptr;
2429 }
2430 case X86::MOVSDrr:
2431 case X86::MOVSSrr:
2432 case X86::VMOVSDrr:
2433 case X86::VMOVSSrr: {
2434 // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
2435 if (Subtarget.hasSSE41()) {
2436 unsigned Mask;
2437 switch (Opc) {
2438 default:
2439 llvm_unreachable("Unreachable!");
2440 case X86::MOVSDrr:
2441 Opc = X86::BLENDPDrri;
2442 Mask = 0x02;
2443 break;
2444 case X86::MOVSSrr:
2445 Opc = X86::BLENDPSrri;
2446 Mask = 0x0E;
2447 break;
2448 case X86::VMOVSDrr:
2449 Opc = X86::VBLENDPDrri;
2450 Mask = 0x02;
2451 break;
2452 case X86::VMOVSSrr:
2453 Opc = X86::VBLENDPSrri;
2454 Mask = 0x0E;
2455 break;
2456 }
2457
2458 WorkingMI = CloneIfNew(MI);
2459 WorkingMI->setDesc(get(Opcode: Opc));
2460 WorkingMI->addOperand(Op: MachineOperand::CreateImm(Val: Mask));
2461 break;
2462 }
2463
2464 assert(Opc == X86::MOVSDrr && "Only MOVSD can commute to SHUFPD");
2465 WorkingMI = CloneIfNew(MI);
2466 WorkingMI->setDesc(get(Opcode: X86::SHUFPDrri));
2467 WorkingMI->addOperand(Op: MachineOperand::CreateImm(Val: 0x02));
2468 break;
2469 }
2470 case X86::SHUFPDrri: {
2471 // Commute to MOVSD.
2472 assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!");
2473 WorkingMI = CloneIfNew(MI);
2474 WorkingMI->setDesc(get(Opcode: X86::MOVSDrr));
2475 WorkingMI->removeOperand(OpNo: 3);
2476 break;
2477 }
2478 case X86::PCLMULQDQrri:
2479 case X86::VPCLMULQDQrri:
2480 case X86::VPCLMULQDQYrri:
2481 case X86::VPCLMULQDQZrri:
2482 case X86::VPCLMULQDQZ128rri:
2483 case X86::VPCLMULQDQZ256rri: {
2484 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2485 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2486 unsigned Imm = MI.getOperand(i: 3).getImm();
2487 unsigned Src1Hi = Imm & 0x01;
2488 unsigned Src2Hi = Imm & 0x10;
2489 WorkingMI = CloneIfNew(MI);
2490 WorkingMI->getOperand(i: 3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
2491 break;
2492 }
2493 case X86::VPCMPBZ128rri:
2494 case X86::VPCMPUBZ128rri:
2495 case X86::VPCMPBZ256rri:
2496 case X86::VPCMPUBZ256rri:
2497 case X86::VPCMPBZrri:
2498 case X86::VPCMPUBZrri:
2499 case X86::VPCMPDZ128rri:
2500 case X86::VPCMPUDZ128rri:
2501 case X86::VPCMPDZ256rri:
2502 case X86::VPCMPUDZ256rri:
2503 case X86::VPCMPDZrri:
2504 case X86::VPCMPUDZrri:
2505 case X86::VPCMPQZ128rri:
2506 case X86::VPCMPUQZ128rri:
2507 case X86::VPCMPQZ256rri:
2508 case X86::VPCMPUQZ256rri:
2509 case X86::VPCMPQZrri:
2510 case X86::VPCMPUQZrri:
2511 case X86::VPCMPWZ128rri:
2512 case X86::VPCMPUWZ128rri:
2513 case X86::VPCMPWZ256rri:
2514 case X86::VPCMPUWZ256rri:
2515 case X86::VPCMPWZrri:
2516 case X86::VPCMPUWZrri:
2517 case X86::VPCMPBZ128rrik:
2518 case X86::VPCMPUBZ128rrik:
2519 case X86::VPCMPBZ256rrik:
2520 case X86::VPCMPUBZ256rrik:
2521 case X86::VPCMPBZrrik:
2522 case X86::VPCMPUBZrrik:
2523 case X86::VPCMPDZ128rrik:
2524 case X86::VPCMPUDZ128rrik:
2525 case X86::VPCMPDZ256rrik:
2526 case X86::VPCMPUDZ256rrik:
2527 case X86::VPCMPDZrrik:
2528 case X86::VPCMPUDZrrik:
2529 case X86::VPCMPQZ128rrik:
2530 case X86::VPCMPUQZ128rrik:
2531 case X86::VPCMPQZ256rrik:
2532 case X86::VPCMPUQZ256rrik:
2533 case X86::VPCMPQZrrik:
2534 case X86::VPCMPUQZrrik:
2535 case X86::VPCMPWZ128rrik:
2536 case X86::VPCMPUWZ128rrik:
2537 case X86::VPCMPWZ256rrik:
2538 case X86::VPCMPUWZ256rrik:
2539 case X86::VPCMPWZrrik:
2540 case X86::VPCMPUWZrrik:
2541 WorkingMI = CloneIfNew(MI);
2542 // Flip comparison mode immediate (if necessary).
2543 WorkingMI->getOperand(i: MI.getNumOperands() - 1)
2544 .setImm(X86::getSwappedVPCMPImm(
2545 Imm: MI.getOperand(i: MI.getNumOperands() - 1).getImm() & 0x7));
2546 break;
2547 case X86::VPCOMBri:
2548 case X86::VPCOMUBri:
2549 case X86::VPCOMDri:
2550 case X86::VPCOMUDri:
2551 case X86::VPCOMQri:
2552 case X86::VPCOMUQri:
2553 case X86::VPCOMWri:
2554 case X86::VPCOMUWri:
2555 WorkingMI = CloneIfNew(MI);
2556 // Flip comparison mode immediate (if necessary).
2557 WorkingMI->getOperand(i: 3).setImm(
2558 X86::getSwappedVPCOMImm(Imm: MI.getOperand(i: 3).getImm() & 0x7));
2559 break;
2560 case X86::VCMPSDZrri:
2561 case X86::VCMPSSZrri:
2562 case X86::VCMPPDZrri:
2563 case X86::VCMPPSZrri:
2564 case X86::VCMPSHZrri:
2565 case X86::VCMPPHZrri:
2566 case X86::VCMPPHZ128rri:
2567 case X86::VCMPPHZ256rri:
2568 case X86::VCMPPDZ128rri:
2569 case X86::VCMPPSZ128rri:
2570 case X86::VCMPPDZ256rri:
2571 case X86::VCMPPSZ256rri:
2572 case X86::VCMPPDZrrik:
2573 case X86::VCMPPSZrrik:
2574 case X86::VCMPPHZrrik:
2575 case X86::VCMPPDZ128rrik:
2576 case X86::VCMPPSZ128rrik:
2577 case X86::VCMPPHZ128rrik:
2578 case X86::VCMPPDZ256rrik:
2579 case X86::VCMPPSZ256rrik:
2580 case X86::VCMPPHZ256rrik:
2581 WorkingMI = CloneIfNew(MI);
2582 WorkingMI->getOperand(i: MI.getNumExplicitOperands() - 1)
2583 .setImm(X86::getSwappedVCMPImm(
2584 Imm: MI.getOperand(i: MI.getNumExplicitOperands() - 1).getImm() & 0x1f));
2585 break;
2586 case X86::VPERM2F128rri:
2587 case X86::VPERM2I128rri:
2588 // Flip permute source immediate.
2589 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
2590 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
2591 WorkingMI = CloneIfNew(MI);
2592 WorkingMI->getOperand(i: 3).setImm((MI.getOperand(i: 3).getImm() & 0xFF) ^ 0x22);
2593 break;
2594 case X86::MOVHLPSrr:
2595 case X86::UNPCKHPDrr:
2596 case X86::VMOVHLPSrr:
2597 case X86::VUNPCKHPDrr:
2598 case X86::VMOVHLPSZrr:
2599 case X86::VUNPCKHPDZ128rr:
2600 assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
2601
2602 switch (Opc) {
2603 default:
2604 llvm_unreachable("Unreachable!");
2605 case X86::MOVHLPSrr:
2606 Opc = X86::UNPCKHPDrr;
2607 break;
2608 case X86::UNPCKHPDrr:
2609 Opc = X86::MOVHLPSrr;
2610 break;
2611 case X86::VMOVHLPSrr:
2612 Opc = X86::VUNPCKHPDrr;
2613 break;
2614 case X86::VUNPCKHPDrr:
2615 Opc = X86::VMOVHLPSrr;
2616 break;
2617 case X86::VMOVHLPSZrr:
2618 Opc = X86::VUNPCKHPDZ128rr;
2619 break;
2620 case X86::VUNPCKHPDZ128rr:
2621 Opc = X86::VMOVHLPSZrr;
2622 break;
2623 }
2624 WorkingMI = CloneIfNew(MI);
2625 WorkingMI->setDesc(get(Opcode: Opc));
2626 break;
2627 CASE_ND(CMOV16rr)
2628 CASE_ND(CMOV32rr)
2629 CASE_ND(CMOV64rr) {
2630 WorkingMI = CloneIfNew(MI);
2631 unsigned OpNo = MI.getDesc().getNumOperands() - 1;
2632 X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(i: OpNo).getImm());
2633 WorkingMI->getOperand(i: OpNo).setImm(X86::GetOppositeBranchCondition(CC));
2634 break;
2635 }
2636 case X86::VPTERNLOGDZrri:
2637 case X86::VPTERNLOGDZrmi:
2638 case X86::VPTERNLOGDZ128rri:
2639 case X86::VPTERNLOGDZ128rmi:
2640 case X86::VPTERNLOGDZ256rri:
2641 case X86::VPTERNLOGDZ256rmi:
2642 case X86::VPTERNLOGQZrri:
2643 case X86::VPTERNLOGQZrmi:
2644 case X86::VPTERNLOGQZ128rri:
2645 case X86::VPTERNLOGQZ128rmi:
2646 case X86::VPTERNLOGQZ256rri:
2647 case X86::VPTERNLOGQZ256rmi:
2648 case X86::VPTERNLOGDZrrik:
2649 case X86::VPTERNLOGDZ128rrik:
2650 case X86::VPTERNLOGDZ256rrik:
2651 case X86::VPTERNLOGQZrrik:
2652 case X86::VPTERNLOGQZ128rrik:
2653 case X86::VPTERNLOGQZ256rrik:
2654 case X86::VPTERNLOGDZrrikz:
2655 case X86::VPTERNLOGDZrmikz:
2656 case X86::VPTERNLOGDZ128rrikz:
2657 case X86::VPTERNLOGDZ128rmikz:
2658 case X86::VPTERNLOGDZ256rrikz:
2659 case X86::VPTERNLOGDZ256rmikz:
2660 case X86::VPTERNLOGQZrrikz:
2661 case X86::VPTERNLOGQZrmikz:
2662 case X86::VPTERNLOGQZ128rrikz:
2663 case X86::VPTERNLOGQZ128rmikz:
2664 case X86::VPTERNLOGQZ256rrikz:
2665 case X86::VPTERNLOGQZ256rmikz:
2666 case X86::VPTERNLOGDZ128rmbi:
2667 case X86::VPTERNLOGDZ256rmbi:
2668 case X86::VPTERNLOGDZrmbi:
2669 case X86::VPTERNLOGQZ128rmbi:
2670 case X86::VPTERNLOGQZ256rmbi:
2671 case X86::VPTERNLOGQZrmbi:
2672 case X86::VPTERNLOGDZ128rmbikz:
2673 case X86::VPTERNLOGDZ256rmbikz:
2674 case X86::VPTERNLOGDZrmbikz:
2675 case X86::VPTERNLOGQZ128rmbikz:
2676 case X86::VPTERNLOGQZ256rmbikz:
2677 case X86::VPTERNLOGQZrmbikz: {
2678 WorkingMI = CloneIfNew(MI);
2679 commuteVPTERNLOG(MI&: *WorkingMI, SrcOpIdx1: OpIdx1, SrcOpIdx2: OpIdx2);
2680 break;
2681 }
2682 default:
2683 if (isCommutableVPERMV3Instruction(Opcode: Opc)) {
2684 WorkingMI = CloneIfNew(MI);
2685 WorkingMI->setDesc(get(Opcode: getCommutedVPERMV3Opcode(Opcode: Opc)));
2686 break;
2687 }
2688
2689 if (auto *FMA3Group = getFMA3Group(Opcode: Opc, TSFlags: MI.getDesc().TSFlags)) {
2690 WorkingMI = CloneIfNew(MI);
2691 WorkingMI->setDesc(
2692 get(Opcode: getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1: OpIdx1, SrcOpIdx2: OpIdx2, FMA3Group: *FMA3Group)));
2693 break;
2694 }
2695 }
2696 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2697}
2698
2699bool X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
2700 unsigned &SrcOpIdx1,
2701 unsigned &SrcOpIdx2,
2702 bool IsIntrinsic) const {
2703 uint64_t TSFlags = MI.getDesc().TSFlags;
2704
2705 unsigned FirstCommutableVecOp = 1;
2706 unsigned LastCommutableVecOp = 3;
2707 unsigned KMaskOp = -1U;
2708 if (X86II::isKMasked(TSFlags)) {
2709 // For k-zero-masked operations it is Ok to commute the first vector
2710 // operand. Unless this is an intrinsic instruction.
2711 // For regular k-masked operations a conservative choice is done as the
2712 // elements of the first vector operand, for which the corresponding bit
2713 // in the k-mask operand is set to 0, are copied to the result of the
2714 // instruction.
2715 // TODO/FIXME: The commute still may be legal if it is known that the
2716 // k-mask operand is set to either all ones or all zeroes.
2717 // It is also Ok to commute the 1st operand if all users of MI use only
2718 // the elements enabled by the k-mask operand. For example,
2719 // v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
2720 // : v1[i];
2721 // VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
2722 // // Ok, to commute v1 in FMADD213PSZrk.
2723
2724 // The k-mask operand has index = 2 for masked and zero-masked operations.
2725 KMaskOp = 2;
2726
2727 // The operand with index = 1 is used as a source for those elements for
2728 // which the corresponding bit in the k-mask is set to 0.
2729 if (X86II::isKMergeMasked(TSFlags) || IsIntrinsic)
2730 FirstCommutableVecOp = 3;
2731
2732 LastCommutableVecOp++;
2733 } else if (IsIntrinsic) {
2734 // Commuting the first operand of an intrinsic instruction isn't possible
2735 // unless we can prove that only the lowest element of the result is used.
2736 FirstCommutableVecOp = 2;
2737 }
2738
2739 if (isMem(MI, Op: LastCommutableVecOp))
2740 LastCommutableVecOp--;
2741
2742 // Only the first RegOpsNum operands are commutable.
2743 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
2744 // that the operand is not specified/fixed.
2745 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
2746 (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
2747 SrcOpIdx1 == KMaskOp))
2748 return false;
2749 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
2750 (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
2751 SrcOpIdx2 == KMaskOp))
2752 return false;
2753
2754 // Look for two different register operands assumed to be commutable
2755 // regardless of the FMA opcode. The FMA opcode is adjusted later.
2756 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
2757 SrcOpIdx2 == CommuteAnyOperandIndex) {
2758 unsigned CommutableOpIdx2 = SrcOpIdx2;
2759
2760 // At least one of operands to be commuted is not specified and
2761 // this method is free to choose appropriate commutable operands.
2762 if (SrcOpIdx1 == SrcOpIdx2)
2763 // Both of operands are not fixed. By default set one of commutable
2764 // operands to the last register operand of the instruction.
2765 CommutableOpIdx2 = LastCommutableVecOp;
2766 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
2767 // Only one of operands is not fixed.
2768 CommutableOpIdx2 = SrcOpIdx1;
2769
2770 // CommutableOpIdx2 is well defined now. Let's choose another commutable
2771 // operand and assign its index to CommutableOpIdx1.
2772 Register Op2Reg = MI.getOperand(i: CommutableOpIdx2).getReg();
2773
2774 unsigned CommutableOpIdx1;
2775 for (CommutableOpIdx1 = LastCommutableVecOp;
2776 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
2777 // Just ignore and skip the k-mask operand.
2778 if (CommutableOpIdx1 == KMaskOp)
2779 continue;
2780
2781 // The commuted operands must have different registers.
2782 // Otherwise, the commute transformation does not change anything and
2783 // is useless then.
2784 if (Op2Reg != MI.getOperand(i: CommutableOpIdx1).getReg())
2785 break;
2786 }
2787
2788 // No appropriate commutable operands were found.
2789 if (CommutableOpIdx1 < FirstCommutableVecOp)
2790 return false;
2791
2792 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
2793 // to return those values.
2794 if (!fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1,
2795 CommutableOpIdx2))
2796 return false;
2797 }
2798
2799 return true;
2800}
2801
2802bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI,
2803 unsigned &SrcOpIdx1,
2804 unsigned &SrcOpIdx2) const {
2805 const MCInstrDesc &Desc = MI.getDesc();
2806 if (!Desc.isCommutable())
2807 return false;
2808
2809 switch (MI.getOpcode()) {
2810 case X86::CMPSDrri:
2811 case X86::CMPSSrri:
2812 case X86::CMPPDrri:
2813 case X86::CMPPSrri:
2814 case X86::VCMPSDrri:
2815 case X86::VCMPSSrri:
2816 case X86::VCMPPDrri:
2817 case X86::VCMPPSrri:
2818 case X86::VCMPPDYrri:
2819 case X86::VCMPPSYrri:
2820 case X86::VCMPSDZrri:
2821 case X86::VCMPSSZrri:
2822 case X86::VCMPPDZrri:
2823 case X86::VCMPPSZrri:
2824 case X86::VCMPSHZrri:
2825 case X86::VCMPPHZrri:
2826 case X86::VCMPPHZ128rri:
2827 case X86::VCMPPHZ256rri:
2828 case X86::VCMPPDZ128rri:
2829 case X86::VCMPPSZ128rri:
2830 case X86::VCMPPDZ256rri:
2831 case X86::VCMPPSZ256rri:
2832 case X86::VCMPPDZrrik:
2833 case X86::VCMPPSZrrik:
2834 case X86::VCMPPHZrrik:
2835 case X86::VCMPPDZ128rrik:
2836 case X86::VCMPPSZ128rrik:
2837 case X86::VCMPPHZ128rrik:
2838 case X86::VCMPPDZ256rrik:
2839 case X86::VCMPPSZ256rrik:
2840 case X86::VCMPPHZ256rrik: {
2841 unsigned OpOffset = X86II::isKMasked(TSFlags: Desc.TSFlags) ? 1 : 0;
2842
2843 // Float comparison can be safely commuted for
2844 // Ordered/Unordered/Equal/NotEqual tests
2845 unsigned Imm = MI.getOperand(i: 3 + OpOffset).getImm() & 0x7;
2846 switch (Imm) {
2847 default:
2848 // EVEX versions can be commuted.
2849 if ((Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX)
2850 break;
2851 return false;
2852 case 0x00: // EQUAL
2853 case 0x03: // UNORDERED
2854 case 0x04: // NOT EQUAL
2855 case 0x07: // ORDERED
2856 break;
2857 }
2858
2859 // The indices of the commutable operands are 1 and 2 (or 2 and 3
2860 // when masked).
2861 // Assign them to the returned operand indices here.
2862 return fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1: 1 + OpOffset,
2863 CommutableOpIdx2: 2 + OpOffset);
2864 }
2865 case X86::MOVSSrr:
2866 // X86::MOVSDrr is always commutable. MOVSS is only commutable if we can
2867 // form sse4.1 blend. We assume VMOVSSrr/VMOVSDrr is always commutable since
2868 // AVX implies sse4.1.
2869 if (Subtarget.hasSSE41())
2870 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2871 return false;
2872 case X86::SHUFPDrri:
2873 // We can commute this to MOVSD.
2874 if (MI.getOperand(i: 3).getImm() == 0x02)
2875 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2876 return false;
2877 case X86::MOVHLPSrr:
2878 case X86::UNPCKHPDrr:
2879 case X86::VMOVHLPSrr:
2880 case X86::VUNPCKHPDrr:
2881 case X86::VMOVHLPSZrr:
2882 case X86::VUNPCKHPDZ128rr:
2883 if (Subtarget.hasSSE2())
2884 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2885 return false;
2886 case X86::VPTERNLOGDZrri:
2887 case X86::VPTERNLOGDZrmi:
2888 case X86::VPTERNLOGDZ128rri:
2889 case X86::VPTERNLOGDZ128rmi:
2890 case X86::VPTERNLOGDZ256rri:
2891 case X86::VPTERNLOGDZ256rmi:
2892 case X86::VPTERNLOGQZrri:
2893 case X86::VPTERNLOGQZrmi:
2894 case X86::VPTERNLOGQZ128rri:
2895 case X86::VPTERNLOGQZ128rmi:
2896 case X86::VPTERNLOGQZ256rri:
2897 case X86::VPTERNLOGQZ256rmi:
2898 case X86::VPTERNLOGDZrrik:
2899 case X86::VPTERNLOGDZ128rrik:
2900 case X86::VPTERNLOGDZ256rrik:
2901 case X86::VPTERNLOGQZrrik:
2902 case X86::VPTERNLOGQZ128rrik:
2903 case X86::VPTERNLOGQZ256rrik:
2904 case X86::VPTERNLOGDZrrikz:
2905 case X86::VPTERNLOGDZrmikz:
2906 case X86::VPTERNLOGDZ128rrikz:
2907 case X86::VPTERNLOGDZ128rmikz:
2908 case X86::VPTERNLOGDZ256rrikz:
2909 case X86::VPTERNLOGDZ256rmikz:
2910 case X86::VPTERNLOGQZrrikz:
2911 case X86::VPTERNLOGQZrmikz:
2912 case X86::VPTERNLOGQZ128rrikz:
2913 case X86::VPTERNLOGQZ128rmikz:
2914 case X86::VPTERNLOGQZ256rrikz:
2915 case X86::VPTERNLOGQZ256rmikz:
2916 case X86::VPTERNLOGDZ128rmbi:
2917 case X86::VPTERNLOGDZ256rmbi:
2918 case X86::VPTERNLOGDZrmbi:
2919 case X86::VPTERNLOGQZ128rmbi:
2920 case X86::VPTERNLOGQZ256rmbi:
2921 case X86::VPTERNLOGQZrmbi:
2922 case X86::VPTERNLOGDZ128rmbikz:
2923 case X86::VPTERNLOGDZ256rmbikz:
2924 case X86::VPTERNLOGDZrmbikz:
2925 case X86::VPTERNLOGQZ128rmbikz:
2926 case X86::VPTERNLOGQZ256rmbikz:
2927 case X86::VPTERNLOGQZrmbikz:
2928 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2929 case X86::VPDPWSSDYrr:
2930 case X86::VPDPWSSDrr:
2931 case X86::VPDPWSSDSYrr:
2932 case X86::VPDPWSSDSrr:
2933 case X86::VPDPWUUDrr:
2934 case X86::VPDPWUUDYrr:
2935 case X86::VPDPWUUDSrr:
2936 case X86::VPDPWUUDSYrr:
2937 case X86::VPDPBSSDSrr:
2938 case X86::VPDPBSSDSYrr:
2939 case X86::VPDPBSSDrr:
2940 case X86::VPDPBSSDYrr:
2941 case X86::VPDPBUUDSrr:
2942 case X86::VPDPBUUDSYrr:
2943 case X86::VPDPBUUDrr:
2944 case X86::VPDPBUUDYrr:
2945 case X86::VPDPBSSDSZ128rr:
2946 case X86::VPDPBSSDSZ128rrk:
2947 case X86::VPDPBSSDSZ128rrkz:
2948 case X86::VPDPBSSDSZ256rr:
2949 case X86::VPDPBSSDSZ256rrk:
2950 case X86::VPDPBSSDSZ256rrkz:
2951 case X86::VPDPBSSDSZrr:
2952 case X86::VPDPBSSDSZrrk:
2953 case X86::VPDPBSSDSZrrkz:
2954 case X86::VPDPBSSDZ128rr:
2955 case X86::VPDPBSSDZ128rrk:
2956 case X86::VPDPBSSDZ128rrkz:
2957 case X86::VPDPBSSDZ256rr:
2958 case X86::VPDPBSSDZ256rrk:
2959 case X86::VPDPBSSDZ256rrkz:
2960 case X86::VPDPBSSDZrr:
2961 case X86::VPDPBSSDZrrk:
2962 case X86::VPDPBSSDZrrkz:
2963 case X86::VPDPBUUDSZ128rr:
2964 case X86::VPDPBUUDSZ128rrk:
2965 case X86::VPDPBUUDSZ128rrkz:
2966 case X86::VPDPBUUDSZ256rr:
2967 case X86::VPDPBUUDSZ256rrk:
2968 case X86::VPDPBUUDSZ256rrkz:
2969 case X86::VPDPBUUDSZrr:
2970 case X86::VPDPBUUDSZrrk:
2971 case X86::VPDPBUUDSZrrkz:
2972 case X86::VPDPBUUDZ128rr:
2973 case X86::VPDPBUUDZ128rrk:
2974 case X86::VPDPBUUDZ128rrkz:
2975 case X86::VPDPBUUDZ256rr:
2976 case X86::VPDPBUUDZ256rrk:
2977 case X86::VPDPBUUDZ256rrkz:
2978 case X86::VPDPBUUDZrr:
2979 case X86::VPDPBUUDZrrk:
2980 case X86::VPDPBUUDZrrkz:
2981 case X86::VPDPWSSDZ128rr:
2982 case X86::VPDPWSSDZ128rrk:
2983 case X86::VPDPWSSDZ128rrkz:
2984 case X86::VPDPWSSDZ256rr:
2985 case X86::VPDPWSSDZ256rrk:
2986 case X86::VPDPWSSDZ256rrkz:
2987 case X86::VPDPWSSDZrr:
2988 case X86::VPDPWSSDZrrk:
2989 case X86::VPDPWSSDZrrkz:
2990 case X86::VPDPWSSDSZ128rr:
2991 case X86::VPDPWSSDSZ128rrk:
2992 case X86::VPDPWSSDSZ128rrkz:
2993 case X86::VPDPWSSDSZ256rr:
2994 case X86::VPDPWSSDSZ256rrk:
2995 case X86::VPDPWSSDSZ256rrkz:
2996 case X86::VPDPWSSDSZrr:
2997 case X86::VPDPWSSDSZrrk:
2998 case X86::VPDPWSSDSZrrkz:
2999 case X86::VPDPWUUDZ128rr:
3000 case X86::VPDPWUUDZ128rrk:
3001 case X86::VPDPWUUDZ128rrkz:
3002 case X86::VPDPWUUDZ256rr:
3003 case X86::VPDPWUUDZ256rrk:
3004 case X86::VPDPWUUDZ256rrkz:
3005 case X86::VPDPWUUDZrr:
3006 case X86::VPDPWUUDZrrk:
3007 case X86::VPDPWUUDZrrkz:
3008 case X86::VPDPWUUDSZ128rr:
3009 case X86::VPDPWUUDSZ128rrk:
3010 case X86::VPDPWUUDSZ128rrkz:
3011 case X86::VPDPWUUDSZ256rr:
3012 case X86::VPDPWUUDSZ256rrk:
3013 case X86::VPDPWUUDSZ256rrkz:
3014 case X86::VPDPWUUDSZrr:
3015 case X86::VPDPWUUDSZrrk:
3016 case X86::VPDPWUUDSZrrkz:
3017 case X86::VPMADD52HUQrr:
3018 case X86::VPMADD52HUQYrr:
3019 case X86::VPMADD52HUQZ128r:
3020 case X86::VPMADD52HUQZ128rk:
3021 case X86::VPMADD52HUQZ128rkz:
3022 case X86::VPMADD52HUQZ256r:
3023 case X86::VPMADD52HUQZ256rk:
3024 case X86::VPMADD52HUQZ256rkz:
3025 case X86::VPMADD52HUQZr:
3026 case X86::VPMADD52HUQZrk:
3027 case X86::VPMADD52HUQZrkz:
3028 case X86::VPMADD52LUQrr:
3029 case X86::VPMADD52LUQYrr:
3030 case X86::VPMADD52LUQZ128r:
3031 case X86::VPMADD52LUQZ128rk:
3032 case X86::VPMADD52LUQZ128rkz:
3033 case X86::VPMADD52LUQZ256r:
3034 case X86::VPMADD52LUQZ256rk:
3035 case X86::VPMADD52LUQZ256rkz:
3036 case X86::VPMADD52LUQZr:
3037 case X86::VPMADD52LUQZrk:
3038 case X86::VPMADD52LUQZrkz:
3039 case X86::VFMADDCPHZr:
3040 case X86::VFMADDCPHZrk:
3041 case X86::VFMADDCPHZrkz:
3042 case X86::VFMADDCPHZ128r:
3043 case X86::VFMADDCPHZ128rk:
3044 case X86::VFMADDCPHZ128rkz:
3045 case X86::VFMADDCPHZ256r:
3046 case X86::VFMADDCPHZ256rk:
3047 case X86::VFMADDCPHZ256rkz:
3048 case X86::VFMADDCSHZr:
3049 case X86::VFMADDCSHZrk:
3050 case X86::VFMADDCSHZrkz: {
3051 unsigned CommutableOpIdx1 = 2;
3052 unsigned CommutableOpIdx2 = 3;
3053 if (X86II::isKMasked(TSFlags: Desc.TSFlags)) {
3054 // Skip the mask register.
3055 ++CommutableOpIdx1;
3056 ++CommutableOpIdx2;
3057 }
3058 if (!fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1,
3059 CommutableOpIdx2))
3060 return false;
3061 if (!MI.getOperand(i: SrcOpIdx1).isReg() || !MI.getOperand(i: SrcOpIdx2).isReg())
3062 // No idea.
3063 return false;
3064 return true;
3065 }
3066
3067 default:
3068 const X86InstrFMA3Group *FMA3Group =
3069 getFMA3Group(Opcode: MI.getOpcode(), TSFlags: MI.getDesc().TSFlags);
3070 if (FMA3Group)
3071 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
3072 IsIntrinsic: FMA3Group->isIntrinsic());
3073
3074 // Handled masked instructions since we need to skip over the mask input
3075 // and the preserved input.
3076 if (X86II::isKMasked(TSFlags: Desc.TSFlags)) {
3077 // First assume that the first input is the mask operand and skip past it.
3078 unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
3079 unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
3080 // Check if the first input is tied. If there isn't one then we only
3081 // need to skip the mask operand which we did above.
3082 if ((MI.getDesc().getOperandConstraint(OpNum: Desc.getNumDefs(),
3083 Constraint: MCOI::TIED_TO) != -1)) {
3084 // If this is zero masking instruction with a tied operand, we need to
3085 // move the first index back to the first input since this must
3086 // be a 3 input instruction and we want the first two non-mask inputs.
3087 // Otherwise this is a 2 input instruction with a preserved input and
3088 // mask, so we need to move the indices to skip one more input.
3089 if (X86II::isKMergeMasked(TSFlags: Desc.TSFlags)) {
3090 ++CommutableOpIdx1;
3091 ++CommutableOpIdx2;
3092 } else {
3093 --CommutableOpIdx1;
3094 }
3095 }
3096
3097 if (!fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1,
3098 CommutableOpIdx2))
3099 return false;
3100
3101 if (!MI.getOperand(i: SrcOpIdx1).isReg() ||
3102 !MI.getOperand(i: SrcOpIdx2).isReg())
3103 // No idea.
3104 return false;
3105 return true;
3106 }
3107
3108 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3109 }
3110 return false;
3111}
3112
3113static bool isConvertibleLEA(MachineInstr *MI) {
3114 unsigned Opcode = MI->getOpcode();
3115 if (Opcode != X86::LEA32r && Opcode != X86::LEA64r &&
3116 Opcode != X86::LEA64_32r)
3117 return false;
3118
3119 const MachineOperand &Scale = MI->getOperand(i: 1 + X86::AddrScaleAmt);
3120 const MachineOperand &Disp = MI->getOperand(i: 1 + X86::AddrDisp);
3121 const MachineOperand &Segment = MI->getOperand(i: 1 + X86::AddrSegmentReg);
3122
3123 if (Segment.getReg() != 0 || !Disp.isImm() || Disp.getImm() != 0 ||
3124 Scale.getImm() > 1)
3125 return false;
3126
3127 return true;
3128}
3129
3130bool X86InstrInfo::hasCommutePreference(MachineInstr &MI, bool &Commute) const {
3131 // Currently we're interested in following sequence only.
3132 // r3 = lea r1, r2
3133 // r5 = add r3, r4
3134 // Both r3 and r4 are killed in add, we hope the add instruction has the
3135 // operand order
3136 // r5 = add r4, r3
3137 // So later in X86FixupLEAs the lea instruction can be rewritten as add.
3138 unsigned Opcode = MI.getOpcode();
3139 if (Opcode != X86::ADD32rr && Opcode != X86::ADD64rr)
3140 return false;
3141
3142 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3143 Register Reg1 = MI.getOperand(i: 1).getReg();
3144 Register Reg2 = MI.getOperand(i: 2).getReg();
3145
3146 // Check if Reg1 comes from LEA in the same MBB.
3147 if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg: Reg1)) {
3148 if (isConvertibleLEA(MI: Inst) && Inst->getParent() == MI.getParent()) {
3149 Commute = true;
3150 return true;
3151 }
3152 }
3153
3154 // Check if Reg2 comes from LEA in the same MBB.
3155 if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg: Reg2)) {
3156 if (isConvertibleLEA(MI: Inst) && Inst->getParent() == MI.getParent()) {
3157 Commute = false;
3158 return true;
3159 }
3160 }
3161
3162 return false;
3163}
3164
3165int X86::getCondSrcNoFromDesc(const MCInstrDesc &MCID) {
3166 unsigned Opcode = MCID.getOpcode();
3167 if (!(X86::isJCC(Opcode) || X86::isSETCC(Opcode) || X86::isSETZUCC(Opcode) ||
3168 X86::isCMOVCC(Opcode) || X86::isCFCMOVCC(Opcode) ||
3169 X86::isCCMPCC(Opcode) || X86::isCTESTCC(Opcode)))
3170 return -1;
3171 // Assume that condition code is always the last use operand.
3172 unsigned NumUses = MCID.getNumOperands() - MCID.getNumDefs();
3173 return NumUses - 1;
3174}
3175
3176X86::CondCode X86::getCondFromMI(const MachineInstr &MI) {
3177 const MCInstrDesc &MCID = MI.getDesc();
3178 int CondNo = getCondSrcNoFromDesc(MCID);
3179 if (CondNo < 0)
3180 return X86::COND_INVALID;
3181 CondNo += MCID.getNumDefs();
3182 return static_cast<X86::CondCode>(MI.getOperand(i: CondNo).getImm());
3183}
3184
3185X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
3186 return X86::isJCC(Opcode: MI.getOpcode()) ? X86::getCondFromMI(MI)
3187 : X86::COND_INVALID;
3188}
3189
3190X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
3191 return X86::isSETCC(Opcode: MI.getOpcode()) || X86::isSETZUCC(Opcode: MI.getOpcode())
3192 ? X86::getCondFromMI(MI)
3193 : X86::COND_INVALID;
3194}
3195
3196X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
3197 return X86::isCMOVCC(Opcode: MI.getOpcode()) ? X86::getCondFromMI(MI)
3198 : X86::COND_INVALID;
3199}
3200
3201X86::CondCode X86::getCondFromCFCMov(const MachineInstr &MI) {
3202 return X86::isCFCMOVCC(Opcode: MI.getOpcode()) ? X86::getCondFromMI(MI)
3203 : X86::COND_INVALID;
3204}
3205
3206X86::CondCode X86::getCondFromCCMP(const MachineInstr &MI) {
3207 return X86::isCCMPCC(Opcode: MI.getOpcode()) || X86::isCTESTCC(Opcode: MI.getOpcode())
3208 ? X86::getCondFromMI(MI)
3209 : X86::COND_INVALID;
3210}
3211
3212int X86::getCCMPCondFlagsFromCondCode(X86::CondCode CC) {
3213 // CCMP/CTEST has two conditional operands:
3214 // - SCC: source conditonal code (same as CMOV)
3215 // - DCF: destination conditional flags, which has 4 valid bits
3216 //
3217 // +----+----+----+----+
3218 // | OF | SF | ZF | CF |
3219 // +----+----+----+----+
3220 //
3221 // If SCC(source conditional code) evaluates to false, CCMP/CTEST will updates
3222 // the conditional flags by as follows:
3223 //
3224 // OF = DCF.OF
3225 // SF = DCF.SF
3226 // ZF = DCF.ZF
3227 // CF = DCF.CF
3228 // PF = DCF.CF
3229 // AF = 0 (Auxiliary Carry Flag)
3230 //
3231 // Otherwise, the CMP or TEST is executed and it updates the
3232 // CSPAZO flags normally.
3233 //
3234 // NOTE:
3235 // If SCC = P, then SCC evaluates to true regardless of the CSPAZO value.
3236 // If SCC = NP, then SCC evaluates to false regardless of the CSPAZO value.
3237
3238 enum { CF = 1, ZF = 2, SF = 4, OF = 8, PF = CF };
3239
3240 switch (CC) {
3241 default:
3242 llvm_unreachable("Illegal condition code!");
3243 case X86::COND_NO:
3244 case X86::COND_NE:
3245 case X86::COND_GE:
3246 case X86::COND_G:
3247 case X86::COND_AE:
3248 case X86::COND_A:
3249 case X86::COND_NS:
3250 case X86::COND_NP:
3251 return 0;
3252 case X86::COND_O:
3253 return OF;
3254 case X86::COND_B:
3255 case X86::COND_BE:
3256 return CF;
3257 break;
3258 case X86::COND_E:
3259 case X86::COND_LE:
3260 return ZF;
3261 case X86::COND_S:
3262 case X86::COND_L:
3263 return SF;
3264 case X86::COND_P:
3265 return PF;
3266 }
3267}
3268
3269#define GET_X86_NF_TRANSFORM_TABLE
3270#define GET_X86_ND2NONND_TABLE
3271#include "X86GenInstrMapping.inc"
3272
3273static unsigned getNewOpcFromTable(ArrayRef<X86TableEntry> Table,
3274 unsigned Opc) {
3275 const auto I = llvm::lower_bound(Range&: Table, Value&: Opc);
3276 return (I == Table.end() || I->OldOpc != Opc) ? 0U : I->NewOpc;
3277}
3278unsigned X86::getNFVariant(unsigned Opc) {
3279#if defined(EXPENSIVE_CHECKS) && !defined(NDEBUG)
3280 // Make sure the tables are sorted.
3281 static std::atomic<bool> NFTableChecked(false);
3282 if (!NFTableChecked.load(std::memory_order_relaxed)) {
3283 assert(llvm::is_sorted(X86NFTransformTable) &&
3284 "X86NFTransformTable is not sorted!");
3285 NFTableChecked.store(true, std::memory_order_relaxed);
3286 }
3287#endif
3288 return getNewOpcFromTable(Table: X86NFTransformTable, Opc);
3289}
3290
3291unsigned X86::getNonNDVariant(unsigned Opc) {
3292#if defined(EXPENSIVE_CHECKS) && !defined(NDEBUG)
3293 // Make sure the tables are sorted.
3294 static std::atomic<bool> NDTableChecked(false);
3295 if (!NDTableChecked.load(std::memory_order_relaxed)) {
3296 assert(llvm::is_sorted(X86ND2NonNDTable) &&
3297 "X86ND2NonNDTableis not sorted!");
3298 NDTableChecked.store(true, std::memory_order_relaxed);
3299 }
3300#endif
3301 return getNewOpcFromTable(Table: X86ND2NonNDTable, Opc);
3302}
3303
3304/// Return the inverse of the specified condition,
3305/// e.g. turning COND_E to COND_NE.
3306X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3307 switch (CC) {
3308 default:
3309 llvm_unreachable("Illegal condition code!");
3310 case X86::COND_E:
3311 return X86::COND_NE;
3312 case X86::COND_NE:
3313 return X86::COND_E;
3314 case X86::COND_L:
3315 return X86::COND_GE;
3316 case X86::COND_LE:
3317 return X86::COND_G;
3318 case X86::COND_G:
3319 return X86::COND_LE;
3320 case X86::COND_GE:
3321 return X86::COND_L;
3322 case X86::COND_B:
3323 return X86::COND_AE;
3324 case X86::COND_BE:
3325 return X86::COND_A;
3326 case X86::COND_A:
3327 return X86::COND_BE;
3328 case X86::COND_AE:
3329 return X86::COND_B;
3330 case X86::COND_S:
3331 return X86::COND_NS;
3332 case X86::COND_NS:
3333 return X86::COND_S;
3334 case X86::COND_P:
3335 return X86::COND_NP;
3336 case X86::COND_NP:
3337 return X86::COND_P;
3338 case X86::COND_O:
3339 return X86::COND_NO;
3340 case X86::COND_NO:
3341 return X86::COND_O;
3342 case X86::COND_NE_OR_P:
3343 return X86::COND_E_AND_NP;
3344 case X86::COND_E_AND_NP:
3345 return X86::COND_NE_OR_P;
3346 }
3347}
3348
3349/// Assuming the flags are set by MI(a,b), return the condition code if we
3350/// modify the instructions such that flags are set by MI(b,a).
3351static X86::CondCode getSwappedCondition(X86::CondCode CC) {
3352 switch (CC) {
3353 default:
3354 return X86::COND_INVALID;
3355 case X86::COND_E:
3356 return X86::COND_E;
3357 case X86::COND_NE:
3358 return X86::COND_NE;
3359 case X86::COND_L:
3360 return X86::COND_G;
3361 case X86::COND_LE:
3362 return X86::COND_GE;
3363 case X86::COND_G:
3364 return X86::COND_L;
3365 case X86::COND_GE:
3366 return X86::COND_LE;
3367 case X86::COND_B:
3368 return X86::COND_A;
3369 case X86::COND_BE:
3370 return X86::COND_AE;
3371 case X86::COND_A:
3372 return X86::COND_B;
3373 case X86::COND_AE:
3374 return X86::COND_BE;
3375 }
3376}
3377
3378std::pair<X86::CondCode, bool>
3379X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
3380 X86::CondCode CC = X86::COND_INVALID;
3381 bool NeedSwap = false;
3382 switch (Predicate) {
3383 default:
3384 break;
3385 // Floating-point Predicates
3386 case CmpInst::FCMP_UEQ:
3387 CC = X86::COND_E;
3388 break;
3389 case CmpInst::FCMP_OLT:
3390 NeedSwap = true;
3391 [[fallthrough]];
3392 case CmpInst::FCMP_OGT:
3393 CC = X86::COND_A;
3394 break;
3395 case CmpInst::FCMP_OLE:
3396 NeedSwap = true;
3397 [[fallthrough]];
3398 case CmpInst::FCMP_OGE:
3399 CC = X86::COND_AE;
3400 break;
3401 case CmpInst::FCMP_UGT:
3402 NeedSwap = true;
3403 [[fallthrough]];
3404 case CmpInst::FCMP_ULT:
3405 CC = X86::COND_B;
3406 break;
3407 case CmpInst::FCMP_UGE:
3408 NeedSwap = true;
3409 [[fallthrough]];
3410 case CmpInst::FCMP_ULE:
3411 CC = X86::COND_BE;
3412 break;
3413 case CmpInst::FCMP_ONE:
3414 CC = X86::COND_NE;
3415 break;
3416 case CmpInst::FCMP_UNO:
3417 CC = X86::COND_P;
3418 break;
3419 case CmpInst::FCMP_ORD:
3420 CC = X86::COND_NP;
3421 break;
3422 case CmpInst::FCMP_OEQ:
3423 [[fallthrough]];
3424 case CmpInst::FCMP_UNE:
3425 CC = X86::COND_INVALID;
3426 break;
3427
3428 // Integer Predicates
3429 case CmpInst::ICMP_EQ:
3430 CC = X86::COND_E;
3431 break;
3432 case CmpInst::ICMP_NE:
3433 CC = X86::COND_NE;
3434 break;
3435 case CmpInst::ICMP_UGT:
3436 CC = X86::COND_A;
3437 break;
3438 case CmpInst::ICMP_UGE:
3439 CC = X86::COND_AE;
3440 break;
3441 case CmpInst::ICMP_ULT:
3442 CC = X86::COND_B;
3443 break;
3444 case CmpInst::ICMP_ULE:
3445 CC = X86::COND_BE;
3446 break;
3447 case CmpInst::ICMP_SGT:
3448 CC = X86::COND_G;
3449 break;
3450 case CmpInst::ICMP_SGE:
3451 CC = X86::COND_GE;
3452 break;
3453 case CmpInst::ICMP_SLT:
3454 CC = X86::COND_L;
3455 break;
3456 case CmpInst::ICMP_SLE:
3457 CC = X86::COND_LE;
3458 break;
3459 }
3460
3461 return std::make_pair(x&: CC, y&: NeedSwap);
3462}
3463
3464/// Return a cmov opcode for the given register size in bytes, and operand type.
3465unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand,
3466 bool HasNDD) {
3467 switch (RegBytes) {
3468 default:
3469 llvm_unreachable("Illegal register size!");
3470#define GET_ND_IF_ENABLED(OPC) (HasNDD ? OPC##_ND : OPC)
3471 case 2:
3472 return HasMemoryOperand ? GET_ND_IF_ENABLED(X86::CMOV16rm)
3473 : GET_ND_IF_ENABLED(X86::CMOV16rr);
3474 case 4:
3475 return HasMemoryOperand ? GET_ND_IF_ENABLED(X86::CMOV32rm)
3476 : GET_ND_IF_ENABLED(X86::CMOV32rr);
3477 case 8:
3478 return HasMemoryOperand ? GET_ND_IF_ENABLED(X86::CMOV64rm)
3479 : GET_ND_IF_ENABLED(X86::CMOV64rr);
3480 }
3481}
3482
3483/// Get the VPCMP immediate for the given condition.
3484unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
3485 switch (CC) {
3486 default:
3487 llvm_unreachable("Unexpected SETCC condition");
3488 case ISD::SETNE:
3489 return 4;
3490 case ISD::SETEQ:
3491 return 0;
3492 case ISD::SETULT:
3493 case ISD::SETLT:
3494 return 1;
3495 case ISD::SETUGT:
3496 case ISD::SETGT:
3497 return 6;
3498 case ISD::SETUGE:
3499 case ISD::SETGE:
3500 return 5;
3501 case ISD::SETULE:
3502 case ISD::SETLE:
3503 return 2;
3504 }
3505}
3506
3507/// Get the VPCMP immediate if the operands are swapped.
3508unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
3509 switch (Imm) {
3510 default:
3511 llvm_unreachable("Unreachable!");
3512 case 0x01:
3513 Imm = 0x06;
3514 break; // LT -> NLE
3515 case 0x02:
3516 Imm = 0x05;
3517 break; // LE -> NLT
3518 case 0x05:
3519 Imm = 0x02;
3520 break; // NLT -> LE
3521 case 0x06:
3522 Imm = 0x01;
3523 break; // NLE -> LT
3524 case 0x00: // EQ
3525 case 0x03: // FALSE
3526 case 0x04: // NE
3527 case 0x07: // TRUE
3528 break;
3529 }
3530
3531 return Imm;
3532}
3533
3534/// Get the VPCOM immediate if the operands are swapped.
3535unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
3536 switch (Imm) {
3537 default:
3538 llvm_unreachable("Unreachable!");
3539 case 0x00:
3540 Imm = 0x02;
3541 break; // LT -> GT
3542 case 0x01:
3543 Imm = 0x03;
3544 break; // LE -> GE
3545 case 0x02:
3546 Imm = 0x00;
3547 break; // GT -> LT
3548 case 0x03:
3549 Imm = 0x01;
3550 break; // GE -> LE
3551 case 0x04: // EQ
3552 case 0x05: // NE
3553 case 0x06: // FALSE
3554 case 0x07: // TRUE
3555 break;
3556 }
3557
3558 return Imm;
3559}
3560
3561/// Get the VCMP immediate if the operands are swapped.
3562unsigned X86::getSwappedVCMPImm(unsigned Imm) {
3563 // Only need the lower 2 bits to distinquish.
3564 switch (Imm & 0x3) {
3565 default:
3566 llvm_unreachable("Unreachable!");
3567 case 0x00:
3568 case 0x03:
3569 // EQ/NE/TRUE/FALSE/ORD/UNORD don't change immediate when commuted.
3570 break;
3571 case 0x01:
3572 case 0x02:
3573 // Need to toggle bits 3:0. Bit 4 stays the same.
3574 Imm ^= 0xf;
3575 break;
3576 }
3577
3578 return Imm;
3579}
3580
3581unsigned X86::getVectorRegisterWidth(const MCOperandInfo &Info) {
3582 if (Info.RegClass == X86::VR128RegClassID ||
3583 Info.RegClass == X86::VR128XRegClassID)
3584 return 128;
3585 if (Info.RegClass == X86::VR256RegClassID ||
3586 Info.RegClass == X86::VR256XRegClassID)
3587 return 256;
3588 if (Info.RegClass == X86::VR512RegClassID)
3589 return 512;
3590 llvm_unreachable("Unknown register class!");
3591}
3592
3593/// Return true if the Reg is X87 register.
3594static bool isX87Reg(Register Reg) {
3595 return (Reg == X86::FPCW || Reg == X86::FPSW ||
3596 (Reg >= X86::ST0 && Reg <= X86::ST7));
3597}
3598
3599/// check if the instruction is X87 instruction
3600bool X86::isX87Instruction(MachineInstr &MI) {
3601 // Call and inlineasm defs X87 register, so we special case it here because
3602 // otherwise calls are incorrectly flagged as x87 instructions
3603 // as a result.
3604 if (MI.isCall() || MI.isInlineAsm())
3605 return false;
3606 for (const MachineOperand &MO : MI.operands()) {
3607 if (!MO.isReg())
3608 continue;
3609 if (isX87Reg(Reg: MO.getReg()))
3610 return true;
3611 }
3612 return false;
3613}
3614
3615int X86::getFirstAddrOperandIdx(const MachineInstr &MI) {
3616 auto IsMemOp = [](const MCOperandInfo &OpInfo) {
3617 return OpInfo.OperandType == MCOI::OPERAND_MEMORY;
3618 };
3619
3620 const MCInstrDesc &Desc = MI.getDesc();
3621
3622 // Directly invoke the MC-layer routine for real (i.e., non-pseudo)
3623 // instructions (fast case).
3624 if (!X86II::isPseudo(TSFlags: Desc.TSFlags)) {
3625 int MemRefIdx = X86II::getMemoryOperandNo(TSFlags: Desc.TSFlags);
3626 if (MemRefIdx >= 0)
3627 return MemRefIdx + X86II::getOperandBias(Desc);
3628#ifdef EXPENSIVE_CHECKS
3629 assert(none_of(Desc.operands(), IsMemOp) &&
3630 "Got false negative from X86II::getMemoryOperandNo()!");
3631#endif
3632 return -1;
3633 }
3634
3635 // Otherwise, handle pseudo instructions by examining the type of their
3636 // operands (slow case). An instruction cannot have a memory reference if it
3637 // has fewer than AddrNumOperands (= 5) explicit operands.
3638 unsigned NumOps = Desc.getNumOperands();
3639 if (NumOps < X86::AddrNumOperands) {
3640#ifdef EXPENSIVE_CHECKS
3641 assert(none_of(Desc.operands(), IsMemOp) &&
3642 "Expected no operands to have OPERAND_MEMORY type!");
3643#endif
3644 return -1;
3645 }
3646
3647 // The first operand with type OPERAND_MEMORY indicates the start of a memory
3648 // reference. We expect the following AddrNumOperand-1 operands to also have
3649 // OPERAND_MEMORY type.
3650 for (unsigned I = 0, E = NumOps - X86::AddrNumOperands; I != E; ++I) {
3651 if (IsMemOp(Desc.operands()[I])) {
3652#ifdef EXPENSIVE_CHECKS
3653 assert(std::all_of(Desc.operands().begin() + I,
3654 Desc.operands().begin() + I + X86::AddrNumOperands,
3655 IsMemOp) &&
3656 "Expected all five operands in the memory reference to have "
3657 "OPERAND_MEMORY type!");
3658#endif
3659 return I;
3660 }
3661 }
3662
3663 return -1;
3664}
3665
3666const Constant *X86::getConstantFromPool(const MachineInstr &MI,
3667 unsigned OpNo) {
3668 assert(MI.getNumOperands() >= (OpNo + X86::AddrNumOperands) &&
3669 "Unexpected number of operands!");
3670
3671 const MachineOperand &Index = MI.getOperand(i: OpNo + X86::AddrIndexReg);
3672 if (!Index.isReg() || Index.getReg() != X86::NoRegister)
3673 return nullptr;
3674
3675 const MachineOperand &Disp = MI.getOperand(i: OpNo + X86::AddrDisp);
3676 if (!Disp.isCPI() || Disp.getOffset() != 0)
3677 return nullptr;
3678
3679 ArrayRef<MachineConstantPoolEntry> Constants =
3680 MI.getParent()->getParent()->getConstantPool()->getConstants();
3681 const MachineConstantPoolEntry &ConstantEntry = Constants[Disp.getIndex()];
3682
3683 // Bail if this is a machine constant pool entry, we won't be able to dig out
3684 // anything useful.
3685 if (ConstantEntry.isMachineConstantPoolEntry())
3686 return nullptr;
3687
3688 return ConstantEntry.Val.ConstVal;
3689}
3690
3691bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
3692 switch (MI.getOpcode()) {
3693 case X86::TCRETURNdi:
3694 case X86::TCRETURNri:
3695 case X86::TCRETURNmi:
3696 case X86::TCRETURNdi64:
3697 case X86::TCRETURNri64:
3698 case X86::TCRETURNri64_ImpCall:
3699 case X86::TCRETURNmi64:
3700 return true;
3701 default:
3702 return false;
3703 }
3704}
3705
3706bool X86InstrInfo::canMakeTailCallConditional(
3707 SmallVectorImpl<MachineOperand> &BranchCond,
3708 const MachineInstr &TailCall) const {
3709
3710 const MachineFunction *MF = TailCall.getMF();
3711
3712 if (MF->getTarget().getCodeModel() == CodeModel::Kernel) {
3713 // Kernel patches thunk calls in runtime, these should never be conditional.
3714 const MachineOperand &Target = TailCall.getOperand(i: 0);
3715 if (Target.isSymbol()) {
3716 StringRef Symbol(Target.getSymbolName());
3717 // this is currently only relevant to r11/kernel indirect thunk.
3718 if (Symbol == "__x86_indirect_thunk_r11")
3719 return false;
3720 }
3721 }
3722
3723 if (TailCall.getOpcode() != X86::TCRETURNdi &&
3724 TailCall.getOpcode() != X86::TCRETURNdi64) {
3725 // Only direct calls can be done with a conditional branch.
3726 return false;
3727 }
3728
3729 if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
3730 // Conditional tail calls confuse the Win64 unwinder.
3731 return false;
3732 }
3733
3734 assert(BranchCond.size() == 1);
3735 if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
3736 // Can't make a conditional tail call with this condition.
3737 return false;
3738 }
3739
3740 const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3741 if (X86FI->getTCReturnAddrDelta() != 0 ||
3742 TailCall.getOperand(i: 1).getImm() != 0) {
3743 // A conditional tail call cannot do any stack adjustment.
3744 return false;
3745 }
3746
3747 return true;
3748}
3749
3750void X86InstrInfo::replaceBranchWithTailCall(
3751 MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
3752 const MachineInstr &TailCall) const {
3753 assert(canMakeTailCallConditional(BranchCond, TailCall));
3754
3755 MachineBasicBlock::iterator I = MBB.end();
3756 while (I != MBB.begin()) {
3757 --I;
3758 if (I->isDebugInstr())
3759 continue;
3760 if (!I->isBranch())
3761 assert(0 && "Can't find the branch to replace!");
3762
3763 X86::CondCode CC = X86::getCondFromBranch(MI: *I);
3764 assert(BranchCond.size() == 1);
3765 if (CC != BranchCond[0].getImm())
3766 continue;
3767
3768 break;
3769 }
3770
3771 unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
3772 : X86::TCRETURNdi64cc;
3773
3774 auto MIB = BuildMI(BB&: MBB, I, MIMD: MBB.findDebugLoc(MBBI: I), MCID: get(Opcode: Opc));
3775 MIB->addOperand(Op: TailCall.getOperand(i: 0)); // Destination.
3776 MIB.addImm(Val: 0); // Stack offset (not used).
3777 MIB->addOperand(Op: BranchCond[0]); // Condition.
3778 MIB.copyImplicitOps(OtherMI: TailCall); // Regmask and (imp-used) parameters.
3779
3780 // Add implicit uses and defs of all live regs potentially clobbered by the
3781 // call. This way they still appear live across the call.
3782 LivePhysRegs LiveRegs(getRegisterInfo());
3783 LiveRegs.addLiveOuts(MBB);
3784 SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
3785 LiveRegs.stepForward(MI: *MIB, Clobbers);
3786 for (const auto &C : Clobbers) {
3787 MIB.addReg(RegNo: C.first, Flags: RegState::Implicit);
3788 MIB.addReg(RegNo: C.first, Flags: RegState::Implicit | RegState::Define);
3789 }
3790
3791 I->eraseFromParent();
3792}
3793
3794// Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
3795// not be a fallthrough MBB now due to layout changes). Return nullptr if the
3796// fallthrough MBB cannot be identified.
3797static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
3798 MachineBasicBlock *TBB) {
3799 // Look for non-EHPad successors other than TBB. If we find exactly one, it
3800 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
3801 // and fallthrough MBB. If we find more than one, we cannot identify the
3802 // fallthrough MBB and should return nullptr.
3803 MachineBasicBlock *FallthroughBB = nullptr;
3804 for (MachineBasicBlock *Succ : MBB->successors()) {
3805 if (Succ->isEHPad() || (Succ == TBB && FallthroughBB))
3806 continue;
3807 // Return a nullptr if we found more than one fallthrough successor.
3808 if (FallthroughBB && FallthroughBB != TBB)
3809 return nullptr;
3810 FallthroughBB = Succ;
3811 }
3812 return FallthroughBB;
3813}
3814
3815bool X86InstrInfo::analyzeBranchImpl(
3816 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
3817 SmallVectorImpl<MachineOperand> &Cond,
3818 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
3819
3820 // Start from the bottom of the block and work up, examining the
3821 // terminator instructions.
3822 MachineBasicBlock::iterator I = MBB.end();
3823 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
3824 while (I != MBB.begin()) {
3825 --I;
3826 if (I->isDebugInstr())
3827 continue;
3828
3829 // Working from the bottom, when we see a non-terminator instruction, we're
3830 // done.
3831 if (!isUnpredicatedTerminator(MI: *I))
3832 break;
3833
3834 // A terminator that isn't a branch can't easily be handled by this
3835 // analysis.
3836 if (!I->isBranch())
3837 return true;
3838
3839 // Handle unconditional branches.
3840 if (I->getOpcode() == X86::JMP_1) {
3841 UnCondBrIter = I;
3842
3843 if (!AllowModify) {
3844 TBB = I->getOperand(i: 0).getMBB();
3845 continue;
3846 }
3847
3848 // If the block has any instructions after a JMP, delete them.
3849 MBB.erase(I: std::next(x: I), E: MBB.end());
3850
3851 Cond.clear();
3852 FBB = nullptr;
3853
3854 // Delete the JMP if it's equivalent to a fall-through.
3855 if (MBB.isLayoutSuccessor(MBB: I->getOperand(i: 0).getMBB())) {
3856 TBB = nullptr;
3857 I->eraseFromParent();
3858 I = MBB.end();
3859 UnCondBrIter = MBB.end();
3860 continue;
3861 }
3862
3863 // TBB is used to indicate the unconditional destination.
3864 TBB = I->getOperand(i: 0).getMBB();
3865 continue;
3866 }
3867
3868 // Handle conditional branches.
3869 X86::CondCode BranchCode = X86::getCondFromBranch(MI: *I);
3870 if (BranchCode == X86::COND_INVALID)
3871 return true; // Can't handle indirect branch.
3872
3873 // In practice we should never have an undef eflags operand, if we do
3874 // abort here as we are not prepared to preserve the flag.
3875 if (I->findRegisterUseOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr)->isUndef())
3876 return true;
3877
3878 // Working from the bottom, handle the first conditional branch.
3879 if (Cond.empty()) {
3880 FBB = TBB;
3881 TBB = I->getOperand(i: 0).getMBB();
3882 Cond.push_back(Elt: MachineOperand::CreateImm(Val: BranchCode));
3883 CondBranches.push_back(Elt: &*I);
3884 continue;
3885 }
3886
3887 // Handle subsequent conditional branches. Only handle the case where all
3888 // conditional branches branch to the same destination and their condition
3889 // opcodes fit one of the special multi-branch idioms.
3890 assert(Cond.size() == 1);
3891 assert(TBB);
3892
3893 // If the conditions are the same, we can leave them alone.
3894 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3895 auto NewTBB = I->getOperand(i: 0).getMBB();
3896 if (OldBranchCode == BranchCode && TBB == NewTBB)
3897 continue;
3898
3899 // If they differ, see if they fit one of the known patterns. Theoretically,
3900 // we could handle more patterns here, but we shouldn't expect to see them
3901 // if instruction selection has done a reasonable job.
3902 if (TBB == NewTBB &&
3903 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
3904 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
3905 BranchCode = X86::COND_NE_OR_P;
3906 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
3907 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
3908 if (NewTBB != (FBB ? FBB : getFallThroughMBB(MBB: &MBB, TBB)))
3909 return true;
3910
3911 // X86::COND_E_AND_NP usually has two different branch destinations.
3912 //
3913 // JP B1
3914 // JE B2
3915 // JMP B1
3916 // B1:
3917 // B2:
3918 //
3919 // Here this condition branches to B2 only if NP && E. It has another
3920 // equivalent form:
3921 //
3922 // JNE B1
3923 // JNP B2
3924 // JMP B1
3925 // B1:
3926 // B2:
3927 //
3928 // Similarly it branches to B2 only if E && NP. That is why this condition
3929 // is named with COND_E_AND_NP.
3930 BranchCode = X86::COND_E_AND_NP;
3931 } else
3932 return true;
3933
3934 // Update the MachineOperand.
3935 Cond[0].setImm(BranchCode);
3936 CondBranches.push_back(Elt: &*I);
3937 }
3938
3939 return false;
3940}
3941
3942bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
3943 MachineBasicBlock *&TBB,
3944 MachineBasicBlock *&FBB,
3945 SmallVectorImpl<MachineOperand> &Cond,
3946 bool AllowModify) const {
3947 SmallVector<MachineInstr *, 4> CondBranches;
3948 return analyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
3949}
3950
3951static int getJumpTableIndexFromAddr(const MachineInstr &MI) {
3952 const MCInstrDesc &Desc = MI.getDesc();
3953 int MemRefBegin = X86II::getMemoryOperandNo(TSFlags: Desc.TSFlags);
3954 assert(MemRefBegin >= 0 && "instr should have memory operand");
3955 MemRefBegin += X86II::getOperandBias(Desc);
3956
3957 const MachineOperand &MO = MI.getOperand(i: MemRefBegin + X86::AddrDisp);
3958 if (!MO.isJTI())
3959 return -1;
3960
3961 return MO.getIndex();
3962}
3963
3964static int getJumpTableIndexFromReg(const MachineRegisterInfo &MRI,
3965 Register Reg) {
3966 if (!Reg.isVirtual())
3967 return -1;
3968 MachineInstr *MI = MRI.getUniqueVRegDef(Reg);
3969 if (MI == nullptr)
3970 return -1;
3971 unsigned Opcode = MI->getOpcode();
3972 if (Opcode != X86::LEA64r && Opcode != X86::LEA32r)
3973 return -1;
3974 return getJumpTableIndexFromAddr(MI: *MI);
3975}
3976
3977int X86InstrInfo::getJumpTableIndex(const MachineInstr &MI) const {
3978 unsigned Opcode = MI.getOpcode();
3979 // Switch-jump pattern for non-PIC code looks like:
3980 // JMP64m $noreg, 8, %X, %jump-table.X, $noreg
3981 if (Opcode == X86::JMP64m || Opcode == X86::JMP32m) {
3982 return getJumpTableIndexFromAddr(MI);
3983 }
3984 // The pattern for PIC code looks like:
3985 // %0 = LEA64r $rip, 1, $noreg, %jump-table.X
3986 // %1 = MOVSX64rm32 %0, 4, XX, 0, $noreg
3987 // %2 = ADD64rr %1, %0
3988 // JMP64r %2
3989 if (Opcode == X86::JMP64r || Opcode == X86::JMP32r) {
3990 Register Reg = MI.getOperand(i: 0).getReg();
3991 if (!Reg.isVirtual())
3992 return -1;
3993 const MachineFunction &MF = *MI.getParent()->getParent();
3994 const MachineRegisterInfo &MRI = MF.getRegInfo();
3995 MachineInstr *Add = MRI.getUniqueVRegDef(Reg);
3996 if (Add == nullptr)
3997 return -1;
3998 if (Add->getOpcode() != X86::ADD64rr && Add->getOpcode() != X86::ADD32rr)
3999 return -1;
4000 int JTI1 = getJumpTableIndexFromReg(MRI, Reg: Add->getOperand(i: 1).getReg());
4001 if (JTI1 >= 0)
4002 return JTI1;
4003 int JTI2 = getJumpTableIndexFromReg(MRI, Reg: Add->getOperand(i: 2).getReg());
4004 if (JTI2 >= 0)
4005 return JTI2;
4006 }
4007 return -1;
4008}
4009
4010bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
4011 MachineBranchPredicate &MBP,
4012 bool AllowModify) const {
4013 using namespace std::placeholders;
4014
4015 SmallVector<MachineOperand, 4> Cond;
4016 SmallVector<MachineInstr *, 4> CondBranches;
4017 if (analyzeBranchImpl(MBB, TBB&: MBP.TrueDest, FBB&: MBP.FalseDest, Cond, CondBranches,
4018 AllowModify))
4019 return true;
4020
4021 if (Cond.size() != 1)
4022 return true;
4023
4024 assert(MBP.TrueDest && "expected!");
4025
4026 if (!MBP.FalseDest)
4027 MBP.FalseDest = MBB.getNextNode();
4028
4029 const TargetRegisterInfo *TRI = &getRegisterInfo();
4030
4031 MachineInstr *ConditionDef = nullptr;
4032 bool SingleUseCondition = true;
4033
4034 for (MachineInstr &MI : llvm::drop_begin(RangeOrContainer: llvm::reverse(C&: MBB))) {
4035 if (MI.modifiesRegister(Reg: X86::EFLAGS, TRI)) {
4036 ConditionDef = &MI;
4037 break;
4038 }
4039
4040 if (MI.readsRegister(Reg: X86::EFLAGS, TRI))
4041 SingleUseCondition = false;
4042 }
4043
4044 if (!ConditionDef)
4045 return true;
4046
4047 if (SingleUseCondition) {
4048 for (auto *Succ : MBB.successors())
4049 if (Succ->isLiveIn(Reg: X86::EFLAGS))
4050 SingleUseCondition = false;
4051 }
4052
4053 MBP.ConditionDef = ConditionDef;
4054 MBP.SingleUseCondition = SingleUseCondition;
4055
4056 // Currently we only recognize the simple pattern:
4057 //
4058 // test %reg, %reg
4059 // je %label
4060 //
4061 const unsigned TestOpcode =
4062 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4063
4064 if (ConditionDef->getOpcode() == TestOpcode &&
4065 ConditionDef->getNumOperands() == 3 &&
4066 ConditionDef->getOperand(i: 0).isIdenticalTo(Other: ConditionDef->getOperand(i: 1)) &&
4067 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4068 MBP.LHS = ConditionDef->getOperand(i: 0);
4069 MBP.RHS = MachineOperand::CreateImm(Val: 0);
4070 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4071 ? MachineBranchPredicate::PRED_NE
4072 : MachineBranchPredicate::PRED_EQ;
4073 return false;
4074 }
4075
4076 return true;
4077}
4078
4079unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
4080 int *BytesRemoved) const {
4081 assert(!BytesRemoved && "code size not handled");
4082
4083 MachineBasicBlock::iterator I = MBB.end();
4084 unsigned Count = 0;
4085
4086 while (I != MBB.begin()) {
4087 --I;
4088 if (I->isDebugInstr())
4089 continue;
4090 if (I->getOpcode() != X86::JMP_1 &&
4091 X86::getCondFromBranch(MI: *I) == X86::COND_INVALID)
4092 break;
4093 // Remove the branch.
4094 I->eraseFromParent();
4095 I = MBB.end();
4096 ++Count;
4097 }
4098
4099 return Count;
4100}
4101
4102unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
4103 MachineBasicBlock *TBB,
4104 MachineBasicBlock *FBB,
4105 ArrayRef<MachineOperand> Cond,
4106 const DebugLoc &DL, int *BytesAdded) const {
4107 // Shouldn't be a fall through.
4108 assert(TBB && "insertBranch must not be told to insert a fallthrough");
4109 assert((Cond.size() == 1 || Cond.size() == 0) &&
4110 "X86 branch conditions have one component!");
4111 assert(!BytesAdded && "code size not handled");
4112
4113 if (Cond.empty()) {
4114 // Unconditional branch?
4115 assert(!FBB && "Unconditional branch with multiple successors!");
4116 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JMP_1)).addMBB(MBB: TBB);
4117 return 1;
4118 }
4119
4120 // If FBB is null, it is implied to be a fall-through block.
4121 bool FallThru = FBB == nullptr;
4122
4123 // Conditional branch.
4124 unsigned Count = 0;
4125 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4126 switch (CC) {
4127 case X86::COND_NE_OR_P:
4128 // Synthesize NE_OR_P with two branches.
4129 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JCC_1)).addMBB(MBB: TBB).addImm(Val: X86::COND_NE);
4130 ++Count;
4131 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JCC_1)).addMBB(MBB: TBB).addImm(Val: X86::COND_P);
4132 ++Count;
4133 break;
4134 case X86::COND_E_AND_NP:
4135 // Use the next block of MBB as FBB if it is null.
4136 if (FBB == nullptr) {
4137 FBB = getFallThroughMBB(MBB: &MBB, TBB);
4138 assert(FBB && "MBB cannot be the last block in function when the false "
4139 "body is a fall-through.");
4140 }
4141 // Synthesize COND_E_AND_NP with two branches.
4142 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JCC_1)).addMBB(MBB: FBB).addImm(Val: X86::COND_NE);
4143 ++Count;
4144 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JCC_1)).addMBB(MBB: TBB).addImm(Val: X86::COND_NP);
4145 ++Count;
4146 break;
4147 default: {
4148 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JCC_1)).addMBB(MBB: TBB).addImm(Val: CC);
4149 ++Count;
4150 }
4151 }
4152 if (!FallThru) {
4153 // Two-way Conditional branch. Insert the second branch.
4154 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JMP_1)).addMBB(MBB: FBB);
4155 ++Count;
4156 }
4157 return Count;
4158}
4159
4160bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
4161 ArrayRef<MachineOperand> Cond,
4162 Register DstReg, Register TrueReg,
4163 Register FalseReg, int &CondCycles,
4164 int &TrueCycles, int &FalseCycles) const {
4165 // Not all subtargets have cmov instructions.
4166 if (!Subtarget.canUseCMOV())
4167 return false;
4168 if (Cond.size() != 1)
4169 return false;
4170 // We cannot do the composite conditions, at least not in SSA form.
4171 if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
4172 return false;
4173
4174 // Check register classes.
4175 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4176 const TargetRegisterClass *RC =
4177 RI.getCommonSubClass(A: MRI.getRegClass(Reg: TrueReg), B: MRI.getRegClass(Reg: FalseReg));
4178 if (!RC)
4179 return false;
4180
4181 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4182 if (X86::GR16RegClass.hasSubClassEq(RC) ||
4183 X86::GR32RegClass.hasSubClassEq(RC) ||
4184 X86::GR64RegClass.hasSubClassEq(RC)) {
4185 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4186 // Bridge. Probably Ivy Bridge as well.
4187 CondCycles = 2;
4188 TrueCycles = 2;
4189 FalseCycles = 2;
4190 return true;
4191 }
4192
4193 // Can't do vectors.
4194 return false;
4195}
4196
4197void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
4198 MachineBasicBlock::iterator I,
4199 const DebugLoc &DL, Register DstReg,
4200 ArrayRef<MachineOperand> Cond, Register TrueReg,
4201 Register FalseReg) const {
4202 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4203 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
4204 const TargetRegisterClass &RC = *MRI.getRegClass(Reg: DstReg);
4205 assert(Cond.size() == 1 && "Invalid Cond array");
4206 unsigned Opc =
4207 X86::getCMovOpcode(RegBytes: TRI.getRegSizeInBits(RC) / 8,
4208 HasMemoryOperand: false /*HasMemoryOperand*/, HasNDD: Subtarget.hasNDD());
4209 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Opc), DestReg: DstReg)
4210 .addReg(RegNo: FalseReg)
4211 .addReg(RegNo: TrueReg)
4212 .addImm(Val: Cond[0].getImm());
4213}
4214
4215/// Test if the given register is a physical h register.
4216static bool isHReg(Register Reg) {
4217 return X86::GR8_ABCD_HRegClass.contains(Reg);
4218}
4219
4220// Try and copy between VR128/VR64 and GR64 registers.
4221static unsigned CopyToFromAsymmetricReg(Register DestReg, Register SrcReg,
4222 const X86Subtarget &Subtarget) {
4223 bool HasAVX = Subtarget.hasAVX();
4224 bool HasAVX512 = Subtarget.hasAVX512();
4225 bool HasEGPR = Subtarget.hasEGPR();
4226
4227 // SrcReg(MaskReg) -> DestReg(GR64)
4228 // SrcReg(MaskReg) -> DestReg(GR32)
4229
4230 // All KMASK RegClasses hold the same k registers, can be tested against
4231 // anyone.
4232 if (X86::VK16RegClass.contains(Reg: SrcReg)) {
4233 if (X86::GR64RegClass.contains(Reg: DestReg)) {
4234 assert(Subtarget.hasBWI());
4235 return HasEGPR ? X86::KMOVQrk_EVEX : X86::KMOVQrk;
4236 }
4237 if (X86::GR32RegClass.contains(Reg: DestReg))
4238 return Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVDrk_EVEX : X86::KMOVDrk)
4239 : (HasEGPR ? X86::KMOVWrk_EVEX : X86::KMOVWrk);
4240 }
4241
4242 // SrcReg(GR64) -> DestReg(MaskReg)
4243 // SrcReg(GR32) -> DestReg(MaskReg)
4244
4245 // All KMASK RegClasses hold the same k registers, can be tested against
4246 // anyone.
4247 if (X86::VK16RegClass.contains(Reg: DestReg)) {
4248 if (X86::GR64RegClass.contains(Reg: SrcReg)) {
4249 assert(Subtarget.hasBWI());
4250 return HasEGPR ? X86::KMOVQkr_EVEX : X86::KMOVQkr;
4251 }
4252 if (X86::GR32RegClass.contains(Reg: SrcReg))
4253 return Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVDkr_EVEX : X86::KMOVDkr)
4254 : (HasEGPR ? X86::KMOVWkr_EVEX : X86::KMOVWkr);
4255 }
4256
4257 // SrcReg(VR128) -> DestReg(GR64)
4258 // SrcReg(VR64) -> DestReg(GR64)
4259 // SrcReg(GR64) -> DestReg(VR128)
4260 // SrcReg(GR64) -> DestReg(VR64)
4261
4262 if (X86::GR64RegClass.contains(Reg: DestReg)) {
4263 if (X86::VR128XRegClass.contains(Reg: SrcReg))
4264 // Copy from a VR128 register to a GR64 register.
4265 return HasAVX512 ? X86::VMOVPQIto64Zrr
4266 : HasAVX ? X86::VMOVPQIto64rr
4267 : X86::MOVPQIto64rr;
4268 if (X86::VR64RegClass.contains(Reg: SrcReg))
4269 // Copy from a VR64 register to a GR64 register.
4270 return X86::MMX_MOVD64from64rr;
4271 } else if (X86::GR64RegClass.contains(Reg: SrcReg)) {
4272 // Copy from a GR64 register to a VR128 register.
4273 if (X86::VR128XRegClass.contains(Reg: DestReg))
4274 return HasAVX512 ? X86::VMOV64toPQIZrr
4275 : HasAVX ? X86::VMOV64toPQIrr
4276 : X86::MOV64toPQIrr;
4277 // Copy from a GR64 register to a VR64 register.
4278 if (X86::VR64RegClass.contains(Reg: DestReg))
4279 return X86::MMX_MOVD64to64rr;
4280 }
4281
4282 // SrcReg(VR128) -> DestReg(GR32)
4283 // SrcReg(GR32) -> DestReg(VR128)
4284
4285 if (X86::GR32RegClass.contains(Reg: DestReg) &&
4286 X86::VR128XRegClass.contains(Reg: SrcReg))
4287 // Copy from a VR128 register to a GR32 register.
4288 return HasAVX512 ? X86::VMOVPDI2DIZrr
4289 : HasAVX ? X86::VMOVPDI2DIrr
4290 : X86::MOVPDI2DIrr;
4291
4292 if (X86::VR128XRegClass.contains(Reg: DestReg) &&
4293 X86::GR32RegClass.contains(Reg: SrcReg))
4294 // Copy from a GR32 register to a VR128 register.
4295 return HasAVX512 ? X86::VMOVDI2PDIZrr
4296 : HasAVX ? X86::VMOVDI2PDIrr
4297 : X86::MOVDI2PDIrr;
4298
4299 return 0;
4300}
4301
4302void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4303 MachineBasicBlock::iterator MI,
4304 const DebugLoc &DL, Register DestReg,
4305 Register SrcReg, bool KillSrc,
4306 bool RenamableDest, bool RenamableSrc) const {
4307 // First deal with the normal symmetric copies.
4308 bool HasAVX = Subtarget.hasAVX();
4309 bool HasVLX = Subtarget.hasVLX();
4310 bool HasEGPR = Subtarget.hasEGPR();
4311 unsigned Opc = 0;
4312 if (X86::GR64RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4313 Opc = X86::MOV64rr;
4314 else if (X86::GR32RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4315 Opc = X86::MOV32rr;
4316 else if (X86::GR16RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4317 Opc = X86::MOV16rr;
4318 else if (X86::GR8RegClass.contains(Reg1: DestReg, Reg2: SrcReg)) {
4319 // Copying to or from a physical H register on x86-64 requires a NOREX
4320 // move. Otherwise use a normal move.
4321 if ((isHReg(Reg: DestReg) || isHReg(Reg: SrcReg)) && Subtarget.is64Bit()) {
4322 Opc = X86::MOV8rr_NOREX;
4323 // Both operands must be encodable without an REX prefix.
4324 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4325 "8-bit H register can not be copied outside GR8_NOREX");
4326 } else
4327 Opc = X86::MOV8rr;
4328 } else if (X86::VR64RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4329 Opc = X86::MMX_MOVQ64rr;
4330 else if (X86::VR128XRegClass.contains(Reg1: DestReg, Reg2: SrcReg)) {
4331 if (HasVLX)
4332 Opc = X86::VMOVAPSZ128rr;
4333 else if (X86::VR128RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4334 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
4335 else {
4336 // If this an extended register and we don't have VLX we need to use a
4337 // 512-bit move.
4338 Opc = X86::VMOVAPSZrr;
4339 const TargetRegisterInfo *TRI = &getRegisterInfo();
4340 DestReg =
4341 TRI->getMatchingSuperReg(Reg: DestReg, SubIdx: X86::sub_xmm, RC: &X86::VR512RegClass);
4342 SrcReg =
4343 TRI->getMatchingSuperReg(Reg: SrcReg, SubIdx: X86::sub_xmm, RC: &X86::VR512RegClass);
4344 }
4345 } else if (X86::VR256XRegClass.contains(Reg1: DestReg, Reg2: SrcReg)) {
4346 if (HasVLX)
4347 Opc = X86::VMOVAPSZ256rr;
4348 else if (X86::VR256RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4349 Opc = X86::VMOVAPSYrr;
4350 else {
4351 // If this an extended register and we don't have VLX we need to use a
4352 // 512-bit move.
4353 Opc = X86::VMOVAPSZrr;
4354 const TargetRegisterInfo *TRI = &getRegisterInfo();
4355 DestReg =
4356 TRI->getMatchingSuperReg(Reg: DestReg, SubIdx: X86::sub_ymm, RC: &X86::VR512RegClass);
4357 SrcReg =
4358 TRI->getMatchingSuperReg(Reg: SrcReg, SubIdx: X86::sub_ymm, RC: &X86::VR512RegClass);
4359 }
4360 } else if (X86::VR512RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4361 Opc = X86::VMOVAPSZrr;
4362 // All KMASK RegClasses hold the same k registers, can be tested against
4363 // anyone.
4364 else if (X86::VK16RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4365 Opc = Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVQkk_EVEX : X86::KMOVQkk)
4366 : (HasEGPR ? X86::KMOVQkk_EVEX : X86::KMOVWkk);
4367
4368 if (!Opc)
4369 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
4370
4371 if (Opc) {
4372 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: get(Opcode: Opc), DestReg)
4373 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc));
4374 return;
4375 }
4376
4377 if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
4378 // FIXME: We use a fatal error here because historically LLVM has tried
4379 // lower some of these physreg copies and we want to ensure we get
4380 // reasonable bug reports if someone encounters a case no other testing
4381 // found. This path should be removed after the LLVM 7 release.
4382 report_fatal_error(reason: "Unable to copy EFLAGS physical register!");
4383 }
4384
4385 LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
4386 << RI.getName(DestReg) << '\n');
4387 report_fatal_error(reason: "Cannot emit physreg copy instruction");
4388}
4389
4390std::optional<DestSourcePair>
4391X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
4392 if (MI.isMoveReg()) {
4393 // FIXME: Dirty hack for apparent invariant that doesn't hold when
4394 // subreg_to_reg is coalesced with ordinary copies, such that the bits that
4395 // were asserted as 0 are now undef.
4396 if (MI.getOperand(i: 0).isUndef() && MI.getOperand(i: 0).getSubReg())
4397 return std::nullopt;
4398
4399 return DestSourcePair{MI.getOperand(i: 0), MI.getOperand(i: 1)};
4400 }
4401 return std::nullopt;
4402}
4403
4404static unsigned getLoadStoreOpcodeForFP16(bool Load, const X86Subtarget &STI) {
4405 if (STI.hasFP16())
4406 return Load ? X86::VMOVSHZrm_alt : X86::VMOVSHZmr;
4407 if (Load)
4408 return X86::MOVSHPrm;
4409 return X86::MOVSHPmr;
4410}
4411
4412static unsigned getLoadStoreRegOpcode(Register Reg,
4413 const TargetRegisterClass *RC,
4414 bool IsStackAligned,
4415 const X86Subtarget &STI, bool Load) {
4416 bool HasAVX = STI.hasAVX();
4417 bool HasAVX512 = STI.hasAVX512();
4418 bool HasVLX = STI.hasVLX();
4419 bool HasEGPR = STI.hasEGPR();
4420
4421 assert(RC != nullptr && "Invalid target register class");
4422 switch (STI.getRegisterInfo()->getSpillSize(RC: *RC)) {
4423 default:
4424 llvm_unreachable("Unknown spill size");
4425 case 1:
4426 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
4427 if (STI.is64Bit())
4428 // Copying to or from a physical H register on x86-64 requires a NOREX
4429 // move. Otherwise use a normal move.
4430 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4431 return Load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4432 return Load ? X86::MOV8rm : X86::MOV8mr;
4433 case 2:
4434 if (X86::VK16RegClass.hasSubClassEq(RC))
4435 return Load ? (HasEGPR ? X86::KMOVWkm_EVEX : X86::KMOVWkm)
4436 : (HasEGPR ? X86::KMOVWmk_EVEX : X86::KMOVWmk);
4437 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4438 return Load ? X86::MOV16rm : X86::MOV16mr;
4439 case 4:
4440 if (X86::GR32RegClass.hasSubClassEq(RC))
4441 return Load ? X86::MOV32rm : X86::MOV32mr;
4442 if (X86::FR32XRegClass.hasSubClassEq(RC))
4443 return Load ? (HasAVX512 ? X86::VMOVSSZrm_alt
4444 : HasAVX ? X86::VMOVSSrm_alt
4445 : X86::MOVSSrm_alt)
4446 : (HasAVX512 ? X86::VMOVSSZmr
4447 : HasAVX ? X86::VMOVSSmr
4448 : X86::MOVSSmr);
4449 if (X86::RFP32RegClass.hasSubClassEq(RC))
4450 return Load ? X86::LD_Fp32m : X86::ST_Fp32m;
4451 if (X86::VK32RegClass.hasSubClassEq(RC)) {
4452 assert(STI.hasBWI() && "KMOVD requires BWI");
4453 return Load ? (HasEGPR ? X86::KMOVDkm_EVEX : X86::KMOVDkm)
4454 : (HasEGPR ? X86::KMOVDmk_EVEX : X86::KMOVDmk);
4455 }
4456 // All of these mask pair classes have the same spill size, the same kind
4457 // of kmov instructions can be used with all of them.
4458 if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
4459 X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
4460 X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
4461 X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
4462 X86::VK16PAIRRegClass.hasSubClassEq(RC))
4463 return Load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
4464 if (X86::FR16RegClass.hasSubClassEq(RC) ||
4465 X86::FR16XRegClass.hasSubClassEq(RC))
4466 return getLoadStoreOpcodeForFP16(Load, STI);
4467 llvm_unreachable("Unknown 4-byte regclass");
4468 case 8:
4469 if (X86::GR64RegClass.hasSubClassEq(RC))
4470 return Load ? X86::MOV64rm : X86::MOV64mr;
4471 if (X86::FR64XRegClass.hasSubClassEq(RC))
4472 return Load ? (HasAVX512 ? X86::VMOVSDZrm_alt
4473 : HasAVX ? X86::VMOVSDrm_alt
4474 : X86::MOVSDrm_alt)
4475 : (HasAVX512 ? X86::VMOVSDZmr
4476 : HasAVX ? X86::VMOVSDmr
4477 : X86::MOVSDmr);
4478 if (X86::VR64RegClass.hasSubClassEq(RC))
4479 return Load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4480 if (X86::RFP64RegClass.hasSubClassEq(RC))
4481 return Load ? X86::LD_Fp64m : X86::ST_Fp64m;
4482 if (X86::VK64RegClass.hasSubClassEq(RC)) {
4483 assert(STI.hasBWI() && "KMOVQ requires BWI");
4484 return Load ? (HasEGPR ? X86::KMOVQkm_EVEX : X86::KMOVQkm)
4485 : (HasEGPR ? X86::KMOVQmk_EVEX : X86::KMOVQmk);
4486 }
4487 llvm_unreachable("Unknown 8-byte regclass");
4488 case 10:
4489 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
4490 return Load ? X86::LD_Fp80m : X86::ST_FpP80m;
4491 case 16: {
4492 if (X86::VR128XRegClass.hasSubClassEq(RC)) {
4493 // If stack is realigned we can use aligned stores.
4494 if (IsStackAligned)
4495 return Load ? (HasVLX ? X86::VMOVAPSZ128rm
4496 : HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX
4497 : HasAVX ? X86::VMOVAPSrm
4498 : X86::MOVAPSrm)
4499 : (HasVLX ? X86::VMOVAPSZ128mr
4500 : HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX
4501 : HasAVX ? X86::VMOVAPSmr
4502 : X86::MOVAPSmr);
4503 else
4504 return Load ? (HasVLX ? X86::VMOVUPSZ128rm
4505 : HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX
4506 : HasAVX ? X86::VMOVUPSrm
4507 : X86::MOVUPSrm)
4508 : (HasVLX ? X86::VMOVUPSZ128mr
4509 : HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX
4510 : HasAVX ? X86::VMOVUPSmr
4511 : X86::MOVUPSmr);
4512 }
4513 llvm_unreachable("Unknown 16-byte regclass");
4514 }
4515 case 32:
4516 assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
4517 // If stack is realigned we can use aligned stores.
4518 if (IsStackAligned)
4519 return Load ? (HasVLX ? X86::VMOVAPSZ256rm
4520 : HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX
4521 : X86::VMOVAPSYrm)
4522 : (HasVLX ? X86::VMOVAPSZ256mr
4523 : HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX
4524 : X86::VMOVAPSYmr);
4525 else
4526 return Load ? (HasVLX ? X86::VMOVUPSZ256rm
4527 : HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX
4528 : X86::VMOVUPSYrm)
4529 : (HasVLX ? X86::VMOVUPSZ256mr
4530 : HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX
4531 : X86::VMOVUPSYmr);
4532 case 64:
4533 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
4534 assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
4535 if (IsStackAligned)
4536 return Load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4537 else
4538 return Load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4539 case 1024:
4540 assert(X86::TILERegClass.hasSubClassEq(RC) && "Unknown 1024-byte regclass");
4541 assert(STI.hasAMXTILE() && "Using 8*1024-bit register requires AMX-TILE");
4542#define GET_EGPR_IF_ENABLED(OPC) (STI.hasEGPR() ? OPC##_EVEX : OPC)
4543 return Load ? GET_EGPR_IF_ENABLED(X86::TILELOADD)
4544 : GET_EGPR_IF_ENABLED(X86::TILESTORED);
4545#undef GET_EGPR_IF_ENABLED
4546 }
4547}
4548
4549std::optional<ExtAddrMode>
4550X86InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI,
4551 const TargetRegisterInfo *TRI) const {
4552 const MCInstrDesc &Desc = MemI.getDesc();
4553 int MemRefBegin = X86II::getMemoryOperandNo(TSFlags: Desc.TSFlags);
4554 if (MemRefBegin < 0)
4555 return std::nullopt;
4556
4557 MemRefBegin += X86II::getOperandBias(Desc);
4558
4559 auto &BaseOp = MemI.getOperand(i: MemRefBegin + X86::AddrBaseReg);
4560 if (!BaseOp.isReg()) // Can be an MO_FrameIndex
4561 return std::nullopt;
4562
4563 const MachineOperand &DispMO = MemI.getOperand(i: MemRefBegin + X86::AddrDisp);
4564 // Displacement can be symbolic
4565 if (!DispMO.isImm())
4566 return std::nullopt;
4567
4568 ExtAddrMode AM;
4569 AM.BaseReg = BaseOp.getReg();
4570 AM.ScaledReg = MemI.getOperand(i: MemRefBegin + X86::AddrIndexReg).getReg();
4571 AM.Scale = MemI.getOperand(i: MemRefBegin + X86::AddrScaleAmt).getImm();
4572 AM.Displacement = DispMO.getImm();
4573 return AM;
4574}
4575
4576bool X86InstrInfo::verifyInstruction(const MachineInstr &MI,
4577 StringRef &ErrInfo) const {
4578 std::optional<ExtAddrMode> AMOrNone = getAddrModeFromMemoryOp(MemI: MI, TRI: nullptr);
4579 if (!AMOrNone)
4580 return true;
4581
4582 ExtAddrMode AM = *AMOrNone;
4583 assert(AM.Form == ExtAddrMode::Formula::Basic);
4584 if (AM.ScaledReg != X86::NoRegister) {
4585 switch (AM.Scale) {
4586 case 1:
4587 case 2:
4588 case 4:
4589 case 8:
4590 break;
4591 default:
4592 ErrInfo = "Scale factor in address must be 1, 2, 4 or 8";
4593 return false;
4594 }
4595 }
4596 if (!isInt<32>(x: AM.Displacement)) {
4597 ErrInfo = "Displacement in address must fit into 32-bit signed "
4598 "integer";
4599 return false;
4600 }
4601
4602 return true;
4603}
4604
4605bool X86InstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
4606 const Register Reg,
4607 int64_t &ImmVal) const {
4608 Register MovReg = Reg;
4609 const MachineInstr *MovMI = &MI;
4610
4611 // Follow use-def for SUBREG_TO_REG to find the real move immediate
4612 // instruction. It is quite common for x86-64.
4613 if (MI.isSubregToReg()) {
4614 // We use following pattern to setup 64b immediate.
4615 // %8:gr32 = MOV32r0 implicit-def dead $eflags
4616 // %6:gr64 = SUBREG_TO_REG killed %8:gr32, %subreg.sub_32bit
4617 unsigned SubIdx = MI.getOperand(i: 2).getImm();
4618 MovReg = MI.getOperand(i: 1).getReg();
4619 if (SubIdx != X86::sub_32bit)
4620 return false;
4621 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
4622 MovMI = MRI.getUniqueVRegDef(Reg: MovReg);
4623 if (!MovMI)
4624 return false;
4625 }
4626
4627 if (MovMI->getOpcode() == X86::MOV32r0 &&
4628 MovMI->getOperand(i: 0).getReg() == MovReg) {
4629 ImmVal = 0;
4630 return true;
4631 }
4632
4633 if (MovMI->getOpcode() != X86::MOV32ri &&
4634 MovMI->getOpcode() != X86::MOV64ri &&
4635 MovMI->getOpcode() != X86::MOV32ri64 && MovMI->getOpcode() != X86::MOV8ri)
4636 return false;
4637 // Mov Src can be a global address.
4638 if (!MovMI->getOperand(i: 1).isImm() || MovMI->getOperand(i: 0).getReg() != MovReg)
4639 return false;
4640 ImmVal = MovMI->getOperand(i: 1).getImm();
4641 return true;
4642}
4643
4644bool X86InstrInfo::preservesZeroValueInReg(
4645 const MachineInstr *MI, const Register NullValueReg,
4646 const TargetRegisterInfo *TRI) const {
4647 if (!MI->modifiesRegister(Reg: NullValueReg, TRI))
4648 return true;
4649 switch (MI->getOpcode()) {
4650 // Shift right/left of a null unto itself is still a null, i.e. rax = shl rax
4651 // X.
4652 case X86::SHR64ri:
4653 case X86::SHR32ri:
4654 case X86::SHL64ri:
4655 case X86::SHL32ri:
4656 assert(MI->getOperand(0).isDef() && MI->getOperand(1).isUse() &&
4657 "expected for shift opcode!");
4658 return MI->getOperand(i: 0).getReg() == NullValueReg &&
4659 MI->getOperand(i: 1).getReg() == NullValueReg;
4660 // Zero extend of a sub-reg of NullValueReg into itself does not change the
4661 // null value.
4662 case X86::MOV32rr:
4663 return llvm::all_of(Range: MI->operands(), P: [&](const MachineOperand &MO) {
4664 return TRI->isSubRegisterEq(RegA: NullValueReg, RegB: MO.getReg());
4665 });
4666 default:
4667 return false;
4668 }
4669 llvm_unreachable("Should be handled above!");
4670}
4671
4672bool X86InstrInfo::getMemOperandsWithOffsetWidth(
4673 const MachineInstr &MemOp, SmallVectorImpl<const MachineOperand *> &BaseOps,
4674 int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
4675 const TargetRegisterInfo *TRI) const {
4676 const MCInstrDesc &Desc = MemOp.getDesc();
4677 int MemRefBegin = X86II::getMemoryOperandNo(TSFlags: Desc.TSFlags);
4678 if (MemRefBegin < 0)
4679 return false;
4680
4681 MemRefBegin += X86II::getOperandBias(Desc);
4682
4683 const MachineOperand *BaseOp =
4684 &MemOp.getOperand(i: MemRefBegin + X86::AddrBaseReg);
4685 if (!BaseOp->isReg()) // Can be an MO_FrameIndex
4686 return false;
4687
4688 if (MemOp.getOperand(i: MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
4689 return false;
4690
4691 if (MemOp.getOperand(i: MemRefBegin + X86::AddrIndexReg).getReg() !=
4692 X86::NoRegister)
4693 return false;
4694
4695 const MachineOperand &DispMO = MemOp.getOperand(i: MemRefBegin + X86::AddrDisp);
4696
4697 // Displacement can be symbolic
4698 if (!DispMO.isImm())
4699 return false;
4700
4701 Offset = DispMO.getImm();
4702
4703 if (!BaseOp->isReg())
4704 return false;
4705
4706 OffsetIsScalable = false;
4707 // FIXME: Relying on memoperands() may not be right thing to do here. Check
4708 // with X86 maintainers, and fix it accordingly. For now, it is ok, since
4709 // there is no use of `Width` for X86 back-end at the moment.
4710 Width = !MemOp.memoperands_empty() ? MemOp.memoperands().front()->getSize()
4711 : LocationSize::precise(Value: 0);
4712 BaseOps.push_back(Elt: BaseOp);
4713 return true;
4714}
4715
4716static unsigned getStoreRegOpcode(Register SrcReg,
4717 const TargetRegisterClass *RC,
4718 bool IsStackAligned,
4719 const X86Subtarget &STI) {
4720 return getLoadStoreRegOpcode(Reg: SrcReg, RC, IsStackAligned, STI, Load: false);
4721}
4722
4723static unsigned getLoadRegOpcode(Register DestReg,
4724 const TargetRegisterClass *RC,
4725 bool IsStackAligned, const X86Subtarget &STI) {
4726 return getLoadStoreRegOpcode(Reg: DestReg, RC, IsStackAligned, STI, Load: true);
4727}
4728
4729static bool isAMXOpcode(unsigned Opc) {
4730 switch (Opc) {
4731 default:
4732 return false;
4733 case X86::TILELOADD:
4734 case X86::TILESTORED:
4735 case X86::TILELOADD_EVEX:
4736 case X86::TILESTORED_EVEX:
4737 return true;
4738 }
4739}
4740
4741void X86InstrInfo::loadStoreTileReg(MachineBasicBlock &MBB,
4742 MachineBasicBlock::iterator MI,
4743 unsigned Opc, Register Reg, int FrameIdx,
4744 bool isKill) const {
4745 switch (Opc) {
4746 default:
4747 llvm_unreachable("Unexpected special opcode!");
4748 case X86::TILESTORED:
4749 case X86::TILESTORED_EVEX: {
4750 // tilestored %tmm, (%sp, %idx)
4751 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
4752 Register VirtReg = RegInfo.createVirtualRegister(RegClass: &X86::GR64_NOSPRegClass);
4753 BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: get(Opcode: X86::MOV64ri), DestReg: VirtReg).addImm(Val: 64);
4754 MachineInstr *NewMI =
4755 addFrameReference(MIB: BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: get(Opcode: Opc)), FI: FrameIdx)
4756 .addReg(RegNo: Reg, Flags: getKillRegState(B: isKill));
4757 MachineOperand &MO = NewMI->getOperand(i: X86::AddrIndexReg);
4758 MO.setReg(VirtReg);
4759 MO.setIsKill(true);
4760 break;
4761 }
4762 case X86::TILELOADD:
4763 case X86::TILELOADD_EVEX: {
4764 // tileloadd (%sp, %idx), %tmm
4765 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
4766 Register VirtReg = RegInfo.createVirtualRegister(RegClass: &X86::GR64_NOSPRegClass);
4767 BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: get(Opcode: X86::MOV64ri), DestReg: VirtReg).addImm(Val: 64);
4768 MachineInstr *NewMI = addFrameReference(
4769 MIB: BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: get(Opcode: Opc), DestReg: Reg), FI: FrameIdx);
4770 MachineOperand &MO = NewMI->getOperand(i: 1 + X86::AddrIndexReg);
4771 MO.setReg(VirtReg);
4772 MO.setIsKill(true);
4773 break;
4774 }
4775 }
4776}
4777
4778void X86InstrInfo::storeRegToStackSlot(
4779 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
4780 bool isKill, int FrameIdx, const TargetRegisterClass *RC,
4781
4782 Register VReg, MachineInstr::MIFlag Flags) const {
4783 const MachineFunction &MF = *MBB.getParent();
4784 const MachineFrameInfo &MFI = MF.getFrameInfo();
4785 assert(MFI.getObjectSize(FrameIdx) >= RI.getSpillSize(*RC) &&
4786 "Stack slot too small for store");
4787
4788 unsigned Alignment = std::max<uint32_t>(a: RI.getSpillSize(RC: *RC), b: 16);
4789 bool isAligned =
4790 (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
4791 (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(ObjectIdx: FrameIdx));
4792
4793 unsigned Opc = getStoreRegOpcode(SrcReg, RC, IsStackAligned: isAligned, STI: Subtarget);
4794 if (isAMXOpcode(Opc))
4795 loadStoreTileReg(MBB, MI, Opc, Reg: SrcReg, FrameIdx, isKill);
4796 else
4797 addFrameReference(MIB: BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: get(Opcode: Opc)), FI: FrameIdx)
4798 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill))
4799 .setMIFlag(Flags);
4800}
4801
4802void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
4803 MachineBasicBlock::iterator MI,
4804 Register DestReg, int FrameIdx,
4805 const TargetRegisterClass *RC,
4806 Register VReg, unsigned SubReg,
4807 MachineInstr::MIFlag Flags) const {
4808 const MachineFunction &MF = *MBB.getParent();
4809 const MachineFrameInfo &MFI = MF.getFrameInfo();
4810 assert(MFI.getObjectSize(FrameIdx) >= RI.getSpillSize(*RC) &&
4811 "Load size exceeds stack slot");
4812 unsigned Alignment = std::max<uint32_t>(a: RI.getSpillSize(RC: *RC), b: 16);
4813 bool isAligned =
4814 (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
4815 (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(ObjectIdx: FrameIdx));
4816
4817 unsigned Opc = getLoadRegOpcode(DestReg, RC, IsStackAligned: isAligned, STI: Subtarget);
4818 if (isAMXOpcode(Opc))
4819 loadStoreTileReg(MBB, MI, Opc, Reg: DestReg, FrameIdx);
4820 else
4821 addFrameReference(MIB: BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: get(Opcode: Opc), DestReg), FI: FrameIdx)
4822 .setMIFlag(Flags);
4823}
4824
4825bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
4826 Register &SrcReg2, int64_t &CmpMask,
4827 int64_t &CmpValue) const {
4828 switch (MI.getOpcode()) {
4829 default:
4830 break;
4831 case X86::CMP64ri32:
4832 case X86::CMP32ri:
4833 case X86::CMP16ri:
4834 case X86::CMP8ri:
4835 SrcReg = MI.getOperand(i: 0).getReg();
4836 SrcReg2 = 0;
4837 if (MI.getOperand(i: 1).isImm()) {
4838 CmpMask = ~0;
4839 CmpValue = MI.getOperand(i: 1).getImm();
4840 } else {
4841 CmpMask = CmpValue = 0;
4842 }
4843 return true;
4844 // A SUB can be used to perform comparison.
4845 CASE_ND(SUB64rm)
4846 CASE_ND(SUB32rm)
4847 CASE_ND(SUB16rm)
4848 CASE_ND(SUB8rm)
4849 SrcReg = MI.getOperand(i: 1).getReg();
4850 SrcReg2 = 0;
4851 CmpMask = 0;
4852 CmpValue = 0;
4853 return true;
4854 CASE_ND(SUB64rr)
4855 CASE_ND(SUB32rr)
4856 CASE_ND(SUB16rr)
4857 CASE_ND(SUB8rr)
4858 SrcReg = MI.getOperand(i: 1).getReg();
4859 SrcReg2 = MI.getOperand(i: 2).getReg();
4860 CmpMask = 0;
4861 CmpValue = 0;
4862 return true;
4863 CASE_ND(SUB64ri32)
4864 CASE_ND(SUB32ri)
4865 CASE_ND(SUB16ri)
4866 CASE_ND(SUB8ri)
4867 SrcReg = MI.getOperand(i: 1).getReg();
4868 SrcReg2 = 0;
4869 if (MI.getOperand(i: 2).isImm()) {
4870 CmpMask = ~0;
4871 CmpValue = MI.getOperand(i: 2).getImm();
4872 } else {
4873 CmpMask = CmpValue = 0;
4874 }
4875 return true;
4876 case X86::CMP64rr:
4877 case X86::CMP32rr:
4878 case X86::CMP16rr:
4879 case X86::CMP8rr:
4880 SrcReg = MI.getOperand(i: 0).getReg();
4881 SrcReg2 = MI.getOperand(i: 1).getReg();
4882 CmpMask = 0;
4883 CmpValue = 0;
4884 return true;
4885 case X86::TEST8rr:
4886 case X86::TEST16rr:
4887 case X86::TEST32rr:
4888 case X86::TEST64rr:
4889 SrcReg = MI.getOperand(i: 0).getReg();
4890 if (MI.getOperand(i: 1).getReg() != SrcReg)
4891 return false;
4892 // Compare against zero.
4893 SrcReg2 = 0;
4894 CmpMask = ~0;
4895 CmpValue = 0;
4896 return true;
4897 case X86::TEST64ri32:
4898 case X86::TEST32ri:
4899 case X86::TEST16ri:
4900 case X86::TEST8ri:
4901 SrcReg = MI.getOperand(i: 0).getReg();
4902 SrcReg2 = 0;
4903 // Force identical compare.
4904 CmpMask = 0;
4905 CmpValue = 0;
4906 return true;
4907 }
4908 return false;
4909}
4910
4911bool X86InstrInfo::isRedundantFlagInstr(const MachineInstr &FlagI,
4912 Register SrcReg, Register SrcReg2,
4913 int64_t ImmMask, int64_t ImmValue,
4914 const MachineInstr &OI, bool *IsSwapped,
4915 int64_t *ImmDelta) const {
4916 switch (OI.getOpcode()) {
4917 case X86::CMP64rr:
4918 case X86::CMP32rr:
4919 case X86::CMP16rr:
4920 case X86::CMP8rr:
4921 CASE_ND(SUB64rr)
4922 CASE_ND(SUB32rr)
4923 CASE_ND(SUB16rr)
4924 CASE_ND(SUB8rr) {
4925 Register OISrcReg;
4926 Register OISrcReg2;
4927 int64_t OIMask;
4928 int64_t OIValue;
4929 if (!analyzeCompare(MI: OI, SrcReg&: OISrcReg, SrcReg2&: OISrcReg2, CmpMask&: OIMask, CmpValue&: OIValue) ||
4930 OIMask != ImmMask || OIValue != ImmValue)
4931 return false;
4932 if (SrcReg == OISrcReg && SrcReg2 == OISrcReg2) {
4933 *IsSwapped = false;
4934 return true;
4935 }
4936 if (SrcReg == OISrcReg2 && SrcReg2 == OISrcReg) {
4937 *IsSwapped = true;
4938 return true;
4939 }
4940 return false;
4941 }
4942 case X86::CMP64ri32:
4943 case X86::CMP32ri:
4944 case X86::CMP16ri:
4945 case X86::CMP8ri:
4946 case X86::TEST64ri32:
4947 case X86::TEST32ri:
4948 case X86::TEST16ri:
4949 case X86::TEST8ri:
4950 CASE_ND(SUB64ri32)
4951 CASE_ND(SUB32ri)
4952 CASE_ND(SUB16ri)
4953 CASE_ND(SUB8ri)
4954 case X86::TEST64rr:
4955 case X86::TEST32rr:
4956 case X86::TEST16rr:
4957 case X86::TEST8rr: {
4958 if (ImmMask != 0) {
4959 Register OISrcReg;
4960 Register OISrcReg2;
4961 int64_t OIMask;
4962 int64_t OIValue;
4963 if (analyzeCompare(MI: OI, SrcReg&: OISrcReg, SrcReg2&: OISrcReg2, CmpMask&: OIMask, CmpValue&: OIValue) &&
4964 SrcReg == OISrcReg && ImmMask == OIMask) {
4965 if (OIValue == ImmValue) {
4966 *ImmDelta = 0;
4967 return true;
4968 } else if (static_cast<uint64_t>(ImmValue) ==
4969 static_cast<uint64_t>(OIValue) - 1) {
4970 *ImmDelta = -1;
4971 return true;
4972 } else if (static_cast<uint64_t>(ImmValue) ==
4973 static_cast<uint64_t>(OIValue) + 1) {
4974 *ImmDelta = 1;
4975 return true;
4976 } else {
4977 return false;
4978 }
4979 }
4980 }
4981 return FlagI.isIdenticalTo(Other: OI);
4982 }
4983 default:
4984 return false;
4985 }
4986}
4987
4988/// Check whether the definition can be converted
4989/// to remove a comparison against zero.
4990inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag,
4991 bool &ClearsOverflowFlag) {
4992 NoSignFlag = false;
4993 ClearsOverflowFlag = false;
4994
4995 // "ELF Handling for Thread-Local Storage" specifies that x86-64 GOTTPOFF, and
4996 // i386 GOTNTPOFF/INDNTPOFF relocations can convert an ADD to a LEA during
4997 // Initial Exec to Local Exec relaxation. In these cases, we must not depend
4998 // on the EFLAGS modification of ADD actually happening in the final binary.
4999 if (MI.getOpcode() == X86::ADD64rm || MI.getOpcode() == X86::ADD32rm) {
5000 unsigned Flags = MI.getOperand(i: 5).getTargetFlags();
5001 if (Flags == X86II::MO_GOTTPOFF || Flags == X86II::MO_INDNTPOFF ||
5002 Flags == X86II::MO_GOTNTPOFF)
5003 return false;
5004 }
5005
5006 switch (MI.getOpcode()) {
5007 default:
5008 return false;
5009
5010 // The shift instructions only modify ZF if their shift count is non-zero.
5011 // N.B.: The processor truncates the shift count depending on the encoding.
5012 CASE_ND(SAR8ri)
5013 CASE_ND(SAR16ri)
5014 CASE_ND(SAR32ri)
5015 CASE_ND(SAR64ri)
5016 CASE_ND(SHR8ri)
5017 CASE_ND(SHR16ri)
5018 CASE_ND(SHR32ri)
5019 CASE_ND(SHR64ri)
5020 return getTruncatedShiftCount(MI, ShiftAmtOperandIdx: 2) != 0;
5021
5022 // Some left shift instructions can be turned into LEA instructions but only
5023 // if their flags aren't used. Avoid transforming such instructions.
5024 CASE_ND(SHL8ri)
5025 CASE_ND(SHL16ri)
5026 CASE_ND(SHL32ri)
5027 CASE_ND(SHL64ri) {
5028 unsigned ShAmt = getTruncatedShiftCount(MI, ShiftAmtOperandIdx: 2);
5029 if (isTruncatedShiftCountForLEA(ShAmt))
5030 return false;
5031 return ShAmt != 0;
5032 }
5033
5034 CASE_ND(SHRD16rri8)
5035 CASE_ND(SHRD32rri8)
5036 CASE_ND(SHRD64rri8)
5037 CASE_ND(SHLD16rri8)
5038 CASE_ND(SHLD32rri8)
5039 CASE_ND(SHLD64rri8)
5040 return getTruncatedShiftCount(MI, ShiftAmtOperandIdx: 3) != 0;
5041
5042 CASE_ND(SUB64ri32)
5043 CASE_ND(SUB32ri)
5044 CASE_ND(SUB16ri)
5045 CASE_ND(SUB8ri)
5046 CASE_ND(SUB64rr)
5047 CASE_ND(SUB32rr)
5048 CASE_ND(SUB16rr)
5049 CASE_ND(SUB8rr)
5050 CASE_ND(SUB64rm)
5051 CASE_ND(SUB32rm)
5052 CASE_ND(SUB16rm)
5053 CASE_ND(SUB8rm)
5054 CASE_ND(DEC64r)
5055 CASE_ND(DEC32r)
5056 CASE_ND(DEC16r)
5057 CASE_ND(DEC8r)
5058 CASE_ND(ADD64ri32)
5059 CASE_ND(ADD32ri)
5060 CASE_ND(ADD16ri)
5061 CASE_ND(ADD8ri)
5062 CASE_ND(ADD64rr)
5063 CASE_ND(ADD32rr)
5064 CASE_ND(ADD16rr)
5065 CASE_ND(ADD8rr)
5066 CASE_ND(ADD64rm)
5067 CASE_ND(ADD32rm)
5068 CASE_ND(ADD16rm)
5069 CASE_ND(ADD8rm)
5070 CASE_ND(INC64r)
5071 CASE_ND(INC32r)
5072 CASE_ND(INC16r)
5073 CASE_ND(INC8r)
5074 CASE_ND(ADC64ri32)
5075 CASE_ND(ADC32ri)
5076 CASE_ND(ADC16ri)
5077 CASE_ND(ADC8ri)
5078 CASE_ND(ADC64rr)
5079 CASE_ND(ADC32rr)
5080 CASE_ND(ADC16rr)
5081 CASE_ND(ADC8rr)
5082 CASE_ND(ADC64rm)
5083 CASE_ND(ADC32rm)
5084 CASE_ND(ADC16rm)
5085 CASE_ND(ADC8rm)
5086 CASE_ND(SBB64ri32)
5087 CASE_ND(SBB32ri)
5088 CASE_ND(SBB16ri)
5089 CASE_ND(SBB8ri)
5090 CASE_ND(SBB64rr)
5091 CASE_ND(SBB32rr)
5092 CASE_ND(SBB16rr)
5093 CASE_ND(SBB8rr)
5094 CASE_ND(SBB64rm)
5095 CASE_ND(SBB32rm)
5096 CASE_ND(SBB16rm)
5097 CASE_ND(SBB8rm)
5098 CASE_ND(NEG8r)
5099 CASE_ND(NEG16r)
5100 CASE_ND(NEG32r)
5101 CASE_ND(NEG64r)
5102 case X86::LZCNT16rr:
5103 case X86::LZCNT16rm:
5104 case X86::LZCNT32rr:
5105 case X86::LZCNT32rm:
5106 case X86::LZCNT64rr:
5107 case X86::LZCNT64rm:
5108 case X86::POPCNT16rr:
5109 case X86::POPCNT16rm:
5110 case X86::POPCNT32rr:
5111 case X86::POPCNT32rm:
5112 case X86::POPCNT64rr:
5113 case X86::POPCNT64rm:
5114 case X86::TZCNT16rr:
5115 case X86::TZCNT16rm:
5116 case X86::TZCNT32rr:
5117 case X86::TZCNT32rm:
5118 case X86::TZCNT64rr:
5119 case X86::TZCNT64rm:
5120 return true;
5121 CASE_ND(AND64ri32)
5122 CASE_ND(AND32ri)
5123 CASE_ND(AND16ri)
5124 CASE_ND(AND8ri)
5125 CASE_ND(AND64rr)
5126 CASE_ND(AND32rr)
5127 CASE_ND(AND16rr)
5128 CASE_ND(AND8rr)
5129 CASE_ND(AND64rm)
5130 CASE_ND(AND32rm)
5131 CASE_ND(AND16rm)
5132 CASE_ND(AND8rm)
5133 CASE_ND(XOR64ri32)
5134 CASE_ND(XOR32ri)
5135 CASE_ND(XOR16ri)
5136 CASE_ND(XOR8ri)
5137 CASE_ND(XOR64rr)
5138 CASE_ND(XOR32rr)
5139 CASE_ND(XOR16rr)
5140 CASE_ND(XOR8rr)
5141 CASE_ND(XOR64rm)
5142 CASE_ND(XOR32rm)
5143 CASE_ND(XOR16rm)
5144 CASE_ND(XOR8rm)
5145 CASE_ND(OR64ri32)
5146 CASE_ND(OR32ri)
5147 CASE_ND(OR16ri)
5148 CASE_ND(OR8ri)
5149 CASE_ND(OR64rr)
5150 CASE_ND(OR32rr)
5151 CASE_ND(OR16rr)
5152 CASE_ND(OR8rr)
5153 CASE_ND(OR64rm)
5154 CASE_ND(OR32rm)
5155 CASE_ND(OR16rm)
5156 CASE_ND(OR8rm)
5157 case X86::ANDN32rr:
5158 case X86::ANDN32rm:
5159 case X86::ANDN64rr:
5160 case X86::ANDN64rm:
5161 case X86::BLSI32rr:
5162 case X86::BLSI32rm:
5163 case X86::BLSI64rr:
5164 case X86::BLSI64rm:
5165 case X86::BLSMSK32rr:
5166 case X86::BLSMSK32rm:
5167 case X86::BLSMSK64rr:
5168 case X86::BLSMSK64rm:
5169 case X86::BLSR32rr:
5170 case X86::BLSR32rm:
5171 case X86::BLSR64rr:
5172 case X86::BLSR64rm:
5173 case X86::BLCFILL32rr:
5174 case X86::BLCFILL32rm:
5175 case X86::BLCFILL64rr:
5176 case X86::BLCFILL64rm:
5177 case X86::BLCI32rr:
5178 case X86::BLCI32rm:
5179 case X86::BLCI64rr:
5180 case X86::BLCI64rm:
5181 case X86::BLCIC32rr:
5182 case X86::BLCIC32rm:
5183 case X86::BLCIC64rr:
5184 case X86::BLCIC64rm:
5185 case X86::BLCMSK32rr:
5186 case X86::BLCMSK32rm:
5187 case X86::BLCMSK64rr:
5188 case X86::BLCMSK64rm:
5189 case X86::BLCS32rr:
5190 case X86::BLCS32rm:
5191 case X86::BLCS64rr:
5192 case X86::BLCS64rm:
5193 case X86::BLSFILL32rr:
5194 case X86::BLSFILL32rm:
5195 case X86::BLSFILL64rr:
5196 case X86::BLSFILL64rm:
5197 case X86::BLSIC32rr:
5198 case X86::BLSIC32rm:
5199 case X86::BLSIC64rr:
5200 case X86::BLSIC64rm:
5201 case X86::BZHI32rr:
5202 case X86::BZHI32rm:
5203 case X86::BZHI64rr:
5204 case X86::BZHI64rm:
5205 case X86::T1MSKC32rr:
5206 case X86::T1MSKC32rm:
5207 case X86::T1MSKC64rr:
5208 case X86::T1MSKC64rm:
5209 case X86::TZMSK32rr:
5210 case X86::TZMSK32rm:
5211 case X86::TZMSK64rr:
5212 case X86::TZMSK64rm:
5213 // These instructions clear the overflow flag just like TEST.
5214 // FIXME: These are not the only instructions in this switch that clear the
5215 // overflow flag.
5216 ClearsOverflowFlag = true;
5217 return true;
5218 case X86::BEXTR32rr:
5219 case X86::BEXTR64rr:
5220 case X86::BEXTR32rm:
5221 case X86::BEXTR64rm:
5222 case X86::BEXTRI32ri:
5223 case X86::BEXTRI32mi:
5224 case X86::BEXTRI64ri:
5225 case X86::BEXTRI64mi:
5226 // BEXTR doesn't update the sign flag so we can't use it. It does clear
5227 // the overflow flag, but that's not useful without the sign flag.
5228 NoSignFlag = true;
5229 return true;
5230 }
5231}
5232
5233/// Check whether the use can be converted to remove a comparison against zero.
5234/// Returns the EFLAGS condition and the operand that we are comparing against zero.
5235static std::pair<X86::CondCode, unsigned> isUseDefConvertible(const MachineInstr &MI) {
5236 switch (MI.getOpcode()) {
5237 default:
5238 return std::make_pair(x: X86::COND_INVALID, y: ~0U);
5239 CASE_ND(NEG8r)
5240 CASE_ND(NEG16r)
5241 CASE_ND(NEG32r)
5242 CASE_ND(NEG64r)
5243 return std::make_pair(x: X86::COND_AE, y: 1U);
5244 case X86::LZCNT16rr:
5245 case X86::LZCNT32rr:
5246 case X86::LZCNT64rr:
5247 return std::make_pair(x: X86::COND_B, y: 1U);
5248 case X86::POPCNT16rr:
5249 case X86::POPCNT32rr:
5250 case X86::POPCNT64rr:
5251 return std::make_pair(x: X86::COND_E, y: 1U);
5252 case X86::TZCNT16rr:
5253 case X86::TZCNT32rr:
5254 case X86::TZCNT64rr:
5255 return std::make_pair(x: X86::COND_B, y: 1U);
5256 case X86::BSF16rr:
5257 case X86::BSF32rr:
5258 case X86::BSF64rr:
5259 case X86::BSR16rr:
5260 case X86::BSR32rr:
5261 case X86::BSR64rr:
5262 return std::make_pair(x: X86::COND_E, y: 2U);
5263 case X86::BLSI32rr:
5264 case X86::BLSI64rr:
5265 return std::make_pair(x: X86::COND_AE, y: 1U);
5266 case X86::BLSR32rr:
5267 case X86::BLSR64rr:
5268 case X86::BLSMSK32rr:
5269 case X86::BLSMSK64rr:
5270 return std::make_pair(x: X86::COND_B, y: 1U);
5271 // TODO: TBM instructions.
5272 }
5273}
5274
5275/// Check if there exists an earlier instruction that
5276/// operates on the same source operands and sets flags in the same way as
5277/// Compare; remove Compare if possible.
5278bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
5279 Register SrcReg2, int64_t CmpMask,
5280 int64_t CmpValue,
5281 const MachineRegisterInfo *MRI) const {
5282 // Check whether we can replace SUB with CMP.
5283 switch (CmpInstr.getOpcode()) {
5284 default:
5285 break;
5286 CASE_ND(SUB64ri32)
5287 CASE_ND(SUB32ri)
5288 CASE_ND(SUB16ri)
5289 CASE_ND(SUB8ri)
5290 CASE_ND(SUB64rm)
5291 CASE_ND(SUB32rm)
5292 CASE_ND(SUB16rm)
5293 CASE_ND(SUB8rm)
5294 CASE_ND(SUB64rr)
5295 CASE_ND(SUB32rr)
5296 CASE_ND(SUB16rr)
5297 CASE_ND(SUB8rr) {
5298 if (!MRI->use_nodbg_empty(RegNo: CmpInstr.getOperand(i: 0).getReg()))
5299 return false;
5300 // There is no use of the destination register, we can replace SUB with CMP.
5301 unsigned NewOpcode = 0;
5302#define FROM_TO(A, B) \
5303 CASE_ND(A) NewOpcode = X86::B; \
5304 break;
5305 switch (CmpInstr.getOpcode()) {
5306 default:
5307 llvm_unreachable("Unreachable!");
5308 FROM_TO(SUB64rm, CMP64rm)
5309 FROM_TO(SUB32rm, CMP32rm)
5310 FROM_TO(SUB16rm, CMP16rm)
5311 FROM_TO(SUB8rm, CMP8rm)
5312 FROM_TO(SUB64rr, CMP64rr)
5313 FROM_TO(SUB32rr, CMP32rr)
5314 FROM_TO(SUB16rr, CMP16rr)
5315 FROM_TO(SUB8rr, CMP8rr)
5316 FROM_TO(SUB64ri32, CMP64ri32)
5317 FROM_TO(SUB32ri, CMP32ri)
5318 FROM_TO(SUB16ri, CMP16ri)
5319 FROM_TO(SUB8ri, CMP8ri)
5320 }
5321#undef FROM_TO
5322 CmpInstr.setDesc(get(Opcode: NewOpcode));
5323 CmpInstr.removeOperand(OpNo: 0);
5324 // Mutating this instruction invalidates any debug data associated with it.
5325 CmpInstr.dropDebugNumber();
5326 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
5327 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5328 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5329 return false;
5330 }
5331 }
5332
5333 // The following code tries to remove the comparison by re-using EFLAGS
5334 // from earlier instructions.
5335
5336 bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
5337
5338 // Transformation currently requires SSA values.
5339 if (SrcReg2.isPhysical())
5340 return false;
5341 MachineInstr *SrcRegDef = MRI->getVRegDef(Reg: SrcReg);
5342 assert(SrcRegDef && "Must have a definition (SSA)");
5343
5344 MachineInstr *MI = nullptr;
5345 MachineInstr *Sub = nullptr;
5346 MachineInstr *Movr0Inst = nullptr;
5347 SmallVector<std::pair<MachineInstr *, unsigned>, 4> InstsToUpdate;
5348 bool NoSignFlag = false;
5349 bool ClearsOverflowFlag = false;
5350 bool ShouldUpdateCC = false;
5351 bool IsSwapped = false;
5352 bool HasNF = Subtarget.hasNF();
5353 unsigned OpNo = 0;
5354 X86::CondCode NewCC = X86::COND_INVALID;
5355 int64_t ImmDelta = 0;
5356
5357 // Search backward from CmpInstr for the next instruction defining EFLAGS.
5358 const TargetRegisterInfo *TRI = &getRegisterInfo();
5359 MachineBasicBlock &CmpMBB = *CmpInstr.getParent();
5360 MachineBasicBlock::reverse_iterator From =
5361 std::next(x: MachineBasicBlock::reverse_iterator(CmpInstr));
5362 for (MachineBasicBlock *MBB = &CmpMBB;;) {
5363 for (MachineInstr &Inst : make_range(x: From, y: MBB->rend())) {
5364 // Try to use EFLAGS from the instruction defining %SrcReg. Example:
5365 // %eax = addl ...
5366 // ... // EFLAGS not changed
5367 // testl %eax, %eax // <-- can be removed
5368 if (&Inst == SrcRegDef) {
5369 if (IsCmpZero &&
5370 isDefConvertible(MI: Inst, NoSignFlag, ClearsOverflowFlag)) {
5371 MI = &Inst;
5372 break;
5373 }
5374
5375 // Look back for the following pattern, in which case the
5376 // test16rr/test64rr instruction could be erased.
5377 //
5378 // Example for test16rr:
5379 // %reg = and32ri %in_reg, 5
5380 // ... // EFLAGS not changed.
5381 // %src_reg = copy %reg.sub_16bit:gr32
5382 // test16rr %src_reg, %src_reg, implicit-def $eflags
5383 // Example for test64rr:
5384 // %reg = and32ri %in_reg, 5
5385 // ... // EFLAGS not changed.
5386 // %src_reg = subreg_to_reg %reg, %subreg.sub_index
5387 // test64rr %src_reg, %src_reg, implicit-def $eflags
5388 MachineInstr *AndInstr = nullptr;
5389 if (IsCmpZero &&
5390 findRedundantFlagInstr(CmpInstr, CmpValDefInstr&: Inst, MRI, AndInstr: &AndInstr, TRI,
5391 ST: Subtarget, NoSignFlag, ClearsOverflowFlag)) {
5392 assert(AndInstr != nullptr && X86::isAND(AndInstr->getOpcode()));
5393 MI = AndInstr;
5394 break;
5395 }
5396 // Cannot find other candidates before definition of SrcReg.
5397 return false;
5398 }
5399
5400 if (Inst.modifiesRegister(Reg: X86::EFLAGS, TRI)) {
5401 // Try to use EFLAGS produced by an instruction reading %SrcReg.
5402 // Example:
5403 // %eax = ...
5404 // ...
5405 // popcntl %eax
5406 // ... // EFLAGS not changed
5407 // testl %eax, %eax // <-- can be removed
5408 if (IsCmpZero) {
5409 std::tie(args&: NewCC, args&: OpNo) = isUseDefConvertible(MI: Inst);
5410 if (NewCC != X86::COND_INVALID && Inst.getOperand(i: OpNo).isReg() &&
5411 Inst.getOperand(i: OpNo).getReg() == SrcReg) {
5412 ShouldUpdateCC = true;
5413 MI = &Inst;
5414 break;
5415 }
5416 }
5417
5418 // Try to use EFLAGS from an instruction with similar flag results.
5419 // Example:
5420 // sub x, y or cmp x, y
5421 // ... // EFLAGS not changed
5422 // cmp x, y // <-- can be removed
5423 if (isRedundantFlagInstr(FlagI: CmpInstr, SrcReg, SrcReg2, ImmMask: CmpMask, ImmValue: CmpValue,
5424 OI: Inst, IsSwapped: &IsSwapped, ImmDelta: &ImmDelta)) {
5425 Sub = &Inst;
5426 break;
5427 }
5428
5429 // MOV32r0 is implemented with xor which clobbers condition code. It is
5430 // safe to move up, if the definition to EFLAGS is dead and earlier
5431 // instructions do not read or write EFLAGS.
5432 if (!Movr0Inst && Inst.getOpcode() == X86::MOV32r0 &&
5433 Inst.registerDefIsDead(Reg: X86::EFLAGS, TRI)) {
5434 Movr0Inst = &Inst;
5435 continue;
5436 }
5437
5438 // For the instructions are ADDrm/ADDmr with relocation, we'll skip the
5439 // optimization for replacing non-NF with NF. This is to keep backward
5440 // compatiblity with old version of linkers without APX relocation type
5441 // support on Linux OS.
5442 bool IsWithReloc = X86EnableAPXForRelocation
5443 ? false
5444 : isAddMemInstrWithRelocation(MI: Inst);
5445
5446 // Try to replace non-NF with NF instructions.
5447 if (HasNF && Inst.registerDefIsDead(Reg: X86::EFLAGS, TRI) && !IsWithReloc) {
5448 unsigned NewOp = X86::getNFVariant(Opc: Inst.getOpcode());
5449 if (!NewOp)
5450 return false;
5451
5452 InstsToUpdate.push_back(Elt: std::make_pair(x: &Inst, y&: NewOp));
5453 continue;
5454 }
5455
5456 // Cannot do anything for any other EFLAG changes.
5457 return false;
5458 }
5459 }
5460
5461 if (MI || Sub)
5462 break;
5463
5464 // Reached begin of basic block. Continue in predecessor if there is
5465 // exactly one.
5466 if (MBB->pred_size() != 1)
5467 return false;
5468 MBB = *MBB->pred_begin();
5469 From = MBB->rbegin();
5470 }
5471
5472 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
5473 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
5474 // If we are done with the basic block, we need to check whether EFLAGS is
5475 // live-out.
5476 bool FlagsMayLiveOut = true;
5477 SmallVector<std::pair<MachineInstr *, X86::CondCode>, 4> OpsToUpdate;
5478 MachineBasicBlock::iterator AfterCmpInstr =
5479 std::next(x: MachineBasicBlock::iterator(CmpInstr));
5480 for (MachineInstr &Instr : make_range(x: AfterCmpInstr, y: CmpMBB.end())) {
5481 bool ModifyEFLAGS = Instr.modifiesRegister(Reg: X86::EFLAGS, TRI);
5482 bool UseEFLAGS = Instr.readsRegister(Reg: X86::EFLAGS, TRI);
5483 // We should check the usage if this instruction uses and updates EFLAGS.
5484 if (!UseEFLAGS && ModifyEFLAGS) {
5485 // It is safe to remove CmpInstr if EFLAGS is updated again.
5486 FlagsMayLiveOut = false;
5487 break;
5488 }
5489 if (!UseEFLAGS && !ModifyEFLAGS)
5490 continue;
5491
5492 // EFLAGS is used by this instruction.
5493 X86::CondCode OldCC = X86::getCondFromMI(MI: Instr);
5494 if ((MI || IsSwapped || ImmDelta != 0) && OldCC == X86::COND_INVALID)
5495 return false;
5496
5497 X86::CondCode ReplacementCC = X86::COND_INVALID;
5498 if (MI) {
5499 switch (OldCC) {
5500 default:
5501 break;
5502 case X86::COND_A:
5503 case X86::COND_AE:
5504 case X86::COND_B:
5505 case X86::COND_BE:
5506 // CF is used, we can't perform this optimization.
5507 return false;
5508 case X86::COND_G:
5509 case X86::COND_GE:
5510 case X86::COND_L:
5511 case X86::COND_LE:
5512 // If SF is used, but the instruction doesn't update the SF, then we
5513 // can't do the optimization.
5514 if (NoSignFlag)
5515 return false;
5516 [[fallthrough]];
5517 case X86::COND_O:
5518 case X86::COND_NO:
5519 // If OF is used, the instruction needs to clear it like CmpZero does.
5520 if (!ClearsOverflowFlag)
5521 return false;
5522 break;
5523 case X86::COND_S:
5524 case X86::COND_NS:
5525 // If SF is used, but the instruction doesn't update the SF, then we
5526 // can't do the optimization.
5527 if (NoSignFlag)
5528 return false;
5529 break;
5530 }
5531
5532 // If we're updating the condition code check if we have to reverse the
5533 // condition.
5534 if (ShouldUpdateCC)
5535 switch (OldCC) {
5536 default:
5537 return false;
5538 case X86::COND_E:
5539 ReplacementCC = NewCC;
5540 break;
5541 case X86::COND_NE:
5542 ReplacementCC = GetOppositeBranchCondition(CC: NewCC);
5543 break;
5544 }
5545 } else if (IsSwapped) {
5546 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
5547 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
5548 // We swap the condition code and synthesize the new opcode.
5549 ReplacementCC = getSwappedCondition(CC: OldCC);
5550 if (ReplacementCC == X86::COND_INVALID)
5551 return false;
5552 ShouldUpdateCC = true;
5553 } else if (ImmDelta != 0) {
5554 unsigned BitWidth = RI.getRegSizeInBits(RC: *MRI->getRegClass(Reg: SrcReg));
5555 // Shift amount for min/max constants to adjust for 8/16/32 instruction
5556 // sizes.
5557 switch (OldCC) {
5558 case X86::COND_L: // x <s (C + 1) --> x <=s C
5559 if (ImmDelta != 1 || APInt::getSignedMinValue(numBits: BitWidth) == CmpValue)
5560 return false;
5561 ReplacementCC = X86::COND_LE;
5562 break;
5563 case X86::COND_B: // x <u (C + 1) --> x <=u C
5564 if (ImmDelta != 1 || CmpValue == 0)
5565 return false;
5566 ReplacementCC = X86::COND_BE;
5567 break;
5568 case X86::COND_GE: // x >=s (C + 1) --> x >s C
5569 if (ImmDelta != 1 || APInt::getSignedMinValue(numBits: BitWidth) == CmpValue)
5570 return false;
5571 ReplacementCC = X86::COND_G;
5572 break;
5573 case X86::COND_AE: // x >=u (C + 1) --> x >u C
5574 if (ImmDelta != 1 || CmpValue == 0)
5575 return false;
5576 ReplacementCC = X86::COND_A;
5577 break;
5578 case X86::COND_G: // x >s (C - 1) --> x >=s C
5579 if (ImmDelta != -1 || APInt::getSignedMaxValue(numBits: BitWidth) == CmpValue)
5580 return false;
5581 ReplacementCC = X86::COND_GE;
5582 break;
5583 case X86::COND_A: // x >u (C - 1) --> x >=u C
5584 if (ImmDelta != -1 || APInt::getMaxValue(numBits: BitWidth) == CmpValue)
5585 return false;
5586 ReplacementCC = X86::COND_AE;
5587 break;
5588 case X86::COND_LE: // x <=s (C - 1) --> x <s C
5589 if (ImmDelta != -1 || APInt::getSignedMaxValue(numBits: BitWidth) == CmpValue)
5590 return false;
5591 ReplacementCC = X86::COND_L;
5592 break;
5593 case X86::COND_BE: // x <=u (C - 1) --> x <u C
5594 if (ImmDelta != -1 || APInt::getMaxValue(numBits: BitWidth) == CmpValue)
5595 return false;
5596 ReplacementCC = X86::COND_B;
5597 break;
5598 default:
5599 return false;
5600 }
5601 ShouldUpdateCC = true;
5602 }
5603
5604 if (ShouldUpdateCC && ReplacementCC != OldCC) {
5605 // Push the MachineInstr to OpsToUpdate.
5606 // If it is safe to remove CmpInstr, the condition code of these
5607 // instructions will be modified.
5608 OpsToUpdate.push_back(Elt: std::make_pair(x: &Instr, y&: ReplacementCC));
5609 }
5610 if (ModifyEFLAGS || Instr.killsRegister(Reg: X86::EFLAGS, TRI)) {
5611 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
5612 FlagsMayLiveOut = false;
5613 break;
5614 }
5615 }
5616
5617 // If we have to update users but EFLAGS is live-out abort, since we cannot
5618 // easily find all of the users.
5619 if ((MI != nullptr || ShouldUpdateCC) && FlagsMayLiveOut) {
5620 for (MachineBasicBlock *Successor : CmpMBB.successors())
5621 if (Successor->isLiveIn(Reg: X86::EFLAGS))
5622 return false;
5623 }
5624
5625 // The instruction to be updated is either Sub or MI.
5626 assert((MI == nullptr || Sub == nullptr) && "Should not have Sub and MI set");
5627 Sub = MI != nullptr ? MI : Sub;
5628 MachineBasicBlock *SubBB = Sub->getParent();
5629 // Move Movr0Inst to the appropriate place before Sub.
5630 if (Movr0Inst) {
5631 // Only move within the same block so we don't accidentally move to a
5632 // block with higher execution frequency.
5633 if (&CmpMBB != SubBB)
5634 return false;
5635 // Look backwards until we find a def that doesn't use the current EFLAGS.
5636 MachineBasicBlock::reverse_iterator InsertI = Sub,
5637 InsertE = Sub->getParent()->rend();
5638 for (; InsertI != InsertE; ++InsertI) {
5639 MachineInstr *Instr = &*InsertI;
5640 if (!Instr->readsRegister(Reg: X86::EFLAGS, TRI) &&
5641 Instr->modifiesRegister(Reg: X86::EFLAGS, TRI)) {
5642 Movr0Inst->getParent()->remove(I: Movr0Inst);
5643 Instr->getParent()->insert(I: MachineBasicBlock::iterator(Instr),
5644 MI: Movr0Inst);
5645 break;
5646 }
5647 }
5648 if (InsertI == InsertE)
5649 return false;
5650 }
5651
5652 // Replace non-NF with NF instructions.
5653 for (auto &Inst : InstsToUpdate) {
5654 Inst.first->setDesc(get(Opcode: Inst.second));
5655 Inst.first->removeOperand(
5656 OpNo: Inst.first->findRegisterDefOperandIdx(Reg: X86::EFLAGS, /*TRI=*/nullptr));
5657 }
5658
5659 // Make sure Sub instruction defines EFLAGS and mark the def live.
5660 MachineOperand *FlagDef =
5661 Sub->findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
5662 assert(FlagDef && "Unable to locate a def EFLAGS operand");
5663 FlagDef->setIsDead(false);
5664
5665 CmpInstr.eraseFromParent();
5666
5667 // Modify the condition code of instructions in OpsToUpdate.
5668 for (auto &Op : OpsToUpdate) {
5669 Op.first->getOperand(i: Op.first->getDesc().getNumOperands() - 1)
5670 .setImm(Op.second);
5671 }
5672 // Add EFLAGS to block live-ins between CmpBB and block of flags producer.
5673 for (MachineBasicBlock *MBB = &CmpMBB; MBB != SubBB;
5674 MBB = *MBB->pred_begin()) {
5675 assert(MBB->pred_size() == 1 && "Expected exactly one predecessor");
5676 if (!MBB->isLiveIn(Reg: X86::EFLAGS))
5677 MBB->addLiveIn(PhysReg: X86::EFLAGS);
5678 }
5679 return true;
5680}
5681
5682/// \returns true if the instruction can be changed to COPY when imm is 0.
5683static bool canConvert2Copy(unsigned Opc) {
5684 switch (Opc) {
5685 default:
5686 return false;
5687 CASE_ND(ADD64ri32)
5688 CASE_ND(SUB64ri32)
5689 CASE_ND(OR64ri32)
5690 CASE_ND(XOR64ri32)
5691 CASE_ND(ADD32ri)
5692 CASE_ND(SUB32ri)
5693 CASE_ND(OR32ri)
5694 CASE_ND(XOR32ri)
5695 return true;
5696 }
5697}
5698
5699/// Convert an ALUrr opcode to corresponding ALUri opcode. Such as
5700/// ADD32rr ==> ADD32ri
5701static unsigned convertALUrr2ALUri(unsigned Opc, bool HasNDDI) {
5702 switch (Opc) {
5703 default:
5704 return 0;
5705#define FROM_TO(FROM, TO) \
5706 case X86::FROM: \
5707 return X86::TO; \
5708 case X86::FROM##_ND: \
5709 return X86::TO##_ND;
5710 FROM_TO(ADC64rr, ADC64ri32)
5711 FROM_TO(SBB64rr, SBB64ri32)
5712 FROM_TO(AND64rr, AND64ri32)
5713 FROM_TO(OR64rr, OR64ri32)
5714 FROM_TO(XOR64rr, XOR64ri32)
5715 FROM_TO(SHR64rCL, SHR64ri)
5716 FROM_TO(SHL64rCL, SHL64ri)
5717 FROM_TO(SAR64rCL, SAR64ri)
5718 FROM_TO(ROL64rCL, ROL64ri)
5719 FROM_TO(ROR64rCL, ROR64ri)
5720 FROM_TO(RCL64rCL, RCL64ri)
5721 FROM_TO(RCR64rCL, RCR64ri)
5722 FROM_TO(ADD32rr, ADD32ri)
5723 FROM_TO(ADC32rr, ADC32ri)
5724 FROM_TO(SUB32rr, SUB32ri)
5725 FROM_TO(SBB32rr, SBB32ri)
5726 FROM_TO(AND32rr, AND32ri)
5727 FROM_TO(OR32rr, OR32ri)
5728 FROM_TO(XOR32rr, XOR32ri)
5729 FROM_TO(SHR32rCL, SHR32ri)
5730 FROM_TO(SHL32rCL, SHL32ri)
5731 FROM_TO(SAR32rCL, SAR32ri)
5732 FROM_TO(ROL32rCL, ROL32ri)
5733 FROM_TO(ROR32rCL, ROR32ri)
5734 FROM_TO(RCL32rCL, RCL32ri)
5735 FROM_TO(RCR32rCL, RCR32ri)
5736#undef FROM_TO
5737#define FROM_TO(FROM, TO) \
5738 case X86::FROM: \
5739 return X86::TO;
5740 FROM_TO(ADD64rr, ADD64ri32)
5741 FROM_TO(SUB64rr, SUB64ri32)
5742 FROM_TO(TEST64rr, TEST64ri32)
5743 FROM_TO(CTEST64rr, CTEST64ri32)
5744 FROM_TO(CMP64rr, CMP64ri32)
5745 FROM_TO(CCMP64rr, CCMP64ri32)
5746 FROM_TO(TEST32rr, TEST32ri)
5747 FROM_TO(CTEST32rr, CTEST32ri)
5748 FROM_TO(CMP32rr, CMP32ri)
5749 FROM_TO(CCMP32rr, CCMP32ri)
5750#undef FROM_TO
5751 case X86::ADD64rr_ND:
5752 return HasNDDI ? X86::ADD64ri32_ND : 0;
5753 case X86::SUB64rr_ND:
5754 return HasNDDI ? X86::SUB64ri32_ND : 0;
5755 }
5756}
5757
5758/// Reg is assigned ImmVal in DefMI, and is used in UseMI.
5759/// If MakeChange is true, this function tries to replace Reg by ImmVal in
5760/// UseMI. If MakeChange is false, just check if folding is possible.
5761//
5762/// \returns true if folding is successful or possible.
5763bool X86InstrInfo::foldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI,
5764 Register Reg, int64_t ImmVal,
5765 MachineRegisterInfo *MRI,
5766 bool MakeChange) const {
5767 bool Modified = false;
5768
5769 // 64 bit operations accept sign extended 32 bit immediates.
5770 // 32 bit operations accept all 32 bit immediates, so we don't need to check
5771 // them.
5772 const TargetRegisterClass *RC = nullptr;
5773 if (Reg.isVirtual())
5774 RC = MRI->getRegClass(Reg);
5775 if ((Reg.isPhysical() && X86::GR64RegClass.contains(Reg)) ||
5776 (Reg.isVirtual() && X86::GR64RegClass.hasSubClassEq(RC))) {
5777 if (!isInt<32>(x: ImmVal))
5778 return false;
5779 }
5780
5781 if (UseMI.findRegisterUseOperand(Reg, /*TRI=*/nullptr)->getSubReg())
5782 return false;
5783 // Immediate has larger code size than register. So avoid folding the
5784 // immediate if it has more than 1 use and we are optimizing for size.
5785 if (UseMI.getMF()->getFunction().hasOptSize() && Reg.isVirtual() &&
5786 !MRI->hasOneNonDBGUse(RegNo: Reg))
5787 return false;
5788
5789 unsigned Opc = UseMI.getOpcode();
5790 unsigned NewOpc;
5791 if (Opc == TargetOpcode::COPY) {
5792 Register ToReg = UseMI.getOperand(i: 0).getReg();
5793 const TargetRegisterClass *RC = nullptr;
5794 if (ToReg.isVirtual())
5795 RC = MRI->getRegClass(Reg: ToReg);
5796 bool GR32Reg = (ToReg.isVirtual() && X86::GR32RegClass.hasSubClassEq(RC)) ||
5797 (ToReg.isPhysical() && X86::GR32RegClass.contains(Reg: ToReg));
5798 bool GR64Reg = (ToReg.isVirtual() && X86::GR64RegClass.hasSubClassEq(RC)) ||
5799 (ToReg.isPhysical() && X86::GR64RegClass.contains(Reg: ToReg));
5800 bool GR8Reg = (ToReg.isVirtual() && X86::GR8RegClass.hasSubClassEq(RC)) ||
5801 (ToReg.isPhysical() && X86::GR8RegClass.contains(Reg: ToReg));
5802
5803 if (ImmVal == 0) {
5804 // We have MOV32r0 only.
5805 if (!GR32Reg)
5806 return false;
5807 }
5808
5809 if (GR64Reg) {
5810 if (isUInt<32>(x: ImmVal))
5811 NewOpc = X86::MOV32ri64;
5812 else
5813 NewOpc = X86::MOV64ri;
5814 } else if (GR32Reg) {
5815 NewOpc = X86::MOV32ri;
5816 if (ImmVal == 0) {
5817 // MOV32r0 clobbers EFLAGS.
5818 const TargetRegisterInfo *TRI = &getRegisterInfo();
5819 if (UseMI.getParent()->computeRegisterLiveness(
5820 TRI, Reg: X86::EFLAGS, Before: UseMI) != MachineBasicBlock::LQR_Dead)
5821 return false;
5822
5823 // MOV32r0 is different than other cases because it doesn't encode the
5824 // immediate in the instruction. So we directly modify it here.
5825 if (!MakeChange)
5826 return true;
5827 UseMI.setDesc(get(Opcode: X86::MOV32r0));
5828 UseMI.removeOperand(
5829 OpNo: UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr));
5830 UseMI.addOperand(Op: MachineOperand::CreateReg(Reg: X86::EFLAGS, /*isDef=*/true,
5831 /*isImp=*/true,
5832 /*isKill=*/false,
5833 /*isDead=*/true));
5834 Modified = true;
5835 }
5836 } else if (GR8Reg)
5837 NewOpc = X86::MOV8ri;
5838 else
5839 return false;
5840 } else
5841 NewOpc = convertALUrr2ALUri(Opc, HasNDDI: Subtarget.hasNDDI());
5842
5843 if (!NewOpc)
5844 return false;
5845
5846 // For SUB instructions the immediate can only be the second source operand.
5847 if ((NewOpc == X86::SUB64ri32 || NewOpc == X86::SUB32ri ||
5848 NewOpc == X86::SBB64ri32 || NewOpc == X86::SBB32ri ||
5849 NewOpc == X86::SUB64ri32_ND || NewOpc == X86::SUB32ri_ND ||
5850 NewOpc == X86::SBB64ri32_ND || NewOpc == X86::SBB32ri_ND) &&
5851 UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr) != 2)
5852 return false;
5853 // For CMP instructions the immediate can only be at index 1.
5854 if (((NewOpc == X86::CMP64ri32 || NewOpc == X86::CMP32ri) ||
5855 (NewOpc == X86::CCMP64ri32 || NewOpc == X86::CCMP32ri)) &&
5856 UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr) != 1)
5857 return false;
5858
5859 using namespace X86;
5860 if (isSHL(Opcode: Opc) || isSHR(Opcode: Opc) || isSAR(Opcode: Opc) || isROL(Opcode: Opc) || isROR(Opcode: Opc) ||
5861 isRCL(Opcode: Opc) || isRCR(Opcode: Opc)) {
5862 unsigned RegIdx = UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr);
5863 if (RegIdx < 2)
5864 return false;
5865 if (!isInt<8>(x: ImmVal))
5866 return false;
5867 assert(Reg == X86::CL);
5868
5869 if (!MakeChange)
5870 return true;
5871 UseMI.setDesc(get(Opcode: NewOpc));
5872 UseMI.removeOperand(OpNo: RegIdx);
5873 UseMI.addOperand(Op: MachineOperand::CreateImm(Val: ImmVal));
5874 // Reg is physical register $cl, so we don't know if DefMI is dead through
5875 // MRI. Let the caller handle it, or pass dead-mi-elimination can delete
5876 // the dead physical register define instruction.
5877 return true;
5878 }
5879
5880 if (!MakeChange)
5881 return true;
5882
5883 if (!Modified) {
5884 // Modify the instruction.
5885 if (ImmVal == 0 && canConvert2Copy(Opc: NewOpc) &&
5886 UseMI.registerDefIsDead(Reg: X86::EFLAGS, /*TRI=*/nullptr)) {
5887 // %100 = add %101, 0
5888 // ==>
5889 // %100 = COPY %101
5890 UseMI.setDesc(get(Opcode: TargetOpcode::COPY));
5891 UseMI.removeOperand(
5892 OpNo: UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr));
5893 UseMI.removeOperand(
5894 OpNo: UseMI.findRegisterDefOperandIdx(Reg: X86::EFLAGS, /*TRI=*/nullptr));
5895 UseMI.untieRegOperand(OpIdx: 0);
5896 UseMI.clearFlag(Flag: MachineInstr::MIFlag::NoSWrap);
5897 UseMI.clearFlag(Flag: MachineInstr::MIFlag::NoUWrap);
5898 } else {
5899 unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
5900 unsigned ImmOpNum = 2;
5901 if (!UseMI.getOperand(i: 0).isDef()) {
5902 Op1 = 0; // TEST, CMP, CTEST, CCMP
5903 ImmOpNum = 1;
5904 }
5905 if (Opc == TargetOpcode::COPY)
5906 ImmOpNum = 1;
5907 if (findCommutedOpIndices(MI: UseMI, SrcOpIdx1&: Op1, SrcOpIdx2&: Op2) &&
5908 UseMI.getOperand(i: Op1).getReg() == Reg)
5909 commuteInstruction(MI&: UseMI);
5910
5911 assert(UseMI.getOperand(ImmOpNum).getReg() == Reg);
5912 UseMI.setDesc(get(Opcode: NewOpc));
5913 UseMI.getOperand(i: ImmOpNum).ChangeToImmediate(ImmVal);
5914 }
5915 }
5916
5917 if (Reg.isVirtual() && MRI->use_nodbg_empty(RegNo: Reg))
5918 DefMI->eraseFromBundle();
5919
5920 return true;
5921}
5922
5923/// foldImmediate - 'Reg' is known to be defined by a move immediate
5924/// instruction, try to fold the immediate into the use instruction.
5925bool X86InstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
5926 Register Reg, MachineRegisterInfo *MRI) const {
5927 int64_t ImmVal;
5928 if (!getConstValDefinedInReg(MI: DefMI, Reg, ImmVal))
5929 return false;
5930
5931 return foldImmediateImpl(UseMI, DefMI: &DefMI, Reg, ImmVal, MRI, MakeChange: true);
5932}
5933
5934/// Expand a single-def pseudo instruction to a two-addr
5935/// instruction with two undef reads of the register being defined.
5936/// This is used for mapping:
5937/// %xmm4 = V_SET0
5938/// to:
5939/// %xmm4 = PXORrr undef %xmm4, undef %xmm4
5940///
5941static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
5942 const MCInstrDesc &Desc) {
5943 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5944 Register Reg = MIB.getReg(Idx: 0);
5945 MIB->setDesc(Desc);
5946
5947 // MachineInstr::addOperand() will insert explicit operands before any
5948 // implicit operands.
5949 MIB.addReg(RegNo: Reg, Flags: RegState::Undef).addReg(RegNo: Reg, Flags: RegState::Undef);
5950 // But we don't trust that.
5951 assert(MIB.getReg(1) == Reg && MIB.getReg(2) == Reg && "Misplaced operand");
5952 return true;
5953}
5954
5955/// Expand a single-def pseudo instruction to a two-addr
5956/// instruction with two %k0 reads.
5957/// This is used for mapping:
5958/// %k4 = K_SET1
5959/// to:
5960/// %k4 = KXNORrr %k0, %k0
5961static bool Expand2AddrKreg(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
5962 Register Reg) {
5963 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5964 MIB->setDesc(Desc);
5965 MIB.addReg(RegNo: Reg, Flags: RegState::Undef).addReg(RegNo: Reg, Flags: RegState::Undef);
5966 return true;
5967}
5968
5969static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
5970 bool MinusOne) {
5971 MachineBasicBlock &MBB = *MIB->getParent();
5972 const DebugLoc &DL = MIB->getDebugLoc();
5973 Register Reg = MIB.getReg(Idx: 0);
5974
5975 // Insert the XOR.
5976 BuildMI(BB&: MBB, I: MIB.getInstr(), MIMD: DL, MCID: TII.get(Opcode: X86::XOR32rr), DestReg: Reg)
5977 .addReg(RegNo: Reg, Flags: RegState::Undef)
5978 .addReg(RegNo: Reg, Flags: RegState::Undef);
5979
5980 // Turn the pseudo into an INC or DEC.
5981 MIB->setDesc(TII.get(Opcode: MinusOne ? X86::DEC32r : X86::INC32r));
5982 MIB.addReg(RegNo: Reg);
5983
5984 return true;
5985}
5986
5987static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
5988 const TargetInstrInfo &TII,
5989 const X86Subtarget &Subtarget) {
5990 MachineBasicBlock &MBB = *MIB->getParent();
5991 const DebugLoc &DL = MIB->getDebugLoc();
5992 int64_t Imm = MIB->getOperand(i: 1).getImm();
5993 assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
5994 MachineBasicBlock::iterator I = MIB.getInstr();
5995
5996 int StackAdjustment;
5997
5998 if (Subtarget.is64Bit()) {
5999 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
6000 MIB->getOpcode() == X86::MOV32ImmSExti8);
6001
6002 // Can't use push/pop lowering if the function might write to the red zone.
6003 X86MachineFunctionInfo *X86FI =
6004 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
6005 if (X86FI->getUsesRedZone()) {
6006 MIB->setDesc(TII.get(Opcode: MIB->getOpcode() == X86::MOV32ImmSExti8
6007 ? X86::MOV32ri
6008 : X86::MOV64ri));
6009 return true;
6010 }
6011
6012 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
6013 // widen the register if necessary.
6014 StackAdjustment = 8;
6015 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII.get(Opcode: X86::PUSH64i32)).addImm(Val: Imm);
6016 MIB->setDesc(TII.get(Opcode: X86::POP64r));
6017 MIB->getOperand(i: 0).setReg(getX86SubSuperRegister(Reg: MIB.getReg(Idx: 0), Size: 64));
6018 } else {
6019 assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
6020 StackAdjustment = 4;
6021 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII.get(Opcode: X86::PUSH32i)).addImm(Val: Imm);
6022 MIB->setDesc(TII.get(Opcode: X86::POP32r));
6023 }
6024 MIB->removeOperand(OpNo: 1);
6025 MIB->addImplicitDefUseOperands(MF&: *MBB.getParent());
6026
6027 // Build CFI if necessary.
6028 MachineFunction &MF = *MBB.getParent();
6029 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
6030 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
6031 bool NeedsDwarfCFI = !IsWin64Prologue && MF.needsFrameMoves();
6032 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
6033 if (EmitCFI) {
6034 TFL->BuildCFI(
6035 MBB, MBBI: I, DL,
6036 CFIInst: MCCFIInstruction::createAdjustCfaOffset(L: nullptr, Adjustment: StackAdjustment));
6037 TFL->BuildCFI(
6038 MBB, MBBI: std::next(x: I), DL,
6039 CFIInst: MCCFIInstruction::createAdjustCfaOffset(L: nullptr, Adjustment: -StackAdjustment));
6040 }
6041
6042 return true;
6043}
6044
6045// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
6046// code sequence is needed for other targets.
6047static void expandLoadStackGuard(MachineInstrBuilder &MIB,
6048 const TargetInstrInfo &TII) {
6049 MachineBasicBlock &MBB = *MIB->getParent();
6050 const DebugLoc &DL = MIB->getDebugLoc();
6051 Register Reg = MIB.getReg(Idx: 0);
6052 const GlobalValue *GV =
6053 cast<GlobalValue>(Val: (*MIB->memoperands_begin())->getValue());
6054 auto Flags = MachineMemOperand::MOLoad |
6055 MachineMemOperand::MODereferenceable |
6056 MachineMemOperand::MOInvariant;
6057 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
6058 PtrInfo: MachinePointerInfo::getGOT(MF&: *MBB.getParent()), F: Flags, Size: 8, BaseAlignment: Align(8));
6059 MachineBasicBlock::iterator I = MIB.getInstr();
6060
6061 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII.get(Opcode: X86::MOV64rm), DestReg: Reg)
6062 .addReg(RegNo: X86::RIP)
6063 .addImm(Val: 1)
6064 .addReg(RegNo: 0)
6065 .addGlobalAddress(GV, Offset: 0, TargetFlags: X86II::MO_GOTPCREL)
6066 .addReg(RegNo: 0)
6067 .addMemOperand(MMO);
6068 MIB->setDebugLoc(DL);
6069 MIB->setDesc(TII.get(Opcode: X86::MOV64rm));
6070 MIB.addReg(RegNo: Reg, Flags: RegState::Kill).addImm(Val: 1).addReg(RegNo: 0).addImm(Val: 0).addReg(RegNo: 0);
6071}
6072
6073static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
6074 MachineBasicBlock &MBB = *MIB->getParent();
6075 MachineFunction &MF = *MBB.getParent();
6076 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
6077 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
6078 unsigned XorOp =
6079 MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
6080 MIB->setDesc(TII.get(Opcode: XorOp));
6081 MIB.addReg(RegNo: TRI->getFrameRegister(MF), Flags: RegState::Undef);
6082 return true;
6083}
6084
6085// This is used to handle spills for 128/256-bit registers when we have AVX512,
6086// but not VLX. If it uses an extended register we need to use an instruction
6087// that loads the lower 128/256-bit, but is available with only AVX512F.
6088static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
6089 const TargetRegisterInfo *TRI,
6090 const MCInstrDesc &LoadDesc,
6091 const MCInstrDesc &BroadcastDesc, unsigned SubIdx) {
6092 Register DestReg = MIB.getReg(Idx: 0);
6093 // Check if DestReg is XMM16-31 or YMM16-31.
6094 if (TRI->getEncodingValue(Reg: DestReg) < 16) {
6095 // We can use a normal VEX encoded load.
6096 MIB->setDesc(LoadDesc);
6097 } else {
6098 // Use a 128/256-bit VBROADCAST instruction.
6099 MIB->setDesc(BroadcastDesc);
6100 // Change the destination to a 512-bit register.
6101 DestReg = TRI->getMatchingSuperReg(Reg: DestReg, SubIdx, RC: &X86::VR512RegClass);
6102 MIB->getOperand(i: 0).setReg(DestReg);
6103 }
6104 return true;
6105}
6106
6107// This is used to handle spills for 128/256-bit registers when we have AVX512,
6108// but not VLX. If it uses an extended register we need to use an instruction
6109// that stores the lower 128/256-bit, but is available with only AVX512F.
6110static bool expandNOVLXStore(MachineInstrBuilder &MIB,
6111 const TargetRegisterInfo *TRI,
6112 const MCInstrDesc &StoreDesc,
6113 const MCInstrDesc &ExtractDesc, unsigned SubIdx) {
6114 Register SrcReg = MIB.getReg(Idx: X86::AddrNumOperands);
6115 // Check if DestReg is XMM16-31 or YMM16-31.
6116 if (TRI->getEncodingValue(Reg: SrcReg) < 16) {
6117 // We can use a normal VEX encoded store.
6118 MIB->setDesc(StoreDesc);
6119 } else {
6120 // Use a VEXTRACTF instruction.
6121 MIB->setDesc(ExtractDesc);
6122 // Change the destination to a 512-bit register.
6123 SrcReg = TRI->getMatchingSuperReg(Reg: SrcReg, SubIdx, RC: &X86::VR512RegClass);
6124 MIB->getOperand(i: X86::AddrNumOperands).setReg(SrcReg);
6125 MIB.addImm(Val: 0x0); // Append immediate to extract from the lower bits.
6126 }
6127
6128 return true;
6129}
6130
6131static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
6132 MIB->setDesc(Desc);
6133 int64_t ShiftAmt = MIB->getOperand(i: 2).getImm();
6134 // Temporarily remove the immediate so we can add another source register.
6135 MIB->removeOperand(OpNo: 2);
6136 // Add the register. Don't copy the kill flag if there is one.
6137 MIB.addReg(RegNo: MIB.getReg(Idx: 1), Flags: getUndefRegState(B: MIB->getOperand(i: 1).isUndef()));
6138 // Add back the immediate.
6139 MIB.addImm(Val: ShiftAmt);
6140 return true;
6141}
6142
6143static bool expandMOVSHP(MachineInstrBuilder &MIB, MachineInstr &MI,
6144 const TargetInstrInfo &TII, bool HasAVX) {
6145 unsigned NewOpc;
6146 if (MI.getOpcode() == X86::MOVSHPrm) {
6147 NewOpc = HasAVX ? X86::VMOVSSrm : X86::MOVSSrm;
6148 Register Reg = MI.getOperand(i: 0).getReg();
6149 if (Reg > X86::XMM15)
6150 NewOpc = X86::VMOVSSZrm;
6151 } else {
6152 NewOpc = HasAVX ? X86::VMOVSSmr : X86::MOVSSmr;
6153 Register Reg = MI.getOperand(i: 5).getReg();
6154 if (Reg > X86::XMM15)
6155 NewOpc = X86::VMOVSSZmr;
6156 }
6157
6158 MIB->setDesc(TII.get(Opcode: NewOpc));
6159 return true;
6160}
6161
6162bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
6163 bool HasAVX = Subtarget.hasAVX();
6164 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
6165 switch (MI.getOpcode()) {
6166 case X86::MOV32r0:
6167 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::XOR32rr));
6168 case X86::MOV32r1:
6169 return expandMOV32r1(MIB, TII: *this, /*MinusOne=*/false);
6170 case X86::MOV32r_1:
6171 return expandMOV32r1(MIB, TII: *this, /*MinusOne=*/true);
6172 case X86::MOV32ImmSExti8:
6173 case X86::MOV64ImmSExti8:
6174 return ExpandMOVImmSExti8(MIB, TII: *this, Subtarget);
6175 case X86::SETB_C32r:
6176 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::SBB32rr));
6177 case X86::SETB_C64r:
6178 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::SBB64rr));
6179 case X86::MMX_SET0:
6180 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::MMX_PXORrr));
6181 case X86::V_SET0:
6182 case X86::FsFLD0SS:
6183 case X86::FsFLD0SD:
6184 case X86::FsFLD0SH:
6185 case X86::FsFLD0F128:
6186 return Expand2AddrUndef(MIB, Desc: get(Opcode: HasAVX ? X86::VXORPSrr : X86::XORPSrr));
6187 case X86::AVX_SET0: {
6188 assert(HasAVX && "AVX not supported");
6189 const TargetRegisterInfo *TRI = &getRegisterInfo();
6190 Register SrcReg = MIB.getReg(Idx: 0);
6191 Register XReg = TRI->getSubReg(Reg: SrcReg, Idx: X86::sub_xmm);
6192 MIB->getOperand(i: 0).setReg(XReg);
6193 Expand2AddrUndef(MIB, Desc: get(Opcode: X86::VXORPSrr));
6194 MIB.addReg(RegNo: SrcReg, Flags: RegState::ImplicitDefine);
6195 return true;
6196 }
6197 case X86::AVX512_128_SET0:
6198 case X86::AVX512_FsFLD0SH:
6199 case X86::AVX512_FsFLD0SS:
6200 case X86::AVX512_FsFLD0SD:
6201 case X86::AVX512_FsFLD0F128: {
6202 bool HasVLX = Subtarget.hasVLX();
6203 Register SrcReg = MIB.getReg(Idx: 0);
6204 const TargetRegisterInfo *TRI = &getRegisterInfo();
6205 if (HasVLX || TRI->getEncodingValue(Reg: SrcReg) < 16)
6206 return Expand2AddrUndef(MIB,
6207 Desc: get(Opcode: HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
6208 // Extended register without VLX. Use a larger XOR.
6209 SrcReg =
6210 TRI->getMatchingSuperReg(Reg: SrcReg, SubIdx: X86::sub_xmm, RC: &X86::VR512RegClass);
6211 MIB->getOperand(i: 0).setReg(SrcReg);
6212 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::VPXORDZrr));
6213 }
6214 case X86::AVX512_256_SET0:
6215 case X86::AVX512_512_SET0: {
6216 bool HasVLX = Subtarget.hasVLX();
6217 Register SrcReg = MIB.getReg(Idx: 0);
6218 const TargetRegisterInfo *TRI = &getRegisterInfo();
6219 if (HasVLX || TRI->getEncodingValue(Reg: SrcReg) < 16) {
6220 Register XReg = TRI->getSubReg(Reg: SrcReg, Idx: X86::sub_xmm);
6221 MIB->getOperand(i: 0).setReg(XReg);
6222 Expand2AddrUndef(MIB, Desc: get(Opcode: HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
6223 MIB.addReg(RegNo: SrcReg, Flags: RegState::ImplicitDefine);
6224 return true;
6225 }
6226 if (MI.getOpcode() == X86::AVX512_256_SET0) {
6227 // No VLX so we must reference a zmm.
6228 MCRegister ZReg =
6229 TRI->getMatchingSuperReg(Reg: SrcReg, SubIdx: X86::sub_ymm, RC: &X86::VR512RegClass);
6230 MIB->getOperand(i: 0).setReg(ZReg);
6231 }
6232 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::VPXORDZrr));
6233 }
6234 case X86::MOVSHPmr:
6235 case X86::MOVSHPrm:
6236 return expandMOVSHP(MIB, MI, TII: *this, HasAVX: Subtarget.hasAVX());
6237 case X86::V_SETALLONES:
6238 return Expand2AddrUndef(MIB,
6239 Desc: get(Opcode: HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
6240 case X86::AVX2_SETALLONES:
6241 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::VPCMPEQDYrr));
6242 case X86::AVX1_SETALLONES: {
6243 Register Reg = MIB.getReg(Idx: 0);
6244 // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
6245 MIB->setDesc(get(Opcode: X86::VCMPPSYrri));
6246 MIB.addReg(RegNo: Reg, Flags: RegState::Undef).addReg(RegNo: Reg, Flags: RegState::Undef).addImm(Val: 0xf);
6247 return true;
6248 }
6249 case X86::AVX512_128_SETALLONES:
6250 case X86::AVX512_256_SETALLONES:
6251 case X86::AVX512_512_SETALLONES: {
6252 Register Reg = MIB.getReg(Idx: 0);
6253 unsigned Opc;
6254 switch (MI.getOpcode()) {
6255 case X86::AVX512_128_SETALLONES: {
6256 if (X86::VR128RegClass.contains(Reg))
6257 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::VPCMPEQDrr));
6258
6259 Opc = X86::VPTERNLOGDZ128rri;
6260 break;
6261 }
6262 case X86::AVX512_256_SETALLONES: {
6263 if (X86::VR256RegClass.contains(Reg))
6264 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::VPCMPEQDYrr));
6265
6266 Opc = X86::VPTERNLOGDZ256rri;
6267 break;
6268 }
6269 case X86::AVX512_512_SETALLONES:
6270 Opc = X86::VPTERNLOGDZrri;
6271 break;
6272 }
6273 MIB->setDesc(get(Opcode: Opc));
6274 // VPTERNLOGD needs 3 register inputs and an immediate.
6275 // 0xff will return 1s for any input.
6276 MIB.addReg(RegNo: Reg, Flags: RegState::Undef)
6277 .addReg(RegNo: Reg, Flags: RegState::Undef)
6278 .addReg(RegNo: Reg, Flags: RegState::Undef)
6279 .addImm(Val: 0xff);
6280 return true;
6281 }
6282 case X86::AVX512_512_SEXT_MASK_32:
6283 case X86::AVX512_512_SEXT_MASK_64: {
6284 Register Reg = MIB.getReg(Idx: 0);
6285 Register MaskReg = MIB.getReg(Idx: 1);
6286 RegState MaskState = getRegState(RegOp: MIB->getOperand(i: 1));
6287 unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64)
6288 ? X86::VPTERNLOGQZrrikz
6289 : X86::VPTERNLOGDZrrikz;
6290 MI.removeOperand(OpNo: 1);
6291 MIB->setDesc(get(Opcode: Opc));
6292 // VPTERNLOG needs 3 register inputs and an immediate.
6293 // 0xff will return 1s for any input.
6294 MIB.addReg(RegNo: Reg, Flags: RegState::Undef)
6295 .addReg(RegNo: MaskReg, Flags: MaskState)
6296 .addReg(RegNo: Reg, Flags: RegState::Undef)
6297 .addReg(RegNo: Reg, Flags: RegState::Undef)
6298 .addImm(Val: 0xff);
6299 return true;
6300 }
6301 case X86::VMOVAPSZ128rm_NOVLX:
6302 return expandNOVLXLoad(MIB, TRI: &getRegisterInfo(), LoadDesc: get(Opcode: X86::VMOVAPSrm),
6303 BroadcastDesc: get(Opcode: X86::VBROADCASTF32X4Zrm), SubIdx: X86::sub_xmm);
6304 case X86::VMOVUPSZ128rm_NOVLX:
6305 return expandNOVLXLoad(MIB, TRI: &getRegisterInfo(), LoadDesc: get(Opcode: X86::VMOVUPSrm),
6306 BroadcastDesc: get(Opcode: X86::VBROADCASTF32X4Zrm), SubIdx: X86::sub_xmm);
6307 case X86::VMOVAPSZ256rm_NOVLX:
6308 return expandNOVLXLoad(MIB, TRI: &getRegisterInfo(), LoadDesc: get(Opcode: X86::VMOVAPSYrm),
6309 BroadcastDesc: get(Opcode: X86::VBROADCASTF64X4Zrm), SubIdx: X86::sub_ymm);
6310 case X86::VMOVUPSZ256rm_NOVLX:
6311 return expandNOVLXLoad(MIB, TRI: &getRegisterInfo(), LoadDesc: get(Opcode: X86::VMOVUPSYrm),
6312 BroadcastDesc: get(Opcode: X86::VBROADCASTF64X4Zrm), SubIdx: X86::sub_ymm);
6313 case X86::VMOVAPSZ128mr_NOVLX:
6314 return expandNOVLXStore(MIB, TRI: &getRegisterInfo(), StoreDesc: get(Opcode: X86::VMOVAPSmr),
6315 ExtractDesc: get(Opcode: X86::VEXTRACTF32X4Zmri), SubIdx: X86::sub_xmm);
6316 case X86::VMOVUPSZ128mr_NOVLX:
6317 return expandNOVLXStore(MIB, TRI: &getRegisterInfo(), StoreDesc: get(Opcode: X86::VMOVUPSmr),
6318 ExtractDesc: get(Opcode: X86::VEXTRACTF32X4Zmri), SubIdx: X86::sub_xmm);
6319 case X86::VMOVAPSZ256mr_NOVLX:
6320 return expandNOVLXStore(MIB, TRI: &getRegisterInfo(), StoreDesc: get(Opcode: X86::VMOVAPSYmr),
6321 ExtractDesc: get(Opcode: X86::VEXTRACTF64X4Zmri), SubIdx: X86::sub_ymm);
6322 case X86::VMOVUPSZ256mr_NOVLX:
6323 return expandNOVLXStore(MIB, TRI: &getRegisterInfo(), StoreDesc: get(Opcode: X86::VMOVUPSYmr),
6324 ExtractDesc: get(Opcode: X86::VEXTRACTF64X4Zmri), SubIdx: X86::sub_ymm);
6325 case X86::MOV32ri64: {
6326 Register Reg = MIB.getReg(Idx: 0);
6327 Register Reg32 = RI.getSubReg(Reg, Idx: X86::sub_32bit);
6328 MI.setDesc(get(Opcode: X86::MOV32ri));
6329 MIB->getOperand(i: 0).setReg(Reg32);
6330 MIB.addReg(RegNo: Reg, Flags: RegState::ImplicitDefine);
6331 return true;
6332 }
6333
6334 case X86::RDFLAGS32:
6335 case X86::RDFLAGS64: {
6336 unsigned Is64Bit = MI.getOpcode() == X86::RDFLAGS64;
6337 MachineBasicBlock &MBB = *MIB->getParent();
6338
6339 MachineInstr *NewMI = BuildMI(BB&: MBB, I&: MI, MIMD: MIB->getDebugLoc(),
6340 MCID: get(Opcode: Is64Bit ? X86::PUSHF64 : X86::PUSHF32))
6341 .getInstr();
6342
6343 // Permit reads of the EFLAGS and DF registers without them being defined.
6344 // This intrinsic exists to read external processor state in flags, such as
6345 // the trap flag, interrupt flag, and direction flag, none of which are
6346 // modeled by the backend.
6347 assert(NewMI->getOperand(2).getReg() == X86::EFLAGS &&
6348 "Unexpected register in operand! Should be EFLAGS.");
6349 NewMI->getOperand(i: 2).setIsUndef();
6350 assert(NewMI->getOperand(3).getReg() == X86::DF &&
6351 "Unexpected register in operand! Should be DF.");
6352 NewMI->getOperand(i: 3).setIsUndef();
6353
6354 MIB->setDesc(get(Opcode: Is64Bit ? X86::POP64r : X86::POP32r));
6355 return true;
6356 }
6357
6358 case X86::WRFLAGS32:
6359 case X86::WRFLAGS64: {
6360 unsigned Is64Bit = MI.getOpcode() == X86::WRFLAGS64;
6361 MachineBasicBlock &MBB = *MIB->getParent();
6362
6363 BuildMI(BB&: MBB, I&: MI, MIMD: MIB->getDebugLoc(),
6364 MCID: get(Opcode: Is64Bit ? X86::PUSH64r : X86::PUSH32r))
6365 .addReg(RegNo: MI.getOperand(i: 0).getReg());
6366 BuildMI(BB&: MBB, I&: MI, MIMD: MIB->getDebugLoc(),
6367 MCID: get(Opcode: Is64Bit ? X86::POPF64 : X86::POPF32));
6368 MI.eraseFromParent();
6369 return true;
6370 }
6371
6372 // KNL does not recognize dependency-breaking idioms for mask registers,
6373 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
6374 // Using %k0 as the undef input register is a performance heuristic based
6375 // on the assumption that %k0 is used less frequently than the other mask
6376 // registers, since it is not usable as a write mask.
6377 // FIXME: A more advanced approach would be to choose the best input mask
6378 // register based on context.
6379 case X86::KSET0B:
6380 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXORBkk), Reg: X86::K0);
6381 case X86::KSET0W:
6382 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXORWkk), Reg: X86::K0);
6383 case X86::KSET0D:
6384 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXORDkk), Reg: X86::K0);
6385 case X86::KSET0Q:
6386 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXORQkk), Reg: X86::K0);
6387 case X86::KSET1B:
6388 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXNORBkk), Reg: X86::K0);
6389 case X86::KSET1W:
6390 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXNORWkk), Reg: X86::K0);
6391 case X86::KSET1D:
6392 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXNORDkk), Reg: X86::K0);
6393 case X86::KSET1Q:
6394 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXNORQkk), Reg: X86::K0);
6395 case TargetOpcode::LOAD_STACK_GUARD:
6396 expandLoadStackGuard(MIB, TII: *this);
6397 return true;
6398 case X86::XOR64_FP:
6399 case X86::XOR32_FP:
6400 return expandXorFP(MIB, TII: *this);
6401 case X86::SHLDROT32ri:
6402 return expandSHXDROT(MIB, Desc: get(Opcode: X86::SHLD32rri8));
6403 case X86::SHLDROT64ri:
6404 return expandSHXDROT(MIB, Desc: get(Opcode: X86::SHLD64rri8));
6405 case X86::SHRDROT32ri:
6406 return expandSHXDROT(MIB, Desc: get(Opcode: X86::SHRD32rri8));
6407 case X86::SHRDROT64ri:
6408 return expandSHXDROT(MIB, Desc: get(Opcode: X86::SHRD64rri8));
6409 case X86::ADD8rr_DB:
6410 MIB->setDesc(get(Opcode: X86::OR8rr));
6411 break;
6412 case X86::ADD16rr_DB:
6413 MIB->setDesc(get(Opcode: X86::OR16rr));
6414 break;
6415 case X86::ADD32rr_DB:
6416 MIB->setDesc(get(Opcode: X86::OR32rr));
6417 break;
6418 case X86::ADD64rr_DB:
6419 MIB->setDesc(get(Opcode: X86::OR64rr));
6420 break;
6421 case X86::ADD8ri_DB:
6422 MIB->setDesc(get(Opcode: X86::OR8ri));
6423 break;
6424 case X86::ADD16ri_DB:
6425 MIB->setDesc(get(Opcode: X86::OR16ri));
6426 break;
6427 case X86::ADD32ri_DB:
6428 MIB->setDesc(get(Opcode: X86::OR32ri));
6429 break;
6430 case X86::ADD64ri32_DB:
6431 MIB->setDesc(get(Opcode: X86::OR64ri32));
6432 break;
6433 }
6434 return false;
6435}
6436
6437/// Return true for all instructions that only update
6438/// the first 32 or 64-bits of the destination register and leave the rest
6439/// unmodified. This can be used to avoid folding loads if the instructions
6440/// only update part of the destination register, and the non-updated part is
6441/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
6442/// instructions breaks the partial register dependency and it can improve
6443/// performance. e.g.:
6444///
6445/// movss (%rdi), %xmm0
6446/// cvtss2sd %xmm0, %xmm0
6447///
6448/// Instead of
6449/// cvtss2sd (%rdi), %xmm0
6450///
6451/// FIXME: This should be turned into a TSFlags.
6452///
6453static bool hasPartialRegUpdate(unsigned Opcode, const X86Subtarget &Subtarget,
6454 bool ForLoadFold = false) {
6455 switch (Opcode) {
6456 case X86::CVTSI2SSrr:
6457 case X86::CVTSI2SSrm:
6458 case X86::CVTSI642SSrr:
6459 case X86::CVTSI642SSrm:
6460 case X86::CVTSI2SDrr:
6461 case X86::CVTSI2SDrm:
6462 case X86::CVTSI642SDrr:
6463 case X86::CVTSI642SDrm:
6464 // Load folding won't effect the undef register update since the input is
6465 // a GPR.
6466 return !ForLoadFold;
6467 case X86::CVTSD2SSrr:
6468 case X86::CVTSD2SSrm:
6469 case X86::CVTSS2SDrr:
6470 case X86::CVTSS2SDrm:
6471 case X86::MOVHPDrm:
6472 case X86::MOVHPSrm:
6473 case X86::MOVLPDrm:
6474 case X86::MOVLPSrm:
6475 case X86::RCPSSr:
6476 case X86::RCPSSm:
6477 case X86::RCPSSr_Int:
6478 case X86::RCPSSm_Int:
6479 case X86::ROUNDSDri:
6480 case X86::ROUNDSDmi:
6481 case X86::ROUNDSSri:
6482 case X86::ROUNDSSmi:
6483 case X86::RSQRTSSr:
6484 case X86::RSQRTSSm:
6485 case X86::RSQRTSSr_Int:
6486 case X86::RSQRTSSm_Int:
6487 case X86::SQRTSSr:
6488 case X86::SQRTSSm:
6489 case X86::SQRTSSr_Int:
6490 case X86::SQRTSSm_Int:
6491 case X86::SQRTSDr:
6492 case X86::SQRTSDm:
6493 case X86::SQRTSDr_Int:
6494 case X86::SQRTSDm_Int:
6495 return true;
6496 case X86::VFCMULCPHZ128rm:
6497 case X86::VFCMULCPHZ128rmb:
6498 case X86::VFCMULCPHZ128rmbkz:
6499 case X86::VFCMULCPHZ128rmkz:
6500 case X86::VFCMULCPHZ128rr:
6501 case X86::VFCMULCPHZ128rrkz:
6502 case X86::VFCMULCPHZ256rm:
6503 case X86::VFCMULCPHZ256rmb:
6504 case X86::VFCMULCPHZ256rmbkz:
6505 case X86::VFCMULCPHZ256rmkz:
6506 case X86::VFCMULCPHZ256rr:
6507 case X86::VFCMULCPHZ256rrkz:
6508 case X86::VFCMULCPHZrm:
6509 case X86::VFCMULCPHZrmb:
6510 case X86::VFCMULCPHZrmbkz:
6511 case X86::VFCMULCPHZrmkz:
6512 case X86::VFCMULCPHZrr:
6513 case X86::VFCMULCPHZrrb:
6514 case X86::VFCMULCPHZrrbkz:
6515 case X86::VFCMULCPHZrrkz:
6516 case X86::VFMULCPHZ128rm:
6517 case X86::VFMULCPHZ128rmb:
6518 case X86::VFMULCPHZ128rmbkz:
6519 case X86::VFMULCPHZ128rmkz:
6520 case X86::VFMULCPHZ128rr:
6521 case X86::VFMULCPHZ128rrkz:
6522 case X86::VFMULCPHZ256rm:
6523 case X86::VFMULCPHZ256rmb:
6524 case X86::VFMULCPHZ256rmbkz:
6525 case X86::VFMULCPHZ256rmkz:
6526 case X86::VFMULCPHZ256rr:
6527 case X86::VFMULCPHZ256rrkz:
6528 case X86::VFMULCPHZrm:
6529 case X86::VFMULCPHZrmb:
6530 case X86::VFMULCPHZrmbkz:
6531 case X86::VFMULCPHZrmkz:
6532 case X86::VFMULCPHZrr:
6533 case X86::VFMULCPHZrrb:
6534 case X86::VFMULCPHZrrbkz:
6535 case X86::VFMULCPHZrrkz:
6536 case X86::VFCMULCSHZrm:
6537 case X86::VFCMULCSHZrmkz:
6538 case X86::VFCMULCSHZrr:
6539 case X86::VFCMULCSHZrrb:
6540 case X86::VFCMULCSHZrrbkz:
6541 case X86::VFCMULCSHZrrkz:
6542 case X86::VFMULCSHZrm:
6543 case X86::VFMULCSHZrmkz:
6544 case X86::VFMULCSHZrr:
6545 case X86::VFMULCSHZrrb:
6546 case X86::VFMULCSHZrrbkz:
6547 case X86::VFMULCSHZrrkz:
6548 return Subtarget.hasMULCFalseDeps();
6549 case X86::VPERMDYrm:
6550 case X86::VPERMDYrr:
6551 case X86::VPERMQYmi:
6552 case X86::VPERMQYri:
6553 case X86::VPERMPSYrm:
6554 case X86::VPERMPSYrr:
6555 case X86::VPERMPDYmi:
6556 case X86::VPERMPDYri:
6557 case X86::VPERMDZ256rm:
6558 case X86::VPERMDZ256rmb:
6559 case X86::VPERMDZ256rmbkz:
6560 case X86::VPERMDZ256rmkz:
6561 case X86::VPERMDZ256rr:
6562 case X86::VPERMDZ256rrkz:
6563 case X86::VPERMDZrm:
6564 case X86::VPERMDZrmb:
6565 case X86::VPERMDZrmbkz:
6566 case X86::VPERMDZrmkz:
6567 case X86::VPERMDZrr:
6568 case X86::VPERMDZrrkz:
6569 case X86::VPERMQZ256mbi:
6570 case X86::VPERMQZ256mbikz:
6571 case X86::VPERMQZ256mi:
6572 case X86::VPERMQZ256mikz:
6573 case X86::VPERMQZ256ri:
6574 case X86::VPERMQZ256rikz:
6575 case X86::VPERMQZ256rm:
6576 case X86::VPERMQZ256rmb:
6577 case X86::VPERMQZ256rmbkz:
6578 case X86::VPERMQZ256rmkz:
6579 case X86::VPERMQZ256rr:
6580 case X86::VPERMQZ256rrkz:
6581 case X86::VPERMQZmbi:
6582 case X86::VPERMQZmbikz:
6583 case X86::VPERMQZmi:
6584 case X86::VPERMQZmikz:
6585 case X86::VPERMQZri:
6586 case X86::VPERMQZrikz:
6587 case X86::VPERMQZrm:
6588 case X86::VPERMQZrmb:
6589 case X86::VPERMQZrmbkz:
6590 case X86::VPERMQZrmkz:
6591 case X86::VPERMQZrr:
6592 case X86::VPERMQZrrkz:
6593 case X86::VPERMPSZ256rm:
6594 case X86::VPERMPSZ256rmb:
6595 case X86::VPERMPSZ256rmbkz:
6596 case X86::VPERMPSZ256rmkz:
6597 case X86::VPERMPSZ256rr:
6598 case X86::VPERMPSZ256rrkz:
6599 case X86::VPERMPSZrm:
6600 case X86::VPERMPSZrmb:
6601 case X86::VPERMPSZrmbkz:
6602 case X86::VPERMPSZrmkz:
6603 case X86::VPERMPSZrr:
6604 case X86::VPERMPSZrrkz:
6605 case X86::VPERMPDZ256mbi:
6606 case X86::VPERMPDZ256mbikz:
6607 case X86::VPERMPDZ256mi:
6608 case X86::VPERMPDZ256mikz:
6609 case X86::VPERMPDZ256ri:
6610 case X86::VPERMPDZ256rikz:
6611 case X86::VPERMPDZ256rm:
6612 case X86::VPERMPDZ256rmb:
6613 case X86::VPERMPDZ256rmbkz:
6614 case X86::VPERMPDZ256rmkz:
6615 case X86::VPERMPDZ256rr:
6616 case X86::VPERMPDZ256rrkz:
6617 case X86::VPERMPDZmbi:
6618 case X86::VPERMPDZmbikz:
6619 case X86::VPERMPDZmi:
6620 case X86::VPERMPDZmikz:
6621 case X86::VPERMPDZri:
6622 case X86::VPERMPDZrikz:
6623 case X86::VPERMPDZrm:
6624 case X86::VPERMPDZrmb:
6625 case X86::VPERMPDZrmbkz:
6626 case X86::VPERMPDZrmkz:
6627 case X86::VPERMPDZrr:
6628 case X86::VPERMPDZrrkz:
6629 return Subtarget.hasPERMFalseDeps();
6630 case X86::VRANGEPDZ128rmbi:
6631 case X86::VRANGEPDZ128rmbikz:
6632 case X86::VRANGEPDZ128rmi:
6633 case X86::VRANGEPDZ128rmikz:
6634 case X86::VRANGEPDZ128rri:
6635 case X86::VRANGEPDZ128rrikz:
6636 case X86::VRANGEPDZ256rmbi:
6637 case X86::VRANGEPDZ256rmbikz:
6638 case X86::VRANGEPDZ256rmi:
6639 case X86::VRANGEPDZ256rmikz:
6640 case X86::VRANGEPDZ256rri:
6641 case X86::VRANGEPDZ256rrikz:
6642 case X86::VRANGEPDZrmbi:
6643 case X86::VRANGEPDZrmbikz:
6644 case X86::VRANGEPDZrmi:
6645 case X86::VRANGEPDZrmikz:
6646 case X86::VRANGEPDZrri:
6647 case X86::VRANGEPDZrrib:
6648 case X86::VRANGEPDZrribkz:
6649 case X86::VRANGEPDZrrikz:
6650 case X86::VRANGEPSZ128rmbi:
6651 case X86::VRANGEPSZ128rmbikz:
6652 case X86::VRANGEPSZ128rmi:
6653 case X86::VRANGEPSZ128rmikz:
6654 case X86::VRANGEPSZ128rri:
6655 case X86::VRANGEPSZ128rrikz:
6656 case X86::VRANGEPSZ256rmbi:
6657 case X86::VRANGEPSZ256rmbikz:
6658 case X86::VRANGEPSZ256rmi:
6659 case X86::VRANGEPSZ256rmikz:
6660 case X86::VRANGEPSZ256rri:
6661 case X86::VRANGEPSZ256rrikz:
6662 case X86::VRANGEPSZrmbi:
6663 case X86::VRANGEPSZrmbikz:
6664 case X86::VRANGEPSZrmi:
6665 case X86::VRANGEPSZrmikz:
6666 case X86::VRANGEPSZrri:
6667 case X86::VRANGEPSZrrib:
6668 case X86::VRANGEPSZrribkz:
6669 case X86::VRANGEPSZrrikz:
6670 case X86::VRANGESDZrmi:
6671 case X86::VRANGESDZrmikz:
6672 case X86::VRANGESDZrri:
6673 case X86::VRANGESDZrrib:
6674 case X86::VRANGESDZrribkz:
6675 case X86::VRANGESDZrrikz:
6676 case X86::VRANGESSZrmi:
6677 case X86::VRANGESSZrmikz:
6678 case X86::VRANGESSZrri:
6679 case X86::VRANGESSZrrib:
6680 case X86::VRANGESSZrribkz:
6681 case X86::VRANGESSZrrikz:
6682 return Subtarget.hasRANGEFalseDeps();
6683 case X86::VGETMANTSSZrmi:
6684 case X86::VGETMANTSSZrmikz:
6685 case X86::VGETMANTSSZrri:
6686 case X86::VGETMANTSSZrrib:
6687 case X86::VGETMANTSSZrribkz:
6688 case X86::VGETMANTSSZrrikz:
6689 case X86::VGETMANTSDZrmi:
6690 case X86::VGETMANTSDZrmikz:
6691 case X86::VGETMANTSDZrri:
6692 case X86::VGETMANTSDZrrib:
6693 case X86::VGETMANTSDZrribkz:
6694 case X86::VGETMANTSDZrrikz:
6695 case X86::VGETMANTSHZrmi:
6696 case X86::VGETMANTSHZrmikz:
6697 case X86::VGETMANTSHZrri:
6698 case X86::VGETMANTSHZrrib:
6699 case X86::VGETMANTSHZrribkz:
6700 case X86::VGETMANTSHZrrikz:
6701 case X86::VGETMANTPSZ128rmbi:
6702 case X86::VGETMANTPSZ128rmbikz:
6703 case X86::VGETMANTPSZ128rmi:
6704 case X86::VGETMANTPSZ128rmikz:
6705 case X86::VGETMANTPSZ256rmbi:
6706 case X86::VGETMANTPSZ256rmbikz:
6707 case X86::VGETMANTPSZ256rmi:
6708 case X86::VGETMANTPSZ256rmikz:
6709 case X86::VGETMANTPSZrmbi:
6710 case X86::VGETMANTPSZrmbikz:
6711 case X86::VGETMANTPSZrmi:
6712 case X86::VGETMANTPSZrmikz:
6713 case X86::VGETMANTPDZ128rmbi:
6714 case X86::VGETMANTPDZ128rmbikz:
6715 case X86::VGETMANTPDZ128rmi:
6716 case X86::VGETMANTPDZ128rmikz:
6717 case X86::VGETMANTPDZ256rmbi:
6718 case X86::VGETMANTPDZ256rmbikz:
6719 case X86::VGETMANTPDZ256rmi:
6720 case X86::VGETMANTPDZ256rmikz:
6721 case X86::VGETMANTPDZrmbi:
6722 case X86::VGETMANTPDZrmbikz:
6723 case X86::VGETMANTPDZrmi:
6724 case X86::VGETMANTPDZrmikz:
6725 return Subtarget.hasGETMANTFalseDeps();
6726 case X86::VPMULLQZ128rm:
6727 case X86::VPMULLQZ128rmb:
6728 case X86::VPMULLQZ128rmbkz:
6729 case X86::VPMULLQZ128rmkz:
6730 case X86::VPMULLQZ128rr:
6731 case X86::VPMULLQZ128rrkz:
6732 case X86::VPMULLQZ256rm:
6733 case X86::VPMULLQZ256rmb:
6734 case X86::VPMULLQZ256rmbkz:
6735 case X86::VPMULLQZ256rmkz:
6736 case X86::VPMULLQZ256rr:
6737 case X86::VPMULLQZ256rrkz:
6738 case X86::VPMULLQZrm:
6739 case X86::VPMULLQZrmb:
6740 case X86::VPMULLQZrmbkz:
6741 case X86::VPMULLQZrmkz:
6742 case X86::VPMULLQZrr:
6743 case X86::VPMULLQZrrkz:
6744 return Subtarget.hasMULLQFalseDeps();
6745 // GPR
6746 case X86::POPCNT32rm:
6747 case X86::POPCNT32rr:
6748 case X86::POPCNT64rm:
6749 case X86::POPCNT64rr:
6750 return Subtarget.hasPOPCNTFalseDeps();
6751 case X86::LZCNT32rm:
6752 case X86::LZCNT32rr:
6753 case X86::LZCNT64rm:
6754 case X86::LZCNT64rr:
6755 case X86::TZCNT32rm:
6756 case X86::TZCNT32rr:
6757 case X86::TZCNT64rm:
6758 case X86::TZCNT64rr:
6759 return Subtarget.hasLZCNTFalseDeps();
6760 }
6761
6762 return false;
6763}
6764
6765/// Inform the BreakFalseDeps pass how many idle
6766/// instructions we would like before a partial register update.
6767unsigned X86InstrInfo::getPartialRegUpdateClearance(
6768 const MachineInstr &MI, unsigned OpNum,
6769 const TargetRegisterInfo *TRI) const {
6770
6771 if (OpNum != 0)
6772 return 0;
6773
6774 // NDD ops with 8/16b results may appear to be partial register
6775 // updates after register allocation.
6776 bool HasNDDPartialWrite = false;
6777 if (X86II::hasNewDataDest(TSFlags: MI.getDesc().TSFlags)) {
6778 Register Reg = MI.getOperand(i: 0).getReg();
6779 if (!Reg.isVirtual())
6780 HasNDDPartialWrite =
6781 X86::GR8RegClass.contains(Reg) || X86::GR16RegClass.contains(Reg);
6782 }
6783
6784 if (!(HasNDDPartialWrite || hasPartialRegUpdate(Opcode: MI.getOpcode(), Subtarget)))
6785 return 0;
6786
6787 // Check if the result register is also used as a source.
6788 // For non-NDD ops, this means a partial update is wanted, hence we return 0.
6789 // For NDD ops, this means it is possible to compress the instruction
6790 // to a legacy form in CompressEVEX, which would create an unwanted partial
6791 // update, so we return the clearance.
6792 const MachineOperand &MO = MI.getOperand(i: 0);
6793 Register Reg = MO.getReg();
6794 bool ReadsReg = false;
6795 if (Reg.isVirtual())
6796 ReadsReg = (MO.readsReg() || MI.readsVirtualRegister(Reg));
6797 else
6798 ReadsReg = MI.readsRegister(Reg, TRI);
6799 if (ReadsReg != HasNDDPartialWrite)
6800 return 0;
6801
6802 // If any instructions in the clearance range are reading Reg, insert a
6803 // dependency breaking instruction, which is inexpensive and is likely to
6804 // be hidden in other instruction's cycles.
6805 return PartialRegUpdateClearance;
6806}
6807
6808// Return true for any instruction the copies the high bits of the first source
6809// operand into the unused high bits of the destination operand.
6810// Also returns true for instructions that have two inputs where one may
6811// be undef and we want it to use the same register as the other input.
6812static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
6813 bool ForLoadFold = false) {
6814 // Set the OpNum parameter to the first source operand.
6815 switch (Opcode) {
6816 case X86::MMX_PUNPCKHBWrr:
6817 case X86::MMX_PUNPCKHWDrr:
6818 case X86::MMX_PUNPCKHDQrr:
6819 case X86::MMX_PUNPCKLBWrr:
6820 case X86::MMX_PUNPCKLWDrr:
6821 case X86::MMX_PUNPCKLDQrr:
6822 case X86::MOVHLPSrr:
6823 case X86::PACKSSWBrr:
6824 case X86::PACKUSWBrr:
6825 case X86::PACKSSDWrr:
6826 case X86::PACKUSDWrr:
6827 case X86::PUNPCKHBWrr:
6828 case X86::PUNPCKLBWrr:
6829 case X86::PUNPCKHWDrr:
6830 case X86::PUNPCKLWDrr:
6831 case X86::PUNPCKHDQrr:
6832 case X86::PUNPCKLDQrr:
6833 case X86::PUNPCKHQDQrr:
6834 case X86::PUNPCKLQDQrr:
6835 case X86::SHUFPDrri:
6836 case X86::SHUFPSrri:
6837 // These instructions are sometimes used with an undef first or second
6838 // source. Return true here so BreakFalseDeps will assign this source to the
6839 // same register as the first source to avoid a false dependency.
6840 // Operand 1 of these instructions is tied so they're separate from their
6841 // VEX counterparts.
6842 return OpNum == 2 && !ForLoadFold;
6843
6844 case X86::VMOVLHPSrr:
6845 case X86::VMOVLHPSZrr:
6846 case X86::VPACKSSWBrr:
6847 case X86::VPACKUSWBrr:
6848 case X86::VPACKSSDWrr:
6849 case X86::VPACKUSDWrr:
6850 case X86::VPACKSSWBZ128rr:
6851 case X86::VPACKUSWBZ128rr:
6852 case X86::VPACKSSDWZ128rr:
6853 case X86::VPACKUSDWZ128rr:
6854 case X86::VPERM2F128rri:
6855 case X86::VPERM2I128rri:
6856 case X86::VSHUFF32X4Z256rri:
6857 case X86::VSHUFF32X4Zrri:
6858 case X86::VSHUFF64X2Z256rri:
6859 case X86::VSHUFF64X2Zrri:
6860 case X86::VSHUFI32X4Z256rri:
6861 case X86::VSHUFI32X4Zrri:
6862 case X86::VSHUFI64X2Z256rri:
6863 case X86::VSHUFI64X2Zrri:
6864 case X86::VPUNPCKHBWrr:
6865 case X86::VPUNPCKLBWrr:
6866 case X86::VPUNPCKHBWYrr:
6867 case X86::VPUNPCKLBWYrr:
6868 case X86::VPUNPCKHBWZ128rr:
6869 case X86::VPUNPCKLBWZ128rr:
6870 case X86::VPUNPCKHBWZ256rr:
6871 case X86::VPUNPCKLBWZ256rr:
6872 case X86::VPUNPCKHBWZrr:
6873 case X86::VPUNPCKLBWZrr:
6874 case X86::VPUNPCKHWDrr:
6875 case X86::VPUNPCKLWDrr:
6876 case X86::VPUNPCKHWDYrr:
6877 case X86::VPUNPCKLWDYrr:
6878 case X86::VPUNPCKHWDZ128rr:
6879 case X86::VPUNPCKLWDZ128rr:
6880 case X86::VPUNPCKHWDZ256rr:
6881 case X86::VPUNPCKLWDZ256rr:
6882 case X86::VPUNPCKHWDZrr:
6883 case X86::VPUNPCKLWDZrr:
6884 case X86::VPUNPCKHDQrr:
6885 case X86::VPUNPCKLDQrr:
6886 case X86::VPUNPCKHDQYrr:
6887 case X86::VPUNPCKLDQYrr:
6888 case X86::VPUNPCKHDQZ128rr:
6889 case X86::VPUNPCKLDQZ128rr:
6890 case X86::VPUNPCKHDQZ256rr:
6891 case X86::VPUNPCKLDQZ256rr:
6892 case X86::VPUNPCKHDQZrr:
6893 case X86::VPUNPCKLDQZrr:
6894 case X86::VPUNPCKHQDQrr:
6895 case X86::VPUNPCKLQDQrr:
6896 case X86::VPUNPCKHQDQYrr:
6897 case X86::VPUNPCKLQDQYrr:
6898 case X86::VPUNPCKHQDQZ128rr:
6899 case X86::VPUNPCKLQDQZ128rr:
6900 case X86::VPUNPCKHQDQZ256rr:
6901 case X86::VPUNPCKLQDQZ256rr:
6902 case X86::VPUNPCKHQDQZrr:
6903 case X86::VPUNPCKLQDQZrr:
6904 // These instructions are sometimes used with an undef first or second
6905 // source. Return true here so BreakFalseDeps will assign this source to the
6906 // same register as the first source to avoid a false dependency.
6907 return (OpNum == 1 || OpNum == 2) && !ForLoadFold;
6908
6909 case X86::VCVTSI2SSrr:
6910 case X86::VCVTSI2SSrm:
6911 case X86::VCVTSI2SSrr_Int:
6912 case X86::VCVTSI2SSrm_Int:
6913 case X86::VCVTSI642SSrr:
6914 case X86::VCVTSI642SSrm:
6915 case X86::VCVTSI642SSrr_Int:
6916 case X86::VCVTSI642SSrm_Int:
6917 case X86::VCVTSI2SDrr:
6918 case X86::VCVTSI2SDrm:
6919 case X86::VCVTSI2SDrr_Int:
6920 case X86::VCVTSI2SDrm_Int:
6921 case X86::VCVTSI642SDrr:
6922 case X86::VCVTSI642SDrm:
6923 case X86::VCVTSI642SDrr_Int:
6924 case X86::VCVTSI642SDrm_Int:
6925 // AVX-512
6926 case X86::VCVTSI2SSZrr:
6927 case X86::VCVTSI2SSZrm:
6928 case X86::VCVTSI2SSZrr_Int:
6929 case X86::VCVTSI2SSZrrb_Int:
6930 case X86::VCVTSI2SSZrm_Int:
6931 case X86::VCVTSI642SSZrr:
6932 case X86::VCVTSI642SSZrm:
6933 case X86::VCVTSI642SSZrr_Int:
6934 case X86::VCVTSI642SSZrrb_Int:
6935 case X86::VCVTSI642SSZrm_Int:
6936 case X86::VCVTSI2SDZrr:
6937 case X86::VCVTSI2SDZrm:
6938 case X86::VCVTSI2SDZrr_Int:
6939 case X86::VCVTSI2SDZrm_Int:
6940 case X86::VCVTSI642SDZrr:
6941 case X86::VCVTSI642SDZrm:
6942 case X86::VCVTSI642SDZrr_Int:
6943 case X86::VCVTSI642SDZrrb_Int:
6944 case X86::VCVTSI642SDZrm_Int:
6945 case X86::VCVTUSI2SSZrr:
6946 case X86::VCVTUSI2SSZrm:
6947 case X86::VCVTUSI2SSZrr_Int:
6948 case X86::VCVTUSI2SSZrrb_Int:
6949 case X86::VCVTUSI2SSZrm_Int:
6950 case X86::VCVTUSI642SSZrr:
6951 case X86::VCVTUSI642SSZrm:
6952 case X86::VCVTUSI642SSZrr_Int:
6953 case X86::VCVTUSI642SSZrrb_Int:
6954 case X86::VCVTUSI642SSZrm_Int:
6955 case X86::VCVTUSI2SDZrr:
6956 case X86::VCVTUSI2SDZrm:
6957 case X86::VCVTUSI2SDZrr_Int:
6958 case X86::VCVTUSI2SDZrm_Int:
6959 case X86::VCVTUSI642SDZrr:
6960 case X86::VCVTUSI642SDZrm:
6961 case X86::VCVTUSI642SDZrr_Int:
6962 case X86::VCVTUSI642SDZrrb_Int:
6963 case X86::VCVTUSI642SDZrm_Int:
6964 case X86::VCVTSI2SHZrr:
6965 case X86::VCVTSI2SHZrm:
6966 case X86::VCVTSI2SHZrr_Int:
6967 case X86::VCVTSI2SHZrrb_Int:
6968 case X86::VCVTSI2SHZrm_Int:
6969 case X86::VCVTSI642SHZrr:
6970 case X86::VCVTSI642SHZrm:
6971 case X86::VCVTSI642SHZrr_Int:
6972 case X86::VCVTSI642SHZrrb_Int:
6973 case X86::VCVTSI642SHZrm_Int:
6974 case X86::VCVTUSI2SHZrr:
6975 case X86::VCVTUSI2SHZrm:
6976 case X86::VCVTUSI2SHZrr_Int:
6977 case X86::VCVTUSI2SHZrrb_Int:
6978 case X86::VCVTUSI2SHZrm_Int:
6979 case X86::VCVTUSI642SHZrr:
6980 case X86::VCVTUSI642SHZrm:
6981 case X86::VCVTUSI642SHZrr_Int:
6982 case X86::VCVTUSI642SHZrrb_Int:
6983 case X86::VCVTUSI642SHZrm_Int:
6984 // Load folding won't effect the undef register update since the input is
6985 // a GPR.
6986 return OpNum == 1 && !ForLoadFold;
6987 case X86::VCVTSD2SSrr:
6988 case X86::VCVTSD2SSrm:
6989 case X86::VCVTSD2SSrr_Int:
6990 case X86::VCVTSD2SSrm_Int:
6991 case X86::VCVTSS2SDrr:
6992 case X86::VCVTSS2SDrm:
6993 case X86::VCVTSS2SDrr_Int:
6994 case X86::VCVTSS2SDrm_Int:
6995 case X86::VRCPSSr:
6996 case X86::VRCPSSr_Int:
6997 case X86::VRCPSSm:
6998 case X86::VRCPSSm_Int:
6999 case X86::VROUNDSDri:
7000 case X86::VROUNDSDmi:
7001 case X86::VROUNDSDri_Int:
7002 case X86::VROUNDSDmi_Int:
7003 case X86::VROUNDSSri:
7004 case X86::VROUNDSSmi:
7005 case X86::VROUNDSSri_Int:
7006 case X86::VROUNDSSmi_Int:
7007 case X86::VRSQRTSSr:
7008 case X86::VRSQRTSSr_Int:
7009 case X86::VRSQRTSSm:
7010 case X86::VRSQRTSSm_Int:
7011 case X86::VSQRTSSr:
7012 case X86::VSQRTSSr_Int:
7013 case X86::VSQRTSSm:
7014 case X86::VSQRTSSm_Int:
7015 case X86::VSQRTSDr:
7016 case X86::VSQRTSDr_Int:
7017 case X86::VSQRTSDm:
7018 case X86::VSQRTSDm_Int:
7019 // AVX-512
7020 case X86::VCVTSD2SSZrr:
7021 case X86::VCVTSD2SSZrr_Int:
7022 case X86::VCVTSD2SSZrrb_Int:
7023 case X86::VCVTSD2SSZrm:
7024 case X86::VCVTSD2SSZrm_Int:
7025 case X86::VCVTSS2SDZrr:
7026 case X86::VCVTSS2SDZrr_Int:
7027 case X86::VCVTSS2SDZrrb_Int:
7028 case X86::VCVTSS2SDZrm:
7029 case X86::VCVTSS2SDZrm_Int:
7030 case X86::VGETEXPSDZr:
7031 case X86::VGETEXPSDZrb:
7032 case X86::VGETEXPSDZm:
7033 case X86::VGETEXPSSZr:
7034 case X86::VGETEXPSSZrb:
7035 case X86::VGETEXPSSZm:
7036 case X86::VGETMANTSDZrri:
7037 case X86::VGETMANTSDZrrib:
7038 case X86::VGETMANTSDZrmi:
7039 case X86::VGETMANTSSZrri:
7040 case X86::VGETMANTSSZrrib:
7041 case X86::VGETMANTSSZrmi:
7042 case X86::VRNDSCALESDZrri:
7043 case X86::VRNDSCALESDZrri_Int:
7044 case X86::VRNDSCALESDZrrib_Int:
7045 case X86::VRNDSCALESDZrmi:
7046 case X86::VRNDSCALESDZrmi_Int:
7047 case X86::VRNDSCALESSZrri:
7048 case X86::VRNDSCALESSZrri_Int:
7049 case X86::VRNDSCALESSZrrib_Int:
7050 case X86::VRNDSCALESSZrmi:
7051 case X86::VRNDSCALESSZrmi_Int:
7052 case X86::VRCP14SDZrr:
7053 case X86::VRCP14SDZrm:
7054 case X86::VRCP14SSZrr:
7055 case X86::VRCP14SSZrm:
7056 case X86::VRCPSHZrr:
7057 case X86::VRCPSHZrm:
7058 case X86::VRSQRTSHZrr:
7059 case X86::VRSQRTSHZrm:
7060 case X86::VREDUCESHZrmi:
7061 case X86::VREDUCESHZrri:
7062 case X86::VREDUCESHZrrib:
7063 case X86::VGETEXPSHZr:
7064 case X86::VGETEXPSHZrb:
7065 case X86::VGETEXPSHZm:
7066 case X86::VGETMANTSHZrri:
7067 case X86::VGETMANTSHZrrib:
7068 case X86::VGETMANTSHZrmi:
7069 case X86::VRNDSCALESHZrri:
7070 case X86::VRNDSCALESHZrri_Int:
7071 case X86::VRNDSCALESHZrrib_Int:
7072 case X86::VRNDSCALESHZrmi:
7073 case X86::VRNDSCALESHZrmi_Int:
7074 case X86::VSQRTSHZr:
7075 case X86::VSQRTSHZr_Int:
7076 case X86::VSQRTSHZrb_Int:
7077 case X86::VSQRTSHZm:
7078 case X86::VSQRTSHZm_Int:
7079 case X86::VRCP28SDZr:
7080 case X86::VRCP28SDZrb:
7081 case X86::VRCP28SDZm:
7082 case X86::VRCP28SSZr:
7083 case X86::VRCP28SSZrb:
7084 case X86::VRCP28SSZm:
7085 case X86::VREDUCESSZrmi:
7086 case X86::VREDUCESSZrri:
7087 case X86::VREDUCESSZrrib:
7088 case X86::VRSQRT14SDZrr:
7089 case X86::VRSQRT14SDZrm:
7090 case X86::VRSQRT14SSZrr:
7091 case X86::VRSQRT14SSZrm:
7092 case X86::VRSQRT28SDZr:
7093 case X86::VRSQRT28SDZrb:
7094 case X86::VRSQRT28SDZm:
7095 case X86::VRSQRT28SSZr:
7096 case X86::VRSQRT28SSZrb:
7097 case X86::VRSQRT28SSZm:
7098 case X86::VSQRTSSZr:
7099 case X86::VSQRTSSZr_Int:
7100 case X86::VSQRTSSZrb_Int:
7101 case X86::VSQRTSSZm:
7102 case X86::VSQRTSSZm_Int:
7103 case X86::VSQRTSDZr:
7104 case X86::VSQRTSDZr_Int:
7105 case X86::VSQRTSDZrb_Int:
7106 case X86::VSQRTSDZm:
7107 case X86::VSQRTSDZm_Int:
7108 case X86::VCVTSD2SHZrr:
7109 case X86::VCVTSD2SHZrr_Int:
7110 case X86::VCVTSD2SHZrrb_Int:
7111 case X86::VCVTSD2SHZrm:
7112 case X86::VCVTSD2SHZrm_Int:
7113 case X86::VCVTSS2SHZrr:
7114 case X86::VCVTSS2SHZrr_Int:
7115 case X86::VCVTSS2SHZrrb_Int:
7116 case X86::VCVTSS2SHZrm:
7117 case X86::VCVTSS2SHZrm_Int:
7118 case X86::VCVTSH2SDZrr:
7119 case X86::VCVTSH2SDZrr_Int:
7120 case X86::VCVTSH2SDZrrb_Int:
7121 case X86::VCVTSH2SDZrm:
7122 case X86::VCVTSH2SDZrm_Int:
7123 case X86::VCVTSH2SSZrr:
7124 case X86::VCVTSH2SSZrr_Int:
7125 case X86::VCVTSH2SSZrrb_Int:
7126 case X86::VCVTSH2SSZrm:
7127 case X86::VCVTSH2SSZrm_Int:
7128 return OpNum == 1;
7129 case X86::VMOVSSZrrk:
7130 case X86::VMOVSDZrrk:
7131 return OpNum == 3 && !ForLoadFold;
7132 case X86::VMOVSSZrrkz:
7133 case X86::VMOVSDZrrkz:
7134 return OpNum == 2 && !ForLoadFold;
7135 }
7136
7137 return false;
7138}
7139
7140/// Inform the BreakFalseDeps pass how many idle instructions we would like
7141/// before certain undef register reads.
7142///
7143/// This catches the VCVTSI2SD family of instructions:
7144///
7145/// vcvtsi2sdq %rax, undef %xmm0, %xmm14
7146///
7147/// We should to be careful *not* to catch VXOR idioms which are presumably
7148/// handled specially in the pipeline:
7149///
7150/// vxorps undef %xmm1, undef %xmm1, %xmm1
7151///
7152/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
7153/// high bits that are passed-through are not live.
7154unsigned
7155X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
7156 const TargetRegisterInfo *TRI) const {
7157 const MachineOperand &MO = MI.getOperand(i: OpNum);
7158 if (MO.getReg().isPhysical() && hasUndefRegUpdate(Opcode: MI.getOpcode(), OpNum))
7159 return UndefRegClearance;
7160
7161 return 0;
7162}
7163
7164void X86InstrInfo::breakPartialRegDependency(
7165 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
7166 Register Reg = MI.getOperand(i: OpNum).getReg();
7167 // If MI kills this register, the false dependence is already broken.
7168 if (MI.killsRegister(Reg, TRI))
7169 return;
7170
7171 if (X86::VR128RegClass.contains(Reg)) {
7172 // These instructions are all floating point domain, so xorps is the best
7173 // choice.
7174 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
7175 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc), DestReg: Reg)
7176 .addReg(RegNo: Reg, Flags: RegState::Undef)
7177 .addReg(RegNo: Reg, Flags: RegState::Undef);
7178 MI.addRegisterKilled(IncomingReg: Reg, RegInfo: TRI, AddIfNotFound: true);
7179 } else if (X86::VR256RegClass.contains(Reg)) {
7180 // Use vxorps to clear the full ymm register.
7181 // It wants to read and write the xmm sub-register.
7182 Register XReg = TRI->getSubReg(Reg, Idx: X86::sub_xmm);
7183 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::VXORPSrr), DestReg: XReg)
7184 .addReg(RegNo: XReg, Flags: RegState::Undef)
7185 .addReg(RegNo: XReg, Flags: RegState::Undef)
7186 .addReg(RegNo: Reg, Flags: RegState::ImplicitDefine);
7187 MI.addRegisterKilled(IncomingReg: Reg, RegInfo: TRI, AddIfNotFound: true);
7188 } else if (X86::VR128XRegClass.contains(Reg)) {
7189 // Only handle VLX targets.
7190 if (!Subtarget.hasVLX())
7191 return;
7192 // Since vxorps requires AVX512DQ, vpxord should be the best choice.
7193 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::VPXORDZ128rr), DestReg: Reg)
7194 .addReg(RegNo: Reg, Flags: RegState::Undef)
7195 .addReg(RegNo: Reg, Flags: RegState::Undef);
7196 MI.addRegisterKilled(IncomingReg: Reg, RegInfo: TRI, AddIfNotFound: true);
7197 } else if (X86::VR256XRegClass.contains(Reg) ||
7198 X86::VR512RegClass.contains(Reg)) {
7199 // Only handle VLX targets.
7200 if (!Subtarget.hasVLX())
7201 return;
7202 // Use vpxord to clear the full ymm/zmm register.
7203 // It wants to read and write the xmm sub-register.
7204 Register XReg = TRI->getSubReg(Reg, Idx: X86::sub_xmm);
7205 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::VPXORDZ128rr), DestReg: XReg)
7206 .addReg(RegNo: XReg, Flags: RegState::Undef)
7207 .addReg(RegNo: XReg, Flags: RegState::Undef)
7208 .addReg(RegNo: Reg, Flags: RegState::ImplicitDefine);
7209 MI.addRegisterKilled(IncomingReg: Reg, RegInfo: TRI, AddIfNotFound: true);
7210 } else if (X86::GR64RegClass.contains(Reg)) {
7211 // Using XOR32rr because it has shorter encoding and zeros up the upper bits
7212 // as well.
7213 Register XReg = TRI->getSubReg(Reg, Idx: X86::sub_32bit);
7214 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::XOR32rr), DestReg: XReg)
7215 .addReg(RegNo: XReg, Flags: RegState::Undef)
7216 .addReg(RegNo: XReg, Flags: RegState::Undef)
7217 .addReg(RegNo: Reg, Flags: RegState::ImplicitDefine);
7218 MI.addRegisterKilled(IncomingReg: Reg, RegInfo: TRI, AddIfNotFound: true);
7219 } else if (X86::GR32RegClass.contains(Reg)) {
7220 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::XOR32rr), DestReg: Reg)
7221 .addReg(RegNo: Reg, Flags: RegState::Undef)
7222 .addReg(RegNo: Reg, Flags: RegState::Undef);
7223 MI.addRegisterKilled(IncomingReg: Reg, RegInfo: TRI, AddIfNotFound: true);
7224 } else if ((X86::GR16RegClass.contains(Reg) ||
7225 X86::GR8RegClass.contains(Reg)) &&
7226 X86II::hasNewDataDest(TSFlags: MI.getDesc().TSFlags)) {
7227 // This case is only expected for NDD ops which appear to be partial
7228 // writes, but are not due to the zeroing of the upper part. Here
7229 // we add an implicit def of the superegister, which prevents
7230 // CompressEVEX from converting this to a legacy form.
7231 Register SuperReg = getX86SubSuperRegister(Reg, Size: 64);
7232 MachineInstrBuilder BuildMI(*MI.getParent()->getParent(), &MI);
7233 if (!MI.definesRegister(Reg: SuperReg, /*TRI=*/nullptr))
7234 BuildMI.addReg(RegNo: SuperReg, Flags: RegState::ImplicitDefine);
7235 }
7236}
7237
7238static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
7239 int PtrOffset = 0) {
7240 unsigned NumAddrOps = MOs.size();
7241
7242 if (NumAddrOps < 4) {
7243 // FrameIndex only - add an immediate offset (whether its zero or not).
7244 for (unsigned i = 0; i != NumAddrOps; ++i)
7245 MIB.add(MO: MOs[i]);
7246 addOffset(MIB, Offset: PtrOffset);
7247 } else {
7248 // General Memory Addressing - we need to add any offset to an existing
7249 // offset.
7250 assert(MOs.size() == 5 && "Unexpected memory operand list length");
7251 for (unsigned i = 0; i != NumAddrOps; ++i) {
7252 const MachineOperand &MO = MOs[i];
7253 if (i == 3 && PtrOffset != 0) {
7254 MIB.addDisp(Disp: MO, off: PtrOffset);
7255 } else {
7256 MIB.add(MO);
7257 }
7258 }
7259 }
7260}
7261
7262static void updateOperandRegConstraints(MachineFunction &MF,
7263 MachineInstr &NewMI,
7264 const TargetInstrInfo &TII) {
7265 MachineRegisterInfo &MRI = MF.getRegInfo();
7266
7267 for (int Idx : llvm::seq<int>(Begin: 0, End: NewMI.getNumOperands())) {
7268 MachineOperand &MO = NewMI.getOperand(i: Idx);
7269 // We only need to update constraints on virtual register operands.
7270 if (!MO.isReg())
7271 continue;
7272 Register Reg = MO.getReg();
7273 if (!Reg.isVirtual())
7274 continue;
7275
7276 auto *NewRC =
7277 MRI.constrainRegClass(Reg, RC: TII.getRegClass(MCID: NewMI.getDesc(), OpNum: Idx));
7278 if (!NewRC) {
7279 LLVM_DEBUG(
7280 dbgs() << "WARNING: Unable to update register constraint for operand "
7281 << Idx << " of instruction:\n";
7282 NewMI.dump(); dbgs() << "\n");
7283 }
7284 }
7285}
7286
7287static MachineInstr *fuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
7288 ArrayRef<MachineOperand> MOs,
7289 MachineBasicBlock::iterator InsertPt,
7290 MachineInstr &MI,
7291 const TargetInstrInfo &TII) {
7292 // Create the base instruction with the memory operand as the first part.
7293 // Omit the implicit operands, something BuildMI can't do.
7294 MachineInstr *NewMI =
7295 MF.CreateMachineInstr(MCID: TII.get(Opcode), DL: MI.getDebugLoc(), NoImplicit: true);
7296 MachineInstrBuilder MIB(MF, NewMI);
7297 addOperands(MIB, MOs);
7298
7299 // Loop over the rest of the ri operands, converting them over.
7300 unsigned NumOps = MI.getDesc().getNumOperands() - 2;
7301 for (unsigned i = 0; i != NumOps; ++i) {
7302 MachineOperand &MO = MI.getOperand(i: i + 2);
7303 MIB.add(MO);
7304 }
7305 for (const MachineOperand &MO : llvm::drop_begin(RangeOrContainer: MI.operands(), N: NumOps + 2))
7306 MIB.add(MO);
7307
7308 updateOperandRegConstraints(MF, NewMI&: *NewMI, TII);
7309
7310 MachineBasicBlock *MBB = InsertPt->getParent();
7311 MBB->insert(I: InsertPt, MI: NewMI);
7312
7313 return MIB;
7314}
7315
7316static MachineInstr *fuseInst(MachineFunction &MF, unsigned Opcode,
7317 unsigned OpNo, ArrayRef<MachineOperand> MOs,
7318 MachineBasicBlock::iterator InsertPt,
7319 MachineInstr &MI, const TargetInstrInfo &TII,
7320 int PtrOffset = 0) {
7321 // Omit the implicit operands, something BuildMI can't do.
7322 MachineInstr *NewMI =
7323 MF.CreateMachineInstr(MCID: TII.get(Opcode), DL: MI.getDebugLoc(), NoImplicit: true);
7324 MachineInstrBuilder MIB(MF, NewMI);
7325
7326 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
7327 MachineOperand &MO = MI.getOperand(i);
7328 if (i == OpNo) {
7329 assert(MO.isReg() && "Expected to fold into reg operand!");
7330 addOperands(MIB, MOs, PtrOffset);
7331 } else {
7332 MIB.add(MO);
7333 }
7334 }
7335
7336 updateOperandRegConstraints(MF, NewMI&: *NewMI, TII);
7337
7338 // Copy the NoFPExcept flag from the instruction we're fusing.
7339 if (MI.getFlag(Flag: MachineInstr::MIFlag::NoFPExcept))
7340 NewMI->setFlag(MachineInstr::MIFlag::NoFPExcept);
7341
7342 MachineBasicBlock *MBB = InsertPt->getParent();
7343 MBB->insert(I: InsertPt, MI: NewMI);
7344
7345 return MIB;
7346}
7347
7348static MachineInstr *makeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
7349 ArrayRef<MachineOperand> MOs,
7350 MachineBasicBlock::iterator InsertPt,
7351 MachineInstr &MI) {
7352 MachineInstrBuilder MIB = BuildMI(BB&: *InsertPt->getParent(), I: InsertPt,
7353 MIMD: MI.getDebugLoc(), MCID: TII.get(Opcode));
7354 addOperands(MIB, MOs);
7355 return MIB.addImm(Val: 0);
7356}
7357
7358MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
7359 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
7360 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
7361 unsigned Size, Align Alignment) const {
7362 switch (MI.getOpcode()) {
7363 case X86::INSERTPSrri:
7364 case X86::VINSERTPSrri:
7365 case X86::VINSERTPSZrri:
7366 // Attempt to convert the load of inserted vector into a fold load
7367 // of a single float.
7368 if (OpNum == 2) {
7369 unsigned Imm = MI.getOperand(i: MI.getNumOperands() - 1).getImm();
7370 unsigned ZMask = Imm & 15;
7371 unsigned DstIdx = (Imm >> 4) & 3;
7372 unsigned SrcIdx = (Imm >> 6) & 3;
7373
7374 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7375 const TargetRegisterClass *RC = getRegClass(MCID: MI.getDesc(), OpNum);
7376 unsigned RCSize = TRI.getRegSizeInBits(RC: *RC) / 8;
7377 if ((Size == 0 || Size >= 16) && RCSize >= 16 &&
7378 (MI.getOpcode() != X86::INSERTPSrri || Alignment >= Align(4))) {
7379 int PtrOffset = SrcIdx * 4;
7380 unsigned NewImm = (DstIdx << 4) | ZMask;
7381 unsigned NewOpCode =
7382 (MI.getOpcode() == X86::VINSERTPSZrri) ? X86::VINSERTPSZrmi
7383 : (MI.getOpcode() == X86::VINSERTPSrri) ? X86::VINSERTPSrmi
7384 : X86::INSERTPSrmi;
7385 MachineInstr *NewMI =
7386 fuseInst(MF, Opcode: NewOpCode, OpNo: OpNum, MOs, InsertPt, MI, TII: *this, PtrOffset);
7387 NewMI->getOperand(i: NewMI->getNumOperands() - 1).setImm(NewImm);
7388 return NewMI;
7389 }
7390 }
7391 break;
7392 case X86::MOVHLPSrr:
7393 case X86::VMOVHLPSrr:
7394 case X86::VMOVHLPSZrr:
7395 // Move the upper 64-bits of the second operand to the lower 64-bits.
7396 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
7397 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
7398 if (OpNum == 2) {
7399 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7400 const TargetRegisterClass *RC = getRegClass(MCID: MI.getDesc(), OpNum);
7401 unsigned RCSize = TRI.getRegSizeInBits(RC: *RC) / 8;
7402 if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(8)) {
7403 unsigned NewOpCode =
7404 (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm
7405 : (MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm
7406 : X86::MOVLPSrm;
7407 MachineInstr *NewMI =
7408 fuseInst(MF, Opcode: NewOpCode, OpNo: OpNum, MOs, InsertPt, MI, TII: *this, PtrOffset: 8);
7409 return NewMI;
7410 }
7411 }
7412 break;
7413 case X86::UNPCKLPDrr:
7414 // If we won't be able to fold this to the memory form of UNPCKL, use
7415 // MOVHPD instead. Done as custom because we can't have this in the load
7416 // table twice.
7417 if (OpNum == 2) {
7418 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7419 const TargetRegisterClass *RC = getRegClass(MCID: MI.getDesc(), OpNum);
7420 unsigned RCSize = TRI.getRegSizeInBits(RC: *RC) / 8;
7421 if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment < Align(16)) {
7422 MachineInstr *NewMI =
7423 fuseInst(MF, Opcode: X86::MOVHPDrm, OpNo: OpNum, MOs, InsertPt, MI, TII: *this);
7424 return NewMI;
7425 }
7426 }
7427 break;
7428 case X86::MOV32r0:
7429 if (auto *NewMI =
7430 makeM0Inst(TII: *this, Opcode: (Size == 4) ? X86::MOV32mi : X86::MOV64mi32, MOs,
7431 InsertPt, MI))
7432 return NewMI;
7433 break;
7434 }
7435
7436 return nullptr;
7437}
7438
7439static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
7440 MachineInstr &MI) {
7441 if (!hasUndefRegUpdate(Opcode: MI.getOpcode(), OpNum: 1, /*ForLoadFold*/ true) ||
7442 !MI.getOperand(i: 1).isReg())
7443 return false;
7444
7445 // The are two cases we need to handle depending on where in the pipeline
7446 // the folding attempt is being made.
7447 // -Register has the undef flag set.
7448 // -Register is produced by the IMPLICIT_DEF instruction.
7449
7450 if (MI.getOperand(i: 1).isUndef())
7451 return true;
7452
7453 MachineRegisterInfo &RegInfo = MF.getRegInfo();
7454 MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(Reg: MI.getOperand(i: 1).getReg());
7455 return VRegDef && VRegDef->isImplicitDef();
7456}
7457
7458unsigned X86InstrInfo::commuteOperandsForFold(MachineInstr &MI,
7459 unsigned Idx1) const {
7460 unsigned Idx2 = CommuteAnyOperandIndex;
7461 if (!findCommutedOpIndices(MI, SrcOpIdx1&: Idx1, SrcOpIdx2&: Idx2))
7462 return Idx1;
7463
7464 bool HasDef = MI.getDesc().getNumDefs();
7465 Register Reg0 = HasDef ? MI.getOperand(i: 0).getReg() : Register();
7466 Register Reg1 = MI.getOperand(i: Idx1).getReg();
7467 Register Reg2 = MI.getOperand(i: Idx2).getReg();
7468 bool Tied1 = 0 == MI.getDesc().getOperandConstraint(OpNum: Idx1, Constraint: MCOI::TIED_TO);
7469 bool Tied2 = 0 == MI.getDesc().getOperandConstraint(OpNum: Idx2, Constraint: MCOI::TIED_TO);
7470
7471 // If either of the commutable operands are tied to the destination
7472 // then we can not commute + fold.
7473 if ((HasDef && Reg0 == Reg1 && Tied1) || (HasDef && Reg0 == Reg2 && Tied2))
7474 return Idx1;
7475
7476 return commuteInstruction(MI, NewMI: false, OpIdx1: Idx1, OpIdx2: Idx2) ? Idx2 : Idx1;
7477}
7478
7479static void printFailMsgforFold(const MachineInstr &MI, unsigned Idx) {
7480 if (PrintFailedFusing && !MI.isCopy())
7481 dbgs() << "We failed to fuse operand " << Idx << " in " << MI;
7482}
7483
7484MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
7485 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
7486 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
7487 unsigned Size, Align Alignment, bool AllowCommute) const {
7488 bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
7489 unsigned Opc = MI.getOpcode();
7490
7491 // For CPUs that favor the register form of a call or push,
7492 // do not fold loads into calls or pushes, unless optimizing for size
7493 // aggressively.
7494 if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
7495 (Opc == X86::CALL32r || Opc == X86::CALL64r ||
7496 Opc == X86::CALL64r_ImpCall || Opc == X86::PUSH16r ||
7497 Opc == X86::PUSH32r || Opc == X86::PUSH64r))
7498 return nullptr;
7499
7500 // Avoid partial and undef register update stalls unless optimizing for size.
7501 if (!MF.getFunction().hasOptSize() &&
7502 (hasPartialRegUpdate(Opcode: Opc, Subtarget, /*ForLoadFold*/ true) ||
7503 shouldPreventUndefRegUpdateMemFold(MF, MI)))
7504 return nullptr;
7505
7506 unsigned NumOps = MI.getDesc().getNumOperands();
7507 bool IsTwoAddr = NumOps > 1 && OpNum < 2 && MI.getOperand(i: 0).isReg() &&
7508 MI.getOperand(i: 1).isReg() &&
7509 MI.getOperand(i: 0).getReg() == MI.getOperand(i: 1).getReg();
7510
7511 // FIXME: AsmPrinter doesn't know how to handle
7512 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
7513 if (Opc == X86::ADD32ri &&
7514 MI.getOperand(i: 2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
7515 return nullptr;
7516
7517 // GOTTPOFF relocation loads can only be folded into add instructions.
7518 // FIXME: Need to exclude other relocations that only support specific
7519 // instructions.
7520 if (MOs.size() == X86::AddrNumOperands &&
7521 MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
7522 Opc != X86::ADD64rr)
7523 return nullptr;
7524
7525 // Don't fold loads into indirect calls that need a KCFI check as we'll
7526 // have to unfold these in X86TargetLowering::EmitKCFICheck anyway.
7527 if (MI.isCall() && MI.getCFIType())
7528 return nullptr;
7529
7530 // Attempt to fold any custom cases we have.
7531 if (auto *CustomMI = foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt,
7532 Size, Alignment))
7533 return CustomMI;
7534
7535 // Folding a memory location into the two-address part of a two-address
7536 // instruction is different than folding it other places. It requires
7537 // replacing the *two* registers with the memory location.
7538 //
7539 // Utilize the mapping NonNDD -> RMW for the NDD variant.
7540 unsigned NonNDOpc = Subtarget.hasNDD() ? X86::getNonNDVariant(Opc) : 0U;
7541 // Disable memory folding for NDD instructions.
7542 if (NonNDOpc && !Subtarget.hasNDDM())
7543 return nullptr;
7544
7545 const X86FoldTableEntry *I =
7546 IsTwoAddr ? lookupTwoAddrFoldTable(RegOp: NonNDOpc ? NonNDOpc : Opc)
7547 : lookupFoldTable(RegOp: Opc, OpNum);
7548
7549 MachineInstr *NewMI = nullptr;
7550 if (I) {
7551 unsigned Opcode = I->DstOp;
7552 if (Alignment <
7553 Align(1ULL << ((I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT)))
7554 return nullptr;
7555 bool NarrowToMOV32rm = false;
7556 if (Size) {
7557 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7558 const TargetRegisterClass *RC = getRegClass(MCID: MI.getDesc(), OpNum);
7559 unsigned RCSize = TRI.getRegSizeInBits(RC: *RC) / 8;
7560 // Check if it's safe to fold the load. If the size of the object is
7561 // narrower than the load width, then it's not.
7562 // FIXME: Allow scalar intrinsic instructions like ADDSSrm_Int.
7563 if ((I->Flags & TB_FOLDED_LOAD) && Size < RCSize) {
7564 // If this is a 64-bit load, but the spill slot is 32, then we can do
7565 // a 32-bit load which is implicitly zero-extended. This likely is
7566 // due to live interval analysis remat'ing a load from stack slot.
7567 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
7568 return nullptr;
7569 if (MI.getOperand(i: 0).getSubReg() || MI.getOperand(i: 1).getSubReg())
7570 return nullptr;
7571 Opcode = X86::MOV32rm;
7572 NarrowToMOV32rm = true;
7573 }
7574 // For stores, make sure the size of the object is equal to the size of
7575 // the store. If the object is larger, the extra bits would be garbage. If
7576 // the object is smaller we might overwrite another object or fault.
7577 if ((I->Flags & TB_FOLDED_STORE) && Size != RCSize)
7578 return nullptr;
7579 }
7580
7581 NewMI = IsTwoAddr ? fuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, TII: *this)
7582 : fuseInst(MF, Opcode, OpNo: OpNum, MOs, InsertPt, MI, TII: *this);
7583
7584 if (NarrowToMOV32rm) {
7585 // If this is the special case where we use a MOV32rm to load a 32-bit
7586 // value and zero-extend the top bits. Change the destination register
7587 // to a 32-bit one.
7588 Register DstReg = NewMI->getOperand(i: 0).getReg();
7589 if (DstReg.isPhysical())
7590 NewMI->getOperand(i: 0).setReg(RI.getSubReg(Reg: DstReg, Idx: X86::sub_32bit));
7591 else
7592 NewMI->getOperand(i: 0).setSubReg(X86::sub_32bit);
7593 }
7594 return NewMI;
7595 }
7596
7597 if (AllowCommute) {
7598 // If the instruction and target operand are commutable, commute the
7599 // instruction and try again.
7600 unsigned CommuteOpIdx2 = commuteOperandsForFold(MI, Idx1: OpNum);
7601 if (CommuteOpIdx2 == OpNum) {
7602 printFailMsgforFold(MI, Idx: OpNum);
7603 return nullptr;
7604 }
7605 // Attempt to fold with the commuted version of the instruction.
7606 NewMI = foldMemoryOperandImpl(MF, MI, OpNum: CommuteOpIdx2, MOs, InsertPt, Size,
7607 Alignment, /*AllowCommute=*/false);
7608 if (NewMI)
7609 return NewMI;
7610 // Folding failed again - undo the commute before returning.
7611 commuteInstruction(MI, NewMI: false, OpIdx1: OpNum, OpIdx2: CommuteOpIdx2);
7612 }
7613
7614 printFailMsgforFold(MI, Idx: OpNum);
7615 return nullptr;
7616}
7617
7618MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
7619 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
7620 MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS,
7621 VirtRegMap *VRM) const {
7622 // Check switch flag
7623 if (NoFusing)
7624 return nullptr;
7625
7626 // Avoid partial and undef register update stalls unless optimizing for size.
7627 if (!MF.getFunction().hasOptSize() &&
7628 (hasPartialRegUpdate(Opcode: MI.getOpcode(), Subtarget, /*ForLoadFold*/ true) ||
7629 shouldPreventUndefRegUpdateMemFold(MF, MI)))
7630 return nullptr;
7631
7632 // Don't fold subreg spills, or reloads that use a high subreg.
7633 for (auto Op : Ops) {
7634 MachineOperand &MO = MI.getOperand(i: Op);
7635 auto SubReg = MO.getSubReg();
7636 // MOV32r0 is special b/c it's used to clear a 64-bit register too.
7637 // (See patterns for MOV32r0 in TD files).
7638 if (MI.getOpcode() == X86::MOV32r0 && SubReg == X86::sub_32bit)
7639 continue;
7640 if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
7641 return nullptr;
7642 }
7643
7644 const MachineFrameInfo &MFI = MF.getFrameInfo();
7645 unsigned Size = MFI.getObjectSize(ObjectIdx: FrameIndex);
7646 Align Alignment = MFI.getObjectAlign(ObjectIdx: FrameIndex);
7647 // If the function stack isn't realigned we don't want to fold instructions
7648 // that need increased alignment.
7649 if (!RI.hasStackRealignment(MF))
7650 Alignment =
7651 std::min(a: Alignment, b: Subtarget.getFrameLowering()->getStackAlign());
7652
7653 auto Impl = [&]() {
7654 return foldMemoryOperandImpl(MF, MI, OpNum: Ops[0],
7655 MOs: MachineOperand::CreateFI(Idx: FrameIndex), InsertPt,
7656 Size, Alignment, /*AllowCommute=*/true);
7657 };
7658 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
7659 unsigned NewOpc = 0;
7660 unsigned RCSize = 0;
7661 unsigned Opc = MI.getOpcode();
7662 switch (Opc) {
7663 default:
7664 // NDD can be folded into RMW though its Op0 and Op1 are not tied.
7665 return (Subtarget.hasNDD() ? X86::getNonNDVariant(Opc) : 0U) ? Impl()
7666 : nullptr;
7667 case X86::TEST8rr:
7668 NewOpc = X86::CMP8ri;
7669 RCSize = 1;
7670 break;
7671 case X86::TEST16rr:
7672 NewOpc = X86::CMP16ri;
7673 RCSize = 2;
7674 break;
7675 case X86::TEST32rr:
7676 NewOpc = X86::CMP32ri;
7677 RCSize = 4;
7678 break;
7679 case X86::TEST64rr:
7680 NewOpc = X86::CMP64ri32;
7681 RCSize = 8;
7682 break;
7683 }
7684 // Check if it's safe to fold the load. If the size of the object is
7685 // narrower than the load width, then it's not.
7686 if (Size < RCSize)
7687 return nullptr;
7688 // Change to CMPXXri r, 0 first.
7689 MI.setDesc(get(Opcode: NewOpc));
7690 MI.getOperand(i: 1).ChangeToImmediate(ImmVal: 0);
7691 } else if (Ops.size() != 1)
7692 return nullptr;
7693
7694 return Impl();
7695}
7696
7697/// Check if \p LoadMI is a partial register load that we can't fold into \p MI
7698/// because the latter uses contents that wouldn't be defined in the folded
7699/// version. For instance, this transformation isn't legal:
7700/// movss (%rdi), %xmm0
7701/// addps %xmm0, %xmm0
7702/// ->
7703/// addps (%rdi), %xmm0
7704///
7705/// But this one is:
7706/// movss (%rdi), %xmm0
7707/// addss %xmm0, %xmm0
7708/// ->
7709/// addss (%rdi), %xmm0
7710///
7711static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
7712 const MachineInstr &UserMI,
7713 const MachineFunction &MF) {
7714 unsigned Opc = LoadMI.getOpcode();
7715 unsigned UserOpc = UserMI.getOpcode();
7716 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7717 const TargetRegisterClass *RC =
7718 MF.getRegInfo().getRegClass(Reg: LoadMI.getOperand(i: 0).getReg());
7719 unsigned RegSize = TRI.getRegSizeInBits(RC: *RC);
7720
7721 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm ||
7722 Opc == X86::MOVSSrm_alt || Opc == X86::VMOVSSrm_alt ||
7723 Opc == X86::VMOVSSZrm_alt) &&
7724 RegSize > 32) {
7725 // These instructions only load 32 bits, we can't fold them if the
7726 // destination register is wider than 32 bits (4 bytes), and its user
7727 // instruction isn't scalar (SS).
7728 switch (UserOpc) {
7729 case X86::CVTSS2SDrr_Int:
7730 case X86::VCVTSS2SDrr_Int:
7731 case X86::VCVTSS2SDZrr_Int:
7732 case X86::VCVTSS2SDZrrk_Int:
7733 case X86::VCVTSS2SDZrrkz_Int:
7734 case X86::CVTSS2SIrr_Int:
7735 case X86::CVTSS2SI64rr_Int:
7736 case X86::VCVTSS2SIrr_Int:
7737 case X86::VCVTSS2SI64rr_Int:
7738 case X86::VCVTSS2SIZrr_Int:
7739 case X86::VCVTSS2SI64Zrr_Int:
7740 case X86::CVTTSS2SIrr_Int:
7741 case X86::CVTTSS2SI64rr_Int:
7742 case X86::VCVTTSS2SIrr_Int:
7743 case X86::VCVTTSS2SI64rr_Int:
7744 case X86::VCVTTSS2SIZrr_Int:
7745 case X86::VCVTTSS2SI64Zrr_Int:
7746 case X86::VCVTSS2USIZrr_Int:
7747 case X86::VCVTSS2USI64Zrr_Int:
7748 case X86::VCVTTSS2USIZrr_Int:
7749 case X86::VCVTTSS2USI64Zrr_Int:
7750 case X86::RCPSSr_Int:
7751 case X86::VRCPSSr_Int:
7752 case X86::RSQRTSSr_Int:
7753 case X86::VRSQRTSSr_Int:
7754 case X86::ROUNDSSri_Int:
7755 case X86::VROUNDSSri_Int:
7756 case X86::COMISSrr_Int:
7757 case X86::VCOMISSrr_Int:
7758 case X86::VCOMISSZrr_Int:
7759 case X86::UCOMISSrr_Int:
7760 case X86::VUCOMISSrr_Int:
7761 case X86::VUCOMISSZrr_Int:
7762 case X86::ADDSSrr_Int:
7763 case X86::VADDSSrr_Int:
7764 case X86::VADDSSZrr_Int:
7765 case X86::CMPSSrri_Int:
7766 case X86::VCMPSSrri_Int:
7767 case X86::VCMPSSZrri_Int:
7768 case X86::DIVSSrr_Int:
7769 case X86::VDIVSSrr_Int:
7770 case X86::VDIVSSZrr_Int:
7771 case X86::MAXSSrr_Int:
7772 case X86::VMAXSSrr_Int:
7773 case X86::VMAXSSZrr_Int:
7774 case X86::MINSSrr_Int:
7775 case X86::VMINSSrr_Int:
7776 case X86::VMINSSZrr_Int:
7777 case X86::MULSSrr_Int:
7778 case X86::VMULSSrr_Int:
7779 case X86::VMULSSZrr_Int:
7780 case X86::SQRTSSr_Int:
7781 case X86::VSQRTSSr_Int:
7782 case X86::VSQRTSSZr_Int:
7783 case X86::SUBSSrr_Int:
7784 case X86::VSUBSSrr_Int:
7785 case X86::VSUBSSZrr_Int:
7786 case X86::VADDSSZrrk_Int:
7787 case X86::VADDSSZrrkz_Int:
7788 case X86::VCMPSSZrrik_Int:
7789 case X86::VDIVSSZrrk_Int:
7790 case X86::VDIVSSZrrkz_Int:
7791 case X86::VMAXSSZrrk_Int:
7792 case X86::VMAXSSZrrkz_Int:
7793 case X86::VMINSSZrrk_Int:
7794 case X86::VMINSSZrrkz_Int:
7795 case X86::VMULSSZrrk_Int:
7796 case X86::VMULSSZrrkz_Int:
7797 case X86::VSQRTSSZrk_Int:
7798 case X86::VSQRTSSZrkz_Int:
7799 case X86::VSUBSSZrrk_Int:
7800 case X86::VSUBSSZrrkz_Int:
7801 case X86::VFMADDSS4rr_Int:
7802 case X86::VFNMADDSS4rr_Int:
7803 case X86::VFMSUBSS4rr_Int:
7804 case X86::VFNMSUBSS4rr_Int:
7805 case X86::VFMADD132SSr_Int:
7806 case X86::VFNMADD132SSr_Int:
7807 case X86::VFMADD213SSr_Int:
7808 case X86::VFNMADD213SSr_Int:
7809 case X86::VFMADD231SSr_Int:
7810 case X86::VFNMADD231SSr_Int:
7811 case X86::VFMSUB132SSr_Int:
7812 case X86::VFNMSUB132SSr_Int:
7813 case X86::VFMSUB213SSr_Int:
7814 case X86::VFNMSUB213SSr_Int:
7815 case X86::VFMSUB231SSr_Int:
7816 case X86::VFNMSUB231SSr_Int:
7817 case X86::VFMADD132SSZr_Int:
7818 case X86::VFNMADD132SSZr_Int:
7819 case X86::VFMADD213SSZr_Int:
7820 case X86::VFNMADD213SSZr_Int:
7821 case X86::VFMADD231SSZr_Int:
7822 case X86::VFNMADD231SSZr_Int:
7823 case X86::VFMSUB132SSZr_Int:
7824 case X86::VFNMSUB132SSZr_Int:
7825 case X86::VFMSUB213SSZr_Int:
7826 case X86::VFNMSUB213SSZr_Int:
7827 case X86::VFMSUB231SSZr_Int:
7828 case X86::VFNMSUB231SSZr_Int:
7829 case X86::VFMADD132SSZrk_Int:
7830 case X86::VFNMADD132SSZrk_Int:
7831 case X86::VFMADD213SSZrk_Int:
7832 case X86::VFNMADD213SSZrk_Int:
7833 case X86::VFMADD231SSZrk_Int:
7834 case X86::VFNMADD231SSZrk_Int:
7835 case X86::VFMSUB132SSZrk_Int:
7836 case X86::VFNMSUB132SSZrk_Int:
7837 case X86::VFMSUB213SSZrk_Int:
7838 case X86::VFNMSUB213SSZrk_Int:
7839 case X86::VFMSUB231SSZrk_Int:
7840 case X86::VFNMSUB231SSZrk_Int:
7841 case X86::VFMADD132SSZrkz_Int:
7842 case X86::VFNMADD132SSZrkz_Int:
7843 case X86::VFMADD213SSZrkz_Int:
7844 case X86::VFNMADD213SSZrkz_Int:
7845 case X86::VFMADD231SSZrkz_Int:
7846 case X86::VFNMADD231SSZrkz_Int:
7847 case X86::VFMSUB132SSZrkz_Int:
7848 case X86::VFNMSUB132SSZrkz_Int:
7849 case X86::VFMSUB213SSZrkz_Int:
7850 case X86::VFNMSUB213SSZrkz_Int:
7851 case X86::VFMSUB231SSZrkz_Int:
7852 case X86::VFNMSUB231SSZrkz_Int:
7853 case X86::VFIXUPIMMSSZrri:
7854 case X86::VFIXUPIMMSSZrrik:
7855 case X86::VFIXUPIMMSSZrrikz:
7856 case X86::VFPCLASSSSZri:
7857 case X86::VFPCLASSSSZrik:
7858 case X86::VGETEXPSSZr:
7859 case X86::VGETEXPSSZrk:
7860 case X86::VGETEXPSSZrkz:
7861 case X86::VGETMANTSSZrri:
7862 case X86::VGETMANTSSZrrik:
7863 case X86::VGETMANTSSZrrikz:
7864 case X86::VRANGESSZrri:
7865 case X86::VRANGESSZrrik:
7866 case X86::VRANGESSZrrikz:
7867 case X86::VRCP14SSZrr:
7868 case X86::VRCP14SSZrrk:
7869 case X86::VRCP14SSZrrkz:
7870 case X86::VRCP28SSZr:
7871 case X86::VRCP28SSZrk:
7872 case X86::VRCP28SSZrkz:
7873 case X86::VREDUCESSZrri:
7874 case X86::VREDUCESSZrrik:
7875 case X86::VREDUCESSZrrikz:
7876 case X86::VRNDSCALESSZrri_Int:
7877 case X86::VRNDSCALESSZrrik_Int:
7878 case X86::VRNDSCALESSZrrikz_Int:
7879 case X86::VRSQRT14SSZrr:
7880 case X86::VRSQRT14SSZrrk:
7881 case X86::VRSQRT14SSZrrkz:
7882 case X86::VRSQRT28SSZr:
7883 case X86::VRSQRT28SSZrk:
7884 case X86::VRSQRT28SSZrkz:
7885 case X86::VSCALEFSSZrr:
7886 case X86::VSCALEFSSZrrk:
7887 case X86::VSCALEFSSZrrkz:
7888 return false;
7889 default:
7890 return true;
7891 }
7892 }
7893
7894 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm ||
7895 Opc == X86::MOVSDrm_alt || Opc == X86::VMOVSDrm_alt ||
7896 Opc == X86::VMOVSDZrm_alt) &&
7897 RegSize > 64) {
7898 // These instructions only load 64 bits, we can't fold them if the
7899 // destination register is wider than 64 bits (8 bytes), and its user
7900 // instruction isn't scalar (SD).
7901 switch (UserOpc) {
7902 case X86::CVTSD2SSrr_Int:
7903 case X86::VCVTSD2SSrr_Int:
7904 case X86::VCVTSD2SSZrr_Int:
7905 case X86::VCVTSD2SSZrrk_Int:
7906 case X86::VCVTSD2SSZrrkz_Int:
7907 case X86::CVTSD2SIrr_Int:
7908 case X86::CVTSD2SI64rr_Int:
7909 case X86::VCVTSD2SIrr_Int:
7910 case X86::VCVTSD2SI64rr_Int:
7911 case X86::VCVTSD2SIZrr_Int:
7912 case X86::VCVTSD2SI64Zrr_Int:
7913 case X86::CVTTSD2SIrr_Int:
7914 case X86::CVTTSD2SI64rr_Int:
7915 case X86::VCVTTSD2SIrr_Int:
7916 case X86::VCVTTSD2SI64rr_Int:
7917 case X86::VCVTTSD2SIZrr_Int:
7918 case X86::VCVTTSD2SI64Zrr_Int:
7919 case X86::VCVTSD2USIZrr_Int:
7920 case X86::VCVTSD2USI64Zrr_Int:
7921 case X86::VCVTTSD2USIZrr_Int:
7922 case X86::VCVTTSD2USI64Zrr_Int:
7923 case X86::ROUNDSDri_Int:
7924 case X86::VROUNDSDri_Int:
7925 case X86::COMISDrr_Int:
7926 case X86::VCOMISDrr_Int:
7927 case X86::VCOMISDZrr_Int:
7928 case X86::UCOMISDrr_Int:
7929 case X86::VUCOMISDrr_Int:
7930 case X86::VUCOMISDZrr_Int:
7931 case X86::ADDSDrr_Int:
7932 case X86::VADDSDrr_Int:
7933 case X86::VADDSDZrr_Int:
7934 case X86::CMPSDrri_Int:
7935 case X86::VCMPSDrri_Int:
7936 case X86::VCMPSDZrri_Int:
7937 case X86::DIVSDrr_Int:
7938 case X86::VDIVSDrr_Int:
7939 case X86::VDIVSDZrr_Int:
7940 case X86::MAXSDrr_Int:
7941 case X86::VMAXSDrr_Int:
7942 case X86::VMAXSDZrr_Int:
7943 case X86::MINSDrr_Int:
7944 case X86::VMINSDrr_Int:
7945 case X86::VMINSDZrr_Int:
7946 case X86::MULSDrr_Int:
7947 case X86::VMULSDrr_Int:
7948 case X86::VMULSDZrr_Int:
7949 case X86::SQRTSDr_Int:
7950 case X86::VSQRTSDr_Int:
7951 case X86::VSQRTSDZr_Int:
7952 case X86::SUBSDrr_Int:
7953 case X86::VSUBSDrr_Int:
7954 case X86::VSUBSDZrr_Int:
7955 case X86::VADDSDZrrk_Int:
7956 case X86::VADDSDZrrkz_Int:
7957 case X86::VCMPSDZrrik_Int:
7958 case X86::VDIVSDZrrk_Int:
7959 case X86::VDIVSDZrrkz_Int:
7960 case X86::VMAXSDZrrk_Int:
7961 case X86::VMAXSDZrrkz_Int:
7962 case X86::VMINSDZrrk_Int:
7963 case X86::VMINSDZrrkz_Int:
7964 case X86::VMULSDZrrk_Int:
7965 case X86::VMULSDZrrkz_Int:
7966 case X86::VSQRTSDZrk_Int:
7967 case X86::VSQRTSDZrkz_Int:
7968 case X86::VSUBSDZrrk_Int:
7969 case X86::VSUBSDZrrkz_Int:
7970 case X86::VFMADDSD4rr_Int:
7971 case X86::VFNMADDSD4rr_Int:
7972 case X86::VFMSUBSD4rr_Int:
7973 case X86::VFNMSUBSD4rr_Int:
7974 case X86::VFMADD132SDr_Int:
7975 case X86::VFNMADD132SDr_Int:
7976 case X86::VFMADD213SDr_Int:
7977 case X86::VFNMADD213SDr_Int:
7978 case X86::VFMADD231SDr_Int:
7979 case X86::VFNMADD231SDr_Int:
7980 case X86::VFMSUB132SDr_Int:
7981 case X86::VFNMSUB132SDr_Int:
7982 case X86::VFMSUB213SDr_Int:
7983 case X86::VFNMSUB213SDr_Int:
7984 case X86::VFMSUB231SDr_Int:
7985 case X86::VFNMSUB231SDr_Int:
7986 case X86::VFMADD132SDZr_Int:
7987 case X86::VFNMADD132SDZr_Int:
7988 case X86::VFMADD213SDZr_Int:
7989 case X86::VFNMADD213SDZr_Int:
7990 case X86::VFMADD231SDZr_Int:
7991 case X86::VFNMADD231SDZr_Int:
7992 case X86::VFMSUB132SDZr_Int:
7993 case X86::VFNMSUB132SDZr_Int:
7994 case X86::VFMSUB213SDZr_Int:
7995 case X86::VFNMSUB213SDZr_Int:
7996 case X86::VFMSUB231SDZr_Int:
7997 case X86::VFNMSUB231SDZr_Int:
7998 case X86::VFMADD132SDZrk_Int:
7999 case X86::VFNMADD132SDZrk_Int:
8000 case X86::VFMADD213SDZrk_Int:
8001 case X86::VFNMADD213SDZrk_Int:
8002 case X86::VFMADD231SDZrk_Int:
8003 case X86::VFNMADD231SDZrk_Int:
8004 case X86::VFMSUB132SDZrk_Int:
8005 case X86::VFNMSUB132SDZrk_Int:
8006 case X86::VFMSUB213SDZrk_Int:
8007 case X86::VFNMSUB213SDZrk_Int:
8008 case X86::VFMSUB231SDZrk_Int:
8009 case X86::VFNMSUB231SDZrk_Int:
8010 case X86::VFMADD132SDZrkz_Int:
8011 case X86::VFNMADD132SDZrkz_Int:
8012 case X86::VFMADD213SDZrkz_Int:
8013 case X86::VFNMADD213SDZrkz_Int:
8014 case X86::VFMADD231SDZrkz_Int:
8015 case X86::VFNMADD231SDZrkz_Int:
8016 case X86::VFMSUB132SDZrkz_Int:
8017 case X86::VFNMSUB132SDZrkz_Int:
8018 case X86::VFMSUB213SDZrkz_Int:
8019 case X86::VFNMSUB213SDZrkz_Int:
8020 case X86::VFMSUB231SDZrkz_Int:
8021 case X86::VFNMSUB231SDZrkz_Int:
8022 case X86::VFIXUPIMMSDZrri:
8023 case X86::VFIXUPIMMSDZrrik:
8024 case X86::VFIXUPIMMSDZrrikz:
8025 case X86::VFPCLASSSDZri:
8026 case X86::VFPCLASSSDZrik:
8027 case X86::VGETEXPSDZr:
8028 case X86::VGETEXPSDZrk:
8029 case X86::VGETEXPSDZrkz:
8030 case X86::VGETMANTSDZrri:
8031 case X86::VGETMANTSDZrrik:
8032 case X86::VGETMANTSDZrrikz:
8033 case X86::VRANGESDZrri:
8034 case X86::VRANGESDZrrik:
8035 case X86::VRANGESDZrrikz:
8036 case X86::VRCP14SDZrr:
8037 case X86::VRCP14SDZrrk:
8038 case X86::VRCP14SDZrrkz:
8039 case X86::VRCP28SDZr:
8040 case X86::VRCP28SDZrk:
8041 case X86::VRCP28SDZrkz:
8042 case X86::VREDUCESDZrri:
8043 case X86::VREDUCESDZrrik:
8044 case X86::VREDUCESDZrrikz:
8045 case X86::VRNDSCALESDZrri_Int:
8046 case X86::VRNDSCALESDZrrik_Int:
8047 case X86::VRNDSCALESDZrrikz_Int:
8048 case X86::VRSQRT14SDZrr:
8049 case X86::VRSQRT14SDZrrk:
8050 case X86::VRSQRT14SDZrrkz:
8051 case X86::VRSQRT28SDZr:
8052 case X86::VRSQRT28SDZrk:
8053 case X86::VRSQRT28SDZrkz:
8054 case X86::VSCALEFSDZrr:
8055 case X86::VSCALEFSDZrrk:
8056 case X86::VSCALEFSDZrrkz:
8057 return false;
8058 default:
8059 return true;
8060 }
8061 }
8062
8063 if ((Opc == X86::VMOVSHZrm || Opc == X86::VMOVSHZrm_alt) && RegSize > 16) {
8064 // These instructions only load 16 bits, we can't fold them if the
8065 // destination register is wider than 16 bits (2 bytes), and its user
8066 // instruction isn't scalar (SH).
8067 switch (UserOpc) {
8068 case X86::VADDSHZrr_Int:
8069 case X86::VCMPSHZrri_Int:
8070 case X86::VDIVSHZrr_Int:
8071 case X86::VMAXSHZrr_Int:
8072 case X86::VMINSHZrr_Int:
8073 case X86::VMULSHZrr_Int:
8074 case X86::VSUBSHZrr_Int:
8075 case X86::VADDSHZrrk_Int:
8076 case X86::VADDSHZrrkz_Int:
8077 case X86::VCMPSHZrrik_Int:
8078 case X86::VDIVSHZrrk_Int:
8079 case X86::VDIVSHZrrkz_Int:
8080 case X86::VMAXSHZrrk_Int:
8081 case X86::VMAXSHZrrkz_Int:
8082 case X86::VMINSHZrrk_Int:
8083 case X86::VMINSHZrrkz_Int:
8084 case X86::VMULSHZrrk_Int:
8085 case X86::VMULSHZrrkz_Int:
8086 case X86::VSUBSHZrrk_Int:
8087 case X86::VSUBSHZrrkz_Int:
8088 case X86::VFMADD132SHZr_Int:
8089 case X86::VFNMADD132SHZr_Int:
8090 case X86::VFMADD213SHZr_Int:
8091 case X86::VFNMADD213SHZr_Int:
8092 case X86::VFMADD231SHZr_Int:
8093 case X86::VFNMADD231SHZr_Int:
8094 case X86::VFMSUB132SHZr_Int:
8095 case X86::VFNMSUB132SHZr_Int:
8096 case X86::VFMSUB213SHZr_Int:
8097 case X86::VFNMSUB213SHZr_Int:
8098 case X86::VFMSUB231SHZr_Int:
8099 case X86::VFNMSUB231SHZr_Int:
8100 case X86::VFMADD132SHZrk_Int:
8101 case X86::VFNMADD132SHZrk_Int:
8102 case X86::VFMADD213SHZrk_Int:
8103 case X86::VFNMADD213SHZrk_Int:
8104 case X86::VFMADD231SHZrk_Int:
8105 case X86::VFNMADD231SHZrk_Int:
8106 case X86::VFMSUB132SHZrk_Int:
8107 case X86::VFNMSUB132SHZrk_Int:
8108 case X86::VFMSUB213SHZrk_Int:
8109 case X86::VFNMSUB213SHZrk_Int:
8110 case X86::VFMSUB231SHZrk_Int:
8111 case X86::VFNMSUB231SHZrk_Int:
8112 case X86::VFMADD132SHZrkz_Int:
8113 case X86::VFNMADD132SHZrkz_Int:
8114 case X86::VFMADD213SHZrkz_Int:
8115 case X86::VFNMADD213SHZrkz_Int:
8116 case X86::VFMADD231SHZrkz_Int:
8117 case X86::VFNMADD231SHZrkz_Int:
8118 case X86::VFMSUB132SHZrkz_Int:
8119 case X86::VFNMSUB132SHZrkz_Int:
8120 case X86::VFMSUB213SHZrkz_Int:
8121 case X86::VFNMSUB213SHZrkz_Int:
8122 case X86::VFMSUB231SHZrkz_Int:
8123 case X86::VFNMSUB231SHZrkz_Int:
8124 return false;
8125 default:
8126 return true;
8127 }
8128 }
8129
8130 return false;
8131}
8132
8133MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
8134 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
8135 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
8136 LiveIntervals *LIS) const {
8137
8138 // If LoadMI is a masked load, check MI having the same mask.
8139 const MCInstrDesc &MCID = get(Opcode: LoadMI.getOpcode());
8140 unsigned NumOps = MCID.getNumOperands();
8141 if (NumOps >= 3) {
8142 Register MaskReg;
8143 const MachineOperand &Op1 = LoadMI.getOperand(i: 1);
8144 const MachineOperand &Op2 = LoadMI.getOperand(i: 2);
8145
8146 auto IsVKWMClass = [](const TargetRegisterClass *RC) {
8147 return RC == &X86::VK2WMRegClass || RC == &X86::VK4WMRegClass ||
8148 RC == &X86::VK8WMRegClass || RC == &X86::VK16WMRegClass ||
8149 RC == &X86::VK32WMRegClass || RC == &X86::VK64WMRegClass;
8150 };
8151
8152 if (Op1.isReg() && IsVKWMClass(getRegClass(MCID, OpNum: 1)))
8153 MaskReg = Op1.getReg();
8154 else if (Op2.isReg() && IsVKWMClass(getRegClass(MCID, OpNum: 2)))
8155 MaskReg = Op2.getReg();
8156
8157 if (MaskReg) {
8158 // Some instructions are invalid to fold into even with the same mask.
8159 // Folding is unsafe if an active destination element may read from a
8160 // source element that is masked off.
8161 if (isNonFoldableWithSameMask(RegOp: MI.getOpcode()))
8162 return nullptr;
8163 bool HasSameMask = false;
8164 for (unsigned I = 1, E = MI.getDesc().getNumOperands(); I < E; ++I) {
8165 const MachineOperand &Op = MI.getOperand(i: I);
8166 if (Op.isReg() && Op.getReg() == MaskReg) {
8167 HasSameMask = true;
8168 break;
8169 }
8170 }
8171 if (!HasSameMask)
8172 return nullptr;
8173 }
8174 }
8175
8176 // TODO: Support the case where LoadMI loads a wide register, but MI
8177 // only uses a subreg.
8178 for (auto Op : Ops) {
8179 if (MI.getOperand(i: Op).getSubReg())
8180 return nullptr;
8181 }
8182
8183 // If loading from a FrameIndex, fold directly from the FrameIndex.
8184 int FrameIndex;
8185 if (isLoadFromStackSlot(MI: LoadMI, FrameIndex)) {
8186 if (isNonFoldablePartialRegisterLoad(LoadMI, UserMI: MI, MF))
8187 return nullptr;
8188 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
8189 }
8190
8191 // Check switch flag
8192 if (NoFusing)
8193 return nullptr;
8194
8195 // Avoid partial and undef register update stalls unless optimizing for size.
8196 if (!MF.getFunction().hasOptSize() &&
8197 (hasPartialRegUpdate(Opcode: MI.getOpcode(), Subtarget, /*ForLoadFold*/ true) ||
8198 shouldPreventUndefRegUpdateMemFold(MF, MI)))
8199 return nullptr;
8200
8201 // Do not fold a NDD instruction and a memory instruction with relocation to
8202 // avoid emit APX relocation when the flag is disabled for backward
8203 // compatibility.
8204 uint64_t TSFlags = MI.getDesc().TSFlags;
8205 if (!X86EnableAPXForRelocation && isMemInstrWithGOTPCREL(MI: LoadMI) &&
8206 X86II::hasNewDataDest(TSFlags))
8207 return nullptr;
8208
8209 // Determine the alignment of the load.
8210 Align Alignment;
8211 unsigned LoadOpc = LoadMI.getOpcode();
8212 if (LoadMI.hasOneMemOperand())
8213 Alignment = (*LoadMI.memoperands_begin())->getAlign();
8214 else
8215 switch (LoadOpc) {
8216 case X86::AVX512_512_SET0:
8217 case X86::AVX512_512_SETALLONES:
8218 Alignment = Align(64);
8219 break;
8220 case X86::AVX2_SETALLONES:
8221 case X86::AVX1_SETALLONES:
8222 case X86::AVX_SET0:
8223 case X86::AVX512_256_SET0:
8224 case X86::AVX512_256_SETALLONES:
8225 Alignment = Align(32);
8226 break;
8227 case X86::V_SET0:
8228 case X86::V_SETALLONES:
8229 case X86::AVX512_128_SET0:
8230 case X86::FsFLD0F128:
8231 case X86::AVX512_FsFLD0F128:
8232 case X86::AVX512_128_SETALLONES:
8233 Alignment = Align(16);
8234 break;
8235 case X86::MMX_SET0:
8236 case X86::FsFLD0SD:
8237 case X86::AVX512_FsFLD0SD:
8238 Alignment = Align(8);
8239 break;
8240 case X86::FsFLD0SS:
8241 case X86::AVX512_FsFLD0SS:
8242 Alignment = Align(4);
8243 break;
8244 case X86::FsFLD0SH:
8245 case X86::AVX512_FsFLD0SH:
8246 Alignment = Align(2);
8247 break;
8248 default:
8249 return nullptr;
8250 }
8251 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
8252 unsigned NewOpc = 0;
8253 switch (MI.getOpcode()) {
8254 default:
8255 return nullptr;
8256 case X86::TEST8rr:
8257 NewOpc = X86::CMP8ri;
8258 break;
8259 case X86::TEST16rr:
8260 NewOpc = X86::CMP16ri;
8261 break;
8262 case X86::TEST32rr:
8263 NewOpc = X86::CMP32ri;
8264 break;
8265 case X86::TEST64rr:
8266 NewOpc = X86::CMP64ri32;
8267 break;
8268 }
8269 // Change to CMPXXri r, 0 first.
8270 MI.setDesc(get(Opcode: NewOpc));
8271 MI.getOperand(i: 1).ChangeToImmediate(ImmVal: 0);
8272 } else if (Ops.size() != 1)
8273 return nullptr;
8274
8275 // Make sure the subregisters match.
8276 // Otherwise we risk changing the size of the load.
8277 if (LoadMI.getOperand(i: 0).getSubReg() != MI.getOperand(i: Ops[0]).getSubReg())
8278 return nullptr;
8279
8280 SmallVector<MachineOperand, X86::AddrNumOperands> MOs;
8281 switch (LoadOpc) {
8282 case X86::MMX_SET0:
8283 case X86::V_SET0:
8284 case X86::V_SETALLONES:
8285 case X86::AVX2_SETALLONES:
8286 case X86::AVX1_SETALLONES:
8287 case X86::AVX_SET0:
8288 case X86::AVX512_128_SET0:
8289 case X86::AVX512_256_SET0:
8290 case X86::AVX512_512_SET0:
8291 case X86::AVX512_128_SETALLONES:
8292 case X86::AVX512_256_SETALLONES:
8293 case X86::AVX512_512_SETALLONES:
8294 case X86::FsFLD0SH:
8295 case X86::AVX512_FsFLD0SH:
8296 case X86::FsFLD0SD:
8297 case X86::AVX512_FsFLD0SD:
8298 case X86::FsFLD0SS:
8299 case X86::AVX512_FsFLD0SS:
8300 case X86::FsFLD0F128:
8301 case X86::AVX512_FsFLD0F128: {
8302 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
8303 // Create a constant-pool entry and operands to load from it.
8304
8305 // Large code model can't fold loads this way.
8306 if (MF.getTarget().getCodeModel() == CodeModel::Large)
8307 return nullptr;
8308
8309 // x86-32 PIC requires a PIC base register for constant pools.
8310 unsigned PICBase = 0;
8311 // Since we're using Small or Kernel code model, we can always use
8312 // RIP-relative addressing for a smaller encoding.
8313 if (Subtarget.is64Bit()) {
8314 PICBase = X86::RIP;
8315 } else if (MF.getTarget().isPositionIndependent()) {
8316 // FIXME: PICBase = getGlobalBaseReg(&MF);
8317 // This doesn't work for several reasons.
8318 // 1. GlobalBaseReg may have been spilled.
8319 // 2. It may not be live at MI.
8320 return nullptr;
8321 }
8322
8323 // Create a constant-pool entry.
8324 MachineConstantPool &MCP = *MF.getConstantPool();
8325 Type *Ty;
8326 bool IsAllOnes = false;
8327 switch (LoadOpc) {
8328 case X86::FsFLD0SS:
8329 case X86::AVX512_FsFLD0SS:
8330 Ty = Type::getFloatTy(C&: MF.getFunction().getContext());
8331 break;
8332 case X86::FsFLD0SD:
8333 case X86::AVX512_FsFLD0SD:
8334 Ty = Type::getDoubleTy(C&: MF.getFunction().getContext());
8335 break;
8336 case X86::FsFLD0F128:
8337 case X86::AVX512_FsFLD0F128:
8338 Ty = Type::getFP128Ty(C&: MF.getFunction().getContext());
8339 break;
8340 case X86::FsFLD0SH:
8341 case X86::AVX512_FsFLD0SH:
8342 Ty = Type::getHalfTy(C&: MF.getFunction().getContext());
8343 break;
8344 case X86::AVX512_512_SETALLONES:
8345 IsAllOnes = true;
8346 [[fallthrough]];
8347 case X86::AVX512_512_SET0:
8348 Ty = FixedVectorType::get(ElementType: Type::getInt32Ty(C&: MF.getFunction().getContext()),
8349 NumElts: 16);
8350 break;
8351 case X86::AVX1_SETALLONES:
8352 case X86::AVX2_SETALLONES:
8353 case X86::AVX512_256_SETALLONES:
8354 IsAllOnes = true;
8355 [[fallthrough]];
8356 case X86::AVX512_256_SET0:
8357 case X86::AVX_SET0:
8358 Ty = FixedVectorType::get(ElementType: Type::getInt32Ty(C&: MF.getFunction().getContext()),
8359 NumElts: 8);
8360
8361 break;
8362 case X86::MMX_SET0:
8363 Ty = FixedVectorType::get(ElementType: Type::getInt32Ty(C&: MF.getFunction().getContext()),
8364 NumElts: 2);
8365 break;
8366 case X86::V_SETALLONES:
8367 case X86::AVX512_128_SETALLONES:
8368 IsAllOnes = true;
8369 [[fallthrough]];
8370 case X86::V_SET0:
8371 case X86::AVX512_128_SET0:
8372 Ty = FixedVectorType::get(ElementType: Type::getInt32Ty(C&: MF.getFunction().getContext()),
8373 NumElts: 4);
8374 break;
8375 }
8376
8377 const Constant *C =
8378 IsAllOnes ? Constant::getAllOnesValue(Ty) : Constant::getNullValue(Ty);
8379 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
8380
8381 // Create operands to load from the constant pool entry.
8382 MOs.push_back(Elt: MachineOperand::CreateReg(Reg: PICBase, isDef: false));
8383 MOs.push_back(Elt: MachineOperand::CreateImm(Val: 1));
8384 MOs.push_back(Elt: MachineOperand::CreateReg(Reg: 0, isDef: false));
8385 MOs.push_back(Elt: MachineOperand::CreateCPI(Idx: CPI, Offset: 0));
8386 MOs.push_back(Elt: MachineOperand::CreateReg(Reg: 0, isDef: false));
8387 break;
8388 }
8389 case X86::VPBROADCASTBZ128rm:
8390 case X86::VPBROADCASTBZ256rm:
8391 case X86::VPBROADCASTBZrm:
8392 case X86::VBROADCASTF32X2Z256rm:
8393 case X86::VBROADCASTF32X2Zrm:
8394 case X86::VBROADCASTI32X2Z128rm:
8395 case X86::VBROADCASTI32X2Z256rm:
8396 case X86::VBROADCASTI32X2Zrm:
8397 // No instructions currently fuse with 8bits or 32bits x 2.
8398 return nullptr;
8399
8400#define FOLD_BROADCAST(SIZE) \
8401 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands, \
8402 LoadMI.operands_begin() + NumOps); \
8403 return foldMemoryBroadcast(MF, MI, Ops[0], MOs, InsertPt, /*Size=*/SIZE, \
8404 /*AllowCommute=*/true);
8405 case X86::VPBROADCASTWZ128rm:
8406 case X86::VPBROADCASTWZ256rm:
8407 case X86::VPBROADCASTWZrm:
8408 FOLD_BROADCAST(16);
8409 case X86::VPBROADCASTDZ128rm:
8410 case X86::VPBROADCASTDZ256rm:
8411 case X86::VPBROADCASTDZrm:
8412 case X86::VBROADCASTSSZ128rm:
8413 case X86::VBROADCASTSSZ256rm:
8414 case X86::VBROADCASTSSZrm:
8415 FOLD_BROADCAST(32);
8416 case X86::VPBROADCASTQZ128rm:
8417 case X86::VPBROADCASTQZ256rm:
8418 case X86::VPBROADCASTQZrm:
8419 case X86::VBROADCASTSDZ256rm:
8420 case X86::VBROADCASTSDZrm:
8421 FOLD_BROADCAST(64);
8422 default: {
8423 if (isNonFoldablePartialRegisterLoad(LoadMI, UserMI: MI, MF))
8424 return nullptr;
8425
8426 // Folding a normal load. Just copy the load's address operands.
8427 MOs.append(in_start: LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
8428 in_end: LoadMI.operands_begin() + NumOps);
8429 break;
8430 }
8431 }
8432 return foldMemoryOperandImpl(MF, MI, OpNum: Ops[0], MOs, InsertPt,
8433 /*Size=*/0, Alignment, /*AllowCommute=*/true);
8434}
8435
8436MachineInstr *
8437X86InstrInfo::foldMemoryBroadcast(MachineFunction &MF, MachineInstr &MI,
8438 unsigned OpNum, ArrayRef<MachineOperand> MOs,
8439 MachineBasicBlock::iterator InsertPt,
8440 unsigned BitsSize, bool AllowCommute) const {
8441
8442 if (auto *I = lookupBroadcastFoldTable(RegOp: MI.getOpcode(), OpNum))
8443 return matchBroadcastSize(Entry: *I, BroadcastBits: BitsSize)
8444 ? fuseInst(MF, Opcode: I->DstOp, OpNo: OpNum, MOs, InsertPt, MI, TII: *this)
8445 : nullptr;
8446
8447 if (AllowCommute) {
8448 // If the instruction and target operand are commutable, commute the
8449 // instruction and try again.
8450 unsigned CommuteOpIdx2 = commuteOperandsForFold(MI, Idx1: OpNum);
8451 if (CommuteOpIdx2 == OpNum) {
8452 printFailMsgforFold(MI, Idx: OpNum);
8453 return nullptr;
8454 }
8455 MachineInstr *NewMI =
8456 foldMemoryBroadcast(MF, MI, OpNum: CommuteOpIdx2, MOs, InsertPt, BitsSize,
8457 /*AllowCommute=*/false);
8458 if (NewMI)
8459 return NewMI;
8460 // Folding failed again - undo the commute before returning.
8461 commuteInstruction(MI, NewMI: false, OpIdx1: OpNum, OpIdx2: CommuteOpIdx2);
8462 }
8463
8464 printFailMsgforFold(MI, Idx: OpNum);
8465 return nullptr;
8466}
8467
8468static SmallVector<MachineMemOperand *, 2>
8469extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
8470 SmallVector<MachineMemOperand *, 2> LoadMMOs;
8471
8472 for (MachineMemOperand *MMO : MMOs) {
8473 if (!MMO->isLoad())
8474 continue;
8475
8476 if (!MMO->isStore()) {
8477 // Reuse the MMO.
8478 LoadMMOs.push_back(Elt: MMO);
8479 } else {
8480 // Clone the MMO and unset the store flag.
8481 LoadMMOs.push_back(Elt: MF.getMachineMemOperand(
8482 MMO, Flags: MMO->getFlags() & ~MachineMemOperand::MOStore));
8483 }
8484 }
8485
8486 return LoadMMOs;
8487}
8488
8489static SmallVector<MachineMemOperand *, 2>
8490extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
8491 SmallVector<MachineMemOperand *, 2> StoreMMOs;
8492
8493 for (MachineMemOperand *MMO : MMOs) {
8494 if (!MMO->isStore())
8495 continue;
8496
8497 if (!MMO->isLoad()) {
8498 // Reuse the MMO.
8499 StoreMMOs.push_back(Elt: MMO);
8500 } else {
8501 // Clone the MMO and unset the load flag.
8502 StoreMMOs.push_back(Elt: MF.getMachineMemOperand(
8503 MMO, Flags: MMO->getFlags() & ~MachineMemOperand::MOLoad));
8504 }
8505 }
8506
8507 return StoreMMOs;
8508}
8509
8510static unsigned getBroadcastOpcode(const X86FoldTableEntry *I,
8511 const TargetRegisterClass *RC,
8512 const X86Subtarget &STI) {
8513 assert(STI.hasAVX512() && "Expected at least AVX512!");
8514 unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(RC: *RC);
8515 assert((SpillSize == 64 || STI.hasVLX()) &&
8516 "Can't broadcast less than 64 bytes without AVX512VL!");
8517
8518#define CASE_BCAST_TYPE_OPC(TYPE, OP16, OP32, OP64) \
8519 case TYPE: \
8520 switch (SpillSize) { \
8521 default: \
8522 llvm_unreachable("Unknown spill size"); \
8523 case 16: \
8524 return X86::OP16; \
8525 case 32: \
8526 return X86::OP32; \
8527 case 64: \
8528 return X86::OP64; \
8529 } \
8530 break;
8531
8532 switch (I->Flags & TB_BCAST_MASK) {
8533 default:
8534 llvm_unreachable("Unexpected broadcast type!");
8535 CASE_BCAST_TYPE_OPC(TB_BCAST_W, VPBROADCASTWZ128rm, VPBROADCASTWZ256rm,
8536 VPBROADCASTWZrm)
8537 CASE_BCAST_TYPE_OPC(TB_BCAST_D, VPBROADCASTDZ128rm, VPBROADCASTDZ256rm,
8538 VPBROADCASTDZrm)
8539 CASE_BCAST_TYPE_OPC(TB_BCAST_Q, VPBROADCASTQZ128rm, VPBROADCASTQZ256rm,
8540 VPBROADCASTQZrm)
8541 CASE_BCAST_TYPE_OPC(TB_BCAST_SH, VPBROADCASTWZ128rm, VPBROADCASTWZ256rm,
8542 VPBROADCASTWZrm)
8543 CASE_BCAST_TYPE_OPC(TB_BCAST_SS, VBROADCASTSSZ128rm, VBROADCASTSSZ256rm,
8544 VBROADCASTSSZrm)
8545 CASE_BCAST_TYPE_OPC(TB_BCAST_SD, VMOVDDUPZ128rm, VBROADCASTSDZ256rm,
8546 VBROADCASTSDZrm)
8547 }
8548}
8549
8550bool X86InstrInfo::unfoldMemoryOperand(
8551 MachineFunction &MF, MachineInstr &MI, Register Reg, bool UnfoldLoad,
8552 bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
8553 const X86FoldTableEntry *I = lookupUnfoldTable(MemOp: MI.getOpcode());
8554 if (I == nullptr)
8555 return false;
8556 unsigned Opc = I->DstOp;
8557 unsigned Index = I->Flags & TB_INDEX_MASK;
8558 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
8559 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
8560 if (UnfoldLoad && !FoldedLoad)
8561 return false;
8562 UnfoldLoad &= FoldedLoad;
8563 if (UnfoldStore && !FoldedStore)
8564 return false;
8565 UnfoldStore &= FoldedStore;
8566
8567 const MCInstrDesc &MCID = get(Opcode: Opc);
8568
8569 const TargetRegisterClass *RC = getRegClass(MCID, OpNum: Index);
8570 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
8571 // TODO: Check if 32-byte or greater accesses are slow too?
8572 if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
8573 Subtarget.isUnalignedMem16Slow())
8574 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
8575 // conservatively assume the address is unaligned. That's bad for
8576 // performance.
8577 return false;
8578 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
8579 SmallVector<MachineOperand, 2> BeforeOps;
8580 SmallVector<MachineOperand, 2> AfterOps;
8581 SmallVector<MachineOperand, 4> ImpOps;
8582 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
8583 MachineOperand &Op = MI.getOperand(i);
8584 if (i >= Index && i < Index + X86::AddrNumOperands)
8585 AddrOps.push_back(Elt: Op);
8586 else if (Op.isReg() && Op.isImplicit())
8587 ImpOps.push_back(Elt: Op);
8588 else if (i < Index)
8589 BeforeOps.push_back(Elt: Op);
8590 else if (i > Index)
8591 AfterOps.push_back(Elt: Op);
8592 }
8593
8594 // Emit the load or broadcast instruction.
8595 if (UnfoldLoad) {
8596 auto MMOs = extractLoadMMOs(MMOs: MI.memoperands(), MF);
8597
8598 unsigned Opc;
8599 if (I->Flags & TB_BCAST_MASK) {
8600 Opc = getBroadcastOpcode(I, RC, STI: Subtarget);
8601 } else {
8602 unsigned Alignment = std::max<uint32_t>(a: TRI.getSpillSize(RC: *RC), b: 16);
8603 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
8604 Opc = getLoadRegOpcode(DestReg: Reg, RC, IsStackAligned: isAligned, STI: Subtarget);
8605 }
8606
8607 DebugLoc DL;
8608 MachineInstrBuilder MIB = BuildMI(MF, MIMD: DL, MCID: get(Opcode: Opc), DestReg: Reg);
8609 for (const MachineOperand &AddrOp : AddrOps)
8610 MIB.add(MO: AddrOp);
8611 MIB.setMemRefs(MMOs);
8612 NewMIs.push_back(Elt: MIB);
8613
8614 if (UnfoldStore) {
8615 // Address operands cannot be marked isKill.
8616 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
8617 MachineOperand &MO = NewMIs[0]->getOperand(i);
8618 if (MO.isReg())
8619 MO.setIsKill(false);
8620 }
8621 }
8622 }
8623
8624 // Emit the data processing instruction.
8625 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, DL: MI.getDebugLoc(), NoImplicit: true);
8626 MachineInstrBuilder MIB(MF, DataMI);
8627
8628 if (FoldedStore)
8629 MIB.addReg(RegNo: Reg, Flags: RegState::Define);
8630 for (MachineOperand &BeforeOp : BeforeOps)
8631 MIB.add(MO: BeforeOp);
8632 if (FoldedLoad)
8633 MIB.addReg(RegNo: Reg);
8634 for (MachineOperand &AfterOp : AfterOps)
8635 MIB.add(MO: AfterOp);
8636 for (MachineOperand &ImpOp : ImpOps) {
8637 MIB.addReg(RegNo: ImpOp.getReg(), Flags: getDefRegState(B: ImpOp.isDef()) |
8638 RegState::Implicit |
8639 getKillRegState(B: ImpOp.isKill()) |
8640 getDeadRegState(B: ImpOp.isDead()) |
8641 getUndefRegState(B: ImpOp.isUndef()));
8642 }
8643 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
8644 switch (DataMI->getOpcode()) {
8645 default:
8646 break;
8647 case X86::CMP64ri32:
8648 case X86::CMP32ri:
8649 case X86::CMP16ri:
8650 case X86::CMP8ri: {
8651 MachineOperand &MO0 = DataMI->getOperand(i: 0);
8652 MachineOperand &MO1 = DataMI->getOperand(i: 1);
8653 if (MO1.isImm() && MO1.getImm() == 0) {
8654 unsigned NewOpc;
8655 switch (DataMI->getOpcode()) {
8656 default:
8657 llvm_unreachable("Unreachable!");
8658 case X86::CMP64ri32:
8659 NewOpc = X86::TEST64rr;
8660 break;
8661 case X86::CMP32ri:
8662 NewOpc = X86::TEST32rr;
8663 break;
8664 case X86::CMP16ri:
8665 NewOpc = X86::TEST16rr;
8666 break;
8667 case X86::CMP8ri:
8668 NewOpc = X86::TEST8rr;
8669 break;
8670 }
8671 DataMI->setDesc(get(Opcode: NewOpc));
8672 MO1.ChangeToRegister(Reg: MO0.getReg(), isDef: false);
8673 }
8674 }
8675 }
8676 NewMIs.push_back(Elt: DataMI);
8677
8678 // Emit the store instruction.
8679 if (UnfoldStore) {
8680 const TargetRegisterClass *DstRC = getRegClass(MCID, OpNum: 0);
8681 auto MMOs = extractStoreMMOs(MMOs: MI.memoperands(), MF);
8682 unsigned Alignment = std::max<uint32_t>(a: TRI.getSpillSize(RC: *DstRC), b: 16);
8683 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
8684 unsigned Opc = getStoreRegOpcode(SrcReg: Reg, RC: DstRC, IsStackAligned: isAligned, STI: Subtarget);
8685 DebugLoc DL;
8686 MachineInstrBuilder MIB = BuildMI(MF, MIMD: DL, MCID: get(Opcode: Opc));
8687 for (const MachineOperand &AddrOp : AddrOps)
8688 MIB.add(MO: AddrOp);
8689 MIB.addReg(RegNo: Reg, Flags: RegState::Kill);
8690 MIB.setMemRefs(MMOs);
8691 NewMIs.push_back(Elt: MIB);
8692 }
8693
8694 return true;
8695}
8696
8697bool X86InstrInfo::unfoldMemoryOperand(
8698 SelectionDAG &DAG, SDNode *N, SmallVectorImpl<SDNode *> &NewNodes) const {
8699 if (!N->isMachineOpcode())
8700 return false;
8701
8702 const X86FoldTableEntry *I = lookupUnfoldTable(MemOp: N->getMachineOpcode());
8703 if (I == nullptr)
8704 return false;
8705 unsigned Opc = I->DstOp;
8706 unsigned Index = I->Flags & TB_INDEX_MASK;
8707 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
8708 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
8709 const MCInstrDesc &MCID = get(Opcode: Opc);
8710 MachineFunction &MF = DAG.getMachineFunction();
8711 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
8712 const TargetRegisterClass *RC = getRegClass(MCID, OpNum: Index);
8713 unsigned NumDefs = MCID.NumDefs;
8714 std::vector<SDValue> AddrOps;
8715 std::vector<SDValue> BeforeOps;
8716 std::vector<SDValue> AfterOps;
8717 SDLoc dl(N);
8718 unsigned NumOps = N->getNumOperands();
8719 for (unsigned i = 0; i != NumOps - 1; ++i) {
8720 SDValue Op = N->getOperand(Num: i);
8721 if (i >= Index - NumDefs && i < Index - NumDefs + X86::AddrNumOperands)
8722 AddrOps.push_back(x: Op);
8723 else if (i < Index - NumDefs)
8724 BeforeOps.push_back(x: Op);
8725 else if (i > Index - NumDefs)
8726 AfterOps.push_back(x: Op);
8727 }
8728 SDValue Chain = N->getOperand(Num: NumOps - 1);
8729 AddrOps.push_back(x: Chain);
8730
8731 // Emit the load instruction.
8732 SDNode *Load = nullptr;
8733 if (FoldedLoad) {
8734 EVT VT = *TRI.legalclasstypes_begin(RC: *RC);
8735 auto MMOs = extractLoadMMOs(MMOs: cast<MachineSDNode>(Val: N)->memoperands(), MF);
8736 if (MMOs.empty() && RC == &X86::VR128RegClass &&
8737 Subtarget.isUnalignedMem16Slow())
8738 // Do not introduce a slow unaligned load.
8739 return false;
8740 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
8741 // memory access is slow above.
8742
8743 unsigned Opc;
8744 if (I->Flags & TB_BCAST_MASK) {
8745 Opc = getBroadcastOpcode(I, RC, STI: Subtarget);
8746 } else {
8747 unsigned Alignment = std::max<uint32_t>(a: TRI.getSpillSize(RC: *RC), b: 16);
8748 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
8749 Opc = getLoadRegOpcode(DestReg: 0, RC, IsStackAligned: isAligned, STI: Subtarget);
8750 }
8751
8752 Load = DAG.getMachineNode(Opcode: Opc, dl, VT1: VT, VT2: MVT::Other, Ops: AddrOps);
8753 NewNodes.push_back(Elt: Load);
8754
8755 // Preserve memory reference information.
8756 DAG.setNodeMemRefs(N: cast<MachineSDNode>(Val: Load), NewMemRefs: MMOs);
8757 }
8758
8759 // Emit the data processing instruction.
8760 std::vector<EVT> VTs;
8761 const TargetRegisterClass *DstRC = nullptr;
8762 if (MCID.getNumDefs() > 0) {
8763 DstRC = getRegClass(MCID, OpNum: 0);
8764 VTs.push_back(x: *TRI.legalclasstypes_begin(RC: *DstRC));
8765 }
8766 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
8767 EVT VT = N->getValueType(ResNo: i);
8768 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
8769 VTs.push_back(x: VT);
8770 }
8771 if (Load)
8772 BeforeOps.push_back(x: SDValue(Load, 0));
8773 llvm::append_range(C&: BeforeOps, R&: AfterOps);
8774 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
8775 switch (Opc) {
8776 default:
8777 break;
8778 case X86::CMP64ri32:
8779 case X86::CMP32ri:
8780 case X86::CMP16ri:
8781 case X86::CMP8ri:
8782 if (isNullConstant(V: BeforeOps[1])) {
8783 switch (Opc) {
8784 default:
8785 llvm_unreachable("Unreachable!");
8786 case X86::CMP64ri32:
8787 Opc = X86::TEST64rr;
8788 break;
8789 case X86::CMP32ri:
8790 Opc = X86::TEST32rr;
8791 break;
8792 case X86::CMP16ri:
8793 Opc = X86::TEST16rr;
8794 break;
8795 case X86::CMP8ri:
8796 Opc = X86::TEST8rr;
8797 break;
8798 }
8799 BeforeOps[1] = BeforeOps[0];
8800 }
8801 }
8802 SDNode *NewNode = DAG.getMachineNode(Opcode: Opc, dl, ResultTys: VTs, Ops: BeforeOps);
8803 NewNodes.push_back(Elt: NewNode);
8804
8805 // Emit the store instruction.
8806 if (FoldedStore) {
8807 AddrOps.pop_back();
8808 AddrOps.push_back(x: SDValue(NewNode, 0));
8809 AddrOps.push_back(x: Chain);
8810 auto MMOs = extractStoreMMOs(MMOs: cast<MachineSDNode>(Val: N)->memoperands(), MF);
8811 if (MMOs.empty() && RC == &X86::VR128RegClass &&
8812 Subtarget.isUnalignedMem16Slow())
8813 // Do not introduce a slow unaligned store.
8814 return false;
8815 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
8816 // memory access is slow above.
8817 unsigned Alignment = std::max<uint32_t>(a: TRI.getSpillSize(RC: *RC), b: 16);
8818 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
8819 SDNode *Store =
8820 DAG.getMachineNode(Opcode: getStoreRegOpcode(SrcReg: 0, RC: DstRC, IsStackAligned: isAligned, STI: Subtarget),
8821 dl, VT: MVT::Other, Ops: AddrOps);
8822 NewNodes.push_back(Elt: Store);
8823
8824 // Preserve memory reference information.
8825 DAG.setNodeMemRefs(N: cast<MachineSDNode>(Val: Store), NewMemRefs: MMOs);
8826 }
8827
8828 return true;
8829}
8830
8831unsigned
8832X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad,
8833 bool UnfoldStore,
8834 unsigned *LoadRegIndex) const {
8835 const X86FoldTableEntry *I = lookupUnfoldTable(MemOp: Opc);
8836 if (I == nullptr)
8837 return 0;
8838 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
8839 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
8840 if (UnfoldLoad && !FoldedLoad)
8841 return 0;
8842 if (UnfoldStore && !FoldedStore)
8843 return 0;
8844 if (LoadRegIndex)
8845 *LoadRegIndex = I->Flags & TB_INDEX_MASK;
8846 return I->DstOp;
8847}
8848
8849bool X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
8850 int64_t &Offset1,
8851 int64_t &Offset2) const {
8852 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
8853 return false;
8854
8855 auto IsLoadOpcode = [&](unsigned Opcode) {
8856 switch (Opcode) {
8857 default:
8858 return false;
8859 case X86::MOV8rm:
8860 case X86::MOV16rm:
8861 case X86::MOV32rm:
8862 case X86::MOV64rm:
8863 case X86::LD_Fp32m:
8864 case X86::LD_Fp64m:
8865 case X86::LD_Fp80m:
8866 case X86::MOVSSrm:
8867 case X86::MOVSSrm_alt:
8868 case X86::MOVSDrm:
8869 case X86::MOVSDrm_alt:
8870 case X86::MMX_MOVD64rm:
8871 case X86::MMX_MOVQ64rm:
8872 case X86::MOVAPSrm:
8873 case X86::MOVUPSrm:
8874 case X86::MOVAPDrm:
8875 case X86::MOVUPDrm:
8876 case X86::MOVDQArm:
8877 case X86::MOVDQUrm:
8878 // AVX load instructions
8879 case X86::VMOVSSrm:
8880 case X86::VMOVSSrm_alt:
8881 case X86::VMOVSDrm:
8882 case X86::VMOVSDrm_alt:
8883 case X86::VMOVAPSrm:
8884 case X86::VMOVUPSrm:
8885 case X86::VMOVAPDrm:
8886 case X86::VMOVUPDrm:
8887 case X86::VMOVDQArm:
8888 case X86::VMOVDQUrm:
8889 case X86::VMOVAPSYrm:
8890 case X86::VMOVUPSYrm:
8891 case X86::VMOVAPDYrm:
8892 case X86::VMOVUPDYrm:
8893 case X86::VMOVDQAYrm:
8894 case X86::VMOVDQUYrm:
8895 // AVX512 load instructions
8896 case X86::VMOVSSZrm:
8897 case X86::VMOVSSZrm_alt:
8898 case X86::VMOVSDZrm:
8899 case X86::VMOVSDZrm_alt:
8900 case X86::VMOVAPSZ128rm:
8901 case X86::VMOVUPSZ128rm:
8902 case X86::VMOVAPSZ128rm_NOVLX:
8903 case X86::VMOVUPSZ128rm_NOVLX:
8904 case X86::VMOVAPDZ128rm:
8905 case X86::VMOVUPDZ128rm:
8906 case X86::VMOVDQU8Z128rm:
8907 case X86::VMOVDQU16Z128rm:
8908 case X86::VMOVDQA32Z128rm:
8909 case X86::VMOVDQU32Z128rm:
8910 case X86::VMOVDQA64Z128rm:
8911 case X86::VMOVDQU64Z128rm:
8912 case X86::VMOVAPSZ256rm:
8913 case X86::VMOVUPSZ256rm:
8914 case X86::VMOVAPSZ256rm_NOVLX:
8915 case X86::VMOVUPSZ256rm_NOVLX:
8916 case X86::VMOVAPDZ256rm:
8917 case X86::VMOVUPDZ256rm:
8918 case X86::VMOVDQU8Z256rm:
8919 case X86::VMOVDQU16Z256rm:
8920 case X86::VMOVDQA32Z256rm:
8921 case X86::VMOVDQU32Z256rm:
8922 case X86::VMOVDQA64Z256rm:
8923 case X86::VMOVDQU64Z256rm:
8924 case X86::VMOVAPSZrm:
8925 case X86::VMOVUPSZrm:
8926 case X86::VMOVAPDZrm:
8927 case X86::VMOVUPDZrm:
8928 case X86::VMOVDQU8Zrm:
8929 case X86::VMOVDQU16Zrm:
8930 case X86::VMOVDQA32Zrm:
8931 case X86::VMOVDQU32Zrm:
8932 case X86::VMOVDQA64Zrm:
8933 case X86::VMOVDQU64Zrm:
8934 case X86::KMOVBkm:
8935 case X86::KMOVBkm_EVEX:
8936 case X86::KMOVWkm:
8937 case X86::KMOVWkm_EVEX:
8938 case X86::KMOVDkm:
8939 case X86::KMOVDkm_EVEX:
8940 case X86::KMOVQkm:
8941 case X86::KMOVQkm_EVEX:
8942 return true;
8943 }
8944 };
8945
8946 if (!IsLoadOpcode(Load1->getMachineOpcode()) ||
8947 !IsLoadOpcode(Load2->getMachineOpcode()))
8948 return false;
8949
8950 // Lambda to check if both the loads have the same value for an operand index.
8951 auto HasSameOp = [&](int I) {
8952 return Load1->getOperand(Num: I) == Load2->getOperand(Num: I);
8953 };
8954
8955 // All operands except the displacement should match.
8956 if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
8957 !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
8958 return false;
8959
8960 // Chain Operand must be the same.
8961 if (!HasSameOp(5))
8962 return false;
8963
8964 // Now let's examine if the displacements are constants.
8965 auto Disp1 = dyn_cast<ConstantSDNode>(Val: Load1->getOperand(Num: X86::AddrDisp));
8966 auto Disp2 = dyn_cast<ConstantSDNode>(Val: Load2->getOperand(Num: X86::AddrDisp));
8967 if (!Disp1 || !Disp2)
8968 return false;
8969
8970 Offset1 = Disp1->getSExtValue();
8971 Offset2 = Disp2->getSExtValue();
8972 return true;
8973}
8974
8975bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
8976 int64_t Offset1, int64_t Offset2,
8977 unsigned NumLoads) const {
8978 assert(Offset2 > Offset1);
8979 if ((Offset2 - Offset1) / 8 > 64)
8980 return false;
8981
8982 unsigned Opc1 = Load1->getMachineOpcode();
8983 unsigned Opc2 = Load2->getMachineOpcode();
8984 if (Opc1 != Opc2)
8985 return false; // FIXME: overly conservative?
8986
8987 switch (Opc1) {
8988 default:
8989 break;
8990 case X86::LD_Fp32m:
8991 case X86::LD_Fp64m:
8992 case X86::LD_Fp80m:
8993 case X86::MMX_MOVD64rm:
8994 case X86::MMX_MOVQ64rm:
8995 return false;
8996 }
8997
8998 EVT VT = Load1->getValueType(ResNo: 0);
8999 switch (VT.getSimpleVT().SimpleTy) {
9000 default:
9001 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
9002 // have 16 of them to play with.
9003 if (Subtarget.is64Bit()) {
9004 if (NumLoads >= 3)
9005 return false;
9006 } else if (NumLoads) {
9007 return false;
9008 }
9009 break;
9010 case MVT::i8:
9011 case MVT::i16:
9012 case MVT::i32:
9013 case MVT::i64:
9014 case MVT::f32:
9015 case MVT::f64:
9016 if (NumLoads)
9017 return false;
9018 break;
9019 }
9020
9021 return true;
9022}
9023
9024bool X86InstrInfo::isSchedulingBoundary(const MachineInstr &MI,
9025 const MachineBasicBlock *MBB,
9026 const MachineFunction &MF) const {
9027
9028 // ENDBR instructions should not be scheduled around.
9029 unsigned Opcode = MI.getOpcode();
9030 if (Opcode == X86::ENDBR64 || Opcode == X86::ENDBR32 ||
9031 Opcode == X86::PLDTILECFGV)
9032 return true;
9033
9034 // Frame setup and destroy can't be scheduled around.
9035 if (MI.getFlag(Flag: MachineInstr::FrameSetup) ||
9036 MI.getFlag(Flag: MachineInstr::FrameDestroy))
9037 return true;
9038
9039 return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF);
9040}
9041
9042bool X86InstrInfo::reverseBranchCondition(
9043 SmallVectorImpl<MachineOperand> &Cond) const {
9044 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
9045 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
9046 Cond[0].setImm(GetOppositeBranchCondition(CC));
9047 return false;
9048}
9049
9050bool X86InstrInfo::isSafeToMoveRegClassDefs(
9051 const TargetRegisterClass *RC) const {
9052 // FIXME: Return false for x87 stack register classes for now. We can't
9053 // allow any loads of these registers before FpGet_ST0_80.
9054 return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
9055 RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
9056 RC == &X86::RFP80RegClass);
9057}
9058
9059/// Return a virtual register initialized with the
9060/// the global base register value. Output instructions required to
9061/// initialize the register in the function entry block, if necessary.
9062///
9063/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
9064///
9065Register X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
9066 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
9067 Register GlobalBaseReg = X86FI->getGlobalBaseReg();
9068 if (GlobalBaseReg)
9069 return GlobalBaseReg;
9070
9071 // Create the register. The code to initialize it is inserted
9072 // later, by the CGBR pass (below).
9073 MachineRegisterInfo &RegInfo = MF->getRegInfo();
9074 GlobalBaseReg = RegInfo.createVirtualRegister(
9075 RegClass: Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
9076 X86FI->setGlobalBaseReg(GlobalBaseReg);
9077 return GlobalBaseReg;
9078}
9079
9080// FIXME: Some shuffle and unpack instructions have equivalents in different
9081// domains, but they require a bit more work than just switching opcodes.
9082
9083static const uint16_t *lookup(unsigned opcode, unsigned domain,
9084 ArrayRef<uint16_t[3]> Table) {
9085 for (const uint16_t(&Row)[3] : Table)
9086 if (Row[domain - 1] == opcode)
9087 return Row;
9088 return nullptr;
9089}
9090
9091static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
9092 ArrayRef<uint16_t[4]> Table) {
9093 // If this is the integer domain make sure to check both integer columns.
9094 for (const uint16_t(&Row)[4] : Table)
9095 if (Row[domain - 1] == opcode || (domain == 3 && Row[3] == opcode))
9096 return Row;
9097 return nullptr;
9098}
9099
9100// Helper to attempt to widen/narrow blend masks.
9101static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
9102 unsigned NewWidth, unsigned *pNewMask = nullptr) {
9103 assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
9104 "Illegal blend mask scale");
9105 unsigned NewMask = 0;
9106
9107 if ((OldWidth % NewWidth) == 0) {
9108 unsigned Scale = OldWidth / NewWidth;
9109 unsigned SubMask = (1u << Scale) - 1;
9110 for (unsigned i = 0; i != NewWidth; ++i) {
9111 unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
9112 if (Sub == SubMask)
9113 NewMask |= (1u << i);
9114 else if (Sub != 0x0)
9115 return false;
9116 }
9117 } else {
9118 unsigned Scale = NewWidth / OldWidth;
9119 unsigned SubMask = (1u << Scale) - 1;
9120 for (unsigned i = 0; i != OldWidth; ++i) {
9121 if (OldMask & (1 << i)) {
9122 NewMask |= (SubMask << (i * Scale));
9123 }
9124 }
9125 }
9126
9127 if (pNewMask)
9128 *pNewMask = NewMask;
9129 return true;
9130}
9131
9132uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
9133 unsigned Opcode = MI.getOpcode();
9134 unsigned NumOperands = MI.getDesc().getNumOperands();
9135
9136 auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
9137 uint16_t validDomains = 0;
9138 if (MI.getOperand(i: NumOperands - 1).isImm()) {
9139 unsigned Imm = MI.getOperand(i: NumOperands - 1).getImm();
9140 if (AdjustBlendMask(OldMask: Imm, OldWidth: ImmWidth, NewWidth: Is256 ? 8 : 4))
9141 validDomains |= 0x2; // PackedSingle
9142 if (AdjustBlendMask(OldMask: Imm, OldWidth: ImmWidth, NewWidth: Is256 ? 4 : 2))
9143 validDomains |= 0x4; // PackedDouble
9144 if (!Is256 || Subtarget.hasAVX2())
9145 validDomains |= 0x8; // PackedInt
9146 }
9147 return validDomains;
9148 };
9149
9150 switch (Opcode) {
9151 case X86::BLENDPDrmi:
9152 case X86::BLENDPDrri:
9153 case X86::VBLENDPDrmi:
9154 case X86::VBLENDPDrri:
9155 return GetBlendDomains(2, false);
9156 case X86::VBLENDPDYrmi:
9157 case X86::VBLENDPDYrri:
9158 return GetBlendDomains(4, true);
9159 case X86::BLENDPSrmi:
9160 case X86::BLENDPSrri:
9161 case X86::VBLENDPSrmi:
9162 case X86::VBLENDPSrri:
9163 case X86::VPBLENDDrmi:
9164 case X86::VPBLENDDrri:
9165 return GetBlendDomains(4, false);
9166 case X86::VBLENDPSYrmi:
9167 case X86::VBLENDPSYrri:
9168 case X86::VPBLENDDYrmi:
9169 case X86::VPBLENDDYrri:
9170 return GetBlendDomains(8, true);
9171 case X86::PBLENDWrmi:
9172 case X86::PBLENDWrri:
9173 case X86::VPBLENDWrmi:
9174 case X86::VPBLENDWrri:
9175 // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
9176 case X86::VPBLENDWYrmi:
9177 case X86::VPBLENDWYrri:
9178 return GetBlendDomains(8, false);
9179 case X86::VPANDDZ128rr:
9180 case X86::VPANDDZ128rm:
9181 case X86::VPANDDZ256rr:
9182 case X86::VPANDDZ256rm:
9183 case X86::VPANDQZ128rr:
9184 case X86::VPANDQZ128rm:
9185 case X86::VPANDQZ256rr:
9186 case X86::VPANDQZ256rm:
9187 case X86::VPANDNDZ128rr:
9188 case X86::VPANDNDZ128rm:
9189 case X86::VPANDNDZ256rr:
9190 case X86::VPANDNDZ256rm:
9191 case X86::VPANDNQZ128rr:
9192 case X86::VPANDNQZ128rm:
9193 case X86::VPANDNQZ256rr:
9194 case X86::VPANDNQZ256rm:
9195 case X86::VPORDZ128rr:
9196 case X86::VPORDZ128rm:
9197 case X86::VPORDZ256rr:
9198 case X86::VPORDZ256rm:
9199 case X86::VPORQZ128rr:
9200 case X86::VPORQZ128rm:
9201 case X86::VPORQZ256rr:
9202 case X86::VPORQZ256rm:
9203 case X86::VPXORDZ128rr:
9204 case X86::VPXORDZ128rm:
9205 case X86::VPXORDZ256rr:
9206 case X86::VPXORDZ256rm:
9207 case X86::VPXORQZ128rr:
9208 case X86::VPXORQZ128rm:
9209 case X86::VPXORQZ256rr:
9210 case X86::VPXORQZ256rm:
9211 // If we don't have DQI see if we can still switch from an EVEX integer
9212 // instruction to a VEX floating point instruction.
9213 if (Subtarget.hasDQI())
9214 return 0;
9215
9216 if (RI.getEncodingValue(Reg: MI.getOperand(i: 0).getReg()) >= 16)
9217 return 0;
9218 if (RI.getEncodingValue(Reg: MI.getOperand(i: 1).getReg()) >= 16)
9219 return 0;
9220 // Register forms will have 3 operands. Memory form will have more.
9221 if (NumOperands == 3 &&
9222 RI.getEncodingValue(Reg: MI.getOperand(i: 2).getReg()) >= 16)
9223 return 0;
9224
9225 // All domains are valid.
9226 return 0xe;
9227 case X86::MOVHLPSrr:
9228 // We can swap domains when both inputs are the same register.
9229 // FIXME: This doesn't catch all the cases we would like. If the input
9230 // register isn't KILLed by the instruction, the two address instruction
9231 // pass puts a COPY on one input. The other input uses the original
9232 // register. This prevents the same physical register from being used by
9233 // both inputs.
9234 if (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 2).getReg() &&
9235 MI.getOperand(i: 0).getSubReg() == 0 &&
9236 MI.getOperand(i: 1).getSubReg() == 0 && MI.getOperand(i: 2).getSubReg() == 0)
9237 return 0x6;
9238 return 0;
9239 case X86::SHUFPDrri:
9240 return 0x6;
9241 }
9242 return 0;
9243}
9244
9245#include "X86ReplaceableInstrs.def"
9246
9247bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
9248 unsigned Domain) const {
9249 assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
9250 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
9251 assert(dom && "Not an SSE instruction");
9252
9253 unsigned Opcode = MI.getOpcode();
9254 unsigned NumOperands = MI.getDesc().getNumOperands();
9255
9256 auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
9257 if (MI.getOperand(i: NumOperands - 1).isImm()) {
9258 unsigned Imm = MI.getOperand(i: NumOperands - 1).getImm() & 255;
9259 Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
9260 unsigned NewImm = Imm;
9261
9262 const uint16_t *table = lookup(opcode: Opcode, domain: dom, Table: ReplaceableBlendInstrs);
9263 if (!table)
9264 table = lookup(opcode: Opcode, domain: dom, Table: ReplaceableBlendAVX2Instrs);
9265
9266 if (Domain == 1) { // PackedSingle
9267 AdjustBlendMask(OldMask: Imm, OldWidth: ImmWidth, NewWidth: Is256 ? 8 : 4, pNewMask: &NewImm);
9268 } else if (Domain == 2) { // PackedDouble
9269 AdjustBlendMask(OldMask: Imm, OldWidth: ImmWidth, NewWidth: Is256 ? 4 : 2, pNewMask: &NewImm);
9270 } else if (Domain == 3) { // PackedInt
9271 if (Subtarget.hasAVX2()) {
9272 // If we are already VPBLENDW use that, else use VPBLENDD.
9273 if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
9274 table = lookup(opcode: Opcode, domain: dom, Table: ReplaceableBlendAVX2Instrs);
9275 AdjustBlendMask(OldMask: Imm, OldWidth: ImmWidth, NewWidth: Is256 ? 8 : 4, pNewMask: &NewImm);
9276 }
9277 } else {
9278 assert(!Is256 && "128-bit vector expected");
9279 AdjustBlendMask(OldMask: Imm, OldWidth: ImmWidth, NewWidth: 8, pNewMask: &NewImm);
9280 }
9281 }
9282
9283 assert(table && table[Domain - 1] && "Unknown domain op");
9284 MI.setDesc(get(Opcode: table[Domain - 1]));
9285 MI.getOperand(i: NumOperands - 1).setImm(NewImm & 255);
9286 }
9287 return true;
9288 };
9289
9290 switch (Opcode) {
9291 case X86::BLENDPDrmi:
9292 case X86::BLENDPDrri:
9293 case X86::VBLENDPDrmi:
9294 case X86::VBLENDPDrri:
9295 return SetBlendDomain(2, false);
9296 case X86::VBLENDPDYrmi:
9297 case X86::VBLENDPDYrri:
9298 return SetBlendDomain(4, true);
9299 case X86::BLENDPSrmi:
9300 case X86::BLENDPSrri:
9301 case X86::VBLENDPSrmi:
9302 case X86::VBLENDPSrri:
9303 case X86::VPBLENDDrmi:
9304 case X86::VPBLENDDrri:
9305 return SetBlendDomain(4, false);
9306 case X86::VBLENDPSYrmi:
9307 case X86::VBLENDPSYrri:
9308 case X86::VPBLENDDYrmi:
9309 case X86::VPBLENDDYrri:
9310 return SetBlendDomain(8, true);
9311 case X86::PBLENDWrmi:
9312 case X86::PBLENDWrri:
9313 case X86::VPBLENDWrmi:
9314 case X86::VPBLENDWrri:
9315 return SetBlendDomain(8, false);
9316 case X86::VPBLENDWYrmi:
9317 case X86::VPBLENDWYrri:
9318 return SetBlendDomain(16, true);
9319 case X86::VPANDDZ128rr:
9320 case X86::VPANDDZ128rm:
9321 case X86::VPANDDZ256rr:
9322 case X86::VPANDDZ256rm:
9323 case X86::VPANDQZ128rr:
9324 case X86::VPANDQZ128rm:
9325 case X86::VPANDQZ256rr:
9326 case X86::VPANDQZ256rm:
9327 case X86::VPANDNDZ128rr:
9328 case X86::VPANDNDZ128rm:
9329 case X86::VPANDNDZ256rr:
9330 case X86::VPANDNDZ256rm:
9331 case X86::VPANDNQZ128rr:
9332 case X86::VPANDNQZ128rm:
9333 case X86::VPANDNQZ256rr:
9334 case X86::VPANDNQZ256rm:
9335 case X86::VPORDZ128rr:
9336 case X86::VPORDZ128rm:
9337 case X86::VPORDZ256rr:
9338 case X86::VPORDZ256rm:
9339 case X86::VPORQZ128rr:
9340 case X86::VPORQZ128rm:
9341 case X86::VPORQZ256rr:
9342 case X86::VPORQZ256rm:
9343 case X86::VPXORDZ128rr:
9344 case X86::VPXORDZ128rm:
9345 case X86::VPXORDZ256rr:
9346 case X86::VPXORDZ256rm:
9347 case X86::VPXORQZ128rr:
9348 case X86::VPXORQZ128rm:
9349 case X86::VPXORQZ256rr:
9350 case X86::VPXORQZ256rm: {
9351 // Without DQI, convert EVEX instructions to VEX instructions.
9352 if (Subtarget.hasDQI())
9353 return false;
9354
9355 const uint16_t *table =
9356 lookupAVX512(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableCustomAVX512LogicInstrs);
9357 assert(table && "Instruction not found in table?");
9358 // Don't change integer Q instructions to D instructions and
9359 // use D intructions if we started with a PS instruction.
9360 if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
9361 Domain = 4;
9362 MI.setDesc(get(Opcode: table[Domain - 1]));
9363 return true;
9364 }
9365 case X86::UNPCKHPDrr:
9366 case X86::MOVHLPSrr:
9367 // We just need to commute the instruction which will switch the domains.
9368 if (Domain != dom && Domain != 3 &&
9369 MI.getOperand(i: 1).getReg() == MI.getOperand(i: 2).getReg() &&
9370 MI.getOperand(i: 0).getSubReg() == 0 &&
9371 MI.getOperand(i: 1).getSubReg() == 0 &&
9372 MI.getOperand(i: 2).getSubReg() == 0) {
9373 commuteInstruction(MI, NewMI: false);
9374 return true;
9375 }
9376 // We must always return true for MOVHLPSrr.
9377 if (Opcode == X86::MOVHLPSrr)
9378 return true;
9379 break;
9380 case X86::SHUFPDrri: {
9381 if (Domain == 1) {
9382 unsigned Imm = MI.getOperand(i: 3).getImm();
9383 unsigned NewImm = 0x44;
9384 if (Imm & 1)
9385 NewImm |= 0x0a;
9386 if (Imm & 2)
9387 NewImm |= 0xa0;
9388 MI.getOperand(i: 3).setImm(NewImm);
9389 MI.setDesc(get(Opcode: X86::SHUFPSrri));
9390 }
9391 return true;
9392 }
9393 }
9394 return false;
9395}
9396
9397std::pair<uint16_t, uint16_t>
9398X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
9399 uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
9400 unsigned opcode = MI.getOpcode();
9401 uint16_t validDomains = 0;
9402 if (domain) {
9403 // Attempt to match for custom instructions.
9404 validDomains = getExecutionDomainCustom(MI);
9405 if (validDomains)
9406 return std::make_pair(x&: domain, y&: validDomains);
9407
9408 if (lookup(opcode, domain, Table: ReplaceableInstrs)) {
9409 validDomains = 0xe;
9410 } else if (lookup(opcode, domain, Table: ReplaceableInstrsAVX2)) {
9411 validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
9412 } else if (lookup(opcode, domain, Table: ReplaceableInstrsFP)) {
9413 validDomains = 0x6;
9414 } else if (lookup(opcode, domain, Table: ReplaceableInstrsAVX2InsertExtract)) {
9415 // Insert/extract instructions should only effect domain if AVX2
9416 // is enabled.
9417 if (!Subtarget.hasAVX2())
9418 return std::make_pair(x: 0, y: 0);
9419 validDomains = 0xe;
9420 } else if (lookupAVX512(opcode, domain, Table: ReplaceableInstrsAVX512)) {
9421 validDomains = 0xe;
9422 } else if (Subtarget.hasDQI() &&
9423 lookupAVX512(opcode, domain, Table: ReplaceableInstrsAVX512DQ)) {
9424 validDomains = 0xe;
9425 } else if (Subtarget.hasDQI()) {
9426 if (const uint16_t *table =
9427 lookupAVX512(opcode, domain, Table: ReplaceableInstrsAVX512DQMasked)) {
9428 if (domain == 1 || (domain == 3 && table[3] == opcode))
9429 validDomains = 0xa;
9430 else
9431 validDomains = 0xc;
9432 }
9433 }
9434 }
9435 return std::make_pair(x&: domain, y&: validDomains);
9436}
9437
9438void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
9439 assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
9440 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
9441 assert(dom && "Not an SSE instruction");
9442
9443 // Attempt to match for custom instructions.
9444 if (setExecutionDomainCustom(MI, Domain))
9445 return;
9446
9447 const uint16_t *table = lookup(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrs);
9448 if (!table) { // try the other table
9449 assert((Subtarget.hasAVX2() || Domain < 3) &&
9450 "256-bit vector operations only available in AVX2");
9451 table = lookup(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrsAVX2);
9452 }
9453 if (!table) { // try the FP table
9454 table = lookup(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrsFP);
9455 assert((!table || Domain < 3) &&
9456 "Can only select PackedSingle or PackedDouble");
9457 }
9458 if (!table) { // try the other table
9459 assert(Subtarget.hasAVX2() &&
9460 "256-bit insert/extract only available in AVX2");
9461 table = lookup(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrsAVX2InsertExtract);
9462 }
9463 if (!table) { // try the AVX512 table
9464 assert(Subtarget.hasAVX512() && "Requires AVX-512");
9465 table = lookupAVX512(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrsAVX512);
9466 // Don't change integer Q instructions to D instructions.
9467 if (table && Domain == 3 && table[3] == MI.getOpcode())
9468 Domain = 4;
9469 }
9470 if (!table) { // try the AVX512DQ table
9471 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
9472 table = lookupAVX512(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrsAVX512DQ);
9473 // Don't change integer Q instructions to D instructions and
9474 // use D instructions if we started with a PS instruction.
9475 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
9476 Domain = 4;
9477 }
9478 if (!table) { // try the AVX512DQMasked table
9479 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
9480 table = lookupAVX512(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrsAVX512DQMasked);
9481 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
9482 Domain = 4;
9483 }
9484 assert(table && "Cannot change domain");
9485 MI.setDesc(get(Opcode: table[Domain - 1]));
9486}
9487
9488void X86InstrInfo::insertNoop(MachineBasicBlock &MBB,
9489 MachineBasicBlock::iterator MI) const {
9490 DebugLoc DL;
9491 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: get(Opcode: X86::NOOP));
9492}
9493
9494/// Return the noop instruction to use for a noop.
9495MCInst X86InstrInfo::getNop() const {
9496 MCInst Nop;
9497 Nop.setOpcode(X86::NOOP);
9498 return Nop;
9499}
9500
9501bool X86InstrInfo::isHighLatencyDef(int opc) const {
9502 switch (opc) {
9503 default:
9504 return false;
9505 case X86::DIVPDrm:
9506 case X86::DIVPDrr:
9507 case X86::DIVPSrm:
9508 case X86::DIVPSrr:
9509 case X86::DIVSDrm:
9510 case X86::DIVSDrm_Int:
9511 case X86::DIVSDrr:
9512 case X86::DIVSDrr_Int:
9513 case X86::DIVSSrm:
9514 case X86::DIVSSrm_Int:
9515 case X86::DIVSSrr:
9516 case X86::DIVSSrr_Int:
9517 case X86::SQRTPDm:
9518 case X86::SQRTPDr:
9519 case X86::SQRTPSm:
9520 case X86::SQRTPSr:
9521 case X86::SQRTSDm:
9522 case X86::SQRTSDm_Int:
9523 case X86::SQRTSDr:
9524 case X86::SQRTSDr_Int:
9525 case X86::SQRTSSm:
9526 case X86::SQRTSSm_Int:
9527 case X86::SQRTSSr:
9528 case X86::SQRTSSr_Int:
9529 // AVX instructions with high latency
9530 case X86::VDIVPDrm:
9531 case X86::VDIVPDrr:
9532 case X86::VDIVPDYrm:
9533 case X86::VDIVPDYrr:
9534 case X86::VDIVPSrm:
9535 case X86::VDIVPSrr:
9536 case X86::VDIVPSYrm:
9537 case X86::VDIVPSYrr:
9538 case X86::VDIVSDrm:
9539 case X86::VDIVSDrm_Int:
9540 case X86::VDIVSDrr:
9541 case X86::VDIVSDrr_Int:
9542 case X86::VDIVSSrm:
9543 case X86::VDIVSSrm_Int:
9544 case X86::VDIVSSrr:
9545 case X86::VDIVSSrr_Int:
9546 case X86::VSQRTPDm:
9547 case X86::VSQRTPDr:
9548 case X86::VSQRTPDYm:
9549 case X86::VSQRTPDYr:
9550 case X86::VSQRTPSm:
9551 case X86::VSQRTPSr:
9552 case X86::VSQRTPSYm:
9553 case X86::VSQRTPSYr:
9554 case X86::VSQRTSDm:
9555 case X86::VSQRTSDm_Int:
9556 case X86::VSQRTSDr:
9557 case X86::VSQRTSDr_Int:
9558 case X86::VSQRTSSm:
9559 case X86::VSQRTSSm_Int:
9560 case X86::VSQRTSSr:
9561 case X86::VSQRTSSr_Int:
9562 // AVX512 instructions with high latency
9563 case X86::VDIVPDZ128rm:
9564 case X86::VDIVPDZ128rmb:
9565 case X86::VDIVPDZ128rmbk:
9566 case X86::VDIVPDZ128rmbkz:
9567 case X86::VDIVPDZ128rmk:
9568 case X86::VDIVPDZ128rmkz:
9569 case X86::VDIVPDZ128rr:
9570 case X86::VDIVPDZ128rrk:
9571 case X86::VDIVPDZ128rrkz:
9572 case X86::VDIVPDZ256rm:
9573 case X86::VDIVPDZ256rmb:
9574 case X86::VDIVPDZ256rmbk:
9575 case X86::VDIVPDZ256rmbkz:
9576 case X86::VDIVPDZ256rmk:
9577 case X86::VDIVPDZ256rmkz:
9578 case X86::VDIVPDZ256rr:
9579 case X86::VDIVPDZ256rrk:
9580 case X86::VDIVPDZ256rrkz:
9581 case X86::VDIVPDZrrb:
9582 case X86::VDIVPDZrrbk:
9583 case X86::VDIVPDZrrbkz:
9584 case X86::VDIVPDZrm:
9585 case X86::VDIVPDZrmb:
9586 case X86::VDIVPDZrmbk:
9587 case X86::VDIVPDZrmbkz:
9588 case X86::VDIVPDZrmk:
9589 case X86::VDIVPDZrmkz:
9590 case X86::VDIVPDZrr:
9591 case X86::VDIVPDZrrk:
9592 case X86::VDIVPDZrrkz:
9593 case X86::VDIVPSZ128rm:
9594 case X86::VDIVPSZ128rmb:
9595 case X86::VDIVPSZ128rmbk:
9596 case X86::VDIVPSZ128rmbkz:
9597 case X86::VDIVPSZ128rmk:
9598 case X86::VDIVPSZ128rmkz:
9599 case X86::VDIVPSZ128rr:
9600 case X86::VDIVPSZ128rrk:
9601 case X86::VDIVPSZ128rrkz:
9602 case X86::VDIVPSZ256rm:
9603 case X86::VDIVPSZ256rmb:
9604 case X86::VDIVPSZ256rmbk:
9605 case X86::VDIVPSZ256rmbkz:
9606 case X86::VDIVPSZ256rmk:
9607 case X86::VDIVPSZ256rmkz:
9608 case X86::VDIVPSZ256rr:
9609 case X86::VDIVPSZ256rrk:
9610 case X86::VDIVPSZ256rrkz:
9611 case X86::VDIVPSZrrb:
9612 case X86::VDIVPSZrrbk:
9613 case X86::VDIVPSZrrbkz:
9614 case X86::VDIVPSZrm:
9615 case X86::VDIVPSZrmb:
9616 case X86::VDIVPSZrmbk:
9617 case X86::VDIVPSZrmbkz:
9618 case X86::VDIVPSZrmk:
9619 case X86::VDIVPSZrmkz:
9620 case X86::VDIVPSZrr:
9621 case X86::VDIVPSZrrk:
9622 case X86::VDIVPSZrrkz:
9623 case X86::VDIVSDZrm:
9624 case X86::VDIVSDZrr:
9625 case X86::VDIVSDZrm_Int:
9626 case X86::VDIVSDZrmk_Int:
9627 case X86::VDIVSDZrmkz_Int:
9628 case X86::VDIVSDZrr_Int:
9629 case X86::VDIVSDZrrk_Int:
9630 case X86::VDIVSDZrrkz_Int:
9631 case X86::VDIVSDZrrb_Int:
9632 case X86::VDIVSDZrrbk_Int:
9633 case X86::VDIVSDZrrbkz_Int:
9634 case X86::VDIVSSZrm:
9635 case X86::VDIVSSZrr:
9636 case X86::VDIVSSZrm_Int:
9637 case X86::VDIVSSZrmk_Int:
9638 case X86::VDIVSSZrmkz_Int:
9639 case X86::VDIVSSZrr_Int:
9640 case X86::VDIVSSZrrk_Int:
9641 case X86::VDIVSSZrrkz_Int:
9642 case X86::VDIVSSZrrb_Int:
9643 case X86::VDIVSSZrrbk_Int:
9644 case X86::VDIVSSZrrbkz_Int:
9645 case X86::VSQRTPDZ128m:
9646 case X86::VSQRTPDZ128mb:
9647 case X86::VSQRTPDZ128mbk:
9648 case X86::VSQRTPDZ128mbkz:
9649 case X86::VSQRTPDZ128mk:
9650 case X86::VSQRTPDZ128mkz:
9651 case X86::VSQRTPDZ128r:
9652 case X86::VSQRTPDZ128rk:
9653 case X86::VSQRTPDZ128rkz:
9654 case X86::VSQRTPDZ256m:
9655 case X86::VSQRTPDZ256mb:
9656 case X86::VSQRTPDZ256mbk:
9657 case X86::VSQRTPDZ256mbkz:
9658 case X86::VSQRTPDZ256mk:
9659 case X86::VSQRTPDZ256mkz:
9660 case X86::VSQRTPDZ256r:
9661 case X86::VSQRTPDZ256rk:
9662 case X86::VSQRTPDZ256rkz:
9663 case X86::VSQRTPDZm:
9664 case X86::VSQRTPDZmb:
9665 case X86::VSQRTPDZmbk:
9666 case X86::VSQRTPDZmbkz:
9667 case X86::VSQRTPDZmk:
9668 case X86::VSQRTPDZmkz:
9669 case X86::VSQRTPDZr:
9670 case X86::VSQRTPDZrb:
9671 case X86::VSQRTPDZrbk:
9672 case X86::VSQRTPDZrbkz:
9673 case X86::VSQRTPDZrk:
9674 case X86::VSQRTPDZrkz:
9675 case X86::VSQRTPSZ128m:
9676 case X86::VSQRTPSZ128mb:
9677 case X86::VSQRTPSZ128mbk:
9678 case X86::VSQRTPSZ128mbkz:
9679 case X86::VSQRTPSZ128mk:
9680 case X86::VSQRTPSZ128mkz:
9681 case X86::VSQRTPSZ128r:
9682 case X86::VSQRTPSZ128rk:
9683 case X86::VSQRTPSZ128rkz:
9684 case X86::VSQRTPSZ256m:
9685 case X86::VSQRTPSZ256mb:
9686 case X86::VSQRTPSZ256mbk:
9687 case X86::VSQRTPSZ256mbkz:
9688 case X86::VSQRTPSZ256mk:
9689 case X86::VSQRTPSZ256mkz:
9690 case X86::VSQRTPSZ256r:
9691 case X86::VSQRTPSZ256rk:
9692 case X86::VSQRTPSZ256rkz:
9693 case X86::VSQRTPSZm:
9694 case X86::VSQRTPSZmb:
9695 case X86::VSQRTPSZmbk:
9696 case X86::VSQRTPSZmbkz:
9697 case X86::VSQRTPSZmk:
9698 case X86::VSQRTPSZmkz:
9699 case X86::VSQRTPSZr:
9700 case X86::VSQRTPSZrb:
9701 case X86::VSQRTPSZrbk:
9702 case X86::VSQRTPSZrbkz:
9703 case X86::VSQRTPSZrk:
9704 case X86::VSQRTPSZrkz:
9705 case X86::VSQRTSDZm:
9706 case X86::VSQRTSDZm_Int:
9707 case X86::VSQRTSDZmk_Int:
9708 case X86::VSQRTSDZmkz_Int:
9709 case X86::VSQRTSDZr:
9710 case X86::VSQRTSDZr_Int:
9711 case X86::VSQRTSDZrk_Int:
9712 case X86::VSQRTSDZrkz_Int:
9713 case X86::VSQRTSDZrb_Int:
9714 case X86::VSQRTSDZrbk_Int:
9715 case X86::VSQRTSDZrbkz_Int:
9716 case X86::VSQRTSSZm:
9717 case X86::VSQRTSSZm_Int:
9718 case X86::VSQRTSSZmk_Int:
9719 case X86::VSQRTSSZmkz_Int:
9720 case X86::VSQRTSSZr:
9721 case X86::VSQRTSSZr_Int:
9722 case X86::VSQRTSSZrk_Int:
9723 case X86::VSQRTSSZrkz_Int:
9724 case X86::VSQRTSSZrb_Int:
9725 case X86::VSQRTSSZrbk_Int:
9726 case X86::VSQRTSSZrbkz_Int:
9727
9728 case X86::VGATHERDPDYrm:
9729 case X86::VGATHERDPDZ128rm:
9730 case X86::VGATHERDPDZ256rm:
9731 case X86::VGATHERDPDZrm:
9732 case X86::VGATHERDPDrm:
9733 case X86::VGATHERDPSYrm:
9734 case X86::VGATHERDPSZ128rm:
9735 case X86::VGATHERDPSZ256rm:
9736 case X86::VGATHERDPSZrm:
9737 case X86::VGATHERDPSrm:
9738 case X86::VGATHERPF0DPDm:
9739 case X86::VGATHERPF0DPSm:
9740 case X86::VGATHERPF0QPDm:
9741 case X86::VGATHERPF0QPSm:
9742 case X86::VGATHERPF1DPDm:
9743 case X86::VGATHERPF1DPSm:
9744 case X86::VGATHERPF1QPDm:
9745 case X86::VGATHERPF1QPSm:
9746 case X86::VGATHERQPDYrm:
9747 case X86::VGATHERQPDZ128rm:
9748 case X86::VGATHERQPDZ256rm:
9749 case X86::VGATHERQPDZrm:
9750 case X86::VGATHERQPDrm:
9751 case X86::VGATHERQPSYrm:
9752 case X86::VGATHERQPSZ128rm:
9753 case X86::VGATHERQPSZ256rm:
9754 case X86::VGATHERQPSZrm:
9755 case X86::VGATHERQPSrm:
9756 case X86::VPGATHERDDYrm:
9757 case X86::VPGATHERDDZ128rm:
9758 case X86::VPGATHERDDZ256rm:
9759 case X86::VPGATHERDDZrm:
9760 case X86::VPGATHERDDrm:
9761 case X86::VPGATHERDQYrm:
9762 case X86::VPGATHERDQZ128rm:
9763 case X86::VPGATHERDQZ256rm:
9764 case X86::VPGATHERDQZrm:
9765 case X86::VPGATHERDQrm:
9766 case X86::VPGATHERQDYrm:
9767 case X86::VPGATHERQDZ128rm:
9768 case X86::VPGATHERQDZ256rm:
9769 case X86::VPGATHERQDZrm:
9770 case X86::VPGATHERQDrm:
9771 case X86::VPGATHERQQYrm:
9772 case X86::VPGATHERQQZ128rm:
9773 case X86::VPGATHERQQZ256rm:
9774 case X86::VPGATHERQQZrm:
9775 case X86::VPGATHERQQrm:
9776 case X86::VSCATTERDPDZ128mr:
9777 case X86::VSCATTERDPDZ256mr:
9778 case X86::VSCATTERDPDZmr:
9779 case X86::VSCATTERDPSZ128mr:
9780 case X86::VSCATTERDPSZ256mr:
9781 case X86::VSCATTERDPSZmr:
9782 case X86::VSCATTERPF0DPDm:
9783 case X86::VSCATTERPF0DPSm:
9784 case X86::VSCATTERPF0QPDm:
9785 case X86::VSCATTERPF0QPSm:
9786 case X86::VSCATTERPF1DPDm:
9787 case X86::VSCATTERPF1DPSm:
9788 case X86::VSCATTERPF1QPDm:
9789 case X86::VSCATTERPF1QPSm:
9790 case X86::VSCATTERQPDZ128mr:
9791 case X86::VSCATTERQPDZ256mr:
9792 case X86::VSCATTERQPDZmr:
9793 case X86::VSCATTERQPSZ128mr:
9794 case X86::VSCATTERQPSZ256mr:
9795 case X86::VSCATTERQPSZmr:
9796 case X86::VPSCATTERDDZ128mr:
9797 case X86::VPSCATTERDDZ256mr:
9798 case X86::VPSCATTERDDZmr:
9799 case X86::VPSCATTERDQZ128mr:
9800 case X86::VPSCATTERDQZ256mr:
9801 case X86::VPSCATTERDQZmr:
9802 case X86::VPSCATTERQDZ128mr:
9803 case X86::VPSCATTERQDZ256mr:
9804 case X86::VPSCATTERQDZmr:
9805 case X86::VPSCATTERQQZ128mr:
9806 case X86::VPSCATTERQQZ256mr:
9807 case X86::VPSCATTERQQZmr:
9808 return true;
9809 }
9810}
9811
9812bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
9813 const MachineRegisterInfo *MRI,
9814 const MachineInstr &DefMI,
9815 unsigned DefIdx,
9816 const MachineInstr &UseMI,
9817 unsigned UseIdx) const {
9818 return isHighLatencyDef(opc: DefMI.getOpcode());
9819}
9820
9821bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
9822 const MachineBasicBlock *MBB) const {
9823 assert(Inst.getNumExplicitOperands() == 3 && Inst.getNumExplicitDefs() == 1 &&
9824 Inst.getNumDefs() <= 2 && "Reassociation needs binary operators");
9825
9826 // Integer binary math/logic instructions have a third source operand:
9827 // the EFLAGS register. That operand must be both defined here and never
9828 // used; ie, it must be dead. If the EFLAGS operand is live, then we can
9829 // not change anything because rearranging the operands could affect other
9830 // instructions that depend on the exact status flags (zero, sign, etc.)
9831 // that are set by using these particular operands with this operation.
9832 const MachineOperand *FlagDef =
9833 Inst.findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
9834 assert((Inst.getNumDefs() == 1 || FlagDef) && "Implicit def isn't flags?");
9835 if (FlagDef && !FlagDef->isDead())
9836 return false;
9837
9838 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
9839}
9840
9841// TODO: There are many more machine instruction opcodes to match:
9842// 1. Other data types (integer, vectors)
9843// 2. Other math / logic operations (xor, or)
9844// 3. Other forms of the same operation (intrinsics and other variants)
9845bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
9846 bool Invert) const {
9847 if (Invert)
9848 return false;
9849 switch (Inst.getOpcode()) {
9850 CASE_ND(ADD8rr)
9851 CASE_ND(ADD16rr)
9852 CASE_ND(ADD32rr)
9853 CASE_ND(ADD64rr)
9854 CASE_ND(AND8rr)
9855 CASE_ND(AND16rr)
9856 CASE_ND(AND32rr)
9857 CASE_ND(AND64rr)
9858 CASE_ND(OR8rr)
9859 CASE_ND(OR16rr)
9860 CASE_ND(OR32rr)
9861 CASE_ND(OR64rr)
9862 CASE_ND(XOR8rr)
9863 CASE_ND(XOR16rr)
9864 CASE_ND(XOR32rr)
9865 CASE_ND(XOR64rr)
9866 CASE_ND(IMUL16rr)
9867 CASE_ND(IMUL32rr)
9868 CASE_ND(IMUL64rr)
9869 case X86::PANDrr:
9870 case X86::PORrr:
9871 case X86::PXORrr:
9872 case X86::ANDPDrr:
9873 case X86::ANDPSrr:
9874 case X86::ORPDrr:
9875 case X86::ORPSrr:
9876 case X86::XORPDrr:
9877 case X86::XORPSrr:
9878 case X86::PADDBrr:
9879 case X86::PADDWrr:
9880 case X86::PADDDrr:
9881 case X86::PADDQrr:
9882 case X86::PMULLWrr:
9883 case X86::PMULLDrr:
9884 case X86::PMAXSBrr:
9885 case X86::PMAXSDrr:
9886 case X86::PMAXSWrr:
9887 case X86::PMAXUBrr:
9888 case X86::PMAXUDrr:
9889 case X86::PMAXUWrr:
9890 case X86::PMINSBrr:
9891 case X86::PMINSDrr:
9892 case X86::PMINSWrr:
9893 case X86::PMINUBrr:
9894 case X86::PMINUDrr:
9895 case X86::PMINUWrr:
9896 case X86::VPANDrr:
9897 case X86::VPANDYrr:
9898 case X86::VPANDDZ128rr:
9899 case X86::VPANDDZ256rr:
9900 case X86::VPANDDZrr:
9901 case X86::VPANDQZ128rr:
9902 case X86::VPANDQZ256rr:
9903 case X86::VPANDQZrr:
9904 case X86::VPORrr:
9905 case X86::VPORYrr:
9906 case X86::VPORDZ128rr:
9907 case X86::VPORDZ256rr:
9908 case X86::VPORDZrr:
9909 case X86::VPORQZ128rr:
9910 case X86::VPORQZ256rr:
9911 case X86::VPORQZrr:
9912 case X86::VPXORrr:
9913 case X86::VPXORYrr:
9914 case X86::VPXORDZ128rr:
9915 case X86::VPXORDZ256rr:
9916 case X86::VPXORDZrr:
9917 case X86::VPXORQZ128rr:
9918 case X86::VPXORQZ256rr:
9919 case X86::VPXORQZrr:
9920 case X86::VANDPDrr:
9921 case X86::VANDPSrr:
9922 case X86::VANDPDYrr:
9923 case X86::VANDPSYrr:
9924 case X86::VANDPDZ128rr:
9925 case X86::VANDPSZ128rr:
9926 case X86::VANDPDZ256rr:
9927 case X86::VANDPSZ256rr:
9928 case X86::VANDPDZrr:
9929 case X86::VANDPSZrr:
9930 case X86::VORPDrr:
9931 case X86::VORPSrr:
9932 case X86::VORPDYrr:
9933 case X86::VORPSYrr:
9934 case X86::VORPDZ128rr:
9935 case X86::VORPSZ128rr:
9936 case X86::VORPDZ256rr:
9937 case X86::VORPSZ256rr:
9938 case X86::VORPDZrr:
9939 case X86::VORPSZrr:
9940 case X86::VXORPDrr:
9941 case X86::VXORPSrr:
9942 case X86::VXORPDYrr:
9943 case X86::VXORPSYrr:
9944 case X86::VXORPDZ128rr:
9945 case X86::VXORPSZ128rr:
9946 case X86::VXORPDZ256rr:
9947 case X86::VXORPSZ256rr:
9948 case X86::VXORPDZrr:
9949 case X86::VXORPSZrr:
9950 case X86::KADDBkk:
9951 case X86::KADDWkk:
9952 case X86::KADDDkk:
9953 case X86::KADDQkk:
9954 case X86::KANDBkk:
9955 case X86::KANDWkk:
9956 case X86::KANDDkk:
9957 case X86::KANDQkk:
9958 case X86::KORBkk:
9959 case X86::KORWkk:
9960 case X86::KORDkk:
9961 case X86::KORQkk:
9962 case X86::KXORBkk:
9963 case X86::KXORWkk:
9964 case X86::KXORDkk:
9965 case X86::KXORQkk:
9966 case X86::VPADDBrr:
9967 case X86::VPADDWrr:
9968 case X86::VPADDDrr:
9969 case X86::VPADDQrr:
9970 case X86::VPADDBYrr:
9971 case X86::VPADDWYrr:
9972 case X86::VPADDDYrr:
9973 case X86::VPADDQYrr:
9974 case X86::VPADDBZ128rr:
9975 case X86::VPADDWZ128rr:
9976 case X86::VPADDDZ128rr:
9977 case X86::VPADDQZ128rr:
9978 case X86::VPADDBZ256rr:
9979 case X86::VPADDWZ256rr:
9980 case X86::VPADDDZ256rr:
9981 case X86::VPADDQZ256rr:
9982 case X86::VPADDBZrr:
9983 case X86::VPADDWZrr:
9984 case X86::VPADDDZrr:
9985 case X86::VPADDQZrr:
9986 case X86::VPMULLWrr:
9987 case X86::VPMULLWYrr:
9988 case X86::VPMULLWZ128rr:
9989 case X86::VPMULLWZ256rr:
9990 case X86::VPMULLWZrr:
9991 case X86::VPMULLDrr:
9992 case X86::VPMULLDYrr:
9993 case X86::VPMULLDZ128rr:
9994 case X86::VPMULLDZ256rr:
9995 case X86::VPMULLDZrr:
9996 case X86::VPMULLQZ128rr:
9997 case X86::VPMULLQZ256rr:
9998 case X86::VPMULLQZrr:
9999 case X86::VPMAXSBrr:
10000 case X86::VPMAXSBYrr:
10001 case X86::VPMAXSBZ128rr:
10002 case X86::VPMAXSBZ256rr:
10003 case X86::VPMAXSBZrr:
10004 case X86::VPMAXSDrr:
10005 case X86::VPMAXSDYrr:
10006 case X86::VPMAXSDZ128rr:
10007 case X86::VPMAXSDZ256rr:
10008 case X86::VPMAXSDZrr:
10009 case X86::VPMAXSQZ128rr:
10010 case X86::VPMAXSQZ256rr:
10011 case X86::VPMAXSQZrr:
10012 case X86::VPMAXSWrr:
10013 case X86::VPMAXSWYrr:
10014 case X86::VPMAXSWZ128rr:
10015 case X86::VPMAXSWZ256rr:
10016 case X86::VPMAXSWZrr:
10017 case X86::VPMAXUBrr:
10018 case X86::VPMAXUBYrr:
10019 case X86::VPMAXUBZ128rr:
10020 case X86::VPMAXUBZ256rr:
10021 case X86::VPMAXUBZrr:
10022 case X86::VPMAXUDrr:
10023 case X86::VPMAXUDYrr:
10024 case X86::VPMAXUDZ128rr:
10025 case X86::VPMAXUDZ256rr:
10026 case X86::VPMAXUDZrr:
10027 case X86::VPMAXUQZ128rr:
10028 case X86::VPMAXUQZ256rr:
10029 case X86::VPMAXUQZrr:
10030 case X86::VPMAXUWrr:
10031 case X86::VPMAXUWYrr:
10032 case X86::VPMAXUWZ128rr:
10033 case X86::VPMAXUWZ256rr:
10034 case X86::VPMAXUWZrr:
10035 case X86::VPMINSBrr:
10036 case X86::VPMINSBYrr:
10037 case X86::VPMINSBZ128rr:
10038 case X86::VPMINSBZ256rr:
10039 case X86::VPMINSBZrr:
10040 case X86::VPMINSDrr:
10041 case X86::VPMINSDYrr:
10042 case X86::VPMINSDZ128rr:
10043 case X86::VPMINSDZ256rr:
10044 case X86::VPMINSDZrr:
10045 case X86::VPMINSQZ128rr:
10046 case X86::VPMINSQZ256rr:
10047 case X86::VPMINSQZrr:
10048 case X86::VPMINSWrr:
10049 case X86::VPMINSWYrr:
10050 case X86::VPMINSWZ128rr:
10051 case X86::VPMINSWZ256rr:
10052 case X86::VPMINSWZrr:
10053 case X86::VPMINUBrr:
10054 case X86::VPMINUBYrr:
10055 case X86::VPMINUBZ128rr:
10056 case X86::VPMINUBZ256rr:
10057 case X86::VPMINUBZrr:
10058 case X86::VPMINUDrr:
10059 case X86::VPMINUDYrr:
10060 case X86::VPMINUDZ128rr:
10061 case X86::VPMINUDZ256rr:
10062 case X86::VPMINUDZrr:
10063 case X86::VPMINUQZ128rr:
10064 case X86::VPMINUQZ256rr:
10065 case X86::VPMINUQZrr:
10066 case X86::VPMINUWrr:
10067 case X86::VPMINUWYrr:
10068 case X86::VPMINUWZ128rr:
10069 case X86::VPMINUWZ256rr:
10070 case X86::VPMINUWZrr:
10071 // Normal min/max instructions are not commutative because of NaN and signed
10072 // zero semantics, but these are. Thus, there's no need to check for global
10073 // relaxed math; the instructions themselves have the properties we need.
10074 case X86::MAXCPDrr:
10075 case X86::MAXCPSrr:
10076 case X86::MAXCSDrr:
10077 case X86::MAXCSSrr:
10078 case X86::MINCPDrr:
10079 case X86::MINCPSrr:
10080 case X86::MINCSDrr:
10081 case X86::MINCSSrr:
10082 case X86::VMAXCPDrr:
10083 case X86::VMAXCPSrr:
10084 case X86::VMAXCPDYrr:
10085 case X86::VMAXCPSYrr:
10086 case X86::VMAXCPDZ128rr:
10087 case X86::VMAXCPSZ128rr:
10088 case X86::VMAXCPDZ256rr:
10089 case X86::VMAXCPSZ256rr:
10090 case X86::VMAXCPDZrr:
10091 case X86::VMAXCPSZrr:
10092 case X86::VMAXCSDrr:
10093 case X86::VMAXCSSrr:
10094 case X86::VMAXCSDZrr:
10095 case X86::VMAXCSSZrr:
10096 case X86::VMINCPDrr:
10097 case X86::VMINCPSrr:
10098 case X86::VMINCPDYrr:
10099 case X86::VMINCPSYrr:
10100 case X86::VMINCPDZ128rr:
10101 case X86::VMINCPSZ128rr:
10102 case X86::VMINCPDZ256rr:
10103 case X86::VMINCPSZ256rr:
10104 case X86::VMINCPDZrr:
10105 case X86::VMINCPSZrr:
10106 case X86::VMINCSDrr:
10107 case X86::VMINCSSrr:
10108 case X86::VMINCSDZrr:
10109 case X86::VMINCSSZrr:
10110 case X86::VMAXCPHZ128rr:
10111 case X86::VMAXCPHZ256rr:
10112 case X86::VMAXCPHZrr:
10113 case X86::VMAXCSHZrr:
10114 case X86::VMINCPHZ128rr:
10115 case X86::VMINCPHZ256rr:
10116 case X86::VMINCPHZrr:
10117 case X86::VMINCSHZrr:
10118 return true;
10119 case X86::ADDPDrr:
10120 case X86::ADDPSrr:
10121 case X86::ADDSDrr:
10122 case X86::ADDSSrr:
10123 case X86::MULPDrr:
10124 case X86::MULPSrr:
10125 case X86::MULSDrr:
10126 case X86::MULSSrr:
10127 case X86::VADDPDrr:
10128 case X86::VADDPSrr:
10129 case X86::VADDPDYrr:
10130 case X86::VADDPSYrr:
10131 case X86::VADDPDZ128rr:
10132 case X86::VADDPSZ128rr:
10133 case X86::VADDPDZ256rr:
10134 case X86::VADDPSZ256rr:
10135 case X86::VADDPDZrr:
10136 case X86::VADDPSZrr:
10137 case X86::VADDSDrr:
10138 case X86::VADDSSrr:
10139 case X86::VADDSDZrr:
10140 case X86::VADDSSZrr:
10141 case X86::VMULPDrr:
10142 case X86::VMULPSrr:
10143 case X86::VMULPDYrr:
10144 case X86::VMULPSYrr:
10145 case X86::VMULPDZ128rr:
10146 case X86::VMULPSZ128rr:
10147 case X86::VMULPDZ256rr:
10148 case X86::VMULPSZ256rr:
10149 case X86::VMULPDZrr:
10150 case X86::VMULPSZrr:
10151 case X86::VMULSDrr:
10152 case X86::VMULSSrr:
10153 case X86::VMULSDZrr:
10154 case X86::VMULSSZrr:
10155 case X86::VADDPHZ128rr:
10156 case X86::VADDPHZ256rr:
10157 case X86::VADDPHZrr:
10158 case X86::VADDSHZrr:
10159 case X86::VMULPHZ128rr:
10160 case X86::VMULPHZ256rr:
10161 case X86::VMULPHZrr:
10162 case X86::VMULSHZrr:
10163 return Inst.getFlag(Flag: MachineInstr::MIFlag::FmReassoc) &&
10164 Inst.getFlag(Flag: MachineInstr::MIFlag::FmNsz);
10165 default:
10166 return false;
10167 }
10168}
10169
10170/// If \p DescribedReg overlaps with the MOVrr instruction's destination
10171/// register then, if possible, describe the value in terms of the source
10172/// register.
10173static std::optional<ParamLoadedValue>
10174describeMOVrrLoadedValue(const MachineInstr &MI, Register DescribedReg,
10175 const TargetRegisterInfo *TRI) {
10176 Register DestReg = MI.getOperand(i: 0).getReg();
10177 Register SrcReg = MI.getOperand(i: 1).getReg();
10178
10179 auto Expr = DIExpression::get(Context&: MI.getMF()->getFunction().getContext(), Elements: {});
10180
10181 // If the described register is the destination, just return the source.
10182 if (DestReg == DescribedReg)
10183 return ParamLoadedValue(MachineOperand::CreateReg(Reg: SrcReg, isDef: false), Expr);
10184
10185 // If the described register is a sub-register of the destination register,
10186 // then pick out the source register's corresponding sub-register.
10187 if (unsigned SubRegIdx = TRI->getSubRegIndex(RegNo: DestReg, SubRegNo: DescribedReg)) {
10188 Register SrcSubReg = TRI->getSubReg(Reg: SrcReg, Idx: SubRegIdx);
10189 return ParamLoadedValue(MachineOperand::CreateReg(Reg: SrcSubReg, isDef: false), Expr);
10190 }
10191
10192 // The remaining case to consider is when the described register is a
10193 // super-register of the destination register. MOV8rr and MOV16rr does not
10194 // write to any of the other bytes in the register, meaning that we'd have to
10195 // describe the value using a combination of the source register and the
10196 // non-overlapping bits in the described register, which is not currently
10197 // possible.
10198 if (MI.getOpcode() == X86::MOV8rr || MI.getOpcode() == X86::MOV16rr ||
10199 !TRI->isSuperRegister(RegA: DestReg, RegB: DescribedReg))
10200 return std::nullopt;
10201
10202 assert(MI.getOpcode() == X86::MOV32rr && "Unexpected super-register case");
10203 return ParamLoadedValue(MachineOperand::CreateReg(Reg: SrcReg, isDef: false), Expr);
10204}
10205
10206std::optional<ParamLoadedValue>
10207X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
10208 const MachineOperand *Op = nullptr;
10209 DIExpression *Expr = nullptr;
10210
10211 const TargetRegisterInfo *TRI = &getRegisterInfo();
10212
10213 switch (MI.getOpcode()) {
10214 case X86::LEA32r:
10215 case X86::LEA64r:
10216 case X86::LEA64_32r: {
10217 // We may need to describe a 64-bit parameter with a 32-bit LEA.
10218 if (!TRI->isSuperRegisterEq(RegA: MI.getOperand(i: 0).getReg(), RegB: Reg))
10219 return std::nullopt;
10220
10221 // Operand 4 could be global address. For now we do not support
10222 // such situation.
10223 if (!MI.getOperand(i: 4).isImm() || !MI.getOperand(i: 2).isImm())
10224 return std::nullopt;
10225
10226 const MachineOperand &Op1 = MI.getOperand(i: 1);
10227 const MachineOperand &Op2 = MI.getOperand(i: 3);
10228 assert(Op2.isReg() &&
10229 (Op2.getReg() == X86::NoRegister || Op2.getReg().isPhysical()));
10230
10231 // Omit situations like:
10232 // %rsi = lea %rsi, 4, ...
10233 if ((Op1.isReg() && Op1.getReg() == MI.getOperand(i: 0).getReg()) ||
10234 Op2.getReg() == MI.getOperand(i: 0).getReg())
10235 return std::nullopt;
10236 else if ((Op1.isReg() && Op1.getReg() != X86::NoRegister &&
10237 TRI->regsOverlap(RegA: Op1.getReg(), RegB: MI.getOperand(i: 0).getReg())) ||
10238 (Op2.getReg() != X86::NoRegister &&
10239 TRI->regsOverlap(RegA: Op2.getReg(), RegB: MI.getOperand(i: 0).getReg())))
10240 return std::nullopt;
10241
10242 int64_t Coef = MI.getOperand(i: 2).getImm();
10243 int64_t Offset = MI.getOperand(i: 4).getImm();
10244 SmallVector<uint64_t, 8> Ops;
10245
10246 if ((Op1.isReg() && Op1.getReg() != X86::NoRegister)) {
10247 Op = &Op1;
10248 } else if (Op1.isFI())
10249 Op = &Op1;
10250
10251 if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) {
10252 Ops.push_back(Elt: dwarf::DW_OP_constu);
10253 Ops.push_back(Elt: Coef + 1);
10254 Ops.push_back(Elt: dwarf::DW_OP_mul);
10255 } else {
10256 if (Op && Op2.getReg() != X86::NoRegister) {
10257 int dwarfReg = TRI->getDwarfRegNum(Reg: Op2.getReg(), isEH: false);
10258 if (dwarfReg < 0)
10259 return std::nullopt;
10260 else if (dwarfReg < 32) {
10261 Ops.push_back(Elt: dwarf::DW_OP_breg0 + dwarfReg);
10262 Ops.push_back(Elt: 0);
10263 } else {
10264 Ops.push_back(Elt: dwarf::DW_OP_bregx);
10265 Ops.push_back(Elt: dwarfReg);
10266 Ops.push_back(Elt: 0);
10267 }
10268 } else if (!Op) {
10269 assert(Op2.getReg() != X86::NoRegister);
10270 Op = &Op2;
10271 }
10272
10273 if (Coef > 1) {
10274 assert(Op2.getReg() != X86::NoRegister);
10275 Ops.push_back(Elt: dwarf::DW_OP_constu);
10276 Ops.push_back(Elt: Coef);
10277 Ops.push_back(Elt: dwarf::DW_OP_mul);
10278 }
10279
10280 if (((Op1.isReg() && Op1.getReg() != X86::NoRegister) || Op1.isFI()) &&
10281 Op2.getReg() != X86::NoRegister) {
10282 Ops.push_back(Elt: dwarf::DW_OP_plus);
10283 }
10284 }
10285
10286 DIExpression::appendOffset(Ops, Offset);
10287 Expr = DIExpression::get(Context&: MI.getMF()->getFunction().getContext(), Elements: Ops);
10288
10289 return ParamLoadedValue(*Op, Expr);
10290 }
10291 case X86::MOV8ri:
10292 case X86::MOV16ri:
10293 // TODO: Handle MOV8ri and MOV16ri.
10294 return std::nullopt;
10295 case X86::MOV32ri:
10296 case X86::MOV64ri:
10297 case X86::MOV64ri32:
10298 // MOV32ri may be used for producing zero-extended 32-bit immediates in
10299 // 64-bit parameters, so we need to consider super-registers.
10300 if (!TRI->isSuperRegisterEq(RegA: MI.getOperand(i: 0).getReg(), RegB: Reg))
10301 return std::nullopt;
10302 return ParamLoadedValue(MI.getOperand(i: 1), Expr);
10303 case X86::MOV8rr:
10304 case X86::MOV16rr:
10305 case X86::MOV32rr:
10306 case X86::MOV64rr:
10307 return describeMOVrrLoadedValue(MI, DescribedReg: Reg, TRI);
10308 case X86::XOR32rr: {
10309 // 64-bit parameters are zero-materialized using XOR32rr, so also consider
10310 // super-registers.
10311 if (!TRI->isSuperRegisterEq(RegA: MI.getOperand(i: 0).getReg(), RegB: Reg))
10312 return std::nullopt;
10313 if (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 2).getReg())
10314 return ParamLoadedValue(MachineOperand::CreateImm(Val: 0), Expr);
10315 return std::nullopt;
10316 }
10317 case X86::MOVSX64rr32: {
10318 // We may need to describe the lower 32 bits of the MOVSX; for example, in
10319 // cases like this:
10320 //
10321 // $ebx = [...]
10322 // $rdi = MOVSX64rr32 $ebx
10323 // $esi = MOV32rr $edi
10324 if (!TRI->isSubRegisterEq(RegA: MI.getOperand(i: 0).getReg(), RegB: Reg))
10325 return std::nullopt;
10326
10327 Expr = DIExpression::get(Context&: MI.getMF()->getFunction().getContext(), Elements: {});
10328
10329 // If the described register is the destination register we need to
10330 // sign-extend the source register from 32 bits. The other case we handle
10331 // is when the described register is the 32-bit sub-register of the
10332 // destination register, in case we just need to return the source
10333 // register.
10334 if (Reg == MI.getOperand(i: 0).getReg())
10335 Expr = DIExpression::appendExt(Expr, FromSize: 32, ToSize: 64, Signed: true);
10336 else
10337 assert(X86MCRegisterClasses[X86::GR32RegClassID].contains(Reg) &&
10338 "Unhandled sub-register case for MOVSX64rr32");
10339
10340 return ParamLoadedValue(MI.getOperand(i: 1), Expr);
10341 }
10342 default:
10343 assert(!MI.isMoveImmediate() && "Unexpected MoveImm instruction");
10344 return TargetInstrInfo::describeLoadedValue(MI, Reg);
10345 }
10346}
10347
10348/// This is an architecture-specific helper function of reassociateOps.
10349/// Set special operand attributes for new instructions after reassociation.
10350void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
10351 MachineInstr &OldMI2,
10352 MachineInstr &NewMI1,
10353 MachineInstr &NewMI2) const {
10354 // Integer instructions may define an implicit EFLAGS dest register operand.
10355 MachineOperand *OldFlagDef1 =
10356 OldMI1.findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
10357 MachineOperand *OldFlagDef2 =
10358 OldMI2.findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
10359
10360 assert(!OldFlagDef1 == !OldFlagDef2 &&
10361 "Unexpected instruction type for reassociation");
10362
10363 if (!OldFlagDef1 || !OldFlagDef2)
10364 return;
10365
10366 assert(OldFlagDef1->isDead() && OldFlagDef2->isDead() &&
10367 "Must have dead EFLAGS operand in reassociable instruction");
10368
10369 MachineOperand *NewFlagDef1 =
10370 NewMI1.findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
10371 MachineOperand *NewFlagDef2 =
10372 NewMI2.findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
10373
10374 assert(NewFlagDef1 && NewFlagDef2 &&
10375 "Unexpected operand in reassociable instruction");
10376
10377 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
10378 // of this pass or other passes. The EFLAGS operands must be dead in these new
10379 // instructions because the EFLAGS operands in the original instructions must
10380 // be dead in order for reassociation to occur.
10381 NewFlagDef1->setIsDead();
10382 NewFlagDef2->setIsDead();
10383}
10384
10385std::pair<unsigned, unsigned>
10386X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
10387 return std::make_pair(x&: TF, y: 0u);
10388}
10389
10390ArrayRef<std::pair<unsigned, const char *>>
10391X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
10392 using namespace X86II;
10393 static const std::pair<unsigned, const char *> TargetFlags[] = {
10394 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
10395 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
10396 {MO_GOT, "x86-got"},
10397 {MO_GOTOFF, "x86-gotoff"},
10398 {MO_GOTPCREL, "x86-gotpcrel"},
10399 {MO_GOTPCREL_NORELAX, "x86-gotpcrel-norelax"},
10400 {MO_PLT, "x86-plt"},
10401 {MO_TLSGD, "x86-tlsgd"},
10402 {MO_TLSLD, "x86-tlsld"},
10403 {MO_TLSLDM, "x86-tlsldm"},
10404 {MO_GOTTPOFF, "x86-gottpoff"},
10405 {MO_INDNTPOFF, "x86-indntpoff"},
10406 {MO_TPOFF, "x86-tpoff"},
10407 {MO_DTPOFF, "x86-dtpoff"},
10408 {MO_NTPOFF, "x86-ntpoff"},
10409 {MO_GOTNTPOFF, "x86-gotntpoff"},
10410 {MO_DLLIMPORT, "x86-dllimport"},
10411 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
10412 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
10413 {MO_TLVP, "x86-tlvp"},
10414 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
10415 {MO_SECREL, "x86-secrel"},
10416 {MO_COFFSTUB, "x86-coffstub"}};
10417 return ArrayRef(TargetFlags);
10418}
10419
10420/// Constants defining how certain sequences should be outlined.
10421///
10422/// \p MachineOutlinerDefault implies that the function is called with a call
10423/// instruction, and a return must be emitted for the outlined function frame.
10424///
10425/// That is,
10426///
10427/// I1 OUTLINED_FUNCTION:
10428/// I2 --> call OUTLINED_FUNCTION I1
10429/// I3 I2
10430/// I3
10431/// ret
10432///
10433/// * Call construction overhead: 1 (call instruction)
10434/// * Frame construction overhead: 1 (return instruction)
10435///
10436/// \p MachineOutlinerTailCall implies that the function is being tail called.
10437/// A jump is emitted instead of a call, and the return is already present in
10438/// the outlined sequence. That is,
10439///
10440/// I1 OUTLINED_FUNCTION:
10441/// I2 --> jmp OUTLINED_FUNCTION I1
10442/// ret I2
10443/// ret
10444///
10445/// * Call construction overhead: 1 (jump instruction)
10446/// * Frame construction overhead: 0 (don't need to return)
10447///
10448enum MachineOutlinerClass { MachineOutlinerDefault, MachineOutlinerTailCall };
10449
10450std::optional<std::unique_ptr<outliner::OutlinedFunction>>
10451X86InstrInfo::getOutliningCandidateInfo(
10452 const MachineModuleInfo &MMI,
10453 std::vector<outliner::Candidate> &RepeatedSequenceLocs,
10454 unsigned MinRepeats) const {
10455 unsigned SequenceSize = 0;
10456 for (auto &MI : RepeatedSequenceLocs[0]) {
10457 // FIXME: x86 doesn't implement getInstSizeInBytes, so
10458 // we can't tell the cost. Just assume each instruction
10459 // is one byte.
10460 if (MI.isDebugInstr() || MI.isKill())
10461 continue;
10462 SequenceSize += 1;
10463 }
10464
10465 // We check to see if CFI Instructions are present, and if they are
10466 // we find the number of CFI Instructions in the candidates.
10467 unsigned CFICount = 0;
10468 for (auto &I : RepeatedSequenceLocs[0]) {
10469 if (I.isCFIInstruction())
10470 CFICount++;
10471 }
10472
10473 // We compare the number of found CFI Instructions to the number of CFI
10474 // instructions in the parent function for each candidate. We must check this
10475 // since if we outline one of the CFI instructions in a function, we have to
10476 // outline them all for correctness. If we do not, the address offsets will be
10477 // incorrect between the two sections of the program.
10478 for (outliner::Candidate &C : RepeatedSequenceLocs) {
10479 std::vector<MCCFIInstruction> CFIInstructions =
10480 C.getMF()->getFrameInstructions();
10481
10482 if (CFICount > 0 && CFICount != CFIInstructions.size())
10483 return std::nullopt;
10484 }
10485
10486 // FIXME: Use real size in bytes for call and ret instructions.
10487 if (RepeatedSequenceLocs[0].back().isTerminator()) {
10488 for (outliner::Candidate &C : RepeatedSequenceLocs)
10489 C.setCallInfo(CID: MachineOutlinerTailCall, CO: 1);
10490
10491 return std::make_unique<outliner::OutlinedFunction>(
10492 args&: RepeatedSequenceLocs, args&: SequenceSize,
10493 args: 0, // Number of bytes to emit frame.
10494 args: MachineOutlinerTailCall // Type of frame.
10495 );
10496 }
10497
10498 if (CFICount > 0)
10499 return std::nullopt;
10500
10501 for (outliner::Candidate &C : RepeatedSequenceLocs)
10502 C.setCallInfo(CID: MachineOutlinerDefault, CO: 1);
10503
10504 return std::make_unique<outliner::OutlinedFunction>(
10505 args&: RepeatedSequenceLocs, args&: SequenceSize, args: 1, args: MachineOutlinerDefault);
10506}
10507
10508bool X86InstrInfo::isFunctionSafeToOutlineFrom(
10509 MachineFunction &MF, bool OutlineFromLinkOnceODRs) const {
10510 const Function &F = MF.getFunction();
10511
10512 // Does the function use a red zone? If it does, then we can't risk messing
10513 // with the stack.
10514 if (Subtarget.getFrameLowering()->has128ByteRedZone(MF)) {
10515 // It could have a red zone. If it does, then we don't want to touch it.
10516 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
10517 if (!X86FI || X86FI->getUsesRedZone())
10518 return false;
10519 }
10520
10521 // If we *don't* want to outline from things that could potentially be deduped
10522 // then return false.
10523 if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
10524 return false;
10525
10526 // This function is viable for outlining, so return true.
10527 return true;
10528}
10529
10530outliner::InstrType
10531X86InstrInfo::getOutliningTypeImpl(const MachineModuleInfo &MMI,
10532 MachineBasicBlock::iterator &MIT,
10533 unsigned Flags) const {
10534 MachineInstr &MI = *MIT;
10535
10536 // Is this a terminator for a basic block?
10537 if (MI.isTerminator())
10538 // TargetInstrInfo::getOutliningType has already filtered out anything
10539 // that would break this, so we can allow it here.
10540 return outliner::InstrType::Legal;
10541
10542 // Don't outline anything that modifies or reads from the stack pointer.
10543 //
10544 // FIXME: There are instructions which are being manually built without
10545 // explicit uses/defs so we also have to check the MCInstrDesc. We should be
10546 // able to remove the extra checks once those are fixed up. For example,
10547 // sometimes we might get something like %rax = POP64r 1. This won't be
10548 // caught by modifiesRegister or readsRegister even though the instruction
10549 // really ought to be formed so that modifiesRegister/readsRegister would
10550 // catch it.
10551 if (MI.modifiesRegister(Reg: X86::RSP, TRI: &RI) || MI.readsRegister(Reg: X86::RSP, TRI: &RI) ||
10552 MI.getDesc().hasImplicitUseOfPhysReg(Reg: X86::RSP) ||
10553 MI.getDesc().hasImplicitDefOfPhysReg(Reg: X86::RSP))
10554 return outliner::InstrType::Illegal;
10555
10556 // Outlined calls change the instruction pointer, so don't read from it.
10557 if (MI.readsRegister(Reg: X86::RIP, TRI: &RI) ||
10558 MI.getDesc().hasImplicitUseOfPhysReg(Reg: X86::RIP) ||
10559 MI.getDesc().hasImplicitDefOfPhysReg(Reg: X86::RIP))
10560 return outliner::InstrType::Illegal;
10561
10562 // Don't outline CFI instructions.
10563 if (MI.isCFIInstruction())
10564 return outliner::InstrType::Illegal;
10565
10566 return outliner::InstrType::Legal;
10567}
10568
10569void X86InstrInfo::buildOutlinedFrame(
10570 MachineBasicBlock &MBB, MachineFunction &MF,
10571 const outliner::OutlinedFunction &OF) const {
10572 // If we're a tail call, we already have a return, so don't do anything.
10573 if (OF.FrameConstructionID == MachineOutlinerTailCall)
10574 return;
10575
10576 // We're a normal call, so our sequence doesn't have a return instruction.
10577 // Add it in.
10578 MachineInstr *retq = BuildMI(MF, MIMD: DebugLoc(), MCID: get(Opcode: X86::RET64));
10579 MBB.insert(I: MBB.end(), MI: retq);
10580}
10581
10582MachineBasicBlock::iterator X86InstrInfo::insertOutlinedCall(
10583 Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It,
10584 MachineFunction &MF, outliner::Candidate &C) const {
10585 // Is it a tail call?
10586 if (C.CallConstructionID == MachineOutlinerTailCall) {
10587 // Yes, just insert a JMP.
10588 It = MBB.insert(I: It, MI: BuildMI(MF, MIMD: DebugLoc(), MCID: get(Opcode: X86::TAILJMPd64))
10589 .addGlobalAddress(GV: M.getNamedValue(Name: MF.getName())));
10590 } else {
10591 // No, insert a call.
10592 It = MBB.insert(I: It, MI: BuildMI(MF, MIMD: DebugLoc(), MCID: get(Opcode: X86::CALL64pcrel32))
10593 .addGlobalAddress(GV: M.getNamedValue(Name: MF.getName())));
10594 }
10595
10596 return It;
10597}
10598
10599void X86InstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB,
10600 MachineBasicBlock::iterator Iter,
10601 DebugLoc &DL,
10602 bool AllowSideEffects) const {
10603 const MachineFunction &MF = *MBB.getParent();
10604 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
10605 const TargetRegisterInfo &TRI = getRegisterInfo();
10606
10607 if (ST.hasMMX() && X86::VR64RegClass.contains(Reg))
10608 // FIXME: Should we ignore MMX registers?
10609 return;
10610
10611 if (TRI.isGeneralPurposeRegister(MF, PhysReg: Reg)) {
10612 // Convert register to the 32-bit version. Both 'movl' and 'xorl' clear the
10613 // upper bits of a 64-bit register automagically.
10614 Reg = getX86SubSuperRegister(Reg, Size: 32);
10615
10616 if (!AllowSideEffects)
10617 // XOR affects flags, so use a MOV instead.
10618 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: X86::MOV32ri), DestReg: Reg).addImm(Val: 0);
10619 else
10620 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: X86::XOR32rr), DestReg: Reg)
10621 .addReg(RegNo: Reg, Flags: RegState::Undef)
10622 .addReg(RegNo: Reg, Flags: RegState::Undef);
10623 } else if (X86::VR128RegClass.contains(Reg)) {
10624 // XMM#
10625 if (!ST.hasSSE1())
10626 return;
10627
10628 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: X86::V_SET0), DestReg: Reg);
10629 } else if (X86::VR256RegClass.contains(Reg)) {
10630 // YMM#
10631 if (!ST.hasAVX())
10632 return;
10633
10634 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: X86::AVX_SET0), DestReg: Reg);
10635 } else if (X86::VR512RegClass.contains(Reg)) {
10636 // ZMM#
10637 if (!ST.hasAVX512())
10638 return;
10639
10640 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: X86::AVX512_512_SET0), DestReg: Reg);
10641 } else if (X86::VK1RegClass.contains(Reg) || X86::VK2RegClass.contains(Reg) ||
10642 X86::VK4RegClass.contains(Reg) || X86::VK8RegClass.contains(Reg) ||
10643 X86::VK16RegClass.contains(Reg)) {
10644 if (!ST.hasVLX())
10645 return;
10646
10647 unsigned Op = ST.hasBWI() ? X86::KSET0Q : X86::KSET0W;
10648 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: Op), DestReg: Reg);
10649 }
10650}
10651
10652bool X86InstrInfo::getMachineCombinerPatterns(
10653 MachineInstr &Root, SmallVectorImpl<unsigned> &Patterns,
10654 bool DoRegPressureReduce) const {
10655 unsigned Opc = Root.getOpcode();
10656 switch (Opc) {
10657 case X86::VPDPWSSDrr:
10658 case X86::VPDPWSSDrm:
10659 case X86::VPDPWSSDYrr:
10660 case X86::VPDPWSSDYrm: {
10661 if (!Subtarget.hasFastDPWSSD()) {
10662 Patterns.push_back(Elt: X86MachineCombinerPattern::DPWSSD);
10663 return true;
10664 }
10665 break;
10666 }
10667 case X86::VPDPWSSDZ128rr:
10668 case X86::VPDPWSSDZ128rm:
10669 case X86::VPDPWSSDZ256rr:
10670 case X86::VPDPWSSDZ256rm:
10671 case X86::VPDPWSSDZrr:
10672 case X86::VPDPWSSDZrm: {
10673 if (Subtarget.hasBWI() && !Subtarget.hasFastDPWSSD()) {
10674 Patterns.push_back(Elt: X86MachineCombinerPattern::DPWSSD);
10675 return true;
10676 }
10677 break;
10678 }
10679 }
10680 return TargetInstrInfo::getMachineCombinerPatterns(Root,
10681 Patterns, DoRegPressureReduce);
10682}
10683
10684static void
10685genAlternativeDpCodeSequence(MachineInstr &Root, const TargetInstrInfo &TII,
10686 SmallVectorImpl<MachineInstr *> &InsInstrs,
10687 SmallVectorImpl<MachineInstr *> &DelInstrs,
10688 DenseMap<Register, unsigned> &InstrIdxForVirtReg) {
10689 MachineFunction *MF = Root.getMF();
10690 MachineRegisterInfo &RegInfo = MF->getRegInfo();
10691
10692 unsigned Opc = Root.getOpcode();
10693 unsigned AddOpc = 0;
10694 unsigned MaddOpc = 0;
10695 switch (Opc) {
10696 default:
10697 assert(false && "It should not reach here");
10698 break;
10699 // vpdpwssd xmm2,xmm3,xmm1
10700 // -->
10701 // vpmaddwd xmm3,xmm3,xmm1
10702 // vpaddd xmm2,xmm2,xmm3
10703 case X86::VPDPWSSDrr:
10704 MaddOpc = X86::VPMADDWDrr;
10705 AddOpc = X86::VPADDDrr;
10706 break;
10707 case X86::VPDPWSSDrm:
10708 MaddOpc = X86::VPMADDWDrm;
10709 AddOpc = X86::VPADDDrr;
10710 break;
10711 case X86::VPDPWSSDZ128rr:
10712 MaddOpc = X86::VPMADDWDZ128rr;
10713 AddOpc = X86::VPADDDZ128rr;
10714 break;
10715 case X86::VPDPWSSDZ128rm:
10716 MaddOpc = X86::VPMADDWDZ128rm;
10717 AddOpc = X86::VPADDDZ128rr;
10718 break;
10719 // vpdpwssd ymm2,ymm3,ymm1
10720 // -->
10721 // vpmaddwd ymm3,ymm3,ymm1
10722 // vpaddd ymm2,ymm2,ymm3
10723 case X86::VPDPWSSDYrr:
10724 MaddOpc = X86::VPMADDWDYrr;
10725 AddOpc = X86::VPADDDYrr;
10726 break;
10727 case X86::VPDPWSSDYrm:
10728 MaddOpc = X86::VPMADDWDYrm;
10729 AddOpc = X86::VPADDDYrr;
10730 break;
10731 case X86::VPDPWSSDZ256rr:
10732 MaddOpc = X86::VPMADDWDZ256rr;
10733 AddOpc = X86::VPADDDZ256rr;
10734 break;
10735 case X86::VPDPWSSDZ256rm:
10736 MaddOpc = X86::VPMADDWDZ256rm;
10737 AddOpc = X86::VPADDDZ256rr;
10738 break;
10739 // vpdpwssd zmm2,zmm3,zmm1
10740 // -->
10741 // vpmaddwd zmm3,zmm3,zmm1
10742 // vpaddd zmm2,zmm2,zmm3
10743 case X86::VPDPWSSDZrr:
10744 MaddOpc = X86::VPMADDWDZrr;
10745 AddOpc = X86::VPADDDZrr;
10746 break;
10747 case X86::VPDPWSSDZrm:
10748 MaddOpc = X86::VPMADDWDZrm;
10749 AddOpc = X86::VPADDDZrr;
10750 break;
10751 }
10752 // Create vpmaddwd.
10753 const TargetRegisterClass *RC =
10754 RegInfo.getRegClass(Reg: Root.getOperand(i: 0).getReg());
10755 Register NewReg = RegInfo.createVirtualRegister(RegClass: RC);
10756 MachineInstr *Madd = Root.getMF()->CloneMachineInstr(Orig: &Root);
10757 Madd->setDesc(TII.get(Opcode: MaddOpc));
10758 Madd->untieRegOperand(OpIdx: 1);
10759 Madd->removeOperand(OpNo: 1);
10760 Madd->getOperand(i: 0).setReg(NewReg);
10761 InstrIdxForVirtReg.insert(KV: std::make_pair(x&: NewReg, y: 0));
10762 // Create vpaddd.
10763 Register DstReg = Root.getOperand(i: 0).getReg();
10764 bool IsKill = Root.getOperand(i: 1).isKill();
10765 MachineInstr *Add =
10766 BuildMI(MF&: *MF, MIMD: MIMetadata(Root), MCID: TII.get(Opcode: AddOpc), DestReg: DstReg)
10767 .addReg(RegNo: Root.getOperand(i: 1).getReg(), Flags: getKillRegState(B: IsKill))
10768 .addReg(RegNo: Madd->getOperand(i: 0).getReg(), Flags: getKillRegState(B: true));
10769 InsInstrs.push_back(Elt: Madd);
10770 InsInstrs.push_back(Elt: Add);
10771 DelInstrs.push_back(Elt: &Root);
10772}
10773
10774void X86InstrInfo::genAlternativeCodeSequence(
10775 MachineInstr &Root, unsigned Pattern,
10776 SmallVectorImpl<MachineInstr *> &InsInstrs,
10777 SmallVectorImpl<MachineInstr *> &DelInstrs,
10778 DenseMap<Register, unsigned> &InstrIdxForVirtReg) const {
10779 switch (Pattern) {
10780 default:
10781 // Reassociate instructions.
10782 TargetInstrInfo::genAlternativeCodeSequence(Root, Pattern, InsInstrs,
10783 DelInstrs, InstIdxForVirtReg&: InstrIdxForVirtReg);
10784 return;
10785 case X86MachineCombinerPattern::DPWSSD:
10786 genAlternativeDpCodeSequence(Root, TII: *this, InsInstrs, DelInstrs,
10787 InstrIdxForVirtReg);
10788 return;
10789 }
10790}
10791
10792// See also: X86DAGToDAGISel::SelectInlineAsmMemoryOperand().
10793void X86InstrInfo::getFrameIndexOperands(SmallVectorImpl<MachineOperand> &Ops,
10794 int FI) const {
10795 X86AddressMode M;
10796 M.BaseType = X86AddressMode::FrameIndexBase;
10797 M.Base.FrameIndex = FI;
10798 M.getFullAddress(MO&: Ops);
10799}
10800
10801#define GET_INSTRINFO_HELPERS
10802#include "X86GenInstrInfo.inc"
10803