1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the X86 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86InstrInfo.h"
14#include "X86.h"
15#include "X86InstrBuilder.h"
16#include "X86InstrFoldTables.h"
17#include "X86MachineFunctionInfo.h"
18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/Sequence.h"
22#include "llvm/CodeGen/LiveIntervals.h"
23#include "llvm/CodeGen/LivePhysRegs.h"
24#include "llvm/CodeGen/MachineConstantPool.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineInstr.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineModuleInfo.h"
29#include "llvm/CodeGen/MachineOperand.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/StackMaps.h"
32#include "llvm/IR/DebugInfoMetadata.h"
33#include "llvm/IR/DerivedTypes.h"
34#include "llvm/IR/Function.h"
35#include "llvm/IR/InstrTypes.h"
36#include "llvm/IR/Module.h"
37#include "llvm/MC/MCAsmInfo.h"
38#include "llvm/MC/MCExpr.h"
39#include "llvm/MC/MCInst.h"
40#include "llvm/Support/Debug.h"
41#include "llvm/Support/ErrorHandling.h"
42#include "llvm/Support/MathExtras.h"
43#include "llvm/Support/raw_ostream.h"
44#include "llvm/Target/TargetOptions.h"
45#include <optional>
46
47using namespace llvm;
48
49#define DEBUG_TYPE "x86-instr-info"
50
51#define GET_INSTRINFO_CTOR_DTOR
52#include "X86GenInstrInfo.inc"
53
54// Pin the vtable to this file.
55void X86InstrInfo::anchor() {}
56
57X86InstrInfo::X86InstrInfo(const X86Subtarget &STI)
58 : X86GenInstrInfo(STI, RI,
59 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
60 : X86::ADJCALLSTACKDOWN32),
61 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
62 : X86::ADJCALLSTACKUP32),
63 X86::CATCHRET, (STI.is64Bit() ? X86::RET64 : X86::RET32)),
64 Subtarget(STI), RI(STI.getTargetTriple()) {}
65
66const TargetRegisterClass *X86InstrInfo::getRegClass(const MCInstrDesc &MCID,
67 unsigned OpNum) const {
68 auto *RC = TargetInstrInfo::getRegClass(MCID, OpNum);
69 // If the target does not have egpr, then r16-r31 will be resereved for all
70 // instructions.
71 if (!RC || !Subtarget.hasEGPR())
72 return RC;
73
74 if (X86II::canUseApxExtendedReg(Desc: MCID))
75 return RC;
76
77 const X86RegisterInfo *RI = Subtarget.getRegisterInfo();
78 return RI->constrainRegClassToNonRex2(RC);
79}
80
81const TargetRegisterClass *X86InstrInfo::getInlineAsmMemoryOperandRegClass(
82 InlineAsm::ConstraintCode C) const {
83 if (Subtarget.isTarget64BitLP64())
84 return &X86::GR64RegClass;
85 // If the target is 64bit but we have been told to use 32bit addresses, we can
86 // still use 64-bit register as long as we know the high bits are zeros.
87 // Reflect that in the returned register class.
88 return Subtarget.is64Bit() ? &X86::LOW32_ADDR_ACCESSRegClass
89 : &X86::GR32RegClass;
90}
91
92bool X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
93 Register &SrcReg, Register &DstReg,
94 unsigned &SubIdx) const {
95 switch (MI.getOpcode()) {
96 default:
97 break;
98 case X86::MOVSX16rr8:
99 case X86::MOVZX16rr8:
100 case X86::MOVSX32rr8:
101 case X86::MOVZX32rr8:
102 case X86::MOVSX64rr8:
103 if (!Subtarget.is64Bit())
104 // It's not always legal to reference the low 8-bit of the larger
105 // register in 32-bit mode.
106 return false;
107 [[fallthrough]];
108 case X86::MOVSX32rr16:
109 case X86::MOVZX32rr16:
110 case X86::MOVSX64rr16:
111 case X86::MOVSX64rr32: {
112 if (MI.getOperand(i: 0).getSubReg() || MI.getOperand(i: 1).getSubReg())
113 // Be conservative.
114 return false;
115 SrcReg = MI.getOperand(i: 1).getReg();
116 DstReg = MI.getOperand(i: 0).getReg();
117 switch (MI.getOpcode()) {
118 default:
119 llvm_unreachable("Unreachable!");
120 case X86::MOVSX16rr8:
121 case X86::MOVZX16rr8:
122 case X86::MOVSX32rr8:
123 case X86::MOVZX32rr8:
124 case X86::MOVSX64rr8:
125 SubIdx = X86::sub_8bit;
126 break;
127 case X86::MOVSX32rr16:
128 case X86::MOVZX32rr16:
129 case X86::MOVSX64rr16:
130 SubIdx = X86::sub_16bit;
131 break;
132 case X86::MOVSX64rr32:
133 SubIdx = X86::sub_32bit;
134 break;
135 }
136 return true;
137 }
138 }
139 return false;
140}
141
142bool X86InstrInfo::isDataInvariant(MachineInstr &MI) {
143 if (MI.mayLoad() || MI.mayStore())
144 return false;
145
146 // Some target-independent operations that trivially lower to data-invariant
147 // instructions.
148 if (MI.isCopyLike() || MI.isInsertSubreg())
149 return true;
150
151 unsigned Opcode = MI.getOpcode();
152 using namespace X86;
153 // On x86 it is believed that imul is constant time w.r.t. the loaded data.
154 // However, they set flags and are perhaps the most surprisingly constant
155 // time operations so we call them out here separately.
156 if (isIMUL(Opcode))
157 return true;
158 // Bit scanning and counting instructions that are somewhat surprisingly
159 // constant time as they scan across bits and do other fairly complex
160 // operations like popcnt, but are believed to be constant time on x86.
161 // However, these set flags.
162 if (isBSF(Opcode) || isBSR(Opcode) || isLZCNT(Opcode) || isPOPCNT(Opcode) ||
163 isTZCNT(Opcode))
164 return true;
165 // Bit manipulation instructions are effectively combinations of basic
166 // arithmetic ops, and should still execute in constant time. These also
167 // set flags.
168 if (isBLCFILL(Opcode) || isBLCI(Opcode) || isBLCIC(Opcode) ||
169 isBLCMSK(Opcode) || isBLCS(Opcode) || isBLSFILL(Opcode) ||
170 isBLSI(Opcode) || isBLSIC(Opcode) || isBLSMSK(Opcode) || isBLSR(Opcode) ||
171 isTZMSK(Opcode))
172 return true;
173 // Bit extracting and clearing instructions should execute in constant time,
174 // and set flags.
175 if (isBEXTR(Opcode) || isBZHI(Opcode))
176 return true;
177 // Shift and rotate.
178 if (isROL(Opcode) || isROR(Opcode) || isSAR(Opcode) || isSHL(Opcode) ||
179 isSHR(Opcode) || isSHLD(Opcode) || isSHRD(Opcode))
180 return true;
181 // Basic arithmetic is constant time on the input but does set flags.
182 if (isADC(Opcode) || isADD(Opcode) || isAND(Opcode) || isOR(Opcode) ||
183 isSBB(Opcode) || isSUB(Opcode) || isXOR(Opcode))
184 return true;
185 // Arithmetic with just 32-bit and 64-bit variants and no immediates.
186 if (isANDN(Opcode))
187 return true;
188 // Unary arithmetic operations.
189 if (isDEC(Opcode) || isINC(Opcode) || isNEG(Opcode))
190 return true;
191 // Unlike other arithmetic, NOT doesn't set EFLAGS.
192 if (isNOT(Opcode))
193 return true;
194 // Various move instructions used to zero or sign extend things. Note that we
195 // intentionally don't support the _NOREX variants as we can't handle that
196 // register constraint anyways.
197 if (isMOVSX(Opcode) || isMOVZX(Opcode) || isMOVSXD(Opcode) || isMOV(Opcode))
198 return true;
199 // Arithmetic instructions that are both constant time and don't set flags.
200 if (isRORX(Opcode) || isSARX(Opcode) || isSHLX(Opcode) || isSHRX(Opcode))
201 return true;
202 // LEA doesn't actually access memory, and its arithmetic is constant time.
203 if (isLEA(Opcode))
204 return true;
205 // By default, assume that the instruction is not data invariant.
206 return false;
207}
208
209bool X86InstrInfo::isDataInvariantLoad(MachineInstr &MI) {
210 switch (MI.getOpcode()) {
211 default:
212 // By default, assume that the load will immediately leak.
213 return false;
214
215 // On x86 it is believed that imul is constant time w.r.t. the loaded data.
216 // However, they set flags and are perhaps the most surprisingly constant
217 // time operations so we call them out here separately.
218 case X86::IMUL16rm:
219 case X86::IMUL16rmi:
220 case X86::IMUL32rm:
221 case X86::IMUL32rmi:
222 case X86::IMUL64rm:
223 case X86::IMUL64rmi32:
224
225 // Bit scanning and counting instructions that are somewhat surprisingly
226 // constant time as they scan across bits and do other fairly complex
227 // operations like popcnt, but are believed to be constant time on x86.
228 // However, these set flags.
229 case X86::BSF16rm:
230 case X86::BSF32rm:
231 case X86::BSF64rm:
232 case X86::BSR16rm:
233 case X86::BSR32rm:
234 case X86::BSR64rm:
235 case X86::LZCNT16rm:
236 case X86::LZCNT32rm:
237 case X86::LZCNT64rm:
238 case X86::POPCNT16rm:
239 case X86::POPCNT32rm:
240 case X86::POPCNT64rm:
241 case X86::TZCNT16rm:
242 case X86::TZCNT32rm:
243 case X86::TZCNT64rm:
244
245 // Bit manipulation instructions are effectively combinations of basic
246 // arithmetic ops, and should still execute in constant time. These also
247 // set flags.
248 case X86::BLCFILL32rm:
249 case X86::BLCFILL64rm:
250 case X86::BLCI32rm:
251 case X86::BLCI64rm:
252 case X86::BLCIC32rm:
253 case X86::BLCIC64rm:
254 case X86::BLCMSK32rm:
255 case X86::BLCMSK64rm:
256 case X86::BLCS32rm:
257 case X86::BLCS64rm:
258 case X86::BLSFILL32rm:
259 case X86::BLSFILL64rm:
260 case X86::BLSI32rm:
261 case X86::BLSI64rm:
262 case X86::BLSIC32rm:
263 case X86::BLSIC64rm:
264 case X86::BLSMSK32rm:
265 case X86::BLSMSK64rm:
266 case X86::BLSR32rm:
267 case X86::BLSR64rm:
268 case X86::TZMSK32rm:
269 case X86::TZMSK64rm:
270
271 // Bit extracting and clearing instructions should execute in constant time,
272 // and set flags.
273 case X86::BEXTR32rm:
274 case X86::BEXTR64rm:
275 case X86::BEXTRI32mi:
276 case X86::BEXTRI64mi:
277 case X86::BZHI32rm:
278 case X86::BZHI64rm:
279
280 // Basic arithmetic is constant time on the input but does set flags.
281 case X86::ADC8rm:
282 case X86::ADC16rm:
283 case X86::ADC32rm:
284 case X86::ADC64rm:
285 case X86::ADD8rm:
286 case X86::ADD16rm:
287 case X86::ADD32rm:
288 case X86::ADD64rm:
289 case X86::AND8rm:
290 case X86::AND16rm:
291 case X86::AND32rm:
292 case X86::AND64rm:
293 case X86::ANDN32rm:
294 case X86::ANDN64rm:
295 case X86::OR8rm:
296 case X86::OR16rm:
297 case X86::OR32rm:
298 case X86::OR64rm:
299 case X86::SBB8rm:
300 case X86::SBB16rm:
301 case X86::SBB32rm:
302 case X86::SBB64rm:
303 case X86::SUB8rm:
304 case X86::SUB16rm:
305 case X86::SUB32rm:
306 case X86::SUB64rm:
307 case X86::XOR8rm:
308 case X86::XOR16rm:
309 case X86::XOR32rm:
310 case X86::XOR64rm:
311
312 // Integer multiply w/o affecting flags is still believed to be constant
313 // time on x86. Called out separately as this is among the most surprising
314 // instructions to exhibit that behavior.
315 case X86::MULX32rm:
316 case X86::MULX64rm:
317
318 // Arithmetic instructions that are both constant time and don't set flags.
319 case X86::RORX32mi:
320 case X86::RORX64mi:
321 case X86::SARX32rm:
322 case X86::SARX64rm:
323 case X86::SHLX32rm:
324 case X86::SHLX64rm:
325 case X86::SHRX32rm:
326 case X86::SHRX64rm:
327
328 // Conversions are believed to be constant time and don't set flags.
329 case X86::CVTTSD2SI64rm:
330 case X86::VCVTTSD2SI64rm:
331 case X86::VCVTTSD2SI64Zrm:
332 case X86::CVTTSD2SIrm:
333 case X86::VCVTTSD2SIrm:
334 case X86::VCVTTSD2SIZrm:
335 case X86::CVTTSS2SI64rm:
336 case X86::VCVTTSS2SI64rm:
337 case X86::VCVTTSS2SI64Zrm:
338 case X86::CVTTSS2SIrm:
339 case X86::VCVTTSS2SIrm:
340 case X86::VCVTTSS2SIZrm:
341 case X86::CVTSI2SDrm:
342 case X86::VCVTSI2SDrm:
343 case X86::VCVTSI2SDZrm:
344 case X86::CVTSI2SSrm:
345 case X86::VCVTSI2SSrm:
346 case X86::VCVTSI2SSZrm:
347 case X86::CVTSI642SDrm:
348 case X86::VCVTSI642SDrm:
349 case X86::VCVTSI642SDZrm:
350 case X86::CVTSI642SSrm:
351 case X86::VCVTSI642SSrm:
352 case X86::VCVTSI642SSZrm:
353 case X86::CVTSS2SDrm:
354 case X86::VCVTSS2SDrm:
355 case X86::VCVTSS2SDZrm:
356 case X86::CVTSD2SSrm:
357 case X86::VCVTSD2SSrm:
358 case X86::VCVTSD2SSZrm:
359 // AVX512 added unsigned integer conversions.
360 case X86::VCVTTSD2USI64Zrm:
361 case X86::VCVTTSD2USIZrm:
362 case X86::VCVTTSS2USI64Zrm:
363 case X86::VCVTTSS2USIZrm:
364 case X86::VCVTUSI2SDZrm:
365 case X86::VCVTUSI642SDZrm:
366 case X86::VCVTUSI2SSZrm:
367 case X86::VCVTUSI642SSZrm:
368
369 // Loads to register don't set flags.
370 case X86::MOV8rm:
371 case X86::MOV8rm_NOREX:
372 case X86::MOV16rm:
373 case X86::MOV32rm:
374 case X86::MOV64rm:
375 case X86::MOVSX16rm8:
376 case X86::MOVSX32rm16:
377 case X86::MOVSX32rm8:
378 case X86::MOVSX32rm8_NOREX:
379 case X86::MOVSX64rm16:
380 case X86::MOVSX64rm32:
381 case X86::MOVSX64rm8:
382 case X86::MOVZX16rm8:
383 case X86::MOVZX32rm16:
384 case X86::MOVZX32rm8:
385 case X86::MOVZX32rm8_NOREX:
386 case X86::MOVZX64rm16:
387 case X86::MOVZX64rm8:
388 return true;
389 }
390}
391
392int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
393 const MachineFunction *MF = MI.getParent()->getParent();
394 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
395
396 if (isFrameInstr(I: MI)) {
397 int SPAdj = alignTo(Size: getFrameSize(I: MI), A: TFI->getStackAlign());
398 SPAdj -= getFrameAdjustment(I: MI);
399 if (!isFrameSetup(I: MI))
400 SPAdj = -SPAdj;
401 return SPAdj;
402 }
403
404 // To know whether a call adjusts the stack, we need information
405 // that is bound to the following ADJCALLSTACKUP pseudo.
406 // Look for the next ADJCALLSTACKUP that follows the call.
407 if (MI.isCall()) {
408 const MachineBasicBlock *MBB = MI.getParent();
409 auto I = ++MachineBasicBlock::const_iterator(MI);
410 for (auto E = MBB->end(); I != E; ++I) {
411 if (I->getOpcode() == getCallFrameDestroyOpcode() || I->isCall())
412 break;
413 }
414
415 // If we could not find a frame destroy opcode, then it has already
416 // been simplified, so we don't care.
417 if (I->getOpcode() != getCallFrameDestroyOpcode())
418 return 0;
419
420 return -(I->getOperand(i: 1).getImm());
421 }
422
423 // Currently handle only PUSHes we can reasonably expect to see
424 // in call sequences
425 switch (MI.getOpcode()) {
426 default:
427 return 0;
428 case X86::PUSH32r:
429 case X86::PUSH32rmm:
430 case X86::PUSH32rmr:
431 case X86::PUSH32i:
432 return 4;
433 case X86::PUSH64r:
434 case X86::PUSH64rmm:
435 case X86::PUSH64rmr:
436 case X86::PUSH64i32:
437 return 8;
438 }
439}
440
441/// Return true and the FrameIndex if the specified
442/// operand and follow operands form a reference to the stack frame.
443bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
444 int &FrameIndex) const {
445 if (MI.getOperand(i: Op + X86::AddrBaseReg).isFI() &&
446 MI.getOperand(i: Op + X86::AddrScaleAmt).isImm() &&
447 MI.getOperand(i: Op + X86::AddrIndexReg).isReg() &&
448 MI.getOperand(i: Op + X86::AddrDisp).isImm() &&
449 MI.getOperand(i: Op + X86::AddrScaleAmt).getImm() == 1 &&
450 MI.getOperand(i: Op + X86::AddrIndexReg).getReg() == 0 &&
451 MI.getOperand(i: Op + X86::AddrDisp).getImm() == 0) {
452 FrameIndex = MI.getOperand(i: Op + X86::AddrBaseReg).getIndex();
453 return true;
454 }
455 return false;
456}
457
458static bool isFrameLoadOpcode(int Opcode, TypeSize &MemBytes) {
459 switch (Opcode) {
460 default:
461 return false;
462 case X86::MOV8rm:
463 case X86::KMOVBkm:
464 case X86::KMOVBkm_EVEX:
465 MemBytes = TypeSize::getFixed(ExactSize: 1);
466 return true;
467 case X86::MOV16rm:
468 case X86::KMOVWkm:
469 case X86::KMOVWkm_EVEX:
470 case X86::VMOVSHZrm:
471 case X86::VMOVSHZrm_alt:
472 MemBytes = TypeSize::getFixed(ExactSize: 2);
473 return true;
474 case X86::MOV32rm:
475 case X86::MOVSSrm:
476 case X86::MOVSSrm_alt:
477 case X86::VMOVSSrm:
478 case X86::VMOVSSrm_alt:
479 case X86::VMOVSSZrm:
480 case X86::VMOVSSZrm_alt:
481 case X86::KMOVDkm:
482 case X86::KMOVDkm_EVEX:
483 MemBytes = TypeSize::getFixed(ExactSize: 4);
484 return true;
485 case X86::MOV64rm:
486 case X86::LD_Fp64m:
487 case X86::MOVSDrm:
488 case X86::MOVSDrm_alt:
489 case X86::VMOVSDrm:
490 case X86::VMOVSDrm_alt:
491 case X86::VMOVSDZrm:
492 case X86::VMOVSDZrm_alt:
493 case X86::MMX_MOVD64rm:
494 case X86::MMX_MOVQ64rm:
495 case X86::KMOVQkm:
496 case X86::KMOVQkm_EVEX:
497 MemBytes = TypeSize::getFixed(ExactSize: 8);
498 return true;
499 case X86::MOVAPSrm:
500 case X86::MOVUPSrm:
501 case X86::MOVAPDrm:
502 case X86::MOVUPDrm:
503 case X86::MOVDQArm:
504 case X86::MOVDQUrm:
505 case X86::VMOVAPSrm:
506 case X86::VMOVUPSrm:
507 case X86::VMOVAPDrm:
508 case X86::VMOVUPDrm:
509 case X86::VMOVDQArm:
510 case X86::VMOVDQUrm:
511 case X86::VMOVAPSZ128rm:
512 case X86::VMOVUPSZ128rm:
513 case X86::VMOVAPSZ128rm_NOVLX:
514 case X86::VMOVUPSZ128rm_NOVLX:
515 case X86::VMOVAPDZ128rm:
516 case X86::VMOVUPDZ128rm:
517 case X86::VMOVDQU8Z128rm:
518 case X86::VMOVDQU16Z128rm:
519 case X86::VMOVDQA32Z128rm:
520 case X86::VMOVDQU32Z128rm:
521 case X86::VMOVDQA64Z128rm:
522 case X86::VMOVDQU64Z128rm:
523 MemBytes = TypeSize::getFixed(ExactSize: 16);
524 return true;
525 case X86::VMOVAPSYrm:
526 case X86::VMOVUPSYrm:
527 case X86::VMOVAPDYrm:
528 case X86::VMOVUPDYrm:
529 case X86::VMOVDQAYrm:
530 case X86::VMOVDQUYrm:
531 case X86::VMOVAPSZ256rm:
532 case X86::VMOVUPSZ256rm:
533 case X86::VMOVAPSZ256rm_NOVLX:
534 case X86::VMOVUPSZ256rm_NOVLX:
535 case X86::VMOVAPDZ256rm:
536 case X86::VMOVUPDZ256rm:
537 case X86::VMOVDQU8Z256rm:
538 case X86::VMOVDQU16Z256rm:
539 case X86::VMOVDQA32Z256rm:
540 case X86::VMOVDQU32Z256rm:
541 case X86::VMOVDQA64Z256rm:
542 case X86::VMOVDQU64Z256rm:
543 MemBytes = TypeSize::getFixed(ExactSize: 32);
544 return true;
545 case X86::VMOVAPSZrm:
546 case X86::VMOVUPSZrm:
547 case X86::VMOVAPDZrm:
548 case X86::VMOVUPDZrm:
549 case X86::VMOVDQU8Zrm:
550 case X86::VMOVDQU16Zrm:
551 case X86::VMOVDQA32Zrm:
552 case X86::VMOVDQU32Zrm:
553 case X86::VMOVDQA64Zrm:
554 case X86::VMOVDQU64Zrm:
555 MemBytes = TypeSize::getFixed(ExactSize: 64);
556 return true;
557 }
558}
559
560static bool isFrameStoreOpcode(int Opcode, TypeSize &MemBytes) {
561 switch (Opcode) {
562 default:
563 return false;
564 case X86::MOV8mr:
565 case X86::KMOVBmk:
566 case X86::KMOVBmk_EVEX:
567 MemBytes = TypeSize::getFixed(ExactSize: 1);
568 return true;
569 case X86::MOV16mr:
570 case X86::KMOVWmk:
571 case X86::KMOVWmk_EVEX:
572 case X86::VMOVSHZmr:
573 MemBytes = TypeSize::getFixed(ExactSize: 2);
574 return true;
575 case X86::MOV32mr:
576 case X86::MOVSSmr:
577 case X86::VMOVSSmr:
578 case X86::VMOVSSZmr:
579 case X86::KMOVDmk:
580 case X86::KMOVDmk_EVEX:
581 MemBytes = TypeSize::getFixed(ExactSize: 4);
582 return true;
583 case X86::MOV64mr:
584 case X86::ST_FpP64m:
585 case X86::MOVSDmr:
586 case X86::VMOVSDmr:
587 case X86::VMOVSDZmr:
588 case X86::MMX_MOVD64mr:
589 case X86::MMX_MOVQ64mr:
590 case X86::MMX_MOVNTQmr:
591 case X86::KMOVQmk:
592 case X86::KMOVQmk_EVEX:
593 MemBytes = TypeSize::getFixed(ExactSize: 8);
594 return true;
595 case X86::MOVAPSmr:
596 case X86::MOVUPSmr:
597 case X86::MOVAPDmr:
598 case X86::MOVUPDmr:
599 case X86::MOVDQAmr:
600 case X86::MOVDQUmr:
601 case X86::VMOVAPSmr:
602 case X86::VMOVUPSmr:
603 case X86::VMOVAPDmr:
604 case X86::VMOVUPDmr:
605 case X86::VMOVDQAmr:
606 case X86::VMOVDQUmr:
607 case X86::VMOVUPSZ128mr:
608 case X86::VMOVAPSZ128mr:
609 case X86::VMOVUPSZ128mr_NOVLX:
610 case X86::VMOVAPSZ128mr_NOVLX:
611 case X86::VMOVUPDZ128mr:
612 case X86::VMOVAPDZ128mr:
613 case X86::VMOVDQA32Z128mr:
614 case X86::VMOVDQU32Z128mr:
615 case X86::VMOVDQA64Z128mr:
616 case X86::VMOVDQU64Z128mr:
617 case X86::VMOVDQU8Z128mr:
618 case X86::VMOVDQU16Z128mr:
619 MemBytes = TypeSize::getFixed(ExactSize: 16);
620 return true;
621 case X86::VMOVUPSYmr:
622 case X86::VMOVAPSYmr:
623 case X86::VMOVUPDYmr:
624 case X86::VMOVAPDYmr:
625 case X86::VMOVDQUYmr:
626 case X86::VMOVDQAYmr:
627 case X86::VMOVUPSZ256mr:
628 case X86::VMOVAPSZ256mr:
629 case X86::VMOVUPSZ256mr_NOVLX:
630 case X86::VMOVAPSZ256mr_NOVLX:
631 case X86::VMOVUPDZ256mr:
632 case X86::VMOVAPDZ256mr:
633 case X86::VMOVDQU8Z256mr:
634 case X86::VMOVDQU16Z256mr:
635 case X86::VMOVDQA32Z256mr:
636 case X86::VMOVDQU32Z256mr:
637 case X86::VMOVDQA64Z256mr:
638 case X86::VMOVDQU64Z256mr:
639 MemBytes = TypeSize::getFixed(ExactSize: 32);
640 return true;
641 case X86::VMOVUPSZmr:
642 case X86::VMOVAPSZmr:
643 case X86::VMOVUPDZmr:
644 case X86::VMOVAPDZmr:
645 case X86::VMOVDQU8Zmr:
646 case X86::VMOVDQU16Zmr:
647 case X86::VMOVDQA32Zmr:
648 case X86::VMOVDQU32Zmr:
649 case X86::VMOVDQA64Zmr:
650 case X86::VMOVDQU64Zmr:
651 MemBytes = TypeSize::getFixed(ExactSize: 64);
652 return true;
653 }
654 return false;
655}
656
657Register X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
658 int &FrameIndex) const {
659 TypeSize Dummy = TypeSize::getZero();
660 return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, MemBytes&: Dummy);
661}
662
663Register X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
664 int &FrameIndex,
665 TypeSize &MemBytes) const {
666 if (isFrameLoadOpcode(Opcode: MI.getOpcode(), MemBytes))
667 if (MI.getOperand(i: 0).getSubReg() == 0 && isFrameOperand(MI, Op: 1, FrameIndex))
668 return MI.getOperand(i: 0).getReg();
669 return Register();
670}
671
672Register X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
673 int &FrameIndex) const {
674 TypeSize Dummy = TypeSize::getZero();
675 if (isFrameLoadOpcode(Opcode: MI.getOpcode(), MemBytes&: Dummy)) {
676 if (Register Reg = isLoadFromStackSlot(MI, FrameIndex))
677 return Reg;
678 // Check for post-frame index elimination operations
679 SmallVector<const MachineMemOperand *, 1> Accesses;
680 if (hasLoadFromStackSlot(MI, Accesses)) {
681 FrameIndex =
682 cast<FixedStackPseudoSourceValue>(Val: Accesses.front()->getPseudoValue())
683 ->getFrameIndex();
684 return MI.getOperand(i: 0).getReg();
685 }
686 }
687 return Register();
688}
689
690Register X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
691 int &FrameIndex) const {
692 TypeSize Dummy = TypeSize::getZero();
693 return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, MemBytes&: Dummy);
694}
695
696Register X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
697 int &FrameIndex,
698 TypeSize &MemBytes) const {
699 if (isFrameStoreOpcode(Opcode: MI.getOpcode(), MemBytes))
700 if (MI.getOperand(i: X86::AddrNumOperands).getSubReg() == 0 &&
701 isFrameOperand(MI, Op: 0, FrameIndex))
702 return MI.getOperand(i: X86::AddrNumOperands).getReg();
703 return Register();
704}
705
706Register X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
707 int &FrameIndex) const {
708 TypeSize Dummy = TypeSize::getZero();
709 if (isFrameStoreOpcode(Opcode: MI.getOpcode(), MemBytes&: Dummy)) {
710 if (Register Reg = isStoreToStackSlot(MI, FrameIndex))
711 return Reg;
712 // Check for post-frame index elimination operations
713 SmallVector<const MachineMemOperand *, 1> Accesses;
714 if (hasStoreToStackSlot(MI, Accesses)) {
715 FrameIndex =
716 cast<FixedStackPseudoSourceValue>(Val: Accesses.front()->getPseudoValue())
717 ->getFrameIndex();
718 return MI.getOperand(i: X86::AddrNumOperands).getReg();
719 }
720 }
721 return Register();
722}
723
724/// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
725static bool regIsPICBase(Register BaseReg, const MachineRegisterInfo &MRI) {
726 // Don't waste compile time scanning use-def chains of physregs.
727 if (!BaseReg.isVirtual())
728 return false;
729 bool isPICBase = false;
730 for (const MachineInstr &DefMI : MRI.def_instructions(Reg: BaseReg)) {
731 if (DefMI.getOpcode() != X86::MOVPC32r)
732 return false;
733 assert(!isPICBase && "More than one PIC base?");
734 isPICBase = true;
735 }
736 return isPICBase;
737}
738
739bool X86InstrInfo::isReMaterializableImpl(
740 const MachineInstr &MI) const {
741 switch (MI.getOpcode()) {
742 default:
743 // This function should only be called for opcodes with the ReMaterializable
744 // flag set.
745 llvm_unreachable("Unknown rematerializable operation!");
746 break;
747 case X86::IMPLICIT_DEF:
748 // Defer to generic logic.
749 break;
750 case X86::LOAD_STACK_GUARD:
751 case X86::LD_Fp032:
752 case X86::LD_Fp064:
753 case X86::LD_Fp080:
754 case X86::LD_Fp132:
755 case X86::LD_Fp164:
756 case X86::LD_Fp180:
757 case X86::AVX1_SETALLONES:
758 case X86::AVX2_SETALLONES:
759 case X86::AVX512_128_SET0:
760 case X86::AVX512_128_SETALLONES:
761 case X86::AVX512_256_SETALLONES:
762 case X86::AVX512_512_SETALLONES:
763 case X86::AVX512_FsFLD0SD:
764 case X86::AVX512_FsFLD0SH:
765 case X86::AVX512_FsFLD0SS:
766 case X86::AVX512_FsFLD0F128:
767 case X86::FsFLD0SD:
768 case X86::FsFLD0SS:
769 case X86::FsFLD0SH:
770 case X86::FsFLD0F128:
771 case X86::KSET0B:
772 case X86::KSET0D:
773 case X86::KSET0Q:
774 case X86::KSET0W:
775 case X86::KSET1B:
776 case X86::KSET1D:
777 case X86::KSET1Q:
778 case X86::KSET1W:
779 case X86::MMX_SET0:
780 case X86::MOV32ImmSExti8:
781 case X86::MOV32r0:
782 case X86::MOV32r1:
783 case X86::MOV32r_1:
784 case X86::MOV32ri64:
785 case X86::MOV64ImmSExti8:
786 case X86::V_SET0:
787 case X86::V_SETALLONES:
788 case X86::MOV16ri:
789 case X86::MOV32ri:
790 case X86::MOV64ri:
791 case X86::MOV64ri32:
792 case X86::MOV8ri:
793 case X86::PTILEZEROV:
794 return true;
795
796 case X86::MOV8rm:
797 case X86::MOV8rm_NOREX:
798 case X86::MOV16rm:
799 case X86::MOV32rm:
800 case X86::MOV64rm:
801 case X86::MOVSSrm:
802 case X86::MOVSSrm_alt:
803 case X86::MOVSDrm:
804 case X86::MOVSDrm_alt:
805 case X86::MOVAPSrm:
806 case X86::MOVUPSrm:
807 case X86::MOVAPDrm:
808 case X86::MOVUPDrm:
809 case X86::MOVDQArm:
810 case X86::MOVDQUrm:
811 case X86::VMOVSSrm:
812 case X86::VMOVSSrm_alt:
813 case X86::VMOVSDrm:
814 case X86::VMOVSDrm_alt:
815 case X86::VMOVAPSrm:
816 case X86::VMOVUPSrm:
817 case X86::VMOVAPDrm:
818 case X86::VMOVUPDrm:
819 case X86::VMOVDQArm:
820 case X86::VMOVDQUrm:
821 case X86::VMOVAPSYrm:
822 case X86::VMOVUPSYrm:
823 case X86::VMOVAPDYrm:
824 case X86::VMOVUPDYrm:
825 case X86::VMOVDQAYrm:
826 case X86::VMOVDQUYrm:
827 case X86::MMX_MOVD64rm:
828 case X86::MMX_MOVQ64rm:
829 case X86::VBROADCASTSSrm:
830 case X86::VBROADCASTSSYrm:
831 case X86::VBROADCASTSDYrm:
832 // AVX-512
833 case X86::VPBROADCASTBZ128rm:
834 case X86::VPBROADCASTBZ256rm:
835 case X86::VPBROADCASTBZrm:
836 case X86::VBROADCASTF32X2Z256rm:
837 case X86::VBROADCASTF32X2Zrm:
838 case X86::VBROADCASTI32X2Z128rm:
839 case X86::VBROADCASTI32X2Z256rm:
840 case X86::VBROADCASTI32X2Zrm:
841 case X86::VPBROADCASTWZ128rm:
842 case X86::VPBROADCASTWZ256rm:
843 case X86::VPBROADCASTWZrm:
844 case X86::VPBROADCASTDZ128rm:
845 case X86::VPBROADCASTDZ256rm:
846 case X86::VPBROADCASTDZrm:
847 case X86::VBROADCASTSSZ128rm:
848 case X86::VBROADCASTSSZ256rm:
849 case X86::VBROADCASTSSZrm:
850 case X86::VPBROADCASTQZ128rm:
851 case X86::VPBROADCASTQZ256rm:
852 case X86::VPBROADCASTQZrm:
853 case X86::VBROADCASTSDZ256rm:
854 case X86::VBROADCASTSDZrm:
855 case X86::VMOVSSZrm:
856 case X86::VMOVSSZrm_alt:
857 case X86::VMOVSDZrm:
858 case X86::VMOVSDZrm_alt:
859 case X86::VMOVSHZrm:
860 case X86::VMOVSHZrm_alt:
861 case X86::VMOVAPDZ128rm:
862 case X86::VMOVAPDZ256rm:
863 case X86::VMOVAPDZrm:
864 case X86::VMOVAPSZ128rm:
865 case X86::VMOVAPSZ256rm:
866 case X86::VMOVAPSZ128rm_NOVLX:
867 case X86::VMOVAPSZ256rm_NOVLX:
868 case X86::VMOVAPSZrm:
869 case X86::VMOVDQA32Z128rm:
870 case X86::VMOVDQA32Z256rm:
871 case X86::VMOVDQA32Zrm:
872 case X86::VMOVDQA64Z128rm:
873 case X86::VMOVDQA64Z256rm:
874 case X86::VMOVDQA64Zrm:
875 case X86::VMOVDQU16Z128rm:
876 case X86::VMOVDQU16Z256rm:
877 case X86::VMOVDQU16Zrm:
878 case X86::VMOVDQU32Z128rm:
879 case X86::VMOVDQU32Z256rm:
880 case X86::VMOVDQU32Zrm:
881 case X86::VMOVDQU64Z128rm:
882 case X86::VMOVDQU64Z256rm:
883 case X86::VMOVDQU64Zrm:
884 case X86::VMOVDQU8Z128rm:
885 case X86::VMOVDQU8Z256rm:
886 case X86::VMOVDQU8Zrm:
887 case X86::VMOVUPDZ128rm:
888 case X86::VMOVUPDZ256rm:
889 case X86::VMOVUPDZrm:
890 case X86::VMOVUPSZ128rm:
891 case X86::VMOVUPSZ256rm:
892 case X86::VMOVUPSZ128rm_NOVLX:
893 case X86::VMOVUPSZ256rm_NOVLX:
894 case X86::VMOVUPSZrm: {
895 // Loads from constant pools are trivially rematerializable.
896 if (MI.getOperand(i: 1 + X86::AddrBaseReg).isReg() &&
897 MI.getOperand(i: 1 + X86::AddrScaleAmt).isImm() &&
898 MI.getOperand(i: 1 + X86::AddrIndexReg).isReg() &&
899 MI.getOperand(i: 1 + X86::AddrIndexReg).getReg() == 0 &&
900 MI.isDereferenceableInvariantLoad()) {
901 Register BaseReg = MI.getOperand(i: 1 + X86::AddrBaseReg).getReg();
902 if (BaseReg == 0 || BaseReg == X86::RIP)
903 return true;
904 // Allow re-materialization of PIC load.
905 if (!(!Subtarget.getCLOpts().remat_pic_stub_load &&
906 MI.getOperand(i: 1 + X86::AddrDisp).isGlobal())) {
907 const MachineFunction &MF = *MI.getParent()->getParent();
908 const MachineRegisterInfo &MRI = MF.getRegInfo();
909 if (regIsPICBase(BaseReg, MRI))
910 return true;
911 }
912 }
913 break;
914 }
915
916 case X86::LEA32r:
917 case X86::LEA64r: {
918 if (MI.getOperand(i: 1 + X86::AddrScaleAmt).isImm() &&
919 MI.getOperand(i: 1 + X86::AddrIndexReg).isReg() &&
920 MI.getOperand(i: 1 + X86::AddrIndexReg).getReg() == 0 &&
921 !MI.getOperand(i: 1 + X86::AddrDisp).isReg()) {
922 // lea fi#, lea GV, etc. are all rematerializable.
923 if (!MI.getOperand(i: 1 + X86::AddrBaseReg).isReg())
924 return true;
925 Register BaseReg = MI.getOperand(i: 1 + X86::AddrBaseReg).getReg();
926 if (BaseReg == 0)
927 return true;
928 // Allow re-materialization of lea PICBase + x.
929 const MachineFunction &MF = *MI.getParent()->getParent();
930 const MachineRegisterInfo &MRI = MF.getRegInfo();
931 if (regIsPICBase(BaseReg, MRI))
932 return true;
933 }
934 break;
935 }
936 }
937 return TargetInstrInfo::isReMaterializableImpl(MI);
938}
939
940void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
941 MachineBasicBlock::iterator I,
942 Register DestReg, unsigned SubIdx,
943 const MachineInstr &Orig,
944 LaneBitmask UsedLanes) const {
945 bool ClobbersEFLAGS = Orig.modifiesRegister(Reg: X86::EFLAGS, TRI: &TRI);
946 if (ClobbersEFLAGS && MBB.computeRegisterLiveness(TRI: &TRI, Reg: X86::EFLAGS, Before: I) !=
947 MachineBasicBlock::LQR_Dead) {
948 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
949 // effects.
950 int Value;
951 switch (Orig.getOpcode()) {
952 case X86::MOV32r0:
953 Value = 0;
954 break;
955 case X86::MOV32r1:
956 Value = 1;
957 break;
958 case X86::MOV32r_1:
959 Value = -1;
960 break;
961 default:
962 llvm_unreachable("Unexpected instruction!");
963 }
964
965 const DebugLoc &DL = Orig.getDebugLoc();
966 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: X86::MOV32ri))
967 .add(MO: Orig.getOperand(i: 0))
968 .addImm(Val: Value);
969 } else {
970 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig: &Orig);
971 MBB.insert(I, MI);
972 }
973
974 MachineInstr &NewMI = *std::prev(x: I);
975 NewMI.substituteRegister(FromReg: Orig.getOperand(i: 0).getReg(), ToReg: DestReg, SubIdx, RegInfo: TRI);
976}
977
978/// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
979bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
980 for (const MachineOperand &MO : MI.operands()) {
981 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS &&
982 !MO.isDead()) {
983 return true;
984 }
985 }
986 return false;
987}
988
989/// Check whether the shift count for a machine operand is non-zero.
990inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
991 unsigned ShiftAmtOperandIdx) {
992 // The shift count is six bits with the REX.W prefix and five bits without.
993 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
994 unsigned Imm = MI.getOperand(i: ShiftAmtOperandIdx).getImm();
995 return Imm & ShiftCountMask;
996}
997
998/// Check whether the given shift count is appropriate
999/// can be represented by a LEA instruction.
1000inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1001 // Left shift instructions can be transformed into load-effective-address
1002 // instructions if we can encode them appropriately.
1003 // A LEA instruction utilizes a SIB byte to encode its scale factor.
1004 // The SIB.scale field is two bits wide which means that we can encode any
1005 // shift amount less than 4.
1006 return ShAmt < 4 && ShAmt > 0;
1007}
1008
1009static bool
1010findRedundantFlagInstr(MachineInstr &CmpInstr, MachineInstr &CmpValDefInstr,
1011 const MachineRegisterInfo *MRI, MachineInstr **AndInstr,
1012 const TargetRegisterInfo *TRI, const X86Subtarget &ST,
1013 bool &NoSignFlag, bool &ClearsOverflowFlag) {
1014 if (!(CmpValDefInstr.getOpcode() == X86::SUBREG_TO_REG &&
1015 CmpInstr.getOpcode() == X86::TEST64rr) &&
1016 !(CmpValDefInstr.getOpcode() == X86::COPY &&
1017 CmpInstr.getOpcode() == X86::TEST16rr))
1018 return false;
1019
1020 // CmpInstr is a TEST16rr/TEST64rr instruction, and
1021 // `X86InstrInfo::analyzeCompare` guarantees that it's analyzable only if two
1022 // registers are identical.
1023 assert((CmpInstr.getOperand(0).getReg() == CmpInstr.getOperand(1).getReg()) &&
1024 "CmpInstr is an analyzable TEST16rr/TEST64rr, and "
1025 "`X86InstrInfo::analyzeCompare` requires two reg operands are the"
1026 "same.");
1027
1028 // Caller (`X86InstrInfo::optimizeCompareInstr`) guarantees that
1029 // `CmpValDefInstr` defines the value that's used by `CmpInstr`; in this case
1030 // if `CmpValDefInstr` sets the EFLAGS, it is likely that `CmpInstr` is
1031 // redundant.
1032 assert(
1033 (MRI->getVRegDef(CmpInstr.getOperand(0).getReg()) == &CmpValDefInstr) &&
1034 "Caller guarantees that TEST64rr is a user of SUBREG_TO_REG or TEST16rr "
1035 "is a user of COPY sub16bit.");
1036 MachineInstr *VregDefInstr = nullptr;
1037 if (CmpInstr.getOpcode() == X86::TEST16rr) {
1038 if (!CmpValDefInstr.getOperand(i: 1).getReg().isVirtual())
1039 return false;
1040 VregDefInstr = MRI->getVRegDef(Reg: CmpValDefInstr.getOperand(i: 1).getReg());
1041 if (!VregDefInstr)
1042 return false;
1043 // We can only remove test when AND32ri or AND64ri32 whose imm can fit 16bit
1044 // size, others 32/64 bit ops would test higher bits which test16rr don't
1045 // want to.
1046 if (!((VregDefInstr->getOpcode() == X86::AND32ri ||
1047 VregDefInstr->getOpcode() == X86::AND64ri32) &&
1048 isUInt<16>(x: VregDefInstr->getOperand(i: 2).getImm())))
1049 return false;
1050 }
1051
1052 if (CmpInstr.getOpcode() == X86::TEST64rr) {
1053 // As seen in X86 td files, CmpValDefInstr.getOperand(3) is typically
1054 // sub_32bit or sub_xmm.
1055 if (CmpValDefInstr.getOperand(i: 2).getImm() != X86::sub_32bit)
1056 return false;
1057
1058 VregDefInstr = MRI->getVRegDef(Reg: CmpValDefInstr.getOperand(i: 1).getReg());
1059 }
1060
1061 assert(VregDefInstr && "Must have a definition (SSA)");
1062
1063 // Requires `CmpValDefInstr` and `VregDefInstr` are from the same MBB
1064 // to simplify the subsequent analysis.
1065 //
1066 // FIXME: If `VregDefInstr->getParent()` is the only predecessor of
1067 // `CmpValDefInstr.getParent()`, this could be handled.
1068 if (VregDefInstr->getParent() != CmpValDefInstr.getParent())
1069 return false;
1070
1071 if (X86::isAND(Opcode: VregDefInstr->getOpcode()) &&
1072 (!ST.hasNF() || VregDefInstr->modifiesRegister(Reg: X86::EFLAGS, TRI))) {
1073 // Get a sequence of instructions like
1074 // %reg = and* ... // Set EFLAGS
1075 // ... // EFLAGS not changed
1076 // %extended_reg = subreg_to_reg %reg, %subreg.sub_32bit
1077 // test64rr %extended_reg, %extended_reg, implicit-def $eflags
1078 // or
1079 // %reg = and32* ...
1080 // ... // EFLAGS not changed.
1081 // %src_reg = copy %reg.sub_16bit:gr32
1082 // test16rr %src_reg, %src_reg, implicit-def $eflags
1083 //
1084 // If subsequent readers use a subset of bits that don't change
1085 // after `and*` instructions, it's likely that the test64rr could
1086 // be optimized away.
1087 for (const MachineInstr &Instr :
1088 make_range(x: std::next(x: MachineBasicBlock::iterator(VregDefInstr)),
1089 y: MachineBasicBlock::iterator(CmpValDefInstr))) {
1090 // There are instructions between 'VregDefInstr' and
1091 // 'CmpValDefInstr' that modifies EFLAGS.
1092 if (Instr.modifiesRegister(Reg: X86::EFLAGS, TRI))
1093 return false;
1094 }
1095
1096 *AndInstr = VregDefInstr;
1097
1098 // AND instruction will essentially update SF and clear OF, so
1099 // NoSignFlag should be false in the sense that SF is modified by `AND`.
1100 //
1101 // However, the implementation artifically sets `NoSignFlag` to true
1102 // to poison the SF bit; that is to say, if SF is looked at later, the
1103 // optimization (to erase TEST64rr) will be disabled.
1104 //
1105 // The reason to poison SF bit is that SF bit value could be different
1106 // in the `AND` and `TEST` operation; signed bit is not known for `AND`,
1107 // and is known to be 0 as a result of `TEST64rr`.
1108 //
1109 // FIXME: As opposed to poisoning the SF bit directly, consider peeking into
1110 // the AND instruction and using the static information to guide peephole
1111 // optimization if possible. For example, it's possible to fold a
1112 // conditional move into a copy if the relevant EFLAG bits could be deduced
1113 // from an immediate operand of and operation.
1114 //
1115 NoSignFlag = true;
1116 // ClearsOverflowFlag is true for AND operation (no surprise).
1117 ClearsOverflowFlag = true;
1118 return true;
1119 }
1120 return false;
1121}
1122
1123bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
1124 unsigned Opc, bool AllowSP, Register &NewSrc,
1125 unsigned &NewSrcSubReg, bool &isKill,
1126 MachineOperand &ImplicitOp,
1127 LiveIntervals *LIS) const {
1128 MachineFunction &MF = *MI.getParent()->getParent();
1129 const TargetRegisterClass *RC;
1130 if (AllowSP) {
1131 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1132 } else {
1133 RC = Opc != X86::LEA32r ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1134 }
1135 Register SrcReg = Src.getReg();
1136 unsigned SubReg = Src.getSubReg();
1137 isKill = MI.killsRegister(Reg: SrcReg, /*TRI=*/nullptr);
1138
1139 NewSrcSubReg = X86::NoSubRegister;
1140
1141 // For both LEA64 and LEA32 the register already has essentially the right
1142 // type (32-bit or 64-bit) we may just need to forbid SP.
1143 if (Opc != X86::LEA64_32r) {
1144 NewSrc = SrcReg;
1145 NewSrcSubReg = SubReg;
1146 assert(!Src.isUndef() && "Undef op doesn't need optimization");
1147
1148 if (NewSrc.isVirtual() && !MF.getRegInfo().constrainRegClass(Reg: NewSrc, RC))
1149 return false;
1150
1151 return true;
1152 }
1153
1154 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1155 // another we need to add 64-bit registers to the final MI.
1156 if (SrcReg.isPhysical()) {
1157 ImplicitOp = Src;
1158 ImplicitOp.setImplicit();
1159
1160 NewSrc = getX86SubSuperRegister(Reg: SrcReg, Size: 64);
1161 assert(!SubReg && "no superregister for source");
1162 assert(NewSrc.isValid() && "Invalid Operand");
1163 assert(!Src.isUndef() && "Undef op doesn't need optimization");
1164 } else {
1165 // Virtual register of the wrong class, we have to create a temporary 64-bit
1166 // vreg to feed into the LEA.
1167 NewSrc = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1168 NewSrcSubReg = X86::NoSubRegister;
1169 MachineInstr *Copy =
1170 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: TargetOpcode::COPY))
1171 .addReg(RegNo: NewSrc, Flags: RegState::Define | RegState::Undef, SubReg: X86::sub_32bit)
1172 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill), SubReg);
1173
1174 // Which is obviously going to be dead after we're done with it.
1175 isKill = true;
1176
1177 if (LIS) {
1178 SlotIndex CopyIdx = LIS->InsertMachineInstrInMaps(MI&: *Copy);
1179 SlotIndex Idx = LIS->getInstructionIndex(Instr: MI);
1180 LiveInterval &LI = LIS->getInterval(Reg: SrcReg);
1181 LiveRange::Segment *S = LI.getSegmentContaining(Idx);
1182 if (S->end.getBaseIndex() == Idx)
1183 S->end = CopyIdx.getRegSlot();
1184 }
1185 }
1186
1187 // We've set all the parameters without issue.
1188 return true;
1189}
1190
1191MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1192 MachineInstr &MI,
1193 LiveIntervals *LIS,
1194 bool Is8BitOp) const {
1195 // We handle 8-bit adds and various 16-bit opcodes in the switch below.
1196 MachineBasicBlock &MBB = *MI.getParent();
1197 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
1198 assert((Is8BitOp ||
1199 RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
1200 *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
1201 "Unexpected type for LEA transform");
1202
1203 // TODO: For a 32-bit target, we need to adjust the LEA variables with
1204 // something like this:
1205 // Opcode = X86::LEA32r;
1206 // InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1207 // OutRegLEA =
1208 // Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
1209 // : RegInfo.createVirtualRegister(&X86::GR32RegClass);
1210 if (!Subtarget.is64Bit())
1211 return nullptr;
1212
1213 unsigned Opcode = X86::LEA64_32r;
1214 Register InRegLEA = RegInfo.createVirtualRegister(RegClass: &X86::GR64_NOSPRegClass);
1215 Register OutRegLEA = RegInfo.createVirtualRegister(RegClass: &X86::GR32RegClass);
1216 Register InRegLEA2;
1217
1218 // Build and insert into an implicit UNDEF value. This is OK because
1219 // we will be shifting and then extracting the lower 8/16-bits.
1220 // This has the potential to cause partial register stall. e.g.
1221 // movw (%rbp,%rcx,2), %dx
1222 // leal -65(%rdx), %esi
1223 // But testing has shown this *does* help performance in 64-bit mode (at
1224 // least on modern x86 machines).
1225 MachineBasicBlock::iterator MBBI = MI.getIterator();
1226 Register Dest = MI.getOperand(i: 0).getReg();
1227 Register Src = MI.getOperand(i: 1).getReg();
1228 unsigned SrcSubReg = MI.getOperand(i: 1).getSubReg();
1229 Register Src2;
1230 unsigned Src2SubReg;
1231 bool IsDead = MI.getOperand(i: 0).isDead();
1232 bool IsKill = MI.getOperand(i: 1).isKill();
1233 unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
1234 assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
1235 MachineInstr *ImpDef =
1236 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::IMPLICIT_DEF), DestReg: InRegLEA);
1237 MachineInstr *InsMI =
1238 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: TargetOpcode::COPY))
1239 .addReg(RegNo: InRegLEA, Flags: RegState::Define, SubReg)
1240 .addReg(RegNo: Src, Flags: getKillRegState(B: IsKill), SubReg: SrcSubReg);
1241 MachineInstr *ImpDef2 = nullptr;
1242 MachineInstr *InsMI2 = nullptr;
1243
1244 MachineInstrBuilder MIB =
1245 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: get(Opcode), DestReg: OutRegLEA);
1246#define CASE_NF(OP) \
1247 case X86::OP: \
1248 case X86::OP##_NF:
1249 switch (MIOpc) {
1250 default:
1251 llvm_unreachable("Unreachable!");
1252 CASE_NF(SHL8ri)
1253 CASE_NF(SHL16ri) {
1254 unsigned ShAmt = MI.getOperand(i: 2).getImm();
1255 MIB.addReg(RegNo: 0)
1256 .addImm(Val: 1LL << ShAmt)
1257 .addReg(RegNo: InRegLEA, Flags: RegState::Kill)
1258 .addImm(Val: 0)
1259 .addReg(RegNo: 0);
1260 break;
1261 }
1262 CASE_NF(INC8r)
1263 CASE_NF(INC16r)
1264 addRegOffset(MIB, Reg: InRegLEA, isKill: true, Offset: 1);
1265 break;
1266 CASE_NF(DEC8r)
1267 CASE_NF(DEC16r)
1268 addRegOffset(MIB, Reg: InRegLEA, isKill: true, Offset: -1);
1269 break;
1270 CASE_NF(ADD8ri)
1271 CASE_NF(ADD16ri)
1272 case X86::ADD8ri_DB:
1273 case X86::ADD16ri_DB:
1274 addRegOffset(MIB, Reg: InRegLEA, isKill: true, Offset: MI.getOperand(i: 2).getImm());
1275 break;
1276 CASE_NF(ADD8rr)
1277 CASE_NF(ADD16rr)
1278 case X86::ADD8rr_DB:
1279 case X86::ADD16rr_DB: {
1280 Src2 = MI.getOperand(i: 2).getReg();
1281 Src2SubReg = MI.getOperand(i: 2).getSubReg();
1282 bool IsKill2 = MI.getOperand(i: 2).isKill();
1283 assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
1284 if (Src == Src2) {
1285 // ADD8rr/ADD16rr killed %reg1028, %reg1028
1286 // just a single insert_subreg.
1287 addRegReg(MIB, Reg1: InRegLEA, isKill1: true, SubReg1: X86::NoSubRegister, Reg2: InRegLEA, isKill2: false,
1288 SubReg2: X86::NoSubRegister);
1289 } else {
1290 if (Subtarget.is64Bit())
1291 InRegLEA2 = RegInfo.createVirtualRegister(RegClass: &X86::GR64_NOSPRegClass);
1292 else
1293 InRegLEA2 = RegInfo.createVirtualRegister(RegClass: &X86::GR32_NOSPRegClass);
1294 // Build and insert into an implicit UNDEF value. This is OK because
1295 // we will be shifting and then extracting the lower 8/16-bits.
1296 ImpDef2 = BuildMI(BB&: MBB, I: &*MIB, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::IMPLICIT_DEF),
1297 DestReg: InRegLEA2);
1298 InsMI2 = BuildMI(BB&: MBB, I: &*MIB, MIMD: MI.getDebugLoc(), MCID: get(Opcode: TargetOpcode::COPY))
1299 .addReg(RegNo: InRegLEA2, Flags: RegState::Define, SubReg)
1300 .addReg(RegNo: Src2, Flags: getKillRegState(B: IsKill2), SubReg: Src2SubReg);
1301 addRegReg(MIB, Reg1: InRegLEA, isKill1: true, SubReg1: X86::NoSubRegister, Reg2: InRegLEA2, isKill2: true,
1302 SubReg2: X86::NoSubRegister);
1303 }
1304 break;
1305 }
1306 }
1307
1308 MachineInstr *NewMI = MIB;
1309 MachineInstr *ExtMI =
1310 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: TargetOpcode::COPY))
1311 .addReg(RegNo: Dest, Flags: RegState::Define | getDeadRegState(B: IsDead))
1312 .addReg(RegNo: OutRegLEA, Flags: RegState::Kill, SubReg);
1313
1314 if (LIS) {
1315 LIS->InsertMachineInstrInMaps(MI&: *ImpDef);
1316 SlotIndex InsIdx = LIS->InsertMachineInstrInMaps(MI&: *InsMI);
1317 if (ImpDef2)
1318 LIS->InsertMachineInstrInMaps(MI&: *ImpDef2);
1319 SlotIndex Ins2Idx;
1320 if (InsMI2)
1321 Ins2Idx = LIS->InsertMachineInstrInMaps(MI&: *InsMI2);
1322 SlotIndex NewIdx = LIS->ReplaceMachineInstrInMaps(MI, NewMI&: *NewMI);
1323 SlotIndex ExtIdx = LIS->InsertMachineInstrInMaps(MI&: *ExtMI);
1324
1325 // Drop the dead EFLAGS def MI had; the replacement does not define EFLAGS.
1326 if (MI.definesRegister(Reg: X86::EFLAGS, TRI: &RI))
1327 LIS->removePhysRegDefAt(Reg: X86::EFLAGS, Pos: NewIdx.getRegSlot());
1328
1329 LIS->getInterval(Reg: InRegLEA);
1330 LIS->getInterval(Reg: OutRegLEA);
1331 if (InRegLEA2)
1332 LIS->getInterval(Reg: InRegLEA2);
1333
1334 // Move the use of Src up to InsMI.
1335 LiveInterval &SrcLI = LIS->getInterval(Reg: Src);
1336 LiveRange::Segment *SrcSeg = SrcLI.getSegmentContaining(Idx: NewIdx);
1337 if (SrcSeg->end == NewIdx.getRegSlot())
1338 SrcSeg->end = InsIdx.getRegSlot();
1339
1340 if (InsMI2) {
1341 // Move the use of Src2 up to InsMI2.
1342 LiveInterval &Src2LI = LIS->getInterval(Reg: Src2);
1343 LiveRange::Segment *Src2Seg = Src2LI.getSegmentContaining(Idx: NewIdx);
1344 if (Src2Seg->end == NewIdx.getRegSlot())
1345 Src2Seg->end = Ins2Idx.getRegSlot();
1346 }
1347
1348 // Move the definition of Dest down to ExtMI.
1349 LiveInterval &DestLI = LIS->getInterval(Reg: Dest);
1350 LiveRange::Segment *DestSeg =
1351 DestLI.getSegmentContaining(Idx: NewIdx.getRegSlot());
1352 assert(DestSeg->start == NewIdx.getRegSlot() &&
1353 DestSeg->valno->def == NewIdx.getRegSlot());
1354 DestSeg->start = ExtIdx.getRegSlot();
1355 DestSeg->valno->def = ExtIdx.getRegSlot();
1356 }
1357
1358 return ExtMI;
1359}
1360
1361/// This method must be implemented by targets that
1362/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1363/// may be able to convert a two-address instruction into a true
1364/// three-address instruction on demand. This allows the X86 target (for
1365/// example) to convert ADD and SHL instructions into LEA instructions if they
1366/// would require register copies due to two-addressness.
1367///
1368/// This method returns a null pointer if the transformation cannot be
1369/// performed, otherwise it returns the new instruction.
1370///
1371MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
1372 LiveIntervals *LIS) const {
1373 // The following opcodes also sets the condition code register(s). Only
1374 // convert them to equivalent lea if the condition code register def's
1375 // are dead!
1376 if (hasLiveCondCodeDef(MI))
1377 return nullptr;
1378
1379 MachineFunction &MF = *MI.getParent()->getParent();
1380 // All instructions input are two-addr instructions. Get the known operands.
1381 const MachineOperand &Dest = MI.getOperand(i: 0);
1382 const MachineOperand &Src = MI.getOperand(i: 1);
1383
1384 // Ideally, operations with undef should be folded before we get here, but we
1385 // can't guarantee it. Bail out because optimizing undefs is a waste of time.
1386 // Without this, we have to forward undef state to new register operands to
1387 // avoid machine verifier errors.
1388 if (Src.isUndef())
1389 return nullptr;
1390 if (MI.getNumOperands() > 2)
1391 if (MI.getOperand(i: 2).isReg() && MI.getOperand(i: 2).isUndef())
1392 return nullptr;
1393
1394 MachineInstr *NewMI = nullptr;
1395 Register SrcReg, SrcReg2;
1396 unsigned SrcSubReg, SrcSubReg2;
1397 bool Is64Bit = Subtarget.is64Bit();
1398
1399 bool Is8BitOp = false;
1400 unsigned MIOpc = MI.getOpcode();
1401 switch (MIOpc) {
1402 default:
1403 llvm_unreachable("Unreachable!");
1404 CASE_NF(SHL64ri) {
1405 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1406 unsigned ShAmt = getTruncatedShiftCount(MI, ShiftAmtOperandIdx: 2);
1407 if (!isTruncatedShiftCountForLEA(ShAmt))
1408 return nullptr;
1409
1410 // LEA can't handle RSP.
1411 if (Src.getReg().isVirtual() && !MF.getRegInfo().constrainRegClass(
1412 Reg: Src.getReg(), RC: &X86::GR64_NOSPRegClass))
1413 return nullptr;
1414
1415 NewMI = BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::LEA64r))
1416 .add(MO: Dest)
1417 .addReg(RegNo: 0)
1418 .addImm(Val: 1LL << ShAmt)
1419 .add(MO: Src)
1420 .addImm(Val: 0)
1421 .addReg(RegNo: 0);
1422 break;
1423 }
1424 CASE_NF(SHL32ri) {
1425 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1426 unsigned ShAmt = getTruncatedShiftCount(MI, ShiftAmtOperandIdx: 2);
1427 if (!isTruncatedShiftCountForLEA(ShAmt))
1428 return nullptr;
1429
1430 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1431
1432 // LEA can't handle ESP.
1433 bool isKill;
1434 MachineOperand ImplicitOp = MachineOperand::CreateReg(Reg: 0, isDef: false);
1435 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, NewSrc&: SrcReg, NewSrcSubReg&: SrcSubReg,
1436 isKill, ImplicitOp, LIS))
1437 return nullptr;
1438
1439 MachineInstrBuilder MIB =
1440 BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
1441 .add(MO: Dest)
1442 .addReg(RegNo: 0)
1443 .addImm(Val: 1LL << ShAmt)
1444 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill), SubReg: SrcSubReg)
1445 .addImm(Val: 0)
1446 .addReg(RegNo: 0);
1447 if (ImplicitOp.getReg() != 0)
1448 MIB.add(MO: ImplicitOp);
1449 NewMI = MIB;
1450
1451 break;
1452 }
1453 CASE_NF(SHL8ri)
1454 Is8BitOp = true;
1455 [[fallthrough]];
1456 CASE_NF(SHL16ri) {
1457 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1458 unsigned ShAmt = getTruncatedShiftCount(MI, ShiftAmtOperandIdx: 2);
1459 if (!isTruncatedShiftCountForLEA(ShAmt))
1460 return nullptr;
1461 return convertToThreeAddressWithLEA(MIOpc, MI, LIS, Is8BitOp);
1462 }
1463 CASE_NF(INC64r)
1464 CASE_NF(INC32r) {
1465 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
1466 unsigned Opc = (MIOpc == X86::INC64r || MIOpc == X86::INC64r_NF)
1467 ? X86::LEA64r
1468 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1469 bool isKill;
1470 MachineOperand ImplicitOp = MachineOperand::CreateReg(Reg: 0, isDef: false);
1471 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, NewSrc&: SrcReg, NewSrcSubReg&: SrcSubReg,
1472 isKill, ImplicitOp, LIS))
1473 return nullptr;
1474
1475 MachineInstrBuilder MIB = BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
1476 .add(MO: Dest)
1477 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill));
1478 if (ImplicitOp.getReg() != 0)
1479 MIB.add(MO: ImplicitOp);
1480
1481 NewMI = addOffset(MIB, Offset: 1);
1482
1483 break;
1484 }
1485 CASE_NF(DEC64r)
1486 CASE_NF(DEC32r) {
1487 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
1488 unsigned Opc = (MIOpc == X86::DEC64r || MIOpc == X86::DEC64r_NF)
1489 ? X86::LEA64r
1490 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1491
1492 bool isKill;
1493 MachineOperand ImplicitOp = MachineOperand::CreateReg(Reg: 0, isDef: false);
1494 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, NewSrc&: SrcReg, NewSrcSubReg&: SrcSubReg,
1495 isKill, ImplicitOp, LIS))
1496 return nullptr;
1497
1498 MachineInstrBuilder MIB = BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
1499 .add(MO: Dest)
1500 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill));
1501 if (ImplicitOp.getReg() != 0)
1502 MIB.add(MO: ImplicitOp);
1503
1504 NewMI = addOffset(MIB, Offset: -1);
1505
1506 break;
1507 }
1508 CASE_NF(DEC8r)
1509 CASE_NF(INC8r)
1510 Is8BitOp = true;
1511 [[fallthrough]];
1512 CASE_NF(DEC16r)
1513 CASE_NF(INC16r)
1514 return convertToThreeAddressWithLEA(MIOpc, MI, LIS, Is8BitOp);
1515 CASE_NF(ADD64rr)
1516 CASE_NF(ADD32rr)
1517 case X86::ADD64rr_DB:
1518 case X86::ADD32rr_DB: {
1519 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1520 unsigned Opc;
1521 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_NF ||
1522 MIOpc == X86::ADD64rr_DB)
1523 Opc = X86::LEA64r;
1524 else
1525 Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1526
1527 const MachineOperand &Src2 = MI.getOperand(i: 2);
1528 bool isKill2;
1529 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(Reg: 0, isDef: false);
1530 if (!classifyLEAReg(MI, Src: Src2, Opc, /*AllowSP=*/false, NewSrc&: SrcReg2, NewSrcSubReg&: SrcSubReg2,
1531 isKill&: isKill2, ImplicitOp&: ImplicitOp2, LIS))
1532 return nullptr;
1533
1534 bool isKill;
1535 MachineOperand ImplicitOp = MachineOperand::CreateReg(Reg: 0, isDef: false);
1536 if (Src.getReg() == Src2.getReg()) {
1537 // Don't call classify LEAReg a second time on the same register, in case
1538 // the first call inserted a COPY from Src2 and marked it as killed.
1539 isKill = isKill2;
1540 SrcReg = SrcReg2;
1541 SrcSubReg = SrcSubReg2;
1542 } else {
1543 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, NewSrc&: SrcReg, NewSrcSubReg&: SrcSubReg,
1544 isKill, ImplicitOp, LIS))
1545 return nullptr;
1546 }
1547
1548 MachineInstrBuilder MIB = BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc)).add(MO: Dest);
1549 if (ImplicitOp.getReg() != 0)
1550 MIB.add(MO: ImplicitOp);
1551 if (ImplicitOp2.getReg() != 0)
1552 MIB.add(MO: ImplicitOp2);
1553
1554 NewMI =
1555 addRegReg(MIB, Reg1: SrcReg, isKill1: isKill, SubReg1: SrcSubReg, Reg2: SrcReg2, isKill2, SubReg2: SrcSubReg2);
1556
1557 break;
1558 }
1559 CASE_NF(ADD8rr)
1560 case X86::ADD8rr_DB:
1561 Is8BitOp = true;
1562 [[fallthrough]];
1563 CASE_NF(ADD16rr)
1564 case X86::ADD16rr_DB:
1565 return convertToThreeAddressWithLEA(MIOpc, MI, LIS, Is8BitOp);
1566 CASE_NF(ADD64ri32)
1567 case X86::ADD64ri32_DB:
1568 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1569 NewMI = addOffset(
1570 MIB: BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::LEA64r)).add(MO: Dest).add(MO: Src),
1571 Offset: MI.getOperand(i: 2));
1572 break;
1573 CASE_NF(ADD32ri)
1574 case X86::ADD32ri_DB: {
1575 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1576 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1577
1578 bool isKill;
1579 MachineOperand ImplicitOp = MachineOperand::CreateReg(Reg: 0, isDef: false);
1580 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, NewSrc&: SrcReg, NewSrcSubReg&: SrcSubReg,
1581 isKill, ImplicitOp, LIS))
1582 return nullptr;
1583
1584 MachineInstrBuilder MIB =
1585 BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
1586 .add(MO: Dest)
1587 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill), SubReg: SrcSubReg);
1588 if (ImplicitOp.getReg() != 0)
1589 MIB.add(MO: ImplicitOp);
1590
1591 NewMI = addOffset(MIB, Offset: MI.getOperand(i: 2));
1592
1593 break;
1594 }
1595 CASE_NF(ADD8ri)
1596 case X86::ADD8ri_DB:
1597 Is8BitOp = true;
1598 [[fallthrough]];
1599 CASE_NF(ADD16ri)
1600 case X86::ADD16ri_DB:
1601 return convertToThreeAddressWithLEA(MIOpc, MI, LIS, Is8BitOp);
1602 CASE_NF(SUB8ri)
1603 CASE_NF(SUB16ri)
1604 /// FIXME: Support these similar to ADD8ri/ADD16ri*.
1605 return nullptr;
1606 CASE_NF(SUB32ri) {
1607 if (!MI.getOperand(i: 2).isImm())
1608 return nullptr;
1609 int64_t Imm = MI.getOperand(i: 2).getImm();
1610 if (!isInt<32>(x: -Imm))
1611 return nullptr;
1612
1613 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1614 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1615
1616 bool isKill;
1617 MachineOperand ImplicitOp = MachineOperand::CreateReg(Reg: 0, isDef: false);
1618 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, NewSrc&: SrcReg, NewSrcSubReg&: SrcSubReg,
1619 isKill, ImplicitOp, LIS))
1620 return nullptr;
1621
1622 MachineInstrBuilder MIB =
1623 BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
1624 .add(MO: Dest)
1625 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill), SubReg: SrcSubReg);
1626 if (ImplicitOp.getReg() != 0)
1627 MIB.add(MO: ImplicitOp);
1628
1629 NewMI = addOffset(MIB, Offset: -Imm);
1630
1631 break;
1632 }
1633
1634 CASE_NF(SUB64ri32) {
1635 if (!MI.getOperand(i: 2).isImm())
1636 return nullptr;
1637 int64_t Imm = MI.getOperand(i: 2).getImm();
1638 if (!isInt<32>(x: -Imm))
1639 return nullptr;
1640
1641 assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!");
1642
1643 MachineInstrBuilder MIB =
1644 BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::LEA64r)).add(MO: Dest).add(MO: Src);
1645 NewMI = addOffset(MIB, Offset: -Imm);
1646 break;
1647 }
1648
1649 case X86::VMOVDQU8Z128rmk:
1650 case X86::VMOVDQU8Z256rmk:
1651 case X86::VMOVDQU8Zrmk:
1652 case X86::VMOVDQU16Z128rmk:
1653 case X86::VMOVDQU16Z256rmk:
1654 case X86::VMOVDQU16Zrmk:
1655 case X86::VMOVDQU32Z128rmk:
1656 case X86::VMOVDQA32Z128rmk:
1657 case X86::VMOVDQU32Z256rmk:
1658 case X86::VMOVDQA32Z256rmk:
1659 case X86::VMOVDQU32Zrmk:
1660 case X86::VMOVDQA32Zrmk:
1661 case X86::VMOVDQU64Z128rmk:
1662 case X86::VMOVDQA64Z128rmk:
1663 case X86::VMOVDQU64Z256rmk:
1664 case X86::VMOVDQA64Z256rmk:
1665 case X86::VMOVDQU64Zrmk:
1666 case X86::VMOVDQA64Zrmk:
1667 case X86::VMOVUPDZ128rmk:
1668 case X86::VMOVAPDZ128rmk:
1669 case X86::VMOVUPDZ256rmk:
1670 case X86::VMOVAPDZ256rmk:
1671 case X86::VMOVUPDZrmk:
1672 case X86::VMOVAPDZrmk:
1673 case X86::VMOVUPSZ128rmk:
1674 case X86::VMOVAPSZ128rmk:
1675 case X86::VMOVUPSZ256rmk:
1676 case X86::VMOVAPSZ256rmk:
1677 case X86::VMOVUPSZrmk:
1678 case X86::VMOVAPSZrmk:
1679 case X86::VBROADCASTSDZ256rmk:
1680 case X86::VBROADCASTSDZrmk:
1681 case X86::VBROADCASTSSZ128rmk:
1682 case X86::VBROADCASTSSZ256rmk:
1683 case X86::VBROADCASTSSZrmk:
1684 case X86::VPBROADCASTDZ128rmk:
1685 case X86::VPBROADCASTDZ256rmk:
1686 case X86::VPBROADCASTDZrmk:
1687 case X86::VPBROADCASTQZ128rmk:
1688 case X86::VPBROADCASTQZ256rmk:
1689 case X86::VPBROADCASTQZrmk: {
1690 unsigned Opc;
1691 switch (MIOpc) {
1692 default:
1693 llvm_unreachable("Unreachable!");
1694 case X86::VMOVDQU8Z128rmk:
1695 Opc = X86::VPBLENDMBZ128rmk;
1696 break;
1697 case X86::VMOVDQU8Z256rmk:
1698 Opc = X86::VPBLENDMBZ256rmk;
1699 break;
1700 case X86::VMOVDQU8Zrmk:
1701 Opc = X86::VPBLENDMBZrmk;
1702 break;
1703 case X86::VMOVDQU16Z128rmk:
1704 Opc = X86::VPBLENDMWZ128rmk;
1705 break;
1706 case X86::VMOVDQU16Z256rmk:
1707 Opc = X86::VPBLENDMWZ256rmk;
1708 break;
1709 case X86::VMOVDQU16Zrmk:
1710 Opc = X86::VPBLENDMWZrmk;
1711 break;
1712 case X86::VMOVDQU32Z128rmk:
1713 Opc = X86::VPBLENDMDZ128rmk;
1714 break;
1715 case X86::VMOVDQU32Z256rmk:
1716 Opc = X86::VPBLENDMDZ256rmk;
1717 break;
1718 case X86::VMOVDQU32Zrmk:
1719 Opc = X86::VPBLENDMDZrmk;
1720 break;
1721 case X86::VMOVDQU64Z128rmk:
1722 Opc = X86::VPBLENDMQZ128rmk;
1723 break;
1724 case X86::VMOVDQU64Z256rmk:
1725 Opc = X86::VPBLENDMQZ256rmk;
1726 break;
1727 case X86::VMOVDQU64Zrmk:
1728 Opc = X86::VPBLENDMQZrmk;
1729 break;
1730 case X86::VMOVUPDZ128rmk:
1731 Opc = X86::VBLENDMPDZ128rmk;
1732 break;
1733 case X86::VMOVUPDZ256rmk:
1734 Opc = X86::VBLENDMPDZ256rmk;
1735 break;
1736 case X86::VMOVUPDZrmk:
1737 Opc = X86::VBLENDMPDZrmk;
1738 break;
1739 case X86::VMOVUPSZ128rmk:
1740 Opc = X86::VBLENDMPSZ128rmk;
1741 break;
1742 case X86::VMOVUPSZ256rmk:
1743 Opc = X86::VBLENDMPSZ256rmk;
1744 break;
1745 case X86::VMOVUPSZrmk:
1746 Opc = X86::VBLENDMPSZrmk;
1747 break;
1748 case X86::VMOVDQA32Z128rmk:
1749 Opc = X86::VPBLENDMDZ128rmk;
1750 break;
1751 case X86::VMOVDQA32Z256rmk:
1752 Opc = X86::VPBLENDMDZ256rmk;
1753 break;
1754 case X86::VMOVDQA32Zrmk:
1755 Opc = X86::VPBLENDMDZrmk;
1756 break;
1757 case X86::VMOVDQA64Z128rmk:
1758 Opc = X86::VPBLENDMQZ128rmk;
1759 break;
1760 case X86::VMOVDQA64Z256rmk:
1761 Opc = X86::VPBLENDMQZ256rmk;
1762 break;
1763 case X86::VMOVDQA64Zrmk:
1764 Opc = X86::VPBLENDMQZrmk;
1765 break;
1766 case X86::VMOVAPDZ128rmk:
1767 Opc = X86::VBLENDMPDZ128rmk;
1768 break;
1769 case X86::VMOVAPDZ256rmk:
1770 Opc = X86::VBLENDMPDZ256rmk;
1771 break;
1772 case X86::VMOVAPDZrmk:
1773 Opc = X86::VBLENDMPDZrmk;
1774 break;
1775 case X86::VMOVAPSZ128rmk:
1776 Opc = X86::VBLENDMPSZ128rmk;
1777 break;
1778 case X86::VMOVAPSZ256rmk:
1779 Opc = X86::VBLENDMPSZ256rmk;
1780 break;
1781 case X86::VMOVAPSZrmk:
1782 Opc = X86::VBLENDMPSZrmk;
1783 break;
1784 case X86::VBROADCASTSDZ256rmk:
1785 Opc = X86::VBLENDMPDZ256rmbk;
1786 break;
1787 case X86::VBROADCASTSDZrmk:
1788 Opc = X86::VBLENDMPDZrmbk;
1789 break;
1790 case X86::VBROADCASTSSZ128rmk:
1791 Opc = X86::VBLENDMPSZ128rmbk;
1792 break;
1793 case X86::VBROADCASTSSZ256rmk:
1794 Opc = X86::VBLENDMPSZ256rmbk;
1795 break;
1796 case X86::VBROADCASTSSZrmk:
1797 Opc = X86::VBLENDMPSZrmbk;
1798 break;
1799 case X86::VPBROADCASTDZ128rmk:
1800 Opc = X86::VPBLENDMDZ128rmbk;
1801 break;
1802 case X86::VPBROADCASTDZ256rmk:
1803 Opc = X86::VPBLENDMDZ256rmbk;
1804 break;
1805 case X86::VPBROADCASTDZrmk:
1806 Opc = X86::VPBLENDMDZrmbk;
1807 break;
1808 case X86::VPBROADCASTQZ128rmk:
1809 Opc = X86::VPBLENDMQZ128rmbk;
1810 break;
1811 case X86::VPBROADCASTQZ256rmk:
1812 Opc = X86::VPBLENDMQZ256rmbk;
1813 break;
1814 case X86::VPBROADCASTQZrmk:
1815 Opc = X86::VPBLENDMQZrmbk;
1816 break;
1817 }
1818
1819 NewMI = BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
1820 .add(MO: Dest)
1821 .add(MO: MI.getOperand(i: 2))
1822 .add(MO: Src)
1823 .add(MO: MI.getOperand(i: 3))
1824 .add(MO: MI.getOperand(i: 4))
1825 .add(MO: MI.getOperand(i: 5))
1826 .add(MO: MI.getOperand(i: 6))
1827 .add(MO: MI.getOperand(i: 7));
1828 break;
1829 }
1830
1831 case X86::VMOVDQU8Z128rrk:
1832 case X86::VMOVDQU8Z256rrk:
1833 case X86::VMOVDQU8Zrrk:
1834 case X86::VMOVDQU16Z128rrk:
1835 case X86::VMOVDQU16Z256rrk:
1836 case X86::VMOVDQU16Zrrk:
1837 case X86::VMOVDQU32Z128rrk:
1838 case X86::VMOVDQA32Z128rrk:
1839 case X86::VMOVDQU32Z256rrk:
1840 case X86::VMOVDQA32Z256rrk:
1841 case X86::VMOVDQU32Zrrk:
1842 case X86::VMOVDQA32Zrrk:
1843 case X86::VMOVDQU64Z128rrk:
1844 case X86::VMOVDQA64Z128rrk:
1845 case X86::VMOVDQU64Z256rrk:
1846 case X86::VMOVDQA64Z256rrk:
1847 case X86::VMOVDQU64Zrrk:
1848 case X86::VMOVDQA64Zrrk:
1849 case X86::VMOVUPDZ128rrk:
1850 case X86::VMOVAPDZ128rrk:
1851 case X86::VMOVUPDZ256rrk:
1852 case X86::VMOVAPDZ256rrk:
1853 case X86::VMOVUPDZrrk:
1854 case X86::VMOVAPDZrrk:
1855 case X86::VMOVUPSZ128rrk:
1856 case X86::VMOVAPSZ128rrk:
1857 case X86::VMOVUPSZ256rrk:
1858 case X86::VMOVAPSZ256rrk:
1859 case X86::VMOVUPSZrrk:
1860 case X86::VMOVAPSZrrk: {
1861 unsigned Opc;
1862 switch (MIOpc) {
1863 default:
1864 llvm_unreachable("Unreachable!");
1865 case X86::VMOVDQU8Z128rrk:
1866 Opc = X86::VPBLENDMBZ128rrk;
1867 break;
1868 case X86::VMOVDQU8Z256rrk:
1869 Opc = X86::VPBLENDMBZ256rrk;
1870 break;
1871 case X86::VMOVDQU8Zrrk:
1872 Opc = X86::VPBLENDMBZrrk;
1873 break;
1874 case X86::VMOVDQU16Z128rrk:
1875 Opc = X86::VPBLENDMWZ128rrk;
1876 break;
1877 case X86::VMOVDQU16Z256rrk:
1878 Opc = X86::VPBLENDMWZ256rrk;
1879 break;
1880 case X86::VMOVDQU16Zrrk:
1881 Opc = X86::VPBLENDMWZrrk;
1882 break;
1883 case X86::VMOVDQU32Z128rrk:
1884 Opc = X86::VPBLENDMDZ128rrk;
1885 break;
1886 case X86::VMOVDQU32Z256rrk:
1887 Opc = X86::VPBLENDMDZ256rrk;
1888 break;
1889 case X86::VMOVDQU32Zrrk:
1890 Opc = X86::VPBLENDMDZrrk;
1891 break;
1892 case X86::VMOVDQU64Z128rrk:
1893 Opc = X86::VPBLENDMQZ128rrk;
1894 break;
1895 case X86::VMOVDQU64Z256rrk:
1896 Opc = X86::VPBLENDMQZ256rrk;
1897 break;
1898 case X86::VMOVDQU64Zrrk:
1899 Opc = X86::VPBLENDMQZrrk;
1900 break;
1901 case X86::VMOVUPDZ128rrk:
1902 Opc = X86::VBLENDMPDZ128rrk;
1903 break;
1904 case X86::VMOVUPDZ256rrk:
1905 Opc = X86::VBLENDMPDZ256rrk;
1906 break;
1907 case X86::VMOVUPDZrrk:
1908 Opc = X86::VBLENDMPDZrrk;
1909 break;
1910 case X86::VMOVUPSZ128rrk:
1911 Opc = X86::VBLENDMPSZ128rrk;
1912 break;
1913 case X86::VMOVUPSZ256rrk:
1914 Opc = X86::VBLENDMPSZ256rrk;
1915 break;
1916 case X86::VMOVUPSZrrk:
1917 Opc = X86::VBLENDMPSZrrk;
1918 break;
1919 case X86::VMOVDQA32Z128rrk:
1920 Opc = X86::VPBLENDMDZ128rrk;
1921 break;
1922 case X86::VMOVDQA32Z256rrk:
1923 Opc = X86::VPBLENDMDZ256rrk;
1924 break;
1925 case X86::VMOVDQA32Zrrk:
1926 Opc = X86::VPBLENDMDZrrk;
1927 break;
1928 case X86::VMOVDQA64Z128rrk:
1929 Opc = X86::VPBLENDMQZ128rrk;
1930 break;
1931 case X86::VMOVDQA64Z256rrk:
1932 Opc = X86::VPBLENDMQZ256rrk;
1933 break;
1934 case X86::VMOVDQA64Zrrk:
1935 Opc = X86::VPBLENDMQZrrk;
1936 break;
1937 case X86::VMOVAPDZ128rrk:
1938 Opc = X86::VBLENDMPDZ128rrk;
1939 break;
1940 case X86::VMOVAPDZ256rrk:
1941 Opc = X86::VBLENDMPDZ256rrk;
1942 break;
1943 case X86::VMOVAPDZrrk:
1944 Opc = X86::VBLENDMPDZrrk;
1945 break;
1946 case X86::VMOVAPSZ128rrk:
1947 Opc = X86::VBLENDMPSZ128rrk;
1948 break;
1949 case X86::VMOVAPSZ256rrk:
1950 Opc = X86::VBLENDMPSZ256rrk;
1951 break;
1952 case X86::VMOVAPSZrrk:
1953 Opc = X86::VBLENDMPSZrrk;
1954 break;
1955 }
1956
1957 NewMI = BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc))
1958 .add(MO: Dest)
1959 .add(MO: MI.getOperand(i: 2))
1960 .add(MO: Src)
1961 .add(MO: MI.getOperand(i: 3));
1962 break;
1963 }
1964 }
1965#undef CASE_NF
1966
1967 if (!NewMI)
1968 return nullptr;
1969
1970 MachineBasicBlock &MBB = *MI.getParent();
1971 MBB.insert(I: MI.getIterator(), M: NewMI); // Insert the new inst
1972
1973 if (LIS) {
1974 // The replacement does not define EFLAGS; drop the dead EFLAGS def MI had.
1975 SlotIndex Idx = LIS->getInstructionIndex(Instr: MI);
1976 LIS->ReplaceMachineInstrInMaps(MI, NewMI&: *NewMI);
1977
1978 if (MI.definesRegister(Reg: X86::EFLAGS, TRI: &RI))
1979 LIS->removePhysRegDefAt(Reg: X86::EFLAGS, Pos: Idx.getRegSlot());
1980 if (SrcReg)
1981 LIS->getInterval(Reg: SrcReg);
1982 if (SrcReg2)
1983 LIS->getInterval(Reg: SrcReg2);
1984 }
1985
1986 return NewMI;
1987}
1988
1989/// This determines which of three possible cases of a three source commute
1990/// the source indexes correspond to taking into account any mask operands.
1991/// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1992/// possible.
1993/// Case 0 - Possible to commute the first and second operands.
1994/// Case 1 - Possible to commute the first and third operands.
1995/// Case 2 - Possible to commute the second and third operands.
1996static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1997 unsigned SrcOpIdx2) {
1998 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1999 if (SrcOpIdx1 > SrcOpIdx2)
2000 std::swap(a&: SrcOpIdx1, b&: SrcOpIdx2);
2001
2002 unsigned Op1 = 1, Op2 = 2, Op3 = 3;
2003 if (X86II::isKMasked(TSFlags)) {
2004 Op2++;
2005 Op3++;
2006 }
2007
2008 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
2009 return 0;
2010 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
2011 return 1;
2012 if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
2013 return 2;
2014 llvm_unreachable("Unknown three src commute case.");
2015}
2016
2017unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
2018 const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
2019 const X86InstrFMA3Group &FMA3Group) const {
2020
2021 unsigned Opc = MI.getOpcode();
2022
2023 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
2024 // analysis. The commute optimization is legal only if all users of FMA*_Int
2025 // use only the lowest element of the FMA*_Int instruction. Such analysis are
2026 // not implemented yet. So, just return 0 in that case.
2027 // When such analysis are available this place will be the right place for
2028 // calling it.
2029 assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
2030 "Intrinsic instructions can't commute operand 1");
2031
2032 // Determine which case this commute is or if it can't be done.
2033 unsigned Case =
2034 getThreeSrcCommuteCase(TSFlags: MI.getDesc().TSFlags, SrcOpIdx1, SrcOpIdx2);
2035 assert(Case < 3 && "Unexpected case number!");
2036
2037 // Define the FMA forms mapping array that helps to map input FMA form
2038 // to output FMA form to preserve the operation semantics after
2039 // commuting the operands.
2040 const unsigned Form132Index = 0;
2041 const unsigned Form213Index = 1;
2042 const unsigned Form231Index = 2;
2043 static const unsigned FormMapping[][3] = {
2044 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
2045 // FMA132 A, C, b; ==> FMA231 C, A, b;
2046 // FMA213 B, A, c; ==> FMA213 A, B, c;
2047 // FMA231 C, A, b; ==> FMA132 A, C, b;
2048 {Form231Index, Form213Index, Form132Index},
2049 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
2050 // FMA132 A, c, B; ==> FMA132 B, c, A;
2051 // FMA213 B, a, C; ==> FMA231 C, a, B;
2052 // FMA231 C, a, B; ==> FMA213 B, a, C;
2053 {Form132Index, Form231Index, Form213Index},
2054 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
2055 // FMA132 a, C, B; ==> FMA213 a, B, C;
2056 // FMA213 b, A, C; ==> FMA132 b, C, A;
2057 // FMA231 c, A, B; ==> FMA231 c, B, A;
2058 {Form213Index, Form132Index, Form231Index}};
2059
2060 unsigned FMAForms[3];
2061 FMAForms[0] = FMA3Group.get132Opcode();
2062 FMAForms[1] = FMA3Group.get213Opcode();
2063 FMAForms[2] = FMA3Group.get231Opcode();
2064
2065 // Everything is ready, just adjust the FMA opcode and return it.
2066 for (unsigned FormIndex = 0; FormIndex < 3; FormIndex++)
2067 if (Opc == FMAForms[FormIndex])
2068 return FMAForms[FormMapping[Case][FormIndex]];
2069
2070 llvm_unreachable("Illegal FMA3 format");
2071}
2072
2073static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
2074 unsigned SrcOpIdx2) {
2075 // Determine which case this commute is or if it can't be done.
2076 unsigned Case =
2077 getThreeSrcCommuteCase(TSFlags: MI.getDesc().TSFlags, SrcOpIdx1, SrcOpIdx2);
2078 assert(Case < 3 && "Unexpected case value!");
2079
2080 // For each case we need to swap two pairs of bits in the final immediate.
2081 static const uint8_t SwapMasks[3][4] = {
2082 {0x04, 0x10, 0x08, 0x20}, // Swap bits 2/4 and 3/5.
2083 {0x02, 0x10, 0x08, 0x40}, // Swap bits 1/4 and 3/6.
2084 {0x02, 0x04, 0x20, 0x40}, // Swap bits 1/2 and 5/6.
2085 };
2086
2087 uint8_t Imm = MI.getOperand(i: MI.getNumOperands() - 1).getImm();
2088 // Clear out the bits we are swapping.
2089 uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
2090 SwapMasks[Case][2] | SwapMasks[Case][3]);
2091 // If the immediate had a bit of the pair set, then set the opposite bit.
2092 if (Imm & SwapMasks[Case][0])
2093 NewImm |= SwapMasks[Case][1];
2094 if (Imm & SwapMasks[Case][1])
2095 NewImm |= SwapMasks[Case][0];
2096 if (Imm & SwapMasks[Case][2])
2097 NewImm |= SwapMasks[Case][3];
2098 if (Imm & SwapMasks[Case][3])
2099 NewImm |= SwapMasks[Case][2];
2100 MI.getOperand(i: MI.getNumOperands() - 1).setImm(NewImm);
2101}
2102
2103// Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
2104// commuted.
2105static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
2106#define VPERM_CASES(Suffix) \
2107 case X86::VPERMI2##Suffix##Z128rr: \
2108 case X86::VPERMT2##Suffix##Z128rr: \
2109 case X86::VPERMI2##Suffix##Z256rr: \
2110 case X86::VPERMT2##Suffix##Z256rr: \
2111 case X86::VPERMI2##Suffix##Zrr: \
2112 case X86::VPERMT2##Suffix##Zrr: \
2113 case X86::VPERMI2##Suffix##Z128rm: \
2114 case X86::VPERMT2##Suffix##Z128rm: \
2115 case X86::VPERMI2##Suffix##Z256rm: \
2116 case X86::VPERMT2##Suffix##Z256rm: \
2117 case X86::VPERMI2##Suffix##Zrm: \
2118 case X86::VPERMT2##Suffix##Zrm: \
2119 case X86::VPERMI2##Suffix##Z128rrkz: \
2120 case X86::VPERMT2##Suffix##Z128rrkz: \
2121 case X86::VPERMI2##Suffix##Z256rrkz: \
2122 case X86::VPERMT2##Suffix##Z256rrkz: \
2123 case X86::VPERMI2##Suffix##Zrrkz: \
2124 case X86::VPERMT2##Suffix##Zrrkz: \
2125 case X86::VPERMI2##Suffix##Z128rmkz: \
2126 case X86::VPERMT2##Suffix##Z128rmkz: \
2127 case X86::VPERMI2##Suffix##Z256rmkz: \
2128 case X86::VPERMT2##Suffix##Z256rmkz: \
2129 case X86::VPERMI2##Suffix##Zrmkz: \
2130 case X86::VPERMT2##Suffix##Zrmkz:
2131
2132#define VPERM_CASES_BROADCAST(Suffix) \
2133 VPERM_CASES(Suffix) \
2134 case X86::VPERMI2##Suffix##Z128rmb: \
2135 case X86::VPERMT2##Suffix##Z128rmb: \
2136 case X86::VPERMI2##Suffix##Z256rmb: \
2137 case X86::VPERMT2##Suffix##Z256rmb: \
2138 case X86::VPERMI2##Suffix##Zrmb: \
2139 case X86::VPERMT2##Suffix##Zrmb: \
2140 case X86::VPERMI2##Suffix##Z128rmbkz: \
2141 case X86::VPERMT2##Suffix##Z128rmbkz: \
2142 case X86::VPERMI2##Suffix##Z256rmbkz: \
2143 case X86::VPERMT2##Suffix##Z256rmbkz: \
2144 case X86::VPERMI2##Suffix##Zrmbkz: \
2145 case X86::VPERMT2##Suffix##Zrmbkz:
2146
2147 switch (Opcode) {
2148 default:
2149 return false;
2150 VPERM_CASES(B)
2151 VPERM_CASES_BROADCAST(D)
2152 VPERM_CASES_BROADCAST(PD)
2153 VPERM_CASES_BROADCAST(PS)
2154 VPERM_CASES_BROADCAST(Q)
2155 VPERM_CASES(W)
2156 return true;
2157 }
2158#undef VPERM_CASES_BROADCAST
2159#undef VPERM_CASES
2160}
2161
2162// Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
2163// from the I opcode to the T opcode and vice versa.
2164static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
2165#define VPERM_CASES(Orig, New) \
2166 case X86::Orig##Z128rr: \
2167 return X86::New##Z128rr; \
2168 case X86::Orig##Z128rrkz: \
2169 return X86::New##Z128rrkz; \
2170 case X86::Orig##Z128rm: \
2171 return X86::New##Z128rm; \
2172 case X86::Orig##Z128rmkz: \
2173 return X86::New##Z128rmkz; \
2174 case X86::Orig##Z256rr: \
2175 return X86::New##Z256rr; \
2176 case X86::Orig##Z256rrkz: \
2177 return X86::New##Z256rrkz; \
2178 case X86::Orig##Z256rm: \
2179 return X86::New##Z256rm; \
2180 case X86::Orig##Z256rmkz: \
2181 return X86::New##Z256rmkz; \
2182 case X86::Orig##Zrr: \
2183 return X86::New##Zrr; \
2184 case X86::Orig##Zrrkz: \
2185 return X86::New##Zrrkz; \
2186 case X86::Orig##Zrm: \
2187 return X86::New##Zrm; \
2188 case X86::Orig##Zrmkz: \
2189 return X86::New##Zrmkz;
2190
2191#define VPERM_CASES_BROADCAST(Orig, New) \
2192 VPERM_CASES(Orig, New) \
2193 case X86::Orig##Z128rmb: \
2194 return X86::New##Z128rmb; \
2195 case X86::Orig##Z128rmbkz: \
2196 return X86::New##Z128rmbkz; \
2197 case X86::Orig##Z256rmb: \
2198 return X86::New##Z256rmb; \
2199 case X86::Orig##Z256rmbkz: \
2200 return X86::New##Z256rmbkz; \
2201 case X86::Orig##Zrmb: \
2202 return X86::New##Zrmb; \
2203 case X86::Orig##Zrmbkz: \
2204 return X86::New##Zrmbkz;
2205
2206 switch (Opcode) {
2207 VPERM_CASES(VPERMI2B, VPERMT2B)
2208 VPERM_CASES_BROADCAST(VPERMI2D, VPERMT2D)
2209 VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
2210 VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
2211 VPERM_CASES_BROADCAST(VPERMI2Q, VPERMT2Q)
2212 VPERM_CASES(VPERMI2W, VPERMT2W)
2213 VPERM_CASES(VPERMT2B, VPERMI2B)
2214 VPERM_CASES_BROADCAST(VPERMT2D, VPERMI2D)
2215 VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
2216 VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
2217 VPERM_CASES_BROADCAST(VPERMT2Q, VPERMI2Q)
2218 VPERM_CASES(VPERMT2W, VPERMI2W)
2219 }
2220
2221 llvm_unreachable("Unreachable!");
2222#undef VPERM_CASES_BROADCAST
2223#undef VPERM_CASES
2224}
2225
2226MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
2227 unsigned OpIdx1,
2228 unsigned OpIdx2) const {
2229 auto CloneIfNew = [&](MachineInstr &MI) {
2230 return std::exchange(obj&: NewMI, new_val: false)
2231 ? MI.getParent()->getParent()->CloneMachineInstr(Orig: &MI)
2232 : &MI;
2233 };
2234 MachineInstr *WorkingMI = nullptr;
2235 unsigned Opc = MI.getOpcode();
2236
2237#define CASE_ND(OP) \
2238 case X86::OP: \
2239 case X86::OP##_ND:
2240
2241 switch (Opc) {
2242 // SHLD B, C, I <-> SHRD C, B, (BitWidth - I)
2243 CASE_ND(SHRD16rri8)
2244 CASE_ND(SHLD16rri8)
2245 CASE_ND(SHRD32rri8)
2246 CASE_ND(SHLD32rri8)
2247 CASE_ND(SHRD64rri8)
2248 CASE_ND(SHLD64rri8) {
2249 unsigned Size;
2250 switch (Opc) {
2251 default:
2252 llvm_unreachable("Unreachable!");
2253#define FROM_TO_SIZE(A, B, S) \
2254 case X86::A: \
2255 Opc = X86::B; \
2256 Size = S; \
2257 break; \
2258 case X86::A##_ND: \
2259 Opc = X86::B##_ND; \
2260 Size = S; \
2261 break; \
2262 case X86::B: \
2263 Opc = X86::A; \
2264 Size = S; \
2265 break; \
2266 case X86::B##_ND: \
2267 Opc = X86::A##_ND; \
2268 Size = S; \
2269 break;
2270
2271 FROM_TO_SIZE(SHRD16rri8, SHLD16rri8, 16)
2272 FROM_TO_SIZE(SHRD32rri8, SHLD32rri8, 32)
2273 FROM_TO_SIZE(SHRD64rri8, SHLD64rri8, 64)
2274#undef FROM_TO_SIZE
2275 }
2276 WorkingMI = CloneIfNew(MI);
2277 WorkingMI->setDesc(get(Opcode: Opc));
2278 WorkingMI->getOperand(i: 3).setImm(Size - MI.getOperand(i: 3).getImm());
2279 break;
2280 }
2281 case X86::PFSUBrr:
2282 case X86::PFSUBRrr:
2283 // PFSUB x, y: x = x - y
2284 // PFSUBR x, y: x = y - x
2285 WorkingMI = CloneIfNew(MI);
2286 WorkingMI->setDesc(
2287 get(Opcode: X86::PFSUBRrr == Opc ? X86::PFSUBrr : X86::PFSUBRrr));
2288 break;
2289 case X86::BLENDPDrri:
2290 case X86::BLENDPSrri:
2291 case X86::PBLENDWrri:
2292 case X86::VBLENDPDrri:
2293 case X86::VBLENDPSrri:
2294 case X86::VBLENDPDYrri:
2295 case X86::VBLENDPSYrri:
2296 case X86::VPBLENDDrri:
2297 case X86::VPBLENDWrri:
2298 case X86::VPBLENDDYrri:
2299 case X86::VPBLENDWYrri: {
2300 int8_t Mask;
2301 switch (Opc) {
2302 default:
2303 llvm_unreachable("Unreachable!");
2304 case X86::BLENDPDrri:
2305 Mask = (int8_t)0x03;
2306 break;
2307 case X86::BLENDPSrri:
2308 Mask = (int8_t)0x0F;
2309 break;
2310 case X86::PBLENDWrri:
2311 Mask = (int8_t)0xFF;
2312 break;
2313 case X86::VBLENDPDrri:
2314 Mask = (int8_t)0x03;
2315 break;
2316 case X86::VBLENDPSrri:
2317 Mask = (int8_t)0x0F;
2318 break;
2319 case X86::VBLENDPDYrri:
2320 Mask = (int8_t)0x0F;
2321 break;
2322 case X86::VBLENDPSYrri:
2323 Mask = (int8_t)0xFF;
2324 break;
2325 case X86::VPBLENDDrri:
2326 Mask = (int8_t)0x0F;
2327 break;
2328 case X86::VPBLENDWrri:
2329 Mask = (int8_t)0xFF;
2330 break;
2331 case X86::VPBLENDDYrri:
2332 Mask = (int8_t)0xFF;
2333 break;
2334 case X86::VPBLENDWYrri:
2335 Mask = (int8_t)0xFF;
2336 break;
2337 }
2338 // Only the least significant bits of Imm are used.
2339 // Using int8_t to ensure it will be sign extended to the int64_t that
2340 // setImm takes in order to match isel behavior.
2341 int8_t Imm = MI.getOperand(i: 3).getImm() & Mask;
2342 WorkingMI = CloneIfNew(MI);
2343 WorkingMI->getOperand(i: 3).setImm(Mask ^ Imm);
2344 break;
2345 }
2346 case X86::INSERTPSrri:
2347 case X86::VINSERTPSrri:
2348 case X86::VINSERTPSZrri: {
2349 unsigned Imm = MI.getOperand(i: MI.getNumOperands() - 1).getImm();
2350 unsigned ZMask = Imm & 15;
2351 unsigned DstIdx = (Imm >> 4) & 3;
2352 unsigned SrcIdx = (Imm >> 6) & 3;
2353
2354 // We can commute insertps if we zero 2 of the elements, the insertion is
2355 // "inline" and we don't override the insertion with a zero.
2356 if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
2357 llvm::popcount(Value: ZMask) == 2) {
2358 unsigned AltIdx = llvm::countr_zero(Val: (ZMask | (1 << DstIdx)) ^ 15);
2359 assert(AltIdx < 4 && "Illegal insertion index");
2360 unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
2361 WorkingMI = CloneIfNew(MI);
2362 WorkingMI->getOperand(i: MI.getNumOperands() - 1).setImm(AltImm);
2363 break;
2364 }
2365 return nullptr;
2366 }
2367 case X86::MOVSDrr:
2368 case X86::MOVSSrr:
2369 case X86::VMOVSDrr:
2370 case X86::VMOVSSrr: {
2371 // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
2372 if (Subtarget.hasSSE41()) {
2373 unsigned Mask;
2374 switch (Opc) {
2375 default:
2376 llvm_unreachable("Unreachable!");
2377 case X86::MOVSDrr:
2378 Opc = X86::BLENDPDrri;
2379 Mask = 0x02;
2380 break;
2381 case X86::MOVSSrr:
2382 Opc = X86::BLENDPSrri;
2383 Mask = 0x0E;
2384 break;
2385 case X86::VMOVSDrr:
2386 Opc = X86::VBLENDPDrri;
2387 Mask = 0x02;
2388 break;
2389 case X86::VMOVSSrr:
2390 Opc = X86::VBLENDPSrri;
2391 Mask = 0x0E;
2392 break;
2393 }
2394
2395 WorkingMI = CloneIfNew(MI);
2396 WorkingMI->setDesc(get(Opcode: Opc));
2397 WorkingMI->addOperand(Op: MachineOperand::CreateImm(Val: Mask));
2398 break;
2399 }
2400
2401 assert(Opc == X86::MOVSDrr && "Only MOVSD can commute to SHUFPD");
2402 WorkingMI = CloneIfNew(MI);
2403 WorkingMI->setDesc(get(Opcode: X86::SHUFPDrri));
2404 WorkingMI->addOperand(Op: MachineOperand::CreateImm(Val: 0x02));
2405 break;
2406 }
2407 case X86::SHUFPDrri: {
2408 // Commute to MOVSD.
2409 assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!");
2410 WorkingMI = CloneIfNew(MI);
2411 WorkingMI->setDesc(get(Opcode: X86::MOVSDrr));
2412 WorkingMI->removeOperand(OpNo: 3);
2413 break;
2414 }
2415 case X86::PCLMULQDQrri:
2416 case X86::VPCLMULQDQrri:
2417 case X86::VPCLMULQDQYrri:
2418 case X86::VPCLMULQDQZrri:
2419 case X86::VPCLMULQDQZ128rri:
2420 case X86::VPCLMULQDQZ256rri: {
2421 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2422 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2423 unsigned Imm = MI.getOperand(i: 3).getImm();
2424 unsigned Src1Hi = Imm & 0x01;
2425 unsigned Src2Hi = Imm & 0x10;
2426 WorkingMI = CloneIfNew(MI);
2427 WorkingMI->getOperand(i: 3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
2428 break;
2429 }
2430 case X86::VPCMPBZ128rri:
2431 case X86::VPCMPUBZ128rri:
2432 case X86::VPCMPBZ256rri:
2433 case X86::VPCMPUBZ256rri:
2434 case X86::VPCMPBZrri:
2435 case X86::VPCMPUBZrri:
2436 case X86::VPCMPDZ128rri:
2437 case X86::VPCMPUDZ128rri:
2438 case X86::VPCMPDZ256rri:
2439 case X86::VPCMPUDZ256rri:
2440 case X86::VPCMPDZrri:
2441 case X86::VPCMPUDZrri:
2442 case X86::VPCMPQZ128rri:
2443 case X86::VPCMPUQZ128rri:
2444 case X86::VPCMPQZ256rri:
2445 case X86::VPCMPUQZ256rri:
2446 case X86::VPCMPQZrri:
2447 case X86::VPCMPUQZrri:
2448 case X86::VPCMPWZ128rri:
2449 case X86::VPCMPUWZ128rri:
2450 case X86::VPCMPWZ256rri:
2451 case X86::VPCMPUWZ256rri:
2452 case X86::VPCMPWZrri:
2453 case X86::VPCMPUWZrri:
2454 case X86::VPCMPBZ128rrik:
2455 case X86::VPCMPUBZ128rrik:
2456 case X86::VPCMPBZ256rrik:
2457 case X86::VPCMPUBZ256rrik:
2458 case X86::VPCMPBZrrik:
2459 case X86::VPCMPUBZrrik:
2460 case X86::VPCMPDZ128rrik:
2461 case X86::VPCMPUDZ128rrik:
2462 case X86::VPCMPDZ256rrik:
2463 case X86::VPCMPUDZ256rrik:
2464 case X86::VPCMPDZrrik:
2465 case X86::VPCMPUDZrrik:
2466 case X86::VPCMPQZ128rrik:
2467 case X86::VPCMPUQZ128rrik:
2468 case X86::VPCMPQZ256rrik:
2469 case X86::VPCMPUQZ256rrik:
2470 case X86::VPCMPQZrrik:
2471 case X86::VPCMPUQZrrik:
2472 case X86::VPCMPWZ128rrik:
2473 case X86::VPCMPUWZ128rrik:
2474 case X86::VPCMPWZ256rrik:
2475 case X86::VPCMPUWZ256rrik:
2476 case X86::VPCMPWZrrik:
2477 case X86::VPCMPUWZrrik:
2478 WorkingMI = CloneIfNew(MI);
2479 // Flip comparison mode immediate (if necessary).
2480 WorkingMI->getOperand(i: MI.getNumOperands() - 1)
2481 .setImm(X86::getSwappedVPCMPImm(
2482 Imm: MI.getOperand(i: MI.getNumOperands() - 1).getImm() & 0x7));
2483 break;
2484 case X86::VPCOMBri:
2485 case X86::VPCOMUBri:
2486 case X86::VPCOMDri:
2487 case X86::VPCOMUDri:
2488 case X86::VPCOMQri:
2489 case X86::VPCOMUQri:
2490 case X86::VPCOMWri:
2491 case X86::VPCOMUWri:
2492 WorkingMI = CloneIfNew(MI);
2493 // Flip comparison mode immediate (if necessary).
2494 WorkingMI->getOperand(i: 3).setImm(
2495 X86::getSwappedVPCOMImm(Imm: MI.getOperand(i: 3).getImm() & 0x7));
2496 break;
2497 case X86::VCMPSDZrri:
2498 case X86::VCMPSSZrri:
2499 case X86::VCMPPDZrri:
2500 case X86::VCMPPSZrri:
2501 case X86::VCMPSHZrri:
2502 case X86::VCMPPHZrri:
2503 case X86::VCMPPHZ128rri:
2504 case X86::VCMPPHZ256rri:
2505 case X86::VCMPPDZ128rri:
2506 case X86::VCMPPSZ128rri:
2507 case X86::VCMPPDZ256rri:
2508 case X86::VCMPPSZ256rri:
2509 case X86::VCMPPDZrrik:
2510 case X86::VCMPPSZrrik:
2511 case X86::VCMPPHZrrik:
2512 case X86::VCMPPDZ128rrik:
2513 case X86::VCMPPSZ128rrik:
2514 case X86::VCMPPHZ128rrik:
2515 case X86::VCMPPDZ256rrik:
2516 case X86::VCMPPSZ256rrik:
2517 case X86::VCMPPHZ256rrik:
2518 WorkingMI = CloneIfNew(MI);
2519 WorkingMI->getOperand(i: MI.getNumExplicitOperands() - 1)
2520 .setImm(X86::getSwappedVCMPImm(
2521 Imm: MI.getOperand(i: MI.getNumExplicitOperands() - 1).getImm() & 0x1f));
2522 break;
2523 case X86::VPERM2F128rri:
2524 case X86::VPERM2I128rri:
2525 // Flip permute source immediate.
2526 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
2527 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
2528 WorkingMI = CloneIfNew(MI);
2529 WorkingMI->getOperand(i: 3).setImm((MI.getOperand(i: 3).getImm() & 0xFF) ^ 0x22);
2530 break;
2531 case X86::MOVHLPSrr:
2532 case X86::UNPCKHPDrr:
2533 case X86::VMOVHLPSrr:
2534 case X86::VUNPCKHPDrr:
2535 case X86::VMOVHLPSZrr:
2536 case X86::VUNPCKHPDZ128rr:
2537 assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
2538
2539 switch (Opc) {
2540 default:
2541 llvm_unreachable("Unreachable!");
2542 case X86::MOVHLPSrr:
2543 Opc = X86::UNPCKHPDrr;
2544 break;
2545 case X86::UNPCKHPDrr:
2546 Opc = X86::MOVHLPSrr;
2547 break;
2548 case X86::VMOVHLPSrr:
2549 Opc = X86::VUNPCKHPDrr;
2550 break;
2551 case X86::VUNPCKHPDrr:
2552 Opc = X86::VMOVHLPSrr;
2553 break;
2554 case X86::VMOVHLPSZrr:
2555 Opc = X86::VUNPCKHPDZ128rr;
2556 break;
2557 case X86::VUNPCKHPDZ128rr:
2558 Opc = X86::VMOVHLPSZrr;
2559 break;
2560 }
2561 WorkingMI = CloneIfNew(MI);
2562 WorkingMI->setDesc(get(Opcode: Opc));
2563 break;
2564 CASE_ND(CMOV16rr)
2565 CASE_ND(CMOV32rr)
2566 CASE_ND(CMOV64rr) {
2567 WorkingMI = CloneIfNew(MI);
2568 unsigned OpNo = MI.getDesc().getNumOperands() - 1;
2569 X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(i: OpNo).getImm());
2570 WorkingMI->getOperand(i: OpNo).setImm(X86::GetOppositeBranchCondition(CC));
2571 break;
2572 }
2573 case X86::VPTERNLOGDZrri:
2574 case X86::VPTERNLOGDZrmi:
2575 case X86::VPTERNLOGDZ128rri:
2576 case X86::VPTERNLOGDZ128rmi:
2577 case X86::VPTERNLOGDZ256rri:
2578 case X86::VPTERNLOGDZ256rmi:
2579 case X86::VPTERNLOGQZrri:
2580 case X86::VPTERNLOGQZrmi:
2581 case X86::VPTERNLOGQZ128rri:
2582 case X86::VPTERNLOGQZ128rmi:
2583 case X86::VPTERNLOGQZ256rri:
2584 case X86::VPTERNLOGQZ256rmi:
2585 case X86::VPTERNLOGDZrrik:
2586 case X86::VPTERNLOGDZ128rrik:
2587 case X86::VPTERNLOGDZ256rrik:
2588 case X86::VPTERNLOGQZrrik:
2589 case X86::VPTERNLOGQZ128rrik:
2590 case X86::VPTERNLOGQZ256rrik:
2591 case X86::VPTERNLOGDZrrikz:
2592 case X86::VPTERNLOGDZrmikz:
2593 case X86::VPTERNLOGDZ128rrikz:
2594 case X86::VPTERNLOGDZ128rmikz:
2595 case X86::VPTERNLOGDZ256rrikz:
2596 case X86::VPTERNLOGDZ256rmikz:
2597 case X86::VPTERNLOGQZrrikz:
2598 case X86::VPTERNLOGQZrmikz:
2599 case X86::VPTERNLOGQZ128rrikz:
2600 case X86::VPTERNLOGQZ128rmikz:
2601 case X86::VPTERNLOGQZ256rrikz:
2602 case X86::VPTERNLOGQZ256rmikz:
2603 case X86::VPTERNLOGDZ128rmbi:
2604 case X86::VPTERNLOGDZ256rmbi:
2605 case X86::VPTERNLOGDZrmbi:
2606 case X86::VPTERNLOGQZ128rmbi:
2607 case X86::VPTERNLOGQZ256rmbi:
2608 case X86::VPTERNLOGQZrmbi:
2609 case X86::VPTERNLOGDZ128rmbikz:
2610 case X86::VPTERNLOGDZ256rmbikz:
2611 case X86::VPTERNLOGDZrmbikz:
2612 case X86::VPTERNLOGQZ128rmbikz:
2613 case X86::VPTERNLOGQZ256rmbikz:
2614 case X86::VPTERNLOGQZrmbikz: {
2615 WorkingMI = CloneIfNew(MI);
2616 commuteVPTERNLOG(MI&: *WorkingMI, SrcOpIdx1: OpIdx1, SrcOpIdx2: OpIdx2);
2617 break;
2618 }
2619 default:
2620 if (isCommutableVPERMV3Instruction(Opcode: Opc)) {
2621 WorkingMI = CloneIfNew(MI);
2622 WorkingMI->setDesc(get(Opcode: getCommutedVPERMV3Opcode(Opcode: Opc)));
2623 break;
2624 }
2625
2626 if (auto *FMA3Group = getFMA3Group(Opcode: Opc, TSFlags: MI.getDesc().TSFlags)) {
2627 WorkingMI = CloneIfNew(MI);
2628 WorkingMI->setDesc(
2629 get(Opcode: getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1: OpIdx1, SrcOpIdx2: OpIdx2, FMA3Group: *FMA3Group)));
2630 break;
2631 }
2632 }
2633 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2634}
2635
2636bool X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
2637 unsigned &SrcOpIdx1,
2638 unsigned &SrcOpIdx2,
2639 bool IsIntrinsic) const {
2640 uint64_t TSFlags = MI.getDesc().TSFlags;
2641
2642 unsigned FirstCommutableVecOp = 1;
2643 unsigned LastCommutableVecOp = 3;
2644 unsigned KMaskOp = -1U;
2645 if (X86II::isKMasked(TSFlags)) {
2646 // For k-zero-masked operations it is Ok to commute the first vector
2647 // operand. Unless this is an intrinsic instruction.
2648 // For regular k-masked operations a conservative choice is done as the
2649 // elements of the first vector operand, for which the corresponding bit
2650 // in the k-mask operand is set to 0, are copied to the result of the
2651 // instruction.
2652 // TODO/FIXME: The commute still may be legal if it is known that the
2653 // k-mask operand is set to either all ones or all zeroes.
2654 // It is also Ok to commute the 1st operand if all users of MI use only
2655 // the elements enabled by the k-mask operand. For example,
2656 // v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
2657 // : v1[i];
2658 // VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
2659 // // Ok, to commute v1 in FMADD213PSZrk.
2660
2661 // The k-mask operand has index = 2 for masked and zero-masked operations.
2662 KMaskOp = 2;
2663
2664 // The operand with index = 1 is used as a source for those elements for
2665 // which the corresponding bit in the k-mask is set to 0.
2666 if (X86II::isKMergeMasked(TSFlags) || IsIntrinsic)
2667 FirstCommutableVecOp = 3;
2668
2669 LastCommutableVecOp++;
2670 } else if (IsIntrinsic) {
2671 // Commuting the first operand of an intrinsic instruction isn't possible
2672 // unless we can prove that only the lowest element of the result is used.
2673 FirstCommutableVecOp = 2;
2674 }
2675
2676 if (isMem(MI, Op: LastCommutableVecOp))
2677 LastCommutableVecOp--;
2678
2679 // Only the first RegOpsNum operands are commutable.
2680 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
2681 // that the operand is not specified/fixed.
2682 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
2683 (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
2684 SrcOpIdx1 == KMaskOp))
2685 return false;
2686 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
2687 (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
2688 SrcOpIdx2 == KMaskOp))
2689 return false;
2690
2691 // Look for two different register operands assumed to be commutable
2692 // regardless of the FMA opcode. The FMA opcode is adjusted later.
2693 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
2694 SrcOpIdx2 == CommuteAnyOperandIndex) {
2695 unsigned CommutableOpIdx2 = SrcOpIdx2;
2696
2697 // At least one of operands to be commuted is not specified and
2698 // this method is free to choose appropriate commutable operands.
2699 if (SrcOpIdx1 == SrcOpIdx2)
2700 // Both of operands are not fixed. By default set one of commutable
2701 // operands to the last register operand of the instruction.
2702 CommutableOpIdx2 = LastCommutableVecOp;
2703 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
2704 // Only one of operands is not fixed.
2705 CommutableOpIdx2 = SrcOpIdx1;
2706
2707 // CommutableOpIdx2 is well defined now. Let's choose another commutable
2708 // operand and assign its index to CommutableOpIdx1.
2709 Register Op2Reg = MI.getOperand(i: CommutableOpIdx2).getReg();
2710
2711 unsigned CommutableOpIdx1;
2712 for (CommutableOpIdx1 = LastCommutableVecOp;
2713 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
2714 // Just ignore and skip the k-mask operand.
2715 if (CommutableOpIdx1 == KMaskOp)
2716 continue;
2717
2718 // The commuted operands must have different registers.
2719 // Otherwise, the commute transformation does not change anything and
2720 // is useless then.
2721 if (Op2Reg != MI.getOperand(i: CommutableOpIdx1).getReg())
2722 break;
2723 }
2724
2725 // No appropriate commutable operands were found.
2726 if (CommutableOpIdx1 < FirstCommutableVecOp)
2727 return false;
2728
2729 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
2730 // to return those values.
2731 if (!fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1,
2732 CommutableOpIdx2))
2733 return false;
2734 }
2735
2736 return true;
2737}
2738
2739bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI,
2740 unsigned &SrcOpIdx1,
2741 unsigned &SrcOpIdx2) const {
2742 const MCInstrDesc &Desc = MI.getDesc();
2743 if (!Desc.isCommutable())
2744 return false;
2745
2746 switch (MI.getOpcode()) {
2747 case X86::CMPSDrri:
2748 case X86::CMPSSrri:
2749 case X86::CMPPDrri:
2750 case X86::CMPPSrri:
2751 case X86::VCMPSDrri:
2752 case X86::VCMPSSrri:
2753 case X86::VCMPPDrri:
2754 case X86::VCMPPSrri:
2755 case X86::VCMPPDYrri:
2756 case X86::VCMPPSYrri:
2757 case X86::VCMPSDZrri:
2758 case X86::VCMPSSZrri:
2759 case X86::VCMPPDZrri:
2760 case X86::VCMPPSZrri:
2761 case X86::VCMPSHZrri:
2762 case X86::VCMPPHZrri:
2763 case X86::VCMPPHZ128rri:
2764 case X86::VCMPPHZ256rri:
2765 case X86::VCMPPDZ128rri:
2766 case X86::VCMPPSZ128rri:
2767 case X86::VCMPPDZ256rri:
2768 case X86::VCMPPSZ256rri:
2769 case X86::VCMPPDZrrik:
2770 case X86::VCMPPSZrrik:
2771 case X86::VCMPPHZrrik:
2772 case X86::VCMPPDZ128rrik:
2773 case X86::VCMPPSZ128rrik:
2774 case X86::VCMPPHZ128rrik:
2775 case X86::VCMPPDZ256rrik:
2776 case X86::VCMPPSZ256rrik:
2777 case X86::VCMPPHZ256rrik: {
2778 unsigned OpOffset = X86II::isKMasked(TSFlags: Desc.TSFlags) ? 1 : 0;
2779
2780 // Float comparison can be safely commuted for
2781 // Ordered/Unordered/Equal/NotEqual tests
2782 unsigned Imm = MI.getOperand(i: 3 + OpOffset).getImm() & 0x7;
2783 switch (Imm) {
2784 default:
2785 // EVEX versions can be commuted.
2786 if ((Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX)
2787 break;
2788 return false;
2789 case 0x00: // EQUAL
2790 case 0x03: // UNORDERED
2791 case 0x04: // NOT EQUAL
2792 case 0x07: // ORDERED
2793 break;
2794 }
2795
2796 // The indices of the commutable operands are 1 and 2 (or 2 and 3
2797 // when masked).
2798 // Assign them to the returned operand indices here.
2799 return fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1: 1 + OpOffset,
2800 CommutableOpIdx2: 2 + OpOffset);
2801 }
2802 case X86::MOVSSrr:
2803 // X86::MOVSDrr is always commutable. MOVSS is only commutable if we can
2804 // form sse4.1 blend. We assume VMOVSSrr/VMOVSDrr is always commutable since
2805 // AVX implies sse4.1.
2806 if (Subtarget.hasSSE41())
2807 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2808 return false;
2809 case X86::SHUFPDrri:
2810 // We can commute this to MOVSD.
2811 if (MI.getOperand(i: 3).getImm() == 0x02)
2812 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2813 return false;
2814 case X86::MOVHLPSrr:
2815 case X86::UNPCKHPDrr:
2816 case X86::VMOVHLPSrr:
2817 case X86::VUNPCKHPDrr:
2818 case X86::VMOVHLPSZrr:
2819 case X86::VUNPCKHPDZ128rr:
2820 if (Subtarget.hasSSE2())
2821 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2822 return false;
2823 case X86::VPTERNLOGDZrri:
2824 case X86::VPTERNLOGDZrmi:
2825 case X86::VPTERNLOGDZ128rri:
2826 case X86::VPTERNLOGDZ128rmi:
2827 case X86::VPTERNLOGDZ256rri:
2828 case X86::VPTERNLOGDZ256rmi:
2829 case X86::VPTERNLOGQZrri:
2830 case X86::VPTERNLOGQZrmi:
2831 case X86::VPTERNLOGQZ128rri:
2832 case X86::VPTERNLOGQZ128rmi:
2833 case X86::VPTERNLOGQZ256rri:
2834 case X86::VPTERNLOGQZ256rmi:
2835 case X86::VPTERNLOGDZrrik:
2836 case X86::VPTERNLOGDZ128rrik:
2837 case X86::VPTERNLOGDZ256rrik:
2838 case X86::VPTERNLOGQZrrik:
2839 case X86::VPTERNLOGQZ128rrik:
2840 case X86::VPTERNLOGQZ256rrik:
2841 case X86::VPTERNLOGDZrrikz:
2842 case X86::VPTERNLOGDZrmikz:
2843 case X86::VPTERNLOGDZ128rrikz:
2844 case X86::VPTERNLOGDZ128rmikz:
2845 case X86::VPTERNLOGDZ256rrikz:
2846 case X86::VPTERNLOGDZ256rmikz:
2847 case X86::VPTERNLOGQZrrikz:
2848 case X86::VPTERNLOGQZrmikz:
2849 case X86::VPTERNLOGQZ128rrikz:
2850 case X86::VPTERNLOGQZ128rmikz:
2851 case X86::VPTERNLOGQZ256rrikz:
2852 case X86::VPTERNLOGQZ256rmikz:
2853 case X86::VPTERNLOGDZ128rmbi:
2854 case X86::VPTERNLOGDZ256rmbi:
2855 case X86::VPTERNLOGDZrmbi:
2856 case X86::VPTERNLOGQZ128rmbi:
2857 case X86::VPTERNLOGQZ256rmbi:
2858 case X86::VPTERNLOGQZrmbi:
2859 case X86::VPTERNLOGDZ128rmbikz:
2860 case X86::VPTERNLOGDZ256rmbikz:
2861 case X86::VPTERNLOGDZrmbikz:
2862 case X86::VPTERNLOGQZ128rmbikz:
2863 case X86::VPTERNLOGQZ256rmbikz:
2864 case X86::VPTERNLOGQZrmbikz:
2865 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2866 case X86::VPDPWSSDYrr:
2867 case X86::VPDPWSSDrr:
2868 case X86::VPDPWSSDSYrr:
2869 case X86::VPDPWSSDSrr:
2870 case X86::VPDPWUUDrr:
2871 case X86::VPDPWUUDYrr:
2872 case X86::VPDPWUUDSrr:
2873 case X86::VPDPWUUDSYrr:
2874 case X86::VPDPBSSDSrr:
2875 case X86::VPDPBSSDSYrr:
2876 case X86::VPDPBSSDrr:
2877 case X86::VPDPBSSDYrr:
2878 case X86::VPDPBUUDSrr:
2879 case X86::VPDPBUUDSYrr:
2880 case X86::VPDPBUUDrr:
2881 case X86::VPDPBUUDYrr:
2882 case X86::VPDPBSSDSZ128rr:
2883 case X86::VPDPBSSDSZ128rrk:
2884 case X86::VPDPBSSDSZ128rrkz:
2885 case X86::VPDPBSSDSZ256rr:
2886 case X86::VPDPBSSDSZ256rrk:
2887 case X86::VPDPBSSDSZ256rrkz:
2888 case X86::VPDPBSSDSZrr:
2889 case X86::VPDPBSSDSZrrk:
2890 case X86::VPDPBSSDSZrrkz:
2891 case X86::VPDPBSSDZ128rr:
2892 case X86::VPDPBSSDZ128rrk:
2893 case X86::VPDPBSSDZ128rrkz:
2894 case X86::VPDPBSSDZ256rr:
2895 case X86::VPDPBSSDZ256rrk:
2896 case X86::VPDPBSSDZ256rrkz:
2897 case X86::VPDPBSSDZrr:
2898 case X86::VPDPBSSDZrrk:
2899 case X86::VPDPBSSDZrrkz:
2900 case X86::VPDPBUUDSZ128rr:
2901 case X86::VPDPBUUDSZ128rrk:
2902 case X86::VPDPBUUDSZ128rrkz:
2903 case X86::VPDPBUUDSZ256rr:
2904 case X86::VPDPBUUDSZ256rrk:
2905 case X86::VPDPBUUDSZ256rrkz:
2906 case X86::VPDPBUUDSZrr:
2907 case X86::VPDPBUUDSZrrk:
2908 case X86::VPDPBUUDSZrrkz:
2909 case X86::VPDPBUUDZ128rr:
2910 case X86::VPDPBUUDZ128rrk:
2911 case X86::VPDPBUUDZ128rrkz:
2912 case X86::VPDPBUUDZ256rr:
2913 case X86::VPDPBUUDZ256rrk:
2914 case X86::VPDPBUUDZ256rrkz:
2915 case X86::VPDPBUUDZrr:
2916 case X86::VPDPBUUDZrrk:
2917 case X86::VPDPBUUDZrrkz:
2918 case X86::VPDPWSSDZ128rr:
2919 case X86::VPDPWSSDZ128rrk:
2920 case X86::VPDPWSSDZ128rrkz:
2921 case X86::VPDPWSSDZ256rr:
2922 case X86::VPDPWSSDZ256rrk:
2923 case X86::VPDPWSSDZ256rrkz:
2924 case X86::VPDPWSSDZrr:
2925 case X86::VPDPWSSDZrrk:
2926 case X86::VPDPWSSDZrrkz:
2927 case X86::VPDPWSSDSZ128rr:
2928 case X86::VPDPWSSDSZ128rrk:
2929 case X86::VPDPWSSDSZ128rrkz:
2930 case X86::VPDPWSSDSZ256rr:
2931 case X86::VPDPWSSDSZ256rrk:
2932 case X86::VPDPWSSDSZ256rrkz:
2933 case X86::VPDPWSSDSZrr:
2934 case X86::VPDPWSSDSZrrk:
2935 case X86::VPDPWSSDSZrrkz:
2936 case X86::VPDPWUUDZ128rr:
2937 case X86::VPDPWUUDZ128rrk:
2938 case X86::VPDPWUUDZ128rrkz:
2939 case X86::VPDPWUUDZ256rr:
2940 case X86::VPDPWUUDZ256rrk:
2941 case X86::VPDPWUUDZ256rrkz:
2942 case X86::VPDPWUUDZrr:
2943 case X86::VPDPWUUDZrrk:
2944 case X86::VPDPWUUDZrrkz:
2945 case X86::VPDPWUUDSZ128rr:
2946 case X86::VPDPWUUDSZ128rrk:
2947 case X86::VPDPWUUDSZ128rrkz:
2948 case X86::VPDPWUUDSZ256rr:
2949 case X86::VPDPWUUDSZ256rrk:
2950 case X86::VPDPWUUDSZ256rrkz:
2951 case X86::VPDPWUUDSZrr:
2952 case X86::VPDPWUUDSZrrk:
2953 case X86::VPDPWUUDSZrrkz:
2954 case X86::VPMADD52HUQrr:
2955 case X86::VPMADD52HUQYrr:
2956 case X86::VPMADD52HUQZ128r:
2957 case X86::VPMADD52HUQZ128rk:
2958 case X86::VPMADD52HUQZ128rkz:
2959 case X86::VPMADD52HUQZ256r:
2960 case X86::VPMADD52HUQZ256rk:
2961 case X86::VPMADD52HUQZ256rkz:
2962 case X86::VPMADD52HUQZr:
2963 case X86::VPMADD52HUQZrk:
2964 case X86::VPMADD52HUQZrkz:
2965 case X86::VPMADD52LUQrr:
2966 case X86::VPMADD52LUQYrr:
2967 case X86::VPMADD52LUQZ128r:
2968 case X86::VPMADD52LUQZ128rk:
2969 case X86::VPMADD52LUQZ128rkz:
2970 case X86::VPMADD52LUQZ256r:
2971 case X86::VPMADD52LUQZ256rk:
2972 case X86::VPMADD52LUQZ256rkz:
2973 case X86::VPMADD52LUQZr:
2974 case X86::VPMADD52LUQZrk:
2975 case X86::VPMADD52LUQZrkz:
2976 case X86::VFMADDCPHZr:
2977 case X86::VFMADDCPHZrk:
2978 case X86::VFMADDCPHZrkz:
2979 case X86::VFMADDCPHZ128r:
2980 case X86::VFMADDCPHZ128rk:
2981 case X86::VFMADDCPHZ128rkz:
2982 case X86::VFMADDCPHZ256r:
2983 case X86::VFMADDCPHZ256rk:
2984 case X86::VFMADDCPHZ256rkz:
2985 case X86::VFMADDCSHZr:
2986 case X86::VFMADDCSHZrk:
2987 case X86::VFMADDCSHZrkz: {
2988 unsigned CommutableOpIdx1 = 2;
2989 unsigned CommutableOpIdx2 = 3;
2990 if (X86II::isKMasked(TSFlags: Desc.TSFlags)) {
2991 // Skip the mask register.
2992 ++CommutableOpIdx1;
2993 ++CommutableOpIdx2;
2994 }
2995 if (!fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1,
2996 CommutableOpIdx2))
2997 return false;
2998 if (!MI.getOperand(i: SrcOpIdx1).isReg() || !MI.getOperand(i: SrcOpIdx2).isReg())
2999 // No idea.
3000 return false;
3001 return true;
3002 }
3003
3004 default:
3005 const X86InstrFMA3Group *FMA3Group =
3006 getFMA3Group(Opcode: MI.getOpcode(), TSFlags: MI.getDesc().TSFlags);
3007 if (FMA3Group)
3008 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
3009 IsIntrinsic: FMA3Group->isIntrinsic());
3010
3011 // Handled masked instructions since we need to skip over the mask input
3012 // and the preserved input.
3013 if (X86II::isKMasked(TSFlags: Desc.TSFlags)) {
3014 // First assume that the first input is the mask operand and skip past it.
3015 unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
3016 unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
3017 // Check if the first input is tied. If there isn't one then we only
3018 // need to skip the mask operand which we did above.
3019 if ((MI.getDesc().getOperandConstraint(OpNum: Desc.getNumDefs(),
3020 Constraint: MCOI::TIED_TO) != -1)) {
3021 // If this is zero masking instruction with a tied operand, we need to
3022 // move the first index back to the first input since this must
3023 // be a 3 input instruction and we want the first two non-mask inputs.
3024 // Otherwise this is a 2 input instruction with a preserved input and
3025 // mask, so we need to move the indices to skip one more input.
3026 if (X86II::isKMergeMasked(TSFlags: Desc.TSFlags)) {
3027 ++CommutableOpIdx1;
3028 ++CommutableOpIdx2;
3029 } else {
3030 --CommutableOpIdx1;
3031 }
3032 }
3033
3034 if (!fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1,
3035 CommutableOpIdx2))
3036 return false;
3037
3038 if (!MI.getOperand(i: SrcOpIdx1).isReg() ||
3039 !MI.getOperand(i: SrcOpIdx2).isReg())
3040 // No idea.
3041 return false;
3042 return true;
3043 }
3044
3045 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3046 }
3047 return false;
3048}
3049
3050static bool isConvertibleLEA(MachineInstr *MI) {
3051 unsigned Opcode = MI->getOpcode();
3052 if (Opcode != X86::LEA32r && Opcode != X86::LEA64r &&
3053 Opcode != X86::LEA64_32r)
3054 return false;
3055
3056 const MachineOperand &Scale = MI->getOperand(i: 1 + X86::AddrScaleAmt);
3057 const MachineOperand &Disp = MI->getOperand(i: 1 + X86::AddrDisp);
3058 const MachineOperand &Segment = MI->getOperand(i: 1 + X86::AddrSegmentReg);
3059
3060 if (Segment.getReg() != 0 || !Disp.isImm() || Disp.getImm() != 0 ||
3061 Scale.getImm() > 1)
3062 return false;
3063
3064 return true;
3065}
3066
3067bool X86InstrInfo::hasCommutePreference(MachineInstr &MI, bool &Commute) const {
3068 // Currently we're interested in following sequence only.
3069 // r3 = lea r1, r2
3070 // r5 = add r3, r4
3071 // Both r3 and r4 are killed in add, we hope the add instruction has the
3072 // operand order
3073 // r5 = add r4, r3
3074 // So later in X86FixupLEAs the lea instruction can be rewritten as add.
3075 unsigned Opcode = MI.getOpcode();
3076 if (Opcode != X86::ADD32rr && Opcode != X86::ADD64rr)
3077 return false;
3078
3079 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3080 Register Reg1 = MI.getOperand(i: 1).getReg();
3081 Register Reg2 = MI.getOperand(i: 2).getReg();
3082
3083 // Check if Reg1 comes from LEA in the same MBB.
3084 if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg: Reg1)) {
3085 if (isConvertibleLEA(MI: Inst) && Inst->getParent() == MI.getParent()) {
3086 Commute = true;
3087 return true;
3088 }
3089 }
3090
3091 // Check if Reg2 comes from LEA in the same MBB.
3092 if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg: Reg2)) {
3093 if (isConvertibleLEA(MI: Inst) && Inst->getParent() == MI.getParent()) {
3094 Commute = false;
3095 return true;
3096 }
3097 }
3098
3099 return false;
3100}
3101
3102int X86::getCondSrcNoFromDesc(const MCInstrDesc &MCID) {
3103 unsigned Opcode = MCID.getOpcode();
3104 if (!(X86::isJCC(Opcode) || X86::isSETCC(Opcode) || X86::isSETZUCC(Opcode) ||
3105 X86::isCMOVCC(Opcode) || X86::isCFCMOVCC(Opcode) ||
3106 X86::isCCMPCC(Opcode) || X86::isCTESTCC(Opcode)))
3107 return -1;
3108 // Assume that condition code is always the last use operand.
3109 unsigned NumUses = MCID.getNumOperands() - MCID.getNumDefs();
3110 return NumUses - 1;
3111}
3112
3113X86::CondCode X86::getCondFromMI(const MachineInstr &MI) {
3114 const MCInstrDesc &MCID = MI.getDesc();
3115 int CondNo = getCondSrcNoFromDesc(MCID);
3116 if (CondNo < 0)
3117 return X86::COND_INVALID;
3118 CondNo += MCID.getNumDefs();
3119 return static_cast<X86::CondCode>(MI.getOperand(i: CondNo).getImm());
3120}
3121
3122X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
3123 return X86::isJCC(Opcode: MI.getOpcode()) ? X86::getCondFromMI(MI)
3124 : X86::COND_INVALID;
3125}
3126
3127X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
3128 return X86::isSETCC(Opcode: MI.getOpcode()) || X86::isSETZUCC(Opcode: MI.getOpcode())
3129 ? X86::getCondFromMI(MI)
3130 : X86::COND_INVALID;
3131}
3132
3133X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
3134 return X86::isCMOVCC(Opcode: MI.getOpcode()) ? X86::getCondFromMI(MI)
3135 : X86::COND_INVALID;
3136}
3137
3138X86::CondCode X86::getCondFromCFCMov(const MachineInstr &MI) {
3139 return X86::isCFCMOVCC(Opcode: MI.getOpcode()) ? X86::getCondFromMI(MI)
3140 : X86::COND_INVALID;
3141}
3142
3143X86::CondCode X86::getCondFromCCMP(const MachineInstr &MI) {
3144 return X86::isCCMPCC(Opcode: MI.getOpcode()) || X86::isCTESTCC(Opcode: MI.getOpcode())
3145 ? X86::getCondFromMI(MI)
3146 : X86::COND_INVALID;
3147}
3148
3149int X86::getCCMPCondFlagsFromCondCode(X86::CondCode CC) {
3150 // CCMP/CTEST has two conditional operands:
3151 // - SCC: source conditonal code (same as CMOV)
3152 // - DCF: destination conditional flags, which has 4 valid bits
3153 //
3154 // +----+----+----+----+
3155 // | OF | SF | ZF | CF |
3156 // +----+----+----+----+
3157 //
3158 // If SCC(source conditional code) evaluates to false, CCMP/CTEST will updates
3159 // the conditional flags by as follows:
3160 //
3161 // OF = DCF.OF
3162 // SF = DCF.SF
3163 // ZF = DCF.ZF
3164 // CF = DCF.CF
3165 // PF = DCF.CF
3166 // AF = 0 (Auxiliary Carry Flag)
3167 //
3168 // Otherwise, the CMP or TEST is executed and it updates the
3169 // CSPAZO flags normally.
3170 //
3171 // NOTE:
3172 // If SCC = P, then SCC evaluates to true regardless of the CSPAZO value.
3173 // If SCC = NP, then SCC evaluates to false regardless of the CSPAZO value.
3174
3175 enum { CF = 1, ZF = 2, SF = 4, OF = 8, PF = CF };
3176
3177 switch (CC) {
3178 default:
3179 llvm_unreachable("Illegal condition code!");
3180 case X86::COND_NO:
3181 case X86::COND_NE:
3182 case X86::COND_GE:
3183 case X86::COND_G:
3184 case X86::COND_AE:
3185 case X86::COND_A:
3186 case X86::COND_NS:
3187 case X86::COND_NP:
3188 return 0;
3189 case X86::COND_O:
3190 return OF;
3191 case X86::COND_B:
3192 case X86::COND_BE:
3193 return CF;
3194 break;
3195 case X86::COND_E:
3196 case X86::COND_LE:
3197 return ZF;
3198 case X86::COND_S:
3199 case X86::COND_L:
3200 return SF;
3201 case X86::COND_P:
3202 return PF;
3203 }
3204}
3205
3206#define GET_X86_NF_TRANSFORM_TABLE
3207#define GET_X86_ND2NONND_TABLE
3208#include "X86GenInstrMapping.inc"
3209
3210static unsigned getNewOpcFromTable(ArrayRef<X86TableEntry> Table,
3211 unsigned Opc) {
3212 const auto I = llvm::lower_bound(Range&: Table, Value&: Opc);
3213 return (I == Table.end() || I->OldOpc != Opc) ? 0U : I->NewOpc;
3214}
3215unsigned X86::getNFVariant(unsigned Opc) {
3216#if defined(EXPENSIVE_CHECKS) && !defined(NDEBUG)
3217 // Make sure the tables are sorted.
3218 static std::atomic<bool> NFTableChecked(false);
3219 if (!NFTableChecked.load(std::memory_order_relaxed)) {
3220 assert(llvm::is_sorted(X86NFTransformTable) &&
3221 "X86NFTransformTable is not sorted!");
3222 NFTableChecked.store(true, std::memory_order_relaxed);
3223 }
3224#endif
3225 return getNewOpcFromTable(Table: X86NFTransformTable, Opc);
3226}
3227
3228unsigned X86::getNFVariantIfClobberRemovable(const MachineInstr &MI,
3229 const TargetRegisterInfo *TRI) {
3230 if (!MI.registerDefIsDead(Reg: X86::EFLAGS, TRI))
3231 return 0;
3232 // For the instructions are ADDrm/ADDmr with relocation, we'll skip the
3233 // optimization for replacing non-NF with NF. This is to keep backward
3234 // compatiblity with old version of linkers without APX relocation type
3235 // support on Linux OS.
3236 const X86Subtarget &ST = MI.getMF()->getSubtarget<X86Subtarget>();
3237 if (!ST.getCLOpts().enable_apx_for_relocation &&
3238 isAddMemInstrWithRelocation(MI))
3239 return 0;
3240 return X86::getNFVariant(Opc: MI.getOpcode());
3241}
3242
3243unsigned X86::getNonNDVariant(unsigned Opc) {
3244#if defined(EXPENSIVE_CHECKS) && !defined(NDEBUG)
3245 // Make sure the tables are sorted.
3246 static std::atomic<bool> NDTableChecked(false);
3247 if (!NDTableChecked.load(std::memory_order_relaxed)) {
3248 assert(llvm::is_sorted(X86ND2NonNDTable) &&
3249 "X86ND2NonNDTableis not sorted!");
3250 NDTableChecked.store(true, std::memory_order_relaxed);
3251 }
3252#endif
3253 return getNewOpcFromTable(Table: X86ND2NonNDTable, Opc);
3254}
3255
3256/// Return the inverse of the specified condition,
3257/// e.g. turning COND_E to COND_NE.
3258X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3259 switch (CC) {
3260 default:
3261 llvm_unreachable("Illegal condition code!");
3262 case X86::COND_E:
3263 return X86::COND_NE;
3264 case X86::COND_NE:
3265 return X86::COND_E;
3266 case X86::COND_L:
3267 return X86::COND_GE;
3268 case X86::COND_LE:
3269 return X86::COND_G;
3270 case X86::COND_G:
3271 return X86::COND_LE;
3272 case X86::COND_GE:
3273 return X86::COND_L;
3274 case X86::COND_B:
3275 return X86::COND_AE;
3276 case X86::COND_BE:
3277 return X86::COND_A;
3278 case X86::COND_A:
3279 return X86::COND_BE;
3280 case X86::COND_AE:
3281 return X86::COND_B;
3282 case X86::COND_S:
3283 return X86::COND_NS;
3284 case X86::COND_NS:
3285 return X86::COND_S;
3286 case X86::COND_P:
3287 return X86::COND_NP;
3288 case X86::COND_NP:
3289 return X86::COND_P;
3290 case X86::COND_O:
3291 return X86::COND_NO;
3292 case X86::COND_NO:
3293 return X86::COND_O;
3294 case X86::COND_NE_OR_P:
3295 return X86::COND_E_AND_NP;
3296 case X86::COND_E_AND_NP:
3297 return X86::COND_NE_OR_P;
3298 }
3299}
3300
3301/// Assuming the flags are set by MI(a,b), return the condition code if we
3302/// modify the instructions such that flags are set by MI(b,a).
3303static X86::CondCode getSwappedCondition(X86::CondCode CC) {
3304 switch (CC) {
3305 default:
3306 return X86::COND_INVALID;
3307 case X86::COND_E:
3308 return X86::COND_E;
3309 case X86::COND_NE:
3310 return X86::COND_NE;
3311 case X86::COND_L:
3312 return X86::COND_G;
3313 case X86::COND_LE:
3314 return X86::COND_GE;
3315 case X86::COND_G:
3316 return X86::COND_L;
3317 case X86::COND_GE:
3318 return X86::COND_LE;
3319 case X86::COND_B:
3320 return X86::COND_A;
3321 case X86::COND_BE:
3322 return X86::COND_AE;
3323 case X86::COND_A:
3324 return X86::COND_B;
3325 case X86::COND_AE:
3326 return X86::COND_BE;
3327 }
3328}
3329
3330std::pair<X86::CondCode, bool>
3331X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
3332 X86::CondCode CC = X86::COND_INVALID;
3333 bool NeedSwap = false;
3334 switch (Predicate) {
3335 default:
3336 break;
3337 // Floating-point Predicates
3338 case CmpInst::FCMP_UEQ:
3339 CC = X86::COND_E;
3340 break;
3341 case CmpInst::FCMP_OLT:
3342 NeedSwap = true;
3343 [[fallthrough]];
3344 case CmpInst::FCMP_OGT:
3345 CC = X86::COND_A;
3346 break;
3347 case CmpInst::FCMP_OLE:
3348 NeedSwap = true;
3349 [[fallthrough]];
3350 case CmpInst::FCMP_OGE:
3351 CC = X86::COND_AE;
3352 break;
3353 case CmpInst::FCMP_UGT:
3354 NeedSwap = true;
3355 [[fallthrough]];
3356 case CmpInst::FCMP_ULT:
3357 CC = X86::COND_B;
3358 break;
3359 case CmpInst::FCMP_UGE:
3360 NeedSwap = true;
3361 [[fallthrough]];
3362 case CmpInst::FCMP_ULE:
3363 CC = X86::COND_BE;
3364 break;
3365 case CmpInst::FCMP_ONE:
3366 CC = X86::COND_NE;
3367 break;
3368 case CmpInst::FCMP_UNO:
3369 CC = X86::COND_P;
3370 break;
3371 case CmpInst::FCMP_ORD:
3372 CC = X86::COND_NP;
3373 break;
3374 case CmpInst::FCMP_OEQ:
3375 [[fallthrough]];
3376 case CmpInst::FCMP_UNE:
3377 CC = X86::COND_INVALID;
3378 break;
3379
3380 // Integer Predicates
3381 case CmpInst::ICMP_EQ:
3382 CC = X86::COND_E;
3383 break;
3384 case CmpInst::ICMP_NE:
3385 CC = X86::COND_NE;
3386 break;
3387 case CmpInst::ICMP_UGT:
3388 CC = X86::COND_A;
3389 break;
3390 case CmpInst::ICMP_UGE:
3391 CC = X86::COND_AE;
3392 break;
3393 case CmpInst::ICMP_ULT:
3394 CC = X86::COND_B;
3395 break;
3396 case CmpInst::ICMP_ULE:
3397 CC = X86::COND_BE;
3398 break;
3399 case CmpInst::ICMP_SGT:
3400 CC = X86::COND_G;
3401 break;
3402 case CmpInst::ICMP_SGE:
3403 CC = X86::COND_GE;
3404 break;
3405 case CmpInst::ICMP_SLT:
3406 CC = X86::COND_L;
3407 break;
3408 case CmpInst::ICMP_SLE:
3409 CC = X86::COND_LE;
3410 break;
3411 }
3412
3413 return std::make_pair(x&: CC, y&: NeedSwap);
3414}
3415
3416/// Return a cmov opcode for the given register size in bytes, and operand type.
3417unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand,
3418 bool HasNDD) {
3419 switch (RegBytes) {
3420 default:
3421 llvm_unreachable("Illegal register size!");
3422#define GET_ND_IF_ENABLED(OPC) (HasNDD ? OPC##_ND : OPC)
3423 case 2:
3424 return HasMemoryOperand ? GET_ND_IF_ENABLED(X86::CMOV16rm)
3425 : GET_ND_IF_ENABLED(X86::CMOV16rr);
3426 case 4:
3427 return HasMemoryOperand ? GET_ND_IF_ENABLED(X86::CMOV32rm)
3428 : GET_ND_IF_ENABLED(X86::CMOV32rr);
3429 case 8:
3430 return HasMemoryOperand ? GET_ND_IF_ENABLED(X86::CMOV64rm)
3431 : GET_ND_IF_ENABLED(X86::CMOV64rr);
3432 }
3433}
3434
3435unsigned X86::getMOVriOpcode(bool Use64BitReg, int64_t Imm) {
3436 if (!Use64BitReg)
3437 return X86::MOV32ri;
3438
3439 if (isUInt<32>(x: Imm))
3440 return X86::MOV32ri64;
3441 if (isInt<32>(x: Imm))
3442 return X86::MOV64ri32;
3443 return X86::MOV64ri;
3444}
3445
3446/// Get the VPCMP immediate for the given condition.
3447unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
3448 switch (CC) {
3449 default:
3450 llvm_unreachable("Unexpected SETCC condition");
3451 case ISD::SETNE:
3452 return 4;
3453 case ISD::SETEQ:
3454 return 0;
3455 case ISD::SETULT:
3456 case ISD::SETLT:
3457 return 1;
3458 case ISD::SETUGT:
3459 case ISD::SETGT:
3460 return 6;
3461 case ISD::SETUGE:
3462 case ISD::SETGE:
3463 return 5;
3464 case ISD::SETULE:
3465 case ISD::SETLE:
3466 return 2;
3467 }
3468}
3469
3470/// Get the VPCMP immediate if the operands are swapped.
3471unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
3472 switch (Imm) {
3473 default:
3474 llvm_unreachable("Unreachable!");
3475 case 0x01:
3476 Imm = 0x06;
3477 break; // LT -> NLE
3478 case 0x02:
3479 Imm = 0x05;
3480 break; // LE -> NLT
3481 case 0x05:
3482 Imm = 0x02;
3483 break; // NLT -> LE
3484 case 0x06:
3485 Imm = 0x01;
3486 break; // NLE -> LT
3487 case 0x00: // EQ
3488 case 0x03: // FALSE
3489 case 0x04: // NE
3490 case 0x07: // TRUE
3491 break;
3492 }
3493
3494 return Imm;
3495}
3496
3497/// Get the VPCOM immediate if the operands are swapped.
3498unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
3499 switch (Imm) {
3500 default:
3501 llvm_unreachable("Unreachable!");
3502 case 0x00:
3503 Imm = 0x02;
3504 break; // LT -> GT
3505 case 0x01:
3506 Imm = 0x03;
3507 break; // LE -> GE
3508 case 0x02:
3509 Imm = 0x00;
3510 break; // GT -> LT
3511 case 0x03:
3512 Imm = 0x01;
3513 break; // GE -> LE
3514 case 0x04: // EQ
3515 case 0x05: // NE
3516 case 0x06: // FALSE
3517 case 0x07: // TRUE
3518 break;
3519 }
3520
3521 return Imm;
3522}
3523
3524/// Get the VCMP immediate if the operands are swapped.
3525unsigned X86::getSwappedVCMPImm(unsigned Imm) {
3526 // Only need the lower 2 bits to distinquish.
3527 switch (Imm & 0x3) {
3528 default:
3529 llvm_unreachable("Unreachable!");
3530 case 0x00:
3531 case 0x03:
3532 // EQ/NE/TRUE/FALSE/ORD/UNORD don't change immediate when commuted.
3533 break;
3534 case 0x01:
3535 case 0x02:
3536 // Need to toggle bits 3:0. Bit 4 stays the same.
3537 Imm ^= 0xf;
3538 break;
3539 }
3540
3541 return Imm;
3542}
3543
3544unsigned X86::getVectorRegisterWidth(const MCOperandInfo &Info) {
3545 if (Info.RegClass == X86::VR128RegClassID ||
3546 Info.RegClass == X86::VR128XRegClassID)
3547 return 128;
3548 if (Info.RegClass == X86::VR256RegClassID ||
3549 Info.RegClass == X86::VR256XRegClassID)
3550 return 256;
3551 if (Info.RegClass == X86::VR512RegClassID)
3552 return 512;
3553 llvm_unreachable("Unknown register class!");
3554}
3555
3556/// Return true if the Reg is X87 register.
3557static bool isX87Reg(Register Reg) {
3558 return (Reg == X86::FPCW || Reg == X86::FPSW ||
3559 (Reg >= X86::ST0 && Reg <= X86::ST7));
3560}
3561
3562/// check if the instruction is X87 instruction
3563bool X86::isX87Instruction(MachineInstr &MI) {
3564 // Call and inlineasm defs X87 register, so we special case it here because
3565 // otherwise calls are incorrectly flagged as x87 instructions
3566 // as a result.
3567 if (MI.isCall() || MI.isInlineAsm())
3568 return false;
3569 for (const MachineOperand &MO : MI.operands()) {
3570 if (!MO.isReg())
3571 continue;
3572 if (isX87Reg(Reg: MO.getReg()))
3573 return true;
3574 }
3575 return false;
3576}
3577
3578int X86::getFirstAddrOperandIdx(const MachineInstr &MI) {
3579 auto IsMemOp = [](const MCOperandInfo &OpInfo) {
3580 return OpInfo.OperandType == MCOI::OPERAND_MEMORY;
3581 };
3582
3583 const MCInstrDesc &Desc = MI.getDesc();
3584
3585 // Directly invoke the MC-layer routine for real (i.e., non-pseudo)
3586 // instructions (fast case).
3587 if (!X86II::isPseudo(TSFlags: Desc.TSFlags)) {
3588 int MemRefIdx = X86II::getMemoryOperandIdx(Desc);
3589 if (MemRefIdx >= 0)
3590 return MemRefIdx;
3591#ifdef EXPENSIVE_CHECKS
3592 assert(none_of(Desc.operands(), IsMemOp) &&
3593 "Got false negative from X86II::getMemoryOperandIdx()!");
3594#endif
3595 return -1;
3596 }
3597
3598 // Otherwise, handle pseudo instructions by examining the type of their
3599 // operands (slow case). An instruction cannot have a memory reference if it
3600 // has fewer than AddrNumOperands (= 5) explicit operands.
3601 unsigned NumOps = Desc.getNumOperands();
3602 if (NumOps < X86::AddrNumOperands) {
3603#ifdef EXPENSIVE_CHECKS
3604 assert(none_of(Desc.operands(), IsMemOp) &&
3605 "Expected no operands to have OPERAND_MEMORY type!");
3606#endif
3607 return -1;
3608 }
3609
3610 // The first operand with type OPERAND_MEMORY indicates the start of a memory
3611 // reference. We expect the following AddrNumOperand-1 operands to also have
3612 // OPERAND_MEMORY type.
3613 for (unsigned I = 0, E = NumOps - X86::AddrNumOperands; I != E; ++I) {
3614 if (IsMemOp(Desc.operands()[I])) {
3615#ifdef EXPENSIVE_CHECKS
3616 assert(std::all_of(Desc.operands().begin() + I,
3617 Desc.operands().begin() + I + X86::AddrNumOperands,
3618 IsMemOp) &&
3619 "Expected all five operands in the memory reference to have "
3620 "OPERAND_MEMORY type!");
3621#endif
3622 return I;
3623 }
3624 }
3625
3626 return -1;
3627}
3628
3629const Constant *X86::getConstantFromPool(const MachineInstr &MI,
3630 unsigned OpNo) {
3631 assert(MI.getNumOperands() >= (OpNo + X86::AddrNumOperands) &&
3632 "Unexpected number of operands!");
3633
3634 const MachineOperand &Index = MI.getOperand(i: OpNo + X86::AddrIndexReg);
3635 if (!Index.isReg() || Index.getReg() != X86::NoRegister)
3636 return nullptr;
3637
3638 const MachineOperand &Disp = MI.getOperand(i: OpNo + X86::AddrDisp);
3639 if (!Disp.isCPI() || Disp.getOffset() != 0)
3640 return nullptr;
3641
3642 ArrayRef<MachineConstantPoolEntry> Constants =
3643 MI.getParent()->getParent()->getConstantPool()->getConstants();
3644 const MachineConstantPoolEntry &ConstantEntry = Constants[Disp.getIndex()];
3645
3646 // Bail if this is a machine constant pool entry, we won't be able to dig out
3647 // anything useful.
3648 if (ConstantEntry.isMachineConstantPoolEntry())
3649 return nullptr;
3650
3651 return ConstantEntry.Val.ConstVal;
3652}
3653
3654bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
3655 switch (MI.getOpcode()) {
3656 case X86::TCRETURNdi:
3657 case X86::TCRETURNri:
3658 case X86::TCRETURNmi:
3659 case X86::TCRETURNdi64:
3660 case X86::TCRETURNri64:
3661 case X86::TCRETURNri64_ImpCall:
3662 case X86::TCRETURNmi64:
3663 return true;
3664 default:
3665 return false;
3666 }
3667}
3668
3669bool X86InstrInfo::canMakeTailCallConditional(
3670 SmallVectorImpl<MachineOperand> &BranchCond,
3671 const MachineInstr &TailCall) const {
3672
3673 const MachineFunction *MF = TailCall.getMF();
3674
3675 if (MF->getTarget().getCodeModel() == CodeModel::Kernel) {
3676 // Kernel patches thunk calls in runtime, these should never be conditional.
3677 const MachineOperand &Target = TailCall.getOperand(i: 0);
3678 if (Target.isSymbol()) {
3679 StringRef Symbol(Target.getSymbolName());
3680 // this is currently only relevant to r11/kernel indirect thunk.
3681 if (Symbol == "__x86_indirect_thunk_r11")
3682 return false;
3683 }
3684 }
3685
3686 if (TailCall.getOpcode() != X86::TCRETURNdi &&
3687 TailCall.getOpcode() != X86::TCRETURNdi64) {
3688 // Only direct calls can be done with a conditional branch.
3689 return false;
3690 }
3691
3692 if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
3693 // Conditional tail calls confuse the Win64 unwinder.
3694 return false;
3695 }
3696
3697 assert(BranchCond.size() == 1);
3698 if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
3699 // Can't make a conditional tail call with this condition.
3700 return false;
3701 }
3702
3703 const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3704 if (X86FI->getTCReturnAddrDelta() != 0 ||
3705 TailCall.getOperand(i: 1).getImm() != 0) {
3706 // A conditional tail call cannot do any stack adjustment.
3707 return false;
3708 }
3709
3710 return true;
3711}
3712
3713void X86InstrInfo::replaceBranchWithTailCall(
3714 MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
3715 const MachineInstr &TailCall) const {
3716 assert(canMakeTailCallConditional(BranchCond, TailCall));
3717
3718 MachineBasicBlock::iterator I = MBB.end();
3719 while (I != MBB.begin()) {
3720 --I;
3721 if (I->isDebugInstr())
3722 continue;
3723 if (!I->isBranch())
3724 assert(0 && "Can't find the branch to replace!");
3725
3726 X86::CondCode CC = X86::getCondFromBranch(MI: *I);
3727 assert(BranchCond.size() == 1);
3728 if (CC != BranchCond[0].getImm())
3729 continue;
3730
3731 break;
3732 }
3733
3734 unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
3735 : X86::TCRETURNdi64cc;
3736
3737 auto MIB = BuildMI(BB&: MBB, I, MIMD: MBB.findDebugLoc(MBBI: I), MCID: get(Opcode: Opc));
3738 MIB->addOperand(Op: TailCall.getOperand(i: 0)); // Destination.
3739 MIB.addImm(Val: 0); // Stack offset (not used).
3740 MIB->addOperand(Op: BranchCond[0]); // Condition.
3741 MIB.copyImplicitOps(OtherMI: TailCall); // Regmask and (imp-used) parameters.
3742
3743 // Add implicit uses and defs of all live regs potentially clobbered by the
3744 // call. This way they still appear live across the call.
3745 LivePhysRegs LiveRegs(getRegisterInfo());
3746 LiveRegs.addLiveOuts(MBB);
3747 SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
3748 LiveRegs.stepForward(MI: *MIB, Clobbers);
3749 for (const auto &C : Clobbers) {
3750 MIB.addReg(RegNo: C.first, Flags: RegState::Implicit);
3751 MIB.addReg(RegNo: C.first, Flags: RegState::Implicit | RegState::Define);
3752 }
3753
3754 I->eraseFromParent();
3755}
3756
3757// Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
3758// not be a fallthrough MBB now due to layout changes). Return nullptr if the
3759// fallthrough MBB cannot be identified.
3760static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
3761 MachineBasicBlock *TBB) {
3762 // Look for non-EHPad successors other than TBB. If we find exactly one, it
3763 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
3764 // and fallthrough MBB. If we find more than one, we cannot identify the
3765 // fallthrough MBB and should return nullptr.
3766 MachineBasicBlock *FallthroughBB = nullptr;
3767 for (MachineBasicBlock *Succ : MBB->successors()) {
3768 if (Succ->isEHPad() || (Succ == TBB && FallthroughBB))
3769 continue;
3770 // Return a nullptr if we found more than one fallthrough successor.
3771 if (FallthroughBB && FallthroughBB != TBB)
3772 return nullptr;
3773 FallthroughBB = Succ;
3774 }
3775 return FallthroughBB;
3776}
3777
3778bool X86InstrInfo::analyzeBranchImpl(
3779 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
3780 SmallVectorImpl<MachineOperand> &Cond,
3781 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
3782
3783 // Start from the bottom of the block and work up, examining the
3784 // terminator instructions.
3785 MachineBasicBlock::iterator I = MBB.end();
3786 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
3787 while (I != MBB.begin()) {
3788 --I;
3789 if (I->isDebugInstr())
3790 continue;
3791
3792 // Working from the bottom, when we see a non-terminator instruction, we're
3793 // done.
3794 if (!isUnpredicatedTerminator(MI: *I))
3795 break;
3796
3797 // A terminator that isn't a branch can't easily be handled by this
3798 // analysis.
3799 if (!I->isBranch())
3800 return true;
3801
3802 // Handle unconditional branches.
3803 if (I->getOpcode() == X86::JMP_1) {
3804 UnCondBrIter = I;
3805
3806 if (!AllowModify) {
3807 TBB = I->getOperand(i: 0).getMBB();
3808 continue;
3809 }
3810
3811 // If the block has any instructions after a JMP, delete them.
3812 MBB.erase(I: std::next(x: I), E: MBB.end());
3813
3814 Cond.clear();
3815 FBB = nullptr;
3816
3817 // Delete the JMP if it's equivalent to a fall-through.
3818 if (MBB.isLayoutSuccessor(MBB: I->getOperand(i: 0).getMBB())) {
3819 TBB = nullptr;
3820 I->eraseFromParent();
3821 I = MBB.end();
3822 UnCondBrIter = MBB.end();
3823 continue;
3824 }
3825
3826 // TBB is used to indicate the unconditional destination.
3827 TBB = I->getOperand(i: 0).getMBB();
3828 continue;
3829 }
3830
3831 // Handle conditional branches.
3832 X86::CondCode BranchCode = X86::getCondFromBranch(MI: *I);
3833 if (BranchCode == X86::COND_INVALID)
3834 return true; // Can't handle indirect branch.
3835
3836 // In practice we should never have an undef eflags operand, if we do
3837 // abort here as we are not prepared to preserve the flag.
3838 if (I->findRegisterUseOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr)->isUndef())
3839 return true;
3840
3841 // Working from the bottom, handle the first conditional branch.
3842 if (Cond.empty()) {
3843 FBB = TBB;
3844 TBB = I->getOperand(i: 0).getMBB();
3845 Cond.push_back(Elt: MachineOperand::CreateImm(Val: BranchCode));
3846 CondBranches.push_back(Elt: &*I);
3847 continue;
3848 }
3849
3850 // Handle subsequent conditional branches. Only handle the case where all
3851 // conditional branches branch to the same destination and their condition
3852 // opcodes fit one of the special multi-branch idioms.
3853 assert(Cond.size() == 1);
3854 assert(TBB);
3855
3856 // If the conditions are the same, we can leave them alone.
3857 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3858 auto NewTBB = I->getOperand(i: 0).getMBB();
3859 if (OldBranchCode == BranchCode && TBB == NewTBB)
3860 continue;
3861
3862 // If they differ, see if they fit one of the known patterns. Theoretically,
3863 // we could handle more patterns here, but we shouldn't expect to see them
3864 // if instruction selection has done a reasonable job.
3865 if (TBB == NewTBB &&
3866 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
3867 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
3868 BranchCode = X86::COND_NE_OR_P;
3869 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
3870 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
3871 if (NewTBB != (FBB ? FBB : getFallThroughMBB(MBB: &MBB, TBB)))
3872 return true;
3873
3874 // X86::COND_E_AND_NP usually has two different branch destinations.
3875 //
3876 // JP B1
3877 // JE B2
3878 // JMP B1
3879 // B1:
3880 // B2:
3881 //
3882 // Here this condition branches to B2 only if NP && E. It has another
3883 // equivalent form:
3884 //
3885 // JNE B1
3886 // JNP B2
3887 // JMP B1
3888 // B1:
3889 // B2:
3890 //
3891 // Similarly it branches to B2 only if E && NP. That is why this condition
3892 // is named with COND_E_AND_NP.
3893 BranchCode = X86::COND_E_AND_NP;
3894 } else
3895 return true;
3896
3897 // Update the MachineOperand.
3898 Cond[0].setImm(BranchCode);
3899 CondBranches.push_back(Elt: &*I);
3900 }
3901
3902 return false;
3903}
3904
3905bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
3906 MachineBasicBlock *&TBB,
3907 MachineBasicBlock *&FBB,
3908 SmallVectorImpl<MachineOperand> &Cond,
3909 bool AllowModify) const {
3910 SmallVector<MachineInstr *, 4> CondBranches;
3911 return analyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
3912}
3913
3914static int getJumpTableIndexFromAddr(const MachineInstr &MI) {
3915 int MemRefBegin = X86II::getMemoryOperandIdx(Desc: MI.getDesc());
3916 assert(MemRefBegin >= 0 && "Expected a memory operand");
3917
3918 const MachineOperand &MO = MI.getOperand(i: MemRefBegin + X86::AddrDisp);
3919 if (!MO.isJTI())
3920 return -1;
3921
3922 return MO.getIndex();
3923}
3924
3925static int getJumpTableIndexFromReg(const MachineRegisterInfo &MRI,
3926 Register Reg) {
3927 if (!Reg.isVirtual())
3928 return -1;
3929 MachineInstr *MI = MRI.getUniqueVRegDef(Reg);
3930 if (MI == nullptr)
3931 return -1;
3932 unsigned Opcode = MI->getOpcode();
3933 if (Opcode != X86::LEA64r && Opcode != X86::LEA32r)
3934 return -1;
3935 return getJumpTableIndexFromAddr(MI: *MI);
3936}
3937
3938int X86InstrInfo::getJumpTableIndex(const MachineInstr &MI) const {
3939 unsigned Opcode = MI.getOpcode();
3940 // Switch-jump pattern for non-PIC code looks like:
3941 // JMP64m $noreg, 8, %X, %jump-table.X, $noreg
3942 if (Opcode == X86::JMP64m || Opcode == X86::JMP32m) {
3943 return getJumpTableIndexFromAddr(MI);
3944 }
3945 // The pattern for PIC code looks like:
3946 // %0 = LEA64r $rip, 1, $noreg, %jump-table.X
3947 // %1 = MOVSX64rm32 %0, 4, XX, 0, $noreg
3948 // %2 = ADD64rr %1, %0
3949 // JMP64r %2
3950 if (Opcode == X86::JMP64r || Opcode == X86::JMP32r) {
3951 Register Reg = MI.getOperand(i: 0).getReg();
3952 if (!Reg.isVirtual())
3953 return -1;
3954 const MachineFunction &MF = *MI.getParent()->getParent();
3955 const MachineRegisterInfo &MRI = MF.getRegInfo();
3956 MachineInstr *Add = MRI.getUniqueVRegDef(Reg);
3957 if (Add == nullptr)
3958 return -1;
3959 if (Add->getOpcode() != X86::ADD64rr && Add->getOpcode() != X86::ADD32rr)
3960 return -1;
3961 int JTI1 = getJumpTableIndexFromReg(MRI, Reg: Add->getOperand(i: 1).getReg());
3962 if (JTI1 >= 0)
3963 return JTI1;
3964 int JTI2 = getJumpTableIndexFromReg(MRI, Reg: Add->getOperand(i: 2).getReg());
3965 if (JTI2 >= 0)
3966 return JTI2;
3967 }
3968 return -1;
3969}
3970
3971bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
3972 MachineBranchPredicate &MBP,
3973 bool AllowModify) const {
3974 using namespace std::placeholders;
3975
3976 SmallVector<MachineOperand, 4> Cond;
3977 SmallVector<MachineInstr *, 4> CondBranches;
3978 if (analyzeBranchImpl(MBB, TBB&: MBP.TrueDest, FBB&: MBP.FalseDest, Cond, CondBranches,
3979 AllowModify))
3980 return true;
3981
3982 if (Cond.size() != 1)
3983 return true;
3984
3985 assert(MBP.TrueDest && "expected!");
3986
3987 if (!MBP.FalseDest)
3988 MBP.FalseDest = MBB.getNextNode();
3989
3990 const TargetRegisterInfo *TRI = &getRegisterInfo();
3991
3992 MachineInstr *ConditionDef = nullptr;
3993 bool SingleUseCondition = true;
3994
3995 for (MachineInstr &MI : llvm::drop_begin(RangeOrContainer: llvm::reverse(C&: MBB))) {
3996 if (MI.modifiesRegister(Reg: X86::EFLAGS, TRI)) {
3997 ConditionDef = &MI;
3998 break;
3999 }
4000
4001 if (MI.readsRegister(Reg: X86::EFLAGS, TRI))
4002 SingleUseCondition = false;
4003 }
4004
4005 if (!ConditionDef)
4006 return true;
4007
4008 if (SingleUseCondition) {
4009 for (auto *Succ : MBB.successors())
4010 if (Succ->isLiveIn(Reg: X86::EFLAGS))
4011 SingleUseCondition = false;
4012 }
4013
4014 MBP.ConditionDef = ConditionDef;
4015 MBP.SingleUseCondition = SingleUseCondition;
4016
4017 // Currently we only recognize the simple pattern:
4018 //
4019 // test %reg, %reg
4020 // je %label
4021 //
4022 const unsigned TestOpcode =
4023 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4024
4025 if (ConditionDef->getOpcode() == TestOpcode &&
4026 ConditionDef->getNumOperands() == 3 &&
4027 ConditionDef->getOperand(i: 0).isIdenticalTo(Other: ConditionDef->getOperand(i: 1)) &&
4028 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4029 MBP.LHS = ConditionDef->getOperand(i: 0);
4030 MBP.RHS = MachineOperand::CreateImm(Val: 0);
4031 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4032 ? MachineBranchPredicate::PRED_NE
4033 : MachineBranchPredicate::PRED_EQ;
4034 return false;
4035 }
4036
4037 return true;
4038}
4039
4040unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
4041 int *BytesRemoved) const {
4042 assert(!BytesRemoved && "code size not handled");
4043
4044 MachineBasicBlock::iterator I = MBB.end();
4045 unsigned Count = 0;
4046
4047 while (I != MBB.begin()) {
4048 --I;
4049 if (I->isDebugInstr())
4050 continue;
4051 if (I->getOpcode() != X86::JMP_1 &&
4052 X86::getCondFromBranch(MI: *I) == X86::COND_INVALID)
4053 break;
4054 // Remove the branch.
4055 I->eraseFromParent();
4056 I = MBB.end();
4057 ++Count;
4058 }
4059
4060 return Count;
4061}
4062
4063unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
4064 MachineBasicBlock *TBB,
4065 MachineBasicBlock *FBB,
4066 ArrayRef<MachineOperand> Cond,
4067 const DebugLoc &DL, int *BytesAdded) const {
4068 // Shouldn't be a fall through.
4069 assert(TBB && "insertBranch must not be told to insert a fallthrough");
4070 assert((Cond.size() == 1 || Cond.size() == 0) &&
4071 "X86 branch conditions have one component!");
4072 assert(!BytesAdded && "code size not handled");
4073
4074 if (Cond.empty()) {
4075 // Unconditional branch?
4076 assert(!FBB && "Unconditional branch with multiple successors!");
4077 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JMP_1)).addMBB(MBB: TBB);
4078 return 1;
4079 }
4080
4081 // If FBB is null, it is implied to be a fall-through block.
4082 bool FallThru = FBB == nullptr;
4083
4084 // Conditional branch.
4085 unsigned Count = 0;
4086 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4087 switch (CC) {
4088 case X86::COND_NE_OR_P:
4089 // Synthesize NE_OR_P with two branches.
4090 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JCC_1)).addMBB(MBB: TBB).addImm(Val: X86::COND_NE);
4091 ++Count;
4092 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JCC_1)).addMBB(MBB: TBB).addImm(Val: X86::COND_P);
4093 ++Count;
4094 break;
4095 case X86::COND_E_AND_NP:
4096 // Use the next block of MBB as FBB if it is null.
4097 if (FBB == nullptr) {
4098 FBB = getFallThroughMBB(MBB: &MBB, TBB);
4099 assert(FBB && "MBB cannot be the last block in function when the false "
4100 "body is a fall-through.");
4101 }
4102 // Synthesize COND_E_AND_NP with two branches.
4103 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JCC_1)).addMBB(MBB: FBB).addImm(Val: X86::COND_NE);
4104 ++Count;
4105 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JCC_1)).addMBB(MBB: TBB).addImm(Val: X86::COND_NP);
4106 ++Count;
4107 break;
4108 default: {
4109 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JCC_1)).addMBB(MBB: TBB).addImm(Val: CC);
4110 ++Count;
4111 }
4112 }
4113 if (!FallThru) {
4114 // Two-way Conditional branch. Insert the second branch.
4115 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: X86::JMP_1)).addMBB(MBB: FBB);
4116 ++Count;
4117 }
4118 return Count;
4119}
4120
4121bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
4122 ArrayRef<MachineOperand> Cond,
4123 Register DstReg, Register TrueReg,
4124 Register FalseReg, int &CondCycles,
4125 int &TrueCycles, int &FalseCycles) const {
4126 // Not all subtargets have cmov instructions.
4127 if (!Subtarget.canUseCMOV())
4128 return false;
4129 if (Cond.size() != 1)
4130 return false;
4131 // We cannot do the composite conditions, at least not in SSA form.
4132 if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
4133 return false;
4134
4135 // Check register classes.
4136 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4137 const TargetRegisterClass *RC =
4138 RI.getCommonSubClass(A: MRI.getRegClass(Reg: TrueReg), B: MRI.getRegClass(Reg: FalseReg));
4139 if (!RC)
4140 return false;
4141
4142 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4143 if (X86::GR16RegClass.hasSubClassEq(RC) ||
4144 X86::GR32RegClass.hasSubClassEq(RC) ||
4145 X86::GR64RegClass.hasSubClassEq(RC)) {
4146 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4147 // Bridge. Probably Ivy Bridge as well.
4148 CondCycles = 2;
4149 TrueCycles = 2;
4150 FalseCycles = 2;
4151 return true;
4152 }
4153
4154 // Can't do vectors.
4155 return false;
4156}
4157
4158void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
4159 MachineBasicBlock::iterator I,
4160 const DebugLoc &DL, Register DstReg,
4161 ArrayRef<MachineOperand> Cond, Register TrueReg,
4162 Register FalseReg) const {
4163 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4164 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
4165 const TargetRegisterClass &RC = *MRI.getRegClass(Reg: DstReg);
4166 assert(Cond.size() == 1 && "Invalid Cond array");
4167 unsigned Opc =
4168 X86::getCMovOpcode(RegBytes: TRI.getRegSizeInBits(RC) / 8,
4169 HasMemoryOperand: false /*HasMemoryOperand*/, HasNDD: Subtarget.hasNDD());
4170 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Opc), DestReg: DstReg)
4171 .addReg(RegNo: FalseReg)
4172 .addReg(RegNo: TrueReg)
4173 .addImm(Val: Cond[0].getImm());
4174}
4175
4176/// Test if the given register is a physical h register.
4177static bool isHReg(Register Reg) {
4178 return X86::GR8_ABCD_HRegClass.contains(Reg);
4179}
4180
4181// Try and copy between VR128/VR64 and GR64 registers.
4182static unsigned CopyToFromAsymmetricReg(Register DestReg, Register SrcReg,
4183 const X86Subtarget &Subtarget) {
4184 bool HasAVX = Subtarget.hasAVX();
4185 bool HasAVX512 = Subtarget.hasAVX512();
4186 bool HasEGPR = Subtarget.hasEGPR();
4187
4188 // SrcReg(MaskReg) -> DestReg(GR64)
4189 // SrcReg(MaskReg) -> DestReg(GR32)
4190
4191 // All KMASK RegClasses hold the same k registers, can be tested against
4192 // anyone.
4193 if (X86::VK16RegClass.contains(Reg: SrcReg)) {
4194 if (X86::GR64RegClass.contains(Reg: DestReg)) {
4195 assert(Subtarget.hasBWI());
4196 return HasEGPR ? X86::KMOVQrk_EVEX : X86::KMOVQrk;
4197 }
4198 if (X86::GR32RegClass.contains(Reg: DestReg))
4199 return Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVDrk_EVEX : X86::KMOVDrk)
4200 : (HasEGPR ? X86::KMOVWrk_EVEX : X86::KMOVWrk);
4201 }
4202
4203 // SrcReg(GR64) -> DestReg(MaskReg)
4204 // SrcReg(GR32) -> DestReg(MaskReg)
4205
4206 // All KMASK RegClasses hold the same k registers, can be tested against
4207 // anyone.
4208 if (X86::VK16RegClass.contains(Reg: DestReg)) {
4209 if (X86::GR64RegClass.contains(Reg: SrcReg)) {
4210 assert(Subtarget.hasBWI());
4211 return HasEGPR ? X86::KMOVQkr_EVEX : X86::KMOVQkr;
4212 }
4213 if (X86::GR32RegClass.contains(Reg: SrcReg))
4214 return Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVDkr_EVEX : X86::KMOVDkr)
4215 : (HasEGPR ? X86::KMOVWkr_EVEX : X86::KMOVWkr);
4216 }
4217
4218 // SrcReg(VR128) -> DestReg(GR64)
4219 // SrcReg(VR64) -> DestReg(GR64)
4220 // SrcReg(GR64) -> DestReg(VR128)
4221 // SrcReg(GR64) -> DestReg(VR64)
4222
4223 if (X86::GR64RegClass.contains(Reg: DestReg)) {
4224 if (X86::VR128XRegClass.contains(Reg: SrcReg))
4225 // Copy from a VR128 register to a GR64 register.
4226 return HasAVX512 ? X86::VMOVPQIto64Zrr
4227 : HasAVX ? X86::VMOVPQIto64rr
4228 : X86::MOVPQIto64rr;
4229 if (X86::VR64RegClass.contains(Reg: SrcReg))
4230 // Copy from a VR64 register to a GR64 register.
4231 return X86::MMX_MOVD64from64rr;
4232 } else if (X86::GR64RegClass.contains(Reg: SrcReg)) {
4233 // Copy from a GR64 register to a VR128 register.
4234 if (X86::VR128XRegClass.contains(Reg: DestReg))
4235 return HasAVX512 ? X86::VMOV64toPQIZrr
4236 : HasAVX ? X86::VMOV64toPQIrr
4237 : X86::MOV64toPQIrr;
4238 // Copy from a GR64 register to a VR64 register.
4239 if (X86::VR64RegClass.contains(Reg: DestReg))
4240 return X86::MMX_MOVD64to64rr;
4241 }
4242
4243 // SrcReg(VR128) -> DestReg(GR32)
4244 // SrcReg(GR32) -> DestReg(VR128)
4245
4246 if (X86::GR32RegClass.contains(Reg: DestReg) &&
4247 X86::VR128XRegClass.contains(Reg: SrcReg))
4248 // Copy from a VR128 register to a GR32 register.
4249 return HasAVX512 ? X86::VMOVPDI2DIZrr
4250 : HasAVX ? X86::VMOVPDI2DIrr
4251 : X86::MOVPDI2DIrr;
4252
4253 if (X86::VR128XRegClass.contains(Reg: DestReg) &&
4254 X86::GR32RegClass.contains(Reg: SrcReg))
4255 // Copy from a GR32 register to a VR128 register.
4256 return HasAVX512 ? X86::VMOVDI2PDIZrr
4257 : HasAVX ? X86::VMOVDI2PDIrr
4258 : X86::MOVDI2PDIrr;
4259
4260 return 0;
4261}
4262
4263void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4264 MachineBasicBlock::iterator MI,
4265 const DebugLoc &DL, Register DestReg,
4266 Register SrcReg, bool KillSrc,
4267 bool RenamableDest, bool RenamableSrc) const {
4268 // First deal with the normal symmetric copies.
4269 bool HasAVX = Subtarget.hasAVX();
4270 bool HasVLX = Subtarget.hasVLX();
4271 bool HasEGPR = Subtarget.hasEGPR();
4272 unsigned Opc = 0;
4273 if (X86::GR64RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4274 Opc = X86::MOV64rr;
4275 else if (X86::GR32RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4276 Opc = X86::MOV32rr;
4277 else if (X86::GR16RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4278 Opc = X86::MOV16rr;
4279 else if (X86::GR8RegClass.contains(Reg1: DestReg, Reg2: SrcReg)) {
4280 // Copying to or from a physical H register on x86-64 requires a NOREX
4281 // move. Otherwise use a normal move.
4282 if ((isHReg(Reg: DestReg) || isHReg(Reg: SrcReg)) && Subtarget.is64Bit()) {
4283 Opc = X86::MOV8rr_NOREX;
4284 // Both operands must be encodable without an REX prefix.
4285 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4286 "8-bit H register can not be copied outside GR8_NOREX");
4287 } else
4288 Opc = X86::MOV8rr;
4289 } else if (X86::VR64RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4290 Opc = X86::MMX_MOVQ64rr;
4291 else if (X86::VR128XRegClass.contains(Reg1: DestReg, Reg2: SrcReg)) {
4292 if (HasVLX)
4293 Opc = X86::VMOVAPSZ128rr;
4294 else if (X86::VR128RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4295 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
4296 else {
4297 // If this an extended register and we don't have VLX we need to use a
4298 // 512-bit move.
4299 Opc = X86::VMOVAPSZrr;
4300 const TargetRegisterInfo *TRI = &getRegisterInfo();
4301 DestReg =
4302 TRI->getMatchingSuperReg(Reg: DestReg, SubIdx: X86::sub_xmm, RC: &X86::VR512RegClass);
4303 SrcReg =
4304 TRI->getMatchingSuperReg(Reg: SrcReg, SubIdx: X86::sub_xmm, RC: &X86::VR512RegClass);
4305 }
4306 } else if (X86::VR256XRegClass.contains(Reg1: DestReg, Reg2: SrcReg)) {
4307 if (HasVLX)
4308 Opc = X86::VMOVAPSZ256rr;
4309 else if (X86::VR256RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4310 Opc = X86::VMOVAPSYrr;
4311 else {
4312 // If this an extended register and we don't have VLX we need to use a
4313 // 512-bit move.
4314 Opc = X86::VMOVAPSZrr;
4315 const TargetRegisterInfo *TRI = &getRegisterInfo();
4316 DestReg =
4317 TRI->getMatchingSuperReg(Reg: DestReg, SubIdx: X86::sub_ymm, RC: &X86::VR512RegClass);
4318 SrcReg =
4319 TRI->getMatchingSuperReg(Reg: SrcReg, SubIdx: X86::sub_ymm, RC: &X86::VR512RegClass);
4320 }
4321 } else if (X86::VR512RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4322 Opc = X86::VMOVAPSZrr;
4323 // All KMASK RegClasses hold the same k registers, can be tested against
4324 // anyone.
4325 else if (X86::VK16RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
4326 Opc = Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVQkk_EVEX : X86::KMOVQkk)
4327 : (HasEGPR ? X86::KMOVWkk_EVEX : X86::KMOVWkk);
4328
4329 if (!Opc)
4330 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
4331
4332 if (Opc) {
4333 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: get(Opcode: Opc), DestReg)
4334 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc));
4335 return;
4336 }
4337
4338 if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
4339 // FIXME: We use a fatal error here because historically LLVM has tried
4340 // lower some of these physreg copies and we want to ensure we get
4341 // reasonable bug reports if someone encounters a case no other testing
4342 // found. This path should be removed after the LLVM 7 release.
4343 report_fatal_error(reason: "Unable to copy EFLAGS physical register!");
4344 }
4345
4346 LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
4347 << RI.getName(DestReg) << '\n');
4348 report_fatal_error(reason: "Cannot emit physreg copy instruction");
4349}
4350
4351std::optional<DestSourcePair>
4352X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
4353 if (MI.isMoveReg()) {
4354 // FIXME: Dirty hack for apparent invariant that doesn't hold when
4355 // subreg_to_reg is coalesced with ordinary copies, such that the bits that
4356 // were asserted as 0 are now undef.
4357 if (MI.getOperand(i: 0).isUndef() && MI.getOperand(i: 0).getSubReg())
4358 return std::nullopt;
4359
4360 return DestSourcePair{MI.getOperand(i: 0), MI.getOperand(i: 1)};
4361 }
4362 return std::nullopt;
4363}
4364
4365static unsigned getLoadStoreOpcodeForFP16(bool Load, const X86Subtarget &STI) {
4366 if (STI.hasFP16())
4367 return Load ? X86::VMOVSHZrm_alt : X86::VMOVSHZmr;
4368 if (Load)
4369 return X86::MOVSHPrm;
4370 return X86::MOVSHPmr;
4371}
4372
4373static unsigned getLoadStoreRegOpcode(Register Reg,
4374 const TargetRegisterClass *RC,
4375 bool IsStackAligned,
4376 const X86Subtarget &STI, bool Load) {
4377 bool HasAVX = STI.hasAVX();
4378 bool HasAVX512 = STI.hasAVX512();
4379 bool HasVLX = STI.hasVLX();
4380 bool HasEGPR = STI.hasEGPR();
4381
4382 assert(RC != nullptr && "Invalid target register class");
4383 switch (STI.getRegisterInfo()->getSpillSize(RC: *RC)) {
4384 default:
4385 llvm_unreachable("Unknown spill size");
4386 case 1:
4387 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
4388 if (STI.is64Bit())
4389 // Copying to or from a physical H register on x86-64 requires a NOREX
4390 // move. Otherwise use a normal move.
4391 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4392 return Load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4393 return Load ? X86::MOV8rm : X86::MOV8mr;
4394 case 2:
4395 if (X86::VK16RegClass.hasSubClassEq(RC))
4396 return Load ? (HasEGPR ? X86::KMOVWkm_EVEX : X86::KMOVWkm)
4397 : (HasEGPR ? X86::KMOVWmk_EVEX : X86::KMOVWmk);
4398 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4399 return Load ? X86::MOV16rm : X86::MOV16mr;
4400 case 4:
4401 if (X86::GR32RegClass.hasSubClassEq(RC))
4402 return Load ? X86::MOV32rm : X86::MOV32mr;
4403 if (X86::FR32XRegClass.hasSubClassEq(RC))
4404 return Load ? (HasAVX512 ? X86::VMOVSSZrm_alt
4405 : HasAVX ? X86::VMOVSSrm_alt
4406 : X86::MOVSSrm_alt)
4407 : (HasAVX512 ? X86::VMOVSSZmr
4408 : HasAVX ? X86::VMOVSSmr
4409 : X86::MOVSSmr);
4410 if (X86::RFP32RegClass.hasSubClassEq(RC))
4411 return Load ? X86::LD_Fp32m : X86::ST_Fp32m;
4412 if (X86::VK32RegClass.hasSubClassEq(RC)) {
4413 assert(STI.hasBWI() && "KMOVD requires BWI");
4414 return Load ? (HasEGPR ? X86::KMOVDkm_EVEX : X86::KMOVDkm)
4415 : (HasEGPR ? X86::KMOVDmk_EVEX : X86::KMOVDmk);
4416 }
4417 // All of these mask pair classes have the same spill size, the same kind
4418 // of kmov instructions can be used with all of them.
4419 if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
4420 X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
4421 X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
4422 X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
4423 X86::VK16PAIRRegClass.hasSubClassEq(RC))
4424 return Load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
4425 if (X86::FR16RegClass.hasSubClassEq(RC) ||
4426 X86::FR16XRegClass.hasSubClassEq(RC))
4427 return getLoadStoreOpcodeForFP16(Load, STI);
4428 llvm_unreachable("Unknown 4-byte regclass");
4429 case 8:
4430 if (X86::GR64RegClass.hasSubClassEq(RC))
4431 return Load ? X86::MOV64rm : X86::MOV64mr;
4432 if (X86::FR64XRegClass.hasSubClassEq(RC))
4433 return Load ? (HasAVX512 ? X86::VMOVSDZrm_alt
4434 : HasAVX ? X86::VMOVSDrm_alt
4435 : X86::MOVSDrm_alt)
4436 : (HasAVX512 ? X86::VMOVSDZmr
4437 : HasAVX ? X86::VMOVSDmr
4438 : X86::MOVSDmr);
4439 if (X86::VR64RegClass.hasSubClassEq(RC))
4440 return Load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4441 if (X86::RFP64RegClass.hasSubClassEq(RC))
4442 return Load ? X86::LD_Fp64m : X86::ST_Fp64m;
4443 if (X86::VK64RegClass.hasSubClassEq(RC)) {
4444 assert(STI.hasBWI() && "KMOVQ requires BWI");
4445 return Load ? (HasEGPR ? X86::KMOVQkm_EVEX : X86::KMOVQkm)
4446 : (HasEGPR ? X86::KMOVQmk_EVEX : X86::KMOVQmk);
4447 }
4448 llvm_unreachable("Unknown 8-byte regclass");
4449 case 10:
4450 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
4451 return Load ? X86::LD_Fp80m : X86::ST_FpP80m;
4452 case 16: {
4453 if (X86::VR128XRegClass.hasSubClassEq(RC)) {
4454 // If stack is realigned we can use aligned stores.
4455 if (IsStackAligned)
4456 return Load ? (HasVLX ? X86::VMOVAPSZ128rm
4457 : HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX
4458 : HasAVX ? X86::VMOVAPSrm
4459 : X86::MOVAPSrm)
4460 : (HasVLX ? X86::VMOVAPSZ128mr
4461 : HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX
4462 : HasAVX ? X86::VMOVAPSmr
4463 : X86::MOVAPSmr);
4464 else
4465 return Load ? (HasVLX ? X86::VMOVUPSZ128rm
4466 : HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX
4467 : HasAVX ? X86::VMOVUPSrm
4468 : X86::MOVUPSrm)
4469 : (HasVLX ? X86::VMOVUPSZ128mr
4470 : HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX
4471 : HasAVX ? X86::VMOVUPSmr
4472 : X86::MOVUPSmr);
4473 }
4474 llvm_unreachable("Unknown 16-byte regclass");
4475 }
4476 case 32:
4477 assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
4478 // If stack is realigned we can use aligned stores.
4479 if (IsStackAligned)
4480 return Load ? (HasVLX ? X86::VMOVAPSZ256rm
4481 : HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX
4482 : X86::VMOVAPSYrm)
4483 : (HasVLX ? X86::VMOVAPSZ256mr
4484 : HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX
4485 : X86::VMOVAPSYmr);
4486 else
4487 return Load ? (HasVLX ? X86::VMOVUPSZ256rm
4488 : HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX
4489 : X86::VMOVUPSYrm)
4490 : (HasVLX ? X86::VMOVUPSZ256mr
4491 : HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX
4492 : X86::VMOVUPSYmr);
4493 case 64:
4494 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
4495 assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
4496 if (IsStackAligned)
4497 return Load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4498 else
4499 return Load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4500 case 1024:
4501 assert(X86::TILERegClass.hasSubClassEq(RC) && "Unknown 1024-byte regclass");
4502 assert(STI.hasAMXTILE() && "Using 8*1024-bit register requires AMX-TILE");
4503#define GET_EGPR_IF_ENABLED(OPC) (STI.hasEGPR() ? OPC##_EVEX : OPC)
4504 return Load ? GET_EGPR_IF_ENABLED(X86::TILELOADD)
4505 : GET_EGPR_IF_ENABLED(X86::TILESTORED);
4506#undef GET_EGPR_IF_ENABLED
4507 }
4508}
4509
4510std::optional<ExtAddrMode>
4511X86InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI) const {
4512 int MemRefBegin = X86II::getMemoryOperandIdx(Desc: MemI.getDesc());
4513 if (MemRefBegin < 0)
4514 return std::nullopt;
4515
4516 auto &BaseOp = MemI.getOperand(i: MemRefBegin + X86::AddrBaseReg);
4517 if (!BaseOp.isReg()) // Can be an MO_FrameIndex
4518 return std::nullopt;
4519
4520 const MachineOperand &DispMO = MemI.getOperand(i: MemRefBegin + X86::AddrDisp);
4521 // Displacement can be symbolic
4522 if (!DispMO.isImm())
4523 return std::nullopt;
4524
4525 ExtAddrMode AM;
4526 AM.BaseReg = BaseOp.getReg();
4527 AM.ScaledReg = MemI.getOperand(i: MemRefBegin + X86::AddrIndexReg).getReg();
4528 AM.Scale = MemI.getOperand(i: MemRefBegin + X86::AddrScaleAmt).getImm();
4529 AM.Displacement = DispMO.getImm();
4530 return AM;
4531}
4532
4533bool X86InstrInfo::verifyInstruction(const MachineInstr &MI,
4534 StringRef &ErrInfo) const {
4535 std::optional<ExtAddrMode> AMOrNone = getAddrModeFromMemoryOp(MemI: MI);
4536 if (!AMOrNone)
4537 return true;
4538
4539 ExtAddrMode AM = *AMOrNone;
4540 assert(AM.Form == ExtAddrMode::Formula::Basic);
4541 if (AM.ScaledReg != X86::NoRegister) {
4542 switch (AM.Scale) {
4543 case 1:
4544 case 2:
4545 case 4:
4546 case 8:
4547 break;
4548 default:
4549 ErrInfo = "Scale factor in address must be 1, 2, 4 or 8";
4550 return false;
4551 }
4552 }
4553 if (!isInt<32>(x: AM.Displacement)) {
4554 ErrInfo = "Displacement in address must fit into 32-bit signed "
4555 "integer";
4556 return false;
4557 }
4558
4559 return true;
4560}
4561
4562bool X86InstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
4563 const Register Reg,
4564 int64_t &ImmVal) const {
4565 Register MovReg = Reg;
4566 const MachineInstr *MovMI = &MI;
4567
4568 // Follow use-def for SUBREG_TO_REG to find the real move immediate
4569 // instruction. It is quite common for x86-64.
4570 if (MI.isSubregToReg()) {
4571 // We use following pattern to setup 64b immediate.
4572 // %8:gr32 = MOV32r0 implicit-def dead $eflags
4573 // %6:gr64 = SUBREG_TO_REG killed %8:gr32, %subreg.sub_32bit
4574 unsigned SubIdx = MI.getOperand(i: 2).getImm();
4575 MovReg = MI.getOperand(i: 1).getReg();
4576 if (SubIdx != X86::sub_32bit)
4577 return false;
4578 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
4579 MovMI = MRI.getUniqueVRegDef(Reg: MovReg);
4580 if (!MovMI)
4581 return false;
4582 }
4583
4584 if (MovMI->getOpcode() == X86::MOV32r0 &&
4585 MovMI->getOperand(i: 0).getReg() == MovReg) {
4586 ImmVal = 0;
4587 return true;
4588 }
4589
4590 if (MovMI->getOpcode() != X86::MOV32ri &&
4591 MovMI->getOpcode() != X86::MOV64ri &&
4592 MovMI->getOpcode() != X86::MOV32ri64 && MovMI->getOpcode() != X86::MOV8ri)
4593 return false;
4594 // Mov Src can be a global address.
4595 if (!MovMI->getOperand(i: 1).isImm() || MovMI->getOperand(i: 0).getReg() != MovReg)
4596 return false;
4597 ImmVal = MovMI->getOperand(i: 1).getImm();
4598 return true;
4599}
4600
4601bool X86InstrInfo::preservesZeroValueInReg(const MachineInstr *MI,
4602 const Register NullValueReg) const {
4603 if (!MI->modifiesRegister(Reg: NullValueReg, TRI: &RI))
4604 return true;
4605 switch (MI->getOpcode()) {
4606 // Shift right/left of a null unto itself is still a null, i.e. rax = shl rax
4607 // X.
4608 case X86::SHR64ri:
4609 case X86::SHR32ri:
4610 case X86::SHL64ri:
4611 case X86::SHL32ri:
4612 assert(MI->getOperand(0).isDef() && MI->getOperand(1).isUse() &&
4613 "expected for shift opcode!");
4614 return MI->getOperand(i: 0).getReg() == NullValueReg &&
4615 MI->getOperand(i: 1).getReg() == NullValueReg;
4616 // Zero extend of a sub-reg of NullValueReg into itself does not change the
4617 // null value.
4618 case X86::MOV32rr:
4619 return llvm::all_of(Range: MI->operands(), P: [&](const MachineOperand &MO) {
4620 return RI.isSubRegisterEq(RegA: NullValueReg, RegB: MO.getReg());
4621 });
4622 default:
4623 return false;
4624 }
4625 llvm_unreachable("Should be handled above!");
4626}
4627
4628bool X86InstrInfo::getMemOperandsWithOffsetWidth(
4629 const MachineInstr &MemOp, SmallVectorImpl<const MachineOperand *> &BaseOps,
4630 int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width) const {
4631 int MemRefBegin = X86II::getMemoryOperandIdx(Desc: MemOp.getDesc());
4632 if (MemRefBegin < 0)
4633 return false;
4634
4635 const MachineOperand *BaseOp =
4636 &MemOp.getOperand(i: MemRefBegin + X86::AddrBaseReg);
4637 if (!BaseOp->isReg()) // Can be an MO_FrameIndex
4638 return false;
4639
4640 if (MemOp.getOperand(i: MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
4641 return false;
4642
4643 if (MemOp.getOperand(i: MemRefBegin + X86::AddrIndexReg).getReg() !=
4644 X86::NoRegister)
4645 return false;
4646
4647 const MachineOperand &DispMO = MemOp.getOperand(i: MemRefBegin + X86::AddrDisp);
4648
4649 // Displacement can be symbolic
4650 if (!DispMO.isImm())
4651 return false;
4652
4653 Offset = DispMO.getImm();
4654
4655 if (!BaseOp->isReg())
4656 return false;
4657
4658 OffsetIsScalable = false;
4659 // FIXME: Relying on memoperands() may not be right thing to do here. Check
4660 // with X86 maintainers, and fix it accordingly. For now, it is ok, since
4661 // there is no use of `Width` for X86 back-end at the moment.
4662 Width = !MemOp.memoperands_empty() ? MemOp.memoperands().front()->getSize()
4663 : LocationSize::precise(Value: 0);
4664 BaseOps.push_back(Elt: BaseOp);
4665 return true;
4666}
4667
4668static unsigned getStoreRegOpcode(Register SrcReg,
4669 const TargetRegisterClass *RC,
4670 bool IsStackAligned,
4671 const X86Subtarget &STI) {
4672 return getLoadStoreRegOpcode(Reg: SrcReg, RC, IsStackAligned, STI, Load: false);
4673}
4674
4675static unsigned getLoadRegOpcode(Register DestReg,
4676 const TargetRegisterClass *RC,
4677 bool IsStackAligned, const X86Subtarget &STI) {
4678 return getLoadStoreRegOpcode(Reg: DestReg, RC, IsStackAligned, STI, Load: true);
4679}
4680
4681static bool isAMXOpcode(unsigned Opc) {
4682 switch (Opc) {
4683 default:
4684 return false;
4685 case X86::TILELOADD:
4686 case X86::TILESTORED:
4687 case X86::TILELOADD_EVEX:
4688 case X86::TILESTORED_EVEX:
4689 return true;
4690 }
4691}
4692
4693void X86InstrInfo::loadStoreTileReg(MachineBasicBlock &MBB,
4694 MachineBasicBlock::iterator MI,
4695 unsigned Opc, Register Reg, int FrameIdx,
4696 bool isKill) const {
4697 switch (Opc) {
4698 default:
4699 llvm_unreachable("Unexpected special opcode!");
4700 case X86::TILESTORED:
4701 case X86::TILESTORED_EVEX: {
4702 // tilestored %tmm, (%sp, %idx)
4703 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
4704 Register VirtReg = RegInfo.createVirtualRegister(RegClass: &X86::GR64_NOSPRegClass);
4705 BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: get(Opcode: X86::MOV64ri), DestReg: VirtReg).addImm(Val: 64);
4706 MachineInstr *NewMI =
4707 addFrameReference(MIB: BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: get(Opcode: Opc)), FI: FrameIdx)
4708 .addReg(RegNo: Reg, Flags: getKillRegState(B: isKill));
4709 MachineOperand &MO = NewMI->getOperand(i: X86::AddrIndexReg);
4710 MO.setReg(VirtReg);
4711 MO.setIsKill(true);
4712 break;
4713 }
4714 case X86::TILELOADD:
4715 case X86::TILELOADD_EVEX: {
4716 // tileloadd (%sp, %idx), %tmm
4717 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
4718 Register VirtReg = RegInfo.createVirtualRegister(RegClass: &X86::GR64_NOSPRegClass);
4719 BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: get(Opcode: X86::MOV64ri), DestReg: VirtReg).addImm(Val: 64);
4720 MachineInstr *NewMI = addFrameReference(
4721 MIB: BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: get(Opcode: Opc), DestReg: Reg), FI: FrameIdx);
4722 MachineOperand &MO = NewMI->getOperand(i: 1 + X86::AddrIndexReg);
4723 MO.setReg(VirtReg);
4724 MO.setIsKill(true);
4725 break;
4726 }
4727 }
4728}
4729
4730void X86InstrInfo::storeRegToStackSlot(
4731 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
4732 bool isKill, int FrameIdx, const TargetRegisterClass *RC,
4733
4734 Register VReg, MachineInstr::MIFlag Flags) const {
4735 const MachineFunction &MF = *MBB.getParent();
4736 const MachineFrameInfo &MFI = MF.getFrameInfo();
4737 assert(MFI.getObjectSize(FrameIdx) >= RI.getSpillSize(*RC) &&
4738 "Stack slot too small for store");
4739
4740 unsigned Alignment = std::max<uint32_t>(a: RI.getSpillSize(RC: *RC), b: 16);
4741 bool isAligned =
4742 (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
4743 (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(ObjectIdx: FrameIdx));
4744
4745 unsigned Opc = getStoreRegOpcode(SrcReg, RC, IsStackAligned: isAligned, STI: Subtarget);
4746 if (isAMXOpcode(Opc))
4747 loadStoreTileReg(MBB, MI, Opc, Reg: SrcReg, FrameIdx, isKill);
4748 else
4749 addFrameReference(MIB: BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: get(Opcode: Opc)), FI: FrameIdx)
4750 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill))
4751 .setMIFlag(Flags);
4752}
4753
4754void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
4755 MachineBasicBlock::iterator MI,
4756 Register DestReg, int FrameIdx,
4757 const TargetRegisterClass *RC,
4758 Register VReg, unsigned SubReg,
4759 MachineInstr::MIFlag Flags) const {
4760 const MachineFunction &MF = *MBB.getParent();
4761 const MachineFrameInfo &MFI = MF.getFrameInfo();
4762 assert(MFI.getObjectSize(FrameIdx) >= RI.getSpillSize(*RC) &&
4763 "Load size exceeds stack slot");
4764 unsigned Alignment = std::max<uint32_t>(a: RI.getSpillSize(RC: *RC), b: 16);
4765 bool isAligned =
4766 (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
4767 (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(ObjectIdx: FrameIdx));
4768
4769 unsigned Opc = getLoadRegOpcode(DestReg, RC, IsStackAligned: isAligned, STI: Subtarget);
4770 if (isAMXOpcode(Opc))
4771 loadStoreTileReg(MBB, MI, Opc, Reg: DestReg, FrameIdx);
4772 else
4773 addFrameReference(MIB: BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: get(Opcode: Opc), DestReg), FI: FrameIdx)
4774 .setMIFlag(Flags);
4775}
4776
4777bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
4778 Register &SrcReg2, int64_t &CmpMask,
4779 int64_t &CmpValue) const {
4780 switch (MI.getOpcode()) {
4781 default:
4782 break;
4783 case X86::CMP64ri32:
4784 case X86::CMP32ri:
4785 case X86::CMP16ri:
4786 case X86::CMP8ri:
4787 SrcReg = MI.getOperand(i: 0).getReg();
4788 SrcReg2 = 0;
4789 if (MI.getOperand(i: 1).isImm()) {
4790 CmpMask = ~0;
4791 CmpValue = MI.getOperand(i: 1).getImm();
4792 } else {
4793 CmpMask = CmpValue = 0;
4794 }
4795 return true;
4796 // A SUB can be used to perform comparison.
4797 CASE_ND(SUB64rm)
4798 CASE_ND(SUB32rm)
4799 CASE_ND(SUB16rm)
4800 CASE_ND(SUB8rm)
4801 SrcReg = MI.getOperand(i: 1).getReg();
4802 SrcReg2 = 0;
4803 CmpMask = 0;
4804 CmpValue = 0;
4805 return true;
4806 CASE_ND(SUB64rr)
4807 CASE_ND(SUB32rr)
4808 CASE_ND(SUB16rr)
4809 CASE_ND(SUB8rr)
4810 SrcReg = MI.getOperand(i: 1).getReg();
4811 SrcReg2 = MI.getOperand(i: 2).getReg();
4812 CmpMask = 0;
4813 CmpValue = 0;
4814 return true;
4815 CASE_ND(SUB64ri32)
4816 CASE_ND(SUB32ri)
4817 CASE_ND(SUB16ri)
4818 CASE_ND(SUB8ri)
4819 SrcReg = MI.getOperand(i: 1).getReg();
4820 SrcReg2 = 0;
4821 if (MI.getOperand(i: 2).isImm()) {
4822 CmpMask = ~0;
4823 CmpValue = MI.getOperand(i: 2).getImm();
4824 } else {
4825 CmpMask = CmpValue = 0;
4826 }
4827 return true;
4828 case X86::CMP64rr:
4829 case X86::CMP32rr:
4830 case X86::CMP16rr:
4831 case X86::CMP8rr:
4832 SrcReg = MI.getOperand(i: 0).getReg();
4833 SrcReg2 = MI.getOperand(i: 1).getReg();
4834 CmpMask = 0;
4835 CmpValue = 0;
4836 return true;
4837 case X86::TEST8rr:
4838 case X86::TEST16rr:
4839 case X86::TEST32rr:
4840 case X86::TEST64rr:
4841 SrcReg = MI.getOperand(i: 0).getReg();
4842 if (MI.getOperand(i: 1).getReg() != SrcReg)
4843 return false;
4844 // Compare against zero.
4845 SrcReg2 = 0;
4846 CmpMask = ~0;
4847 CmpValue = 0;
4848 return true;
4849 case X86::TEST64ri32:
4850 case X86::TEST32ri:
4851 case X86::TEST16ri:
4852 case X86::TEST8ri:
4853 SrcReg = MI.getOperand(i: 0).getReg();
4854 SrcReg2 = 0;
4855 // Force identical compare.
4856 CmpMask = 0;
4857 CmpValue = 0;
4858 return true;
4859 }
4860 return false;
4861}
4862
4863bool X86InstrInfo::isRedundantFlagInstr(const MachineInstr &FlagI,
4864 Register SrcReg, Register SrcReg2,
4865 int64_t ImmMask, int64_t ImmValue,
4866 const MachineInstr &OI, bool *IsSwapped,
4867 int64_t *ImmDelta) const {
4868 switch (OI.getOpcode()) {
4869 case X86::CMP64rr:
4870 case X86::CMP32rr:
4871 case X86::CMP16rr:
4872 case X86::CMP8rr:
4873 CASE_ND(SUB64rr)
4874 CASE_ND(SUB32rr)
4875 CASE_ND(SUB16rr)
4876 CASE_ND(SUB8rr) {
4877 Register OISrcReg;
4878 Register OISrcReg2;
4879 int64_t OIMask;
4880 int64_t OIValue;
4881 if (!analyzeCompare(MI: OI, SrcReg&: OISrcReg, SrcReg2&: OISrcReg2, CmpMask&: OIMask, CmpValue&: OIValue) ||
4882 OIMask != ImmMask || OIValue != ImmValue)
4883 return false;
4884 if (SrcReg == OISrcReg && SrcReg2 == OISrcReg2) {
4885 *IsSwapped = false;
4886 return true;
4887 }
4888 if (SrcReg == OISrcReg2 && SrcReg2 == OISrcReg) {
4889 *IsSwapped = true;
4890 return true;
4891 }
4892 return false;
4893 }
4894 case X86::CMP64ri32:
4895 case X86::CMP32ri:
4896 case X86::CMP16ri:
4897 case X86::CMP8ri:
4898 case X86::TEST64ri32:
4899 case X86::TEST32ri:
4900 case X86::TEST16ri:
4901 case X86::TEST8ri:
4902 CASE_ND(SUB64ri32)
4903 CASE_ND(SUB32ri)
4904 CASE_ND(SUB16ri)
4905 CASE_ND(SUB8ri)
4906 case X86::TEST64rr:
4907 case X86::TEST32rr:
4908 case X86::TEST16rr:
4909 case X86::TEST8rr: {
4910 if (ImmMask != 0) {
4911 Register OISrcReg;
4912 Register OISrcReg2;
4913 int64_t OIMask;
4914 int64_t OIValue;
4915 if (analyzeCompare(MI: OI, SrcReg&: OISrcReg, SrcReg2&: OISrcReg2, CmpMask&: OIMask, CmpValue&: OIValue) &&
4916 SrcReg == OISrcReg && ImmMask == OIMask) {
4917 if (OIValue == ImmValue) {
4918 *ImmDelta = 0;
4919 return true;
4920 } else if (static_cast<uint64_t>(ImmValue) ==
4921 static_cast<uint64_t>(OIValue) - 1) {
4922 *ImmDelta = -1;
4923 return true;
4924 } else if (static_cast<uint64_t>(ImmValue) ==
4925 static_cast<uint64_t>(OIValue) + 1) {
4926 *ImmDelta = 1;
4927 return true;
4928 } else {
4929 return false;
4930 }
4931 }
4932 }
4933 return FlagI.isIdenticalTo(Other: OI);
4934 }
4935 default:
4936 return false;
4937 }
4938}
4939
4940inline static bool isCmpRedundantAfterLTZCNT(Register SrcReg, Register SrcReg2,
4941 int64_t ImmMask, int64_t ImmValue,
4942 const MachineInstr &OI) {
4943 switch (OI.getOpcode()) {
4944 default:
4945 return false;
4946 case X86::LZCNT16rr:
4947 case X86::LZCNT32rr:
4948 case X86::LZCNT64rr:
4949 case X86::TZCNT16rr:
4950 case X86::TZCNT32rr:
4951 case X86::TZCNT64rr: {
4952 if (ImmMask != 0 && !SrcReg2.isValid() && ImmValue == 1 &&
4953 OI.getOperand(i: 1).isReg() && SrcReg == OI.getOperand(i: 1).getReg()) {
4954 return true;
4955 }
4956 return false;
4957 }
4958 }
4959}
4960
4961#define CASE_EVEX(OP) \
4962 case X86::OP: \
4963 case X86::OP##_EVEX:
4964
4965/// Check whether the definition can be converted
4966/// to remove a comparison against zero.
4967inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag,
4968 bool &ClearsOverflowFlag) {
4969 NoSignFlag = false;
4970 ClearsOverflowFlag = false;
4971
4972 // "ELF Handling for Thread-Local Storage" specifies that x86-64 GOTTPOFF, and
4973 // i386 GOTNTPOFF/INDNTPOFF relocations can convert an ADD to a LEA during
4974 // Initial Exec to Local Exec relaxation. In these cases, we must not depend
4975 // on the EFLAGS modification of ADD actually happening in the final binary.
4976 if (MI.getOpcode() == X86::ADD64rm || MI.getOpcode() == X86::ADD32rm) {
4977 unsigned Flags = MI.getOperand(i: 5).getTargetFlags();
4978 if (Flags == X86II::MO_GOTTPOFF || Flags == X86II::MO_INDNTPOFF ||
4979 Flags == X86II::MO_GOTNTPOFF)
4980 return false;
4981 }
4982
4983 switch (MI.getOpcode()) {
4984 default:
4985 return false;
4986
4987 // The shift instructions only modify ZF if their shift count is non-zero.
4988 // N.B.: The processor truncates the shift count depending on the encoding.
4989 CASE_ND(SAR8ri)
4990 CASE_ND(SAR16ri)
4991 CASE_ND(SAR32ri)
4992 CASE_ND(SAR64ri)
4993 CASE_ND(SHR8ri)
4994 CASE_ND(SHR16ri)
4995 CASE_ND(SHR32ri)
4996 CASE_ND(SHR64ri)
4997 return getTruncatedShiftCount(MI, ShiftAmtOperandIdx: 2) != 0;
4998
4999 // Some left shift instructions can be turned into LEA instructions but only
5000 // if their flags aren't used. Avoid transforming such instructions.
5001 CASE_ND(SHL8ri)
5002 CASE_ND(SHL16ri)
5003 CASE_ND(SHL32ri)
5004 CASE_ND(SHL64ri) {
5005 unsigned ShAmt = getTruncatedShiftCount(MI, ShiftAmtOperandIdx: 2);
5006 // Converting to LEA only pays off when the shifted operand stays live,
5007 // since it spares a register copy; when the shift is the operand's only
5008 // user, reusing the flags is strictly better.
5009 if (isTruncatedShiftCountForLEA(ShAmt)) {
5010 Register SrcReg = MI.getOperand(i: 1).getReg();
5011 const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
5012 if (!SrcReg.isVirtual() || !MRI.hasOneNonDBGUse(RegNo: SrcReg))
5013 return false;
5014 }
5015 return ShAmt != 0;
5016 }
5017
5018 CASE_ND(SHRD16rri8)
5019 CASE_ND(SHRD32rri8)
5020 CASE_ND(SHRD64rri8)
5021 CASE_ND(SHLD16rri8)
5022 CASE_ND(SHLD32rri8)
5023 CASE_ND(SHLD64rri8)
5024 return getTruncatedShiftCount(MI, ShiftAmtOperandIdx: 3) != 0;
5025
5026 CASE_ND(SUB64ri32)
5027 CASE_ND(SUB32ri)
5028 CASE_ND(SUB16ri)
5029 CASE_ND(SUB8ri)
5030 CASE_ND(SUB64rr)
5031 CASE_ND(SUB32rr)
5032 CASE_ND(SUB16rr)
5033 CASE_ND(SUB8rr)
5034 CASE_ND(SUB64rm)
5035 CASE_ND(SUB32rm)
5036 CASE_ND(SUB16rm)
5037 CASE_ND(SUB8rm)
5038 CASE_ND(DEC64r)
5039 CASE_ND(DEC32r)
5040 CASE_ND(DEC16r)
5041 CASE_ND(DEC8r)
5042 CASE_ND(ADD64ri32)
5043 CASE_ND(ADD32ri)
5044 CASE_ND(ADD16ri)
5045 CASE_ND(ADD8ri)
5046 CASE_ND(ADD64rr)
5047 CASE_ND(ADD32rr)
5048 CASE_ND(ADD16rr)
5049 CASE_ND(ADD8rr)
5050 CASE_ND(ADD64rm)
5051 CASE_ND(ADD32rm)
5052 CASE_ND(ADD16rm)
5053 CASE_ND(ADD8rm)
5054 CASE_ND(INC64r)
5055 CASE_ND(INC32r)
5056 CASE_ND(INC16r)
5057 CASE_ND(INC8r)
5058 CASE_ND(ADC64ri32)
5059 CASE_ND(ADC32ri)
5060 CASE_ND(ADC16ri)
5061 CASE_ND(ADC8ri)
5062 CASE_ND(ADC64rr)
5063 CASE_ND(ADC32rr)
5064 CASE_ND(ADC16rr)
5065 CASE_ND(ADC8rr)
5066 CASE_ND(ADC64rm)
5067 CASE_ND(ADC32rm)
5068 CASE_ND(ADC16rm)
5069 CASE_ND(ADC8rm)
5070 CASE_ND(SBB64ri32)
5071 CASE_ND(SBB32ri)
5072 CASE_ND(SBB16ri)
5073 CASE_ND(SBB8ri)
5074 CASE_ND(SBB64rr)
5075 CASE_ND(SBB32rr)
5076 CASE_ND(SBB16rr)
5077 CASE_ND(SBB8rr)
5078 CASE_ND(SBB64rm)
5079 CASE_ND(SBB32rm)
5080 CASE_ND(SBB16rm)
5081 CASE_ND(SBB8rm)
5082 CASE_ND(NEG8r)
5083 CASE_ND(NEG16r)
5084 CASE_ND(NEG32r)
5085 CASE_ND(NEG64r)
5086 case X86::LZCNT16rr:
5087 case X86::LZCNT16rm:
5088 case X86::LZCNT32rr:
5089 case X86::LZCNT32rm:
5090 case X86::LZCNT64rr:
5091 case X86::LZCNT64rm:
5092 case X86::POPCNT16rr:
5093 case X86::POPCNT16rm:
5094 case X86::POPCNT32rr:
5095 case X86::POPCNT32rm:
5096 case X86::POPCNT64rr:
5097 case X86::POPCNT64rm:
5098 case X86::TZCNT16rr:
5099 case X86::TZCNT16rm:
5100 case X86::TZCNT32rr:
5101 case X86::TZCNT32rm:
5102 case X86::TZCNT64rr:
5103 case X86::TZCNT64rm:
5104 return true;
5105 CASE_ND(AND64ri32)
5106 CASE_ND(AND32ri)
5107 CASE_ND(AND16ri)
5108 CASE_ND(AND8ri)
5109 CASE_ND(AND64rr)
5110 CASE_ND(AND32rr)
5111 CASE_ND(AND16rr)
5112 CASE_ND(AND8rr)
5113 CASE_ND(AND64rm)
5114 CASE_ND(AND32rm)
5115 CASE_ND(AND16rm)
5116 CASE_ND(AND8rm)
5117 CASE_ND(XOR64ri32)
5118 CASE_ND(XOR32ri)
5119 CASE_ND(XOR16ri)
5120 CASE_ND(XOR8ri)
5121 CASE_ND(XOR64rr)
5122 CASE_ND(XOR32rr)
5123 CASE_ND(XOR16rr)
5124 CASE_ND(XOR8rr)
5125 CASE_ND(XOR64rm)
5126 CASE_ND(XOR32rm)
5127 CASE_ND(XOR16rm)
5128 CASE_ND(XOR8rm)
5129 CASE_ND(OR64ri32)
5130 CASE_ND(OR32ri)
5131 CASE_ND(OR16ri)
5132 CASE_ND(OR8ri)
5133 CASE_ND(OR64rr)
5134 CASE_ND(OR32rr)
5135 CASE_ND(OR16rr)
5136 CASE_ND(OR8rr)
5137 CASE_ND(OR64rm)
5138 CASE_ND(OR32rm)
5139 CASE_ND(OR16rm)
5140 CASE_ND(OR8rm)
5141 CASE_EVEX(ANDN32rr)
5142 CASE_EVEX(ANDN32rm)
5143 CASE_EVEX(ANDN64rr)
5144 CASE_EVEX(ANDN64rm)
5145 CASE_EVEX(BLSI32rr)
5146 CASE_EVEX(BLSI32rm)
5147 CASE_EVEX(BLSI64rr)
5148 CASE_EVEX(BLSI64rm)
5149 CASE_EVEX(BLSMSK32rr)
5150 CASE_EVEX(BLSMSK32rm)
5151 CASE_EVEX(BLSMSK64rr)
5152 CASE_EVEX(BLSMSK64rm)
5153 CASE_EVEX(BLSR32rr)
5154 CASE_EVEX(BLSR32rm)
5155 CASE_EVEX(BLSR64rr)
5156 CASE_EVEX(BLSR64rm)
5157 case X86::BLCFILL32rr:
5158 case X86::BLCFILL32rm:
5159 case X86::BLCFILL64rr:
5160 case X86::BLCFILL64rm:
5161 case X86::BLCI32rr:
5162 case X86::BLCI32rm:
5163 case X86::BLCI64rr:
5164 case X86::BLCI64rm:
5165 case X86::BLCIC32rr:
5166 case X86::BLCIC32rm:
5167 case X86::BLCIC64rr:
5168 case X86::BLCIC64rm:
5169 case X86::BLCMSK32rr:
5170 case X86::BLCMSK32rm:
5171 case X86::BLCMSK64rr:
5172 case X86::BLCMSK64rm:
5173 case X86::BLCS32rr:
5174 case X86::BLCS32rm:
5175 case X86::BLCS64rr:
5176 case X86::BLCS64rm:
5177 case X86::BLSFILL32rr:
5178 case X86::BLSFILL32rm:
5179 case X86::BLSFILL64rr:
5180 case X86::BLSFILL64rm:
5181 case X86::BLSIC32rr:
5182 case X86::BLSIC32rm:
5183 case X86::BLSIC64rr:
5184 case X86::BLSIC64rm:
5185 CASE_EVEX(BZHI32rr)
5186 CASE_EVEX(BZHI32rm)
5187 CASE_EVEX(BZHI64rr)
5188 CASE_EVEX(BZHI64rm)
5189 case X86::T1MSKC32rr:
5190 case X86::T1MSKC32rm:
5191 case X86::T1MSKC64rr:
5192 case X86::T1MSKC64rm:
5193 case X86::TZMSK32rr:
5194 case X86::TZMSK32rm:
5195 case X86::TZMSK64rr:
5196 case X86::TZMSK64rm:
5197 // These instructions clear the overflow flag just like TEST.
5198 // FIXME: These are not the only instructions in this switch that clear the
5199 // overflow flag.
5200 ClearsOverflowFlag = true;
5201 return true;
5202 CASE_EVEX(BEXTR32rr)
5203 CASE_EVEX(BEXTR64rr)
5204 CASE_EVEX(BEXTR32rm)
5205 CASE_EVEX(BEXTR64rm)
5206 case X86::BEXTRI32ri:
5207 case X86::BEXTRI32mi:
5208 case X86::BEXTRI64ri:
5209 case X86::BEXTRI64mi:
5210 // BEXTR doesn't update the sign flag so we can't use it. It does clear
5211 // the overflow flag, but that's not useful without the sign flag.
5212 NoSignFlag = true;
5213 return true;
5214 }
5215}
5216
5217/// Check whether the use can be converted to remove a comparison against zero.
5218/// Returns the EFLAGS condition and the operand that we are comparing against zero.
5219static std::pair<X86::CondCode, unsigned> isUseDefConvertible(const MachineInstr &MI) {
5220 switch (MI.getOpcode()) {
5221 default:
5222 return std::make_pair(x: X86::COND_INVALID, y: ~0U);
5223 CASE_ND(NEG8r)
5224 CASE_ND(NEG16r)
5225 CASE_ND(NEG32r)
5226 CASE_ND(NEG64r)
5227 return std::make_pair(x: X86::COND_AE, y: 1U);
5228 case X86::LZCNT16rr:
5229 case X86::LZCNT32rr:
5230 case X86::LZCNT64rr:
5231 return std::make_pair(x: X86::COND_B, y: 1U);
5232 case X86::POPCNT16rr:
5233 case X86::POPCNT32rr:
5234 case X86::POPCNT64rr:
5235 return std::make_pair(x: X86::COND_E, y: 1U);
5236 case X86::TZCNT16rr:
5237 case X86::TZCNT32rr:
5238 case X86::TZCNT64rr:
5239 return std::make_pair(x: X86::COND_B, y: 1U);
5240 case X86::BSF16rr:
5241 case X86::BSF32rr:
5242 case X86::BSF64rr:
5243 case X86::BSR16rr:
5244 case X86::BSR32rr:
5245 case X86::BSR64rr:
5246 return std::make_pair(x: X86::COND_E, y: 2U);
5247 CASE_EVEX(BLSI32rr)
5248 CASE_EVEX(BLSI64rr)
5249 return std::make_pair(x: X86::COND_AE, y: 1U);
5250 CASE_EVEX(BLSR32rr)
5251 CASE_EVEX(BLSR64rr)
5252 CASE_EVEX(BLSMSK32rr)
5253 CASE_EVEX(BLSMSK64rr)
5254 return std::make_pair(x: X86::COND_B, y: 1U);
5255 // TODO: TBM instructions.
5256 }
5257}
5258#undef CASE_EVEX
5259
5260MachineInstr *X86InstrInfo::findDominatingRedundantFlagInstr(
5261 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask,
5262 int64_t CmpValue, MachineBasicBlock *MultiPredMBB, bool &IsSwapped,
5263 int64_t &ImmDelta,
5264 SmallVectorImpl<std::pair<MachineInstr *, unsigned>> &InstsToUpdate) const {
5265 assert(Subtarget.hasNF() && "NF feature required");
5266 const TargetRegisterInfo *TRI = &getRegisterInfo();
5267 const unsigned MaxNFConversions =
5268 Subtarget.getCLOpts().max_nf_conversions_for_cmp_reuse;
5269
5270 // The caller already scanned MultiPredMBB without finding the producer, so it
5271 // must live in a block that strictly dominates MultiPredMBB. Walk
5272 // predecessors backward to find it and prove dominance, avoiding a
5273 // whole-function MachineDominatorTree that would be rebuilt in O(function
5274 // size) per compare.
5275 //
5276 // The producer's block dominates MultiPredMBB iff every backward path funnels
5277 // through it before a function-entry block, so expand predecessors but stop
5278 // at a block holding the producer. Bail if a predecessor-less block is
5279 // reached without the producer (a path bypasses it) or the producer is found
5280 // in two blocks (neither dominates alone). Within a block, scan backward,
5281 // collecting the NF-convertible EFLAGS clobbers above the producer and
5282 // bailing on any other clobber (it would shadow the producer's flags from
5283 // CmpInstr).
5284 //
5285 // Clobbers are staged in Pending and committed only on success. Visited
5286 // is seeded with the caller's single-predecessor chain (CmpMBB through
5287 // MultiPredMBB) so the walk doesn't re-scan blocks the caller already
5288 // staged. The walk doubles as a cycle detector: a predecessor equal to
5289 // CmpMBB is a back-edge from CmpMBB's successors into the walked region,
5290 // which means CmpMBB is on a CFG cycle. In that case the region below
5291 // CmpInstr executes on the back-edge before the next iteration's CmpInstr
5292 // and must be checked too: bail on any non-NF-convertible EFLAGS clobber,
5293 // stage NF-convertible ones.
5294 //
5295 // Each NF conversion trades a compact legacy/EVEX-compressed encoding for a
5296 // wider EVEX (often NDD three-operand) one, growing code size, while the
5297 // reuse only removes a single compare. Cap the total number of conversions
5298 // (caller chain + predecessor walk + below-scan) so the reuse cannot bloat
5299 // code just to delete one compare.
5300 MachineInstr *Sub = nullptr;
5301 MachineBasicBlock *SubMBB = nullptr;
5302 SmallVector<std::pair<MachineInstr *, unsigned>, 4> Pending;
5303
5304 MachineBasicBlock *CmpMBB = CmpInstr.getParent();
5305 SmallPtrSet<MachineBasicBlock *, 8> Visited;
5306 SmallVector<MachineBasicBlock *, 8> Worklist;
5307 for (MachineBasicBlock *MBB = CmpMBB; MBB != MultiPredMBB;
5308 MBB = MBB->getSinglePredecessor())
5309 Visited.insert(Ptr: MBB);
5310 Visited.insert(Ptr: MultiPredMBB);
5311
5312 bool CmpMBBOnCycle = false;
5313 auto TryPush = [&](MachineBasicBlock *Pred) {
5314 if (Pred == CmpMBB)
5315 CmpMBBOnCycle = true;
5316 if (Visited.insert(Ptr: Pred).second)
5317 Worklist.push_back(Elt: Pred);
5318 };
5319
5320 for (MachineBasicBlock *Pred : MultiPredMBB->predecessors())
5321 TryPush(Pred);
5322 while (!Worklist.empty()) {
5323 MachineBasicBlock *MBB = Worklist.pop_back_val();
5324 MachineInstr *Producer = nullptr;
5325 for (MachineInstr &Inst : reverse(C&: *MBB)) {
5326 if (!Inst.modifiesRegister(Reg: X86::EFLAGS, TRI))
5327 continue;
5328 if (isRedundantFlagInstr(FlagI: CmpInstr, SrcReg, SrcReg2, ImmMask: CmpMask, ImmValue: CmpValue,
5329 OI: Inst, IsSwapped: &IsSwapped, ImmDelta: &ImmDelta)) {
5330 Producer = &Inst;
5331 break;
5332 }
5333 unsigned NewOpc = X86::getNFVariantIfClobberRemovable(MI: Inst, TRI);
5334 if (!NewOpc)
5335 return nullptr;
5336 if (InstsToUpdate.size() + Pending.size() >= MaxNFConversions)
5337 return nullptr;
5338 Pending.push_back(Elt: std::make_pair(x: &Inst, y&: NewOpc));
5339 }
5340 if (Producer) {
5341 // A producer in a second block means neither dominates alone.
5342 if (Sub && SubMBB != MBB)
5343 return nullptr;
5344 Sub = Producer;
5345 SubMBB = MBB;
5346 continue;
5347 }
5348 // Entry reached without the producer: some path bypasses it.
5349 if (MBB->pred_empty())
5350 return nullptr;
5351 for (MachineBasicBlock *Pred : MBB->predecessors())
5352 TryPush(Pred);
5353 }
5354 if (!Sub)
5355 return nullptr;
5356
5357 // The forward condition-code fixup in the caller (OpsToUpdate) only rewrites
5358 // EFLAGS users within CmpMBB. When the producer's flags require a condition
5359 // swap or an immediate adjustment, EFLAGS users elsewhere in the dominated
5360 // region or in CmpMBB's successors (when EFLAGS is live-out) would also need
5361 // rewriting, which is not handled here. Restrict the multi-predecessor case
5362 // to producers that yield identical flags.
5363 if (IsSwapped || ImmDelta != 0)
5364 return nullptr;
5365
5366 // If CmpMBB is on a CFG cycle, its below-CmpInstr region is on the back-edge
5367 // path and must also be free of non-NF-convertible EFLAGS clobbers.
5368 if (CmpMBBOnCycle) {
5369 for (MachineInstr &Inst : make_range(
5370 x: std::next(x: MachineBasicBlock::iterator(CmpInstr)), y: CmpMBB->end())) {
5371 if (!Inst.modifiesRegister(Reg: X86::EFLAGS, TRI))
5372 continue;
5373 unsigned NewOpc = X86::getNFVariantIfClobberRemovable(MI: Inst, TRI);
5374 if (!NewOpc)
5375 return nullptr;
5376 if (InstsToUpdate.size() + Pending.size() >= MaxNFConversions)
5377 return nullptr;
5378 Pending.push_back(Elt: std::make_pair(x: &Inst, y&: NewOpc));
5379 }
5380 }
5381
5382 InstsToUpdate.append(in_start: Pending.begin(), in_end: Pending.end());
5383 return Sub;
5384}
5385
5386/// Check if there exists an earlier instruction that
5387/// operates on the same source operands and sets flags in the same way as
5388/// Compare; remove Compare if possible.
5389bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
5390 Register SrcReg2, int64_t CmpMask,
5391 int64_t CmpValue,
5392 const MachineRegisterInfo *MRI) const {
5393 // Check whether we can replace SUB with CMP.
5394 switch (CmpInstr.getOpcode()) {
5395 default:
5396 break;
5397 CASE_ND(SUB64ri32)
5398 CASE_ND(SUB32ri)
5399 CASE_ND(SUB16ri)
5400 CASE_ND(SUB8ri)
5401 CASE_ND(SUB64rm)
5402 CASE_ND(SUB32rm)
5403 CASE_ND(SUB16rm)
5404 CASE_ND(SUB8rm)
5405 CASE_ND(SUB64rr)
5406 CASE_ND(SUB32rr)
5407 CASE_ND(SUB16rr)
5408 CASE_ND(SUB8rr) {
5409 if (!MRI->use_nodbg_empty(RegNo: CmpInstr.getOperand(i: 0).getReg()))
5410 return false;
5411 // There is no use of the destination register, we can replace SUB with CMP.
5412 unsigned NewOpcode = 0;
5413#define FROM_TO(A, B) \
5414 CASE_ND(A) NewOpcode = X86::B; \
5415 break;
5416 switch (CmpInstr.getOpcode()) {
5417 default:
5418 llvm_unreachable("Unreachable!");
5419 FROM_TO(SUB64rm, CMP64rm)
5420 FROM_TO(SUB32rm, CMP32rm)
5421 FROM_TO(SUB16rm, CMP16rm)
5422 FROM_TO(SUB8rm, CMP8rm)
5423 FROM_TO(SUB64rr, CMP64rr)
5424 FROM_TO(SUB32rr, CMP32rr)
5425 FROM_TO(SUB16rr, CMP16rr)
5426 FROM_TO(SUB8rr, CMP8rr)
5427 FROM_TO(SUB64ri32, CMP64ri32)
5428 FROM_TO(SUB32ri, CMP32ri)
5429 FROM_TO(SUB16ri, CMP16ri)
5430 FROM_TO(SUB8ri, CMP8ri)
5431 }
5432#undef FROM_TO
5433 CmpInstr.setDesc(get(Opcode: NewOpcode));
5434 CmpInstr.removeOperand(OpNo: 0);
5435 // Mutating this instruction invalidates any debug data associated with it.
5436 CmpInstr.dropDebugNumber();
5437 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
5438 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5439 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5440 return false;
5441 }
5442 }
5443
5444 // The following code tries to remove the comparison by re-using EFLAGS
5445 // from earlier instructions.
5446
5447 bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
5448
5449 // Transformation currently requires SSA values.
5450 if (SrcReg2.isPhysical())
5451 return false;
5452 MachineInstr *SrcRegDef = MRI->getVRegDef(Reg: SrcReg);
5453 if (!SrcRegDef)
5454 return false;
5455
5456 MachineInstr *MI = nullptr;
5457 MachineInstr *Sub = nullptr;
5458 MachineInstr *Movr0Inst = nullptr;
5459 MachineInstr *LTZCNTInst = nullptr;
5460 SmallVector<std::pair<MachineInstr *, unsigned>, 4> InstsToUpdate;
5461 bool NoSignFlag = false;
5462 bool ClearsOverflowFlag = false;
5463 bool ShouldUpdateCC = false;
5464 bool IsSwapped = false;
5465 bool HasNF = Subtarget.hasNF();
5466 unsigned OpNo = 0;
5467 X86::CondCode NewCC = X86::COND_INVALID;
5468 int64_t ImmDelta = 0;
5469
5470 // Search backward from CmpInstr for the next instruction defining EFLAGS.
5471 const TargetRegisterInfo *TRI = &getRegisterInfo();
5472 MachineBasicBlock &CmpMBB = *CmpInstr.getParent();
5473 MachineBasicBlock::reverse_iterator From =
5474 std::next(x: MachineBasicBlock::reverse_iterator(CmpInstr));
5475 for (MachineBasicBlock *MBB = &CmpMBB;;) {
5476 for (MachineInstr &Inst : make_range(x: From, y: MBB->rend())) {
5477 // Try to use EFLAGS from the instruction defining %SrcReg. Example:
5478 // %eax = addl ...
5479 // ... // EFLAGS not changed
5480 // testl %eax, %eax // <-- can be removed
5481 if (&Inst == SrcRegDef) {
5482 if (IsCmpZero &&
5483 isDefConvertible(MI: Inst, NoSignFlag, ClearsOverflowFlag)) {
5484 MI = &Inst;
5485 break;
5486 }
5487
5488 // Look back for the following pattern, in which case the
5489 // test16rr/test64rr instruction could be erased.
5490 //
5491 // Example for test16rr:
5492 // %reg = and32ri %in_reg, 5
5493 // ... // EFLAGS not changed.
5494 // %src_reg = copy %reg.sub_16bit:gr32
5495 // test16rr %src_reg, %src_reg, implicit-def $eflags
5496 // Example for test64rr:
5497 // %reg = and32ri %in_reg, 5
5498 // ... // EFLAGS not changed.
5499 // %src_reg = subreg_to_reg %reg, %subreg.sub_index
5500 // test64rr %src_reg, %src_reg, implicit-def $eflags
5501 MachineInstr *AndInstr = nullptr;
5502 if (IsCmpZero &&
5503 findRedundantFlagInstr(CmpInstr, CmpValDefInstr&: Inst, MRI, AndInstr: &AndInstr, TRI,
5504 ST: Subtarget, NoSignFlag, ClearsOverflowFlag)) {
5505 assert(AndInstr != nullptr && X86::isAND(AndInstr->getOpcode()));
5506 MI = AndInstr;
5507 break;
5508 }
5509 // Cannot find other candidates before definition of SrcReg.
5510 return false;
5511 }
5512
5513 if (Inst.modifiesRegister(Reg: X86::EFLAGS, TRI)) {
5514 // Try to use EFLAGS produced by an instruction reading %SrcReg.
5515 // Example:
5516 // %eax = ...
5517 // ...
5518 // popcntl %eax
5519 // ... // EFLAGS not changed
5520 // testl %eax, %eax // <-- can be removed
5521 if (IsCmpZero) {
5522 std::tie(args&: NewCC, args&: OpNo) = isUseDefConvertible(MI: Inst);
5523 if (NewCC != X86::COND_INVALID && Inst.getOperand(i: OpNo).isReg() &&
5524 Inst.getOperand(i: OpNo).getReg() == SrcReg) {
5525 ShouldUpdateCC = true;
5526 MI = &Inst;
5527 break;
5528 }
5529 }
5530
5531 // Try to use EFLAGS from an instruction with similar flag results.
5532 // Example:
5533 // sub x, y or cmp x, y
5534 // ... // EFLAGS not changed
5535 // cmp x, y // <-- can be removed
5536 if (isRedundantFlagInstr(FlagI: CmpInstr, SrcReg, SrcReg2, ImmMask: CmpMask, ImmValue: CmpValue,
5537 OI: Inst, IsSwapped: &IsSwapped, ImmDelta: &ImmDelta)) {
5538 Sub = &Inst;
5539 break;
5540 }
5541
5542 // Try to use CF produced by an LZCNT/TZCNT reading %SrcReg: it and
5543 // "cmp $1, %SrcReg" both set CF iff %SrcReg is zero. The other flags
5544 // differ, so all EFLAGS users need to read CF only (ADC/SBB/RCL/RCR).
5545 // Example:
5546 // lzcntq %rdi, %rax
5547 // ... // EFLAGS not changed
5548 // cmpq $1, %rdi // <-- can be removed
5549 // adcq $0, %rax // reads CF only
5550 if (isCmpRedundantAfterLTZCNT(SrcReg, SrcReg2, ImmMask: CmpMask, ImmValue: CmpValue,
5551 OI: Inst)) {
5552 LTZCNTInst = &Inst;
5553 break;
5554 }
5555
5556 // MOV32r0 is implemented with xor which clobbers condition code. It is
5557 // safe to move up, if the definition to EFLAGS is dead and earlier
5558 // instructions do not read or write EFLAGS.
5559 if (!Movr0Inst && Inst.getOpcode() == X86::MOV32r0 &&
5560 Inst.registerDefIsDead(Reg: X86::EFLAGS, TRI)) {
5561 Movr0Inst = &Inst;
5562 continue;
5563 }
5564
5565 // Try to replace non-NF with NF instructions.
5566 if (HasNF) {
5567 unsigned NewOp = X86::getNFVariantIfClobberRemovable(MI: Inst, TRI);
5568 if (!NewOp)
5569 return false;
5570
5571 InstsToUpdate.push_back(Elt: std::make_pair(x: &Inst, y&: NewOp));
5572 continue;
5573 }
5574
5575 // Cannot do anything for any other EFLAG changes.
5576 return false;
5577 }
5578 }
5579
5580 if (MI || Sub || LTZCNTInst)
5581 break;
5582
5583 // Reached the begin of the basic block. If it has exactly one predecessor,
5584 // continue the backward scan there. Otherwise (multiple predecessors), try
5585 // to reuse EFLAGS from a dominating producer (handled below).
5586 if (MBB->pred_size() != 1) {
5587 // The block has multiple predecessors. We can still reuse EFLAGS from an
5588 // equivalent flag producer that dominates CmpInstr, provided every path
5589 // from that producer to CmpInstr only clobbers EFLAGS via instructions
5590 // that have an NF (no-flags) variant (which requires APX). This handles
5591 // patterns like (CMP duplicated by CodeGenPrepare across a diamond):
5592 // entry: cmp %x, C ; br
5593 // bb1: imul ... ; clobbers EFLAGS -> {nf} imul
5594 // bb2: ...
5595 // bb3: cmp %x, C ; <-- redundant, reuse EFLAGS from entry
5596 // cmovcc ...
5597 // The helper caps the total number of NF conversions so this cannot grow
5598 // code size without bound just to delete one compare.
5599 if (HasNF)
5600 Sub = findDominatingRedundantFlagInstr(
5601 CmpInstr, SrcReg, SrcReg2, CmpMask, CmpValue, MultiPredMBB: MBB, IsSwapped,
5602 ImmDelta, InstsToUpdate);
5603 if (!Sub)
5604 return false;
5605 break;
5606 }
5607 MBB = *MBB->pred_begin();
5608 From = MBB->rbegin();
5609 }
5610
5611 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
5612 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
5613 // If we are done with the basic block, we need to check whether EFLAGS is
5614 // live-out.
5615 bool FlagsMayLiveOut = true;
5616 SmallVector<std::pair<MachineInstr *, X86::CondCode>, 4> OpsToUpdate;
5617 MachineBasicBlock::iterator AfterCmpInstr =
5618 std::next(x: MachineBasicBlock::iterator(CmpInstr));
5619 for (MachineInstr &Instr : make_range(x: AfterCmpInstr, y: CmpMBB.end())) {
5620 bool ModifyEFLAGS = Instr.modifiesRegister(Reg: X86::EFLAGS, TRI);
5621 bool UseEFLAGS = Instr.readsRegister(Reg: X86::EFLAGS, TRI);
5622 // We should check the usage if this instruction uses and updates EFLAGS.
5623 if (!UseEFLAGS && ModifyEFLAGS) {
5624 // It is safe to remove CmpInstr if EFLAGS is updated again.
5625 FlagsMayLiveOut = false;
5626 break;
5627 }
5628 if (!UseEFLAGS && !ModifyEFLAGS)
5629 continue;
5630
5631 // EFLAGS is used by this instruction.
5632 X86::CondCode OldCC = X86::getCondFromMI(MI: Instr);
5633 if ((MI || IsSwapped || ImmDelta != 0) && OldCC == X86::COND_INVALID)
5634 return false;
5635
5636 X86::CondCode ReplacementCC = X86::COND_INVALID;
5637 if (MI) {
5638 switch (OldCC) {
5639 default:
5640 break;
5641 case X86::COND_A:
5642 case X86::COND_AE:
5643 case X86::COND_B:
5644 case X86::COND_BE:
5645 // CF is used, we can't perform this optimization.
5646 return false;
5647 case X86::COND_G:
5648 case X86::COND_GE:
5649 case X86::COND_L:
5650 case X86::COND_LE:
5651 // If SF is used, but the instruction doesn't update the SF, then we
5652 // can't do the optimization.
5653 if (NoSignFlag)
5654 return false;
5655 [[fallthrough]];
5656 case X86::COND_O:
5657 case X86::COND_NO:
5658 // If OF is used, the instruction needs to clear it like CmpZero does.
5659 if (!ClearsOverflowFlag)
5660 return false;
5661 break;
5662 case X86::COND_S:
5663 case X86::COND_NS:
5664 // If SF is used, but the instruction doesn't update the SF, then we
5665 // can't do the optimization.
5666 if (NoSignFlag)
5667 return false;
5668 break;
5669 }
5670
5671 // If we're updating the condition code check if we have to reverse the
5672 // condition.
5673 if (ShouldUpdateCC)
5674 switch (OldCC) {
5675 default:
5676 return false;
5677 case X86::COND_E:
5678 ReplacementCC = NewCC;
5679 break;
5680 case X86::COND_NE:
5681 ReplacementCC = GetOppositeBranchCondition(CC: NewCC);
5682 break;
5683 }
5684 } else if (IsSwapped) {
5685 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
5686 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
5687 // We swap the condition code and synthesize the new opcode.
5688 ReplacementCC = getSwappedCondition(CC: OldCC);
5689 if (ReplacementCC == X86::COND_INVALID)
5690 return false;
5691 ShouldUpdateCC = true;
5692 } else if (ImmDelta != 0) {
5693 unsigned BitWidth = RI.getRegSizeInBits(RC: *MRI->getRegClass(Reg: SrcReg));
5694 // Shift amount for min/max constants to adjust for 8/16/32 instruction
5695 // sizes.
5696 switch (OldCC) {
5697 case X86::COND_L: // x <s (C + 1) --> x <=s C
5698 if (ImmDelta != 1 || APInt::getSignedMinValue(numBits: BitWidth) == CmpValue)
5699 return false;
5700 ReplacementCC = X86::COND_LE;
5701 break;
5702 case X86::COND_B: // x <u (C + 1) --> x <=u C
5703 if (ImmDelta != 1 || CmpValue == 0)
5704 return false;
5705 ReplacementCC = X86::COND_BE;
5706 break;
5707 case X86::COND_GE: // x >=s (C + 1) --> x >s C
5708 if (ImmDelta != 1 || APInt::getSignedMinValue(numBits: BitWidth) == CmpValue)
5709 return false;
5710 ReplacementCC = X86::COND_G;
5711 break;
5712 case X86::COND_AE: // x >=u (C + 1) --> x >u C
5713 if (ImmDelta != 1 || CmpValue == 0)
5714 return false;
5715 ReplacementCC = X86::COND_A;
5716 break;
5717 case X86::COND_G: // x >s (C - 1) --> x >=s C
5718 if (ImmDelta != -1 || APInt::getSignedMaxValue(numBits: BitWidth) == CmpValue)
5719 return false;
5720 ReplacementCC = X86::COND_GE;
5721 break;
5722 case X86::COND_A: // x >u (C - 1) --> x >=u C
5723 if (ImmDelta != -1 || APInt::getMaxValue(numBits: BitWidth) == CmpValue)
5724 return false;
5725 ReplacementCC = X86::COND_AE;
5726 break;
5727 case X86::COND_LE: // x <=s (C - 1) --> x <s C
5728 if (ImmDelta != -1 || APInt::getSignedMaxValue(numBits: BitWidth) == CmpValue)
5729 return false;
5730 ReplacementCC = X86::COND_L;
5731 break;
5732 case X86::COND_BE: // x <=u (C - 1) --> x <u C
5733 if (ImmDelta != -1 || APInt::getMaxValue(numBits: BitWidth) == CmpValue)
5734 return false;
5735 ReplacementCC = X86::COND_B;
5736 break;
5737 default:
5738 return false;
5739 }
5740 ShouldUpdateCC = true;
5741 }
5742
5743 if (LTZCNTInst) {
5744 unsigned InstCode = Instr.getOpcode();
5745 if (!X86::isADC(Opcode: InstCode) && !X86::isSBB(Opcode: InstCode) &&
5746 !X86::isRCL(Opcode: InstCode) && !X86::isRCR(Opcode: InstCode))
5747 return false;
5748
5749 MI = LTZCNTInst;
5750 }
5751
5752 if (ShouldUpdateCC && ReplacementCC != OldCC) {
5753 // Push the MachineInstr to OpsToUpdate.
5754 // If it is safe to remove CmpInstr, the condition code of these
5755 // instructions will be modified.
5756 OpsToUpdate.push_back(Elt: std::make_pair(x: &Instr, y&: ReplacementCC));
5757 }
5758 if (ModifyEFLAGS || Instr.killsRegister(Reg: X86::EFLAGS, TRI)) {
5759 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
5760 FlagsMayLiveOut = false;
5761 break;
5762 }
5763 }
5764
5765 if (LTZCNTInst && !MI)
5766 return false;
5767
5768 // If we have to update users but EFLAGS is live-out abort, since we cannot
5769 // easily find all of the users.
5770 if ((MI != nullptr || ShouldUpdateCC) && FlagsMayLiveOut) {
5771 for (MachineBasicBlock *Successor : CmpMBB.successors())
5772 if (Successor->isLiveIn(Reg: X86::EFLAGS))
5773 return false;
5774 }
5775
5776 // The instruction to be updated is either Sub or MI.
5777 assert((MI == nullptr || Sub == nullptr) && "Should not have Sub and MI set");
5778 Sub = MI != nullptr ? MI : Sub;
5779 MachineBasicBlock *SubBB = Sub->getParent();
5780 // Move Movr0Inst to the appropriate place before Sub.
5781 if (Movr0Inst) {
5782 // Only move within the same block so we don't accidentally move to a
5783 // block with higher execution frequency.
5784 if (&CmpMBB != SubBB)
5785 return false;
5786 // Look backwards until we find a def that doesn't use the current EFLAGS.
5787 MachineBasicBlock::reverse_iterator InsertI = Sub,
5788 InsertE = Sub->getParent()->rend();
5789 for (; InsertI != InsertE; ++InsertI) {
5790 MachineInstr *Instr = &*InsertI;
5791 if (!Instr->readsRegister(Reg: X86::EFLAGS, TRI) &&
5792 Instr->modifiesRegister(Reg: X86::EFLAGS, TRI)) {
5793 Movr0Inst->getParent()->remove(I: Movr0Inst);
5794 Instr->getParent()->insert(I: MachineBasicBlock::iterator(Instr),
5795 MI: Movr0Inst);
5796 break;
5797 }
5798 }
5799 if (InsertI == InsertE)
5800 return false;
5801 }
5802
5803 // Replace non-NF with NF instructions.
5804 for (auto &Inst : InstsToUpdate) {
5805 Inst.first->setDesc(get(Opcode: Inst.second));
5806 Inst.first->removeOperand(
5807 OpNo: Inst.first->findRegisterDefOperandIdx(Reg: X86::EFLAGS, /*TRI=*/nullptr));
5808 }
5809
5810 // Make sure Sub instruction defines EFLAGS and mark the def live.
5811 MachineOperand *FlagDef =
5812 Sub->findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
5813 assert(FlagDef && "Unable to locate a def EFLAGS operand");
5814 FlagDef->setIsDead(false);
5815
5816 CmpInstr.eraseFromParent();
5817
5818 // Modify the condition code of instructions in OpsToUpdate.
5819 for (auto &Op : OpsToUpdate) {
5820 Op.first->getOperand(i: Op.first->getDesc().getNumOperands() - 1)
5821 .setImm(Op.second);
5822 }
5823 // Add EFLAGS to block live-ins between CmpBB and block of flags producer.
5824 // Walk the CFG backward from CmpMBB up to (but excluding) SubBB, marking
5825 // EFLAGS live-in on every block in between. SubBB dominates CmpMBB (whether
5826 // the producer was found by the single-predecessor backward walk or the
5827 // multi-predecessor dominator search), so the walk reaches SubBB on every
5828 // path and never escapes above it. A single-predecessor chain is just the
5829 // degenerate case where every block has exactly one predecessor.
5830 SmallPtrSet<MachineBasicBlock *, 8> Visited;
5831 SmallVector<MachineBasicBlock *, 8> Worklist(1, &CmpMBB);
5832 Visited.insert(Ptr: &CmpMBB);
5833 while (!Worklist.empty()) {
5834 MachineBasicBlock *MBB = Worklist.pop_back_val();
5835 // EFLAGS is produced inside SubBB, so it is not live-in there.
5836 if (MBB == SubBB)
5837 continue;
5838 if (!MBB->isLiveIn(Reg: X86::EFLAGS))
5839 MBB->addLiveIn(PhysReg: X86::EFLAGS);
5840 for (MachineBasicBlock *Pred : MBB->predecessors())
5841 if (Visited.insert(Ptr: Pred).second)
5842 Worklist.push_back(Elt: Pred);
5843 }
5844 return true;
5845}
5846
5847/// \returns true if the instruction can be changed to COPY when imm is 0.
5848static bool canConvert2Copy(unsigned Opc) {
5849 switch (Opc) {
5850 default:
5851 return false;
5852 CASE_ND(ADD64ri32)
5853 CASE_ND(SUB64ri32)
5854 CASE_ND(OR64ri32)
5855 CASE_ND(XOR64ri32)
5856 CASE_ND(ADD32ri)
5857 CASE_ND(SUB32ri)
5858 CASE_ND(OR32ri)
5859 CASE_ND(XOR32ri)
5860 return true;
5861 }
5862}
5863
5864/// Convert an ALUrr opcode to corresponding ALUri opcode. Such as
5865/// ADD32rr ==> ADD32ri
5866static unsigned convertALUrr2ALUri(unsigned Opc) {
5867 switch (Opc) {
5868 default:
5869 return 0;
5870#define FROM_TO(FROM, TO) \
5871 case X86::FROM: \
5872 return X86::TO; \
5873 case X86::FROM##_ND: \
5874 return X86::TO##_ND;
5875 FROM_TO(ADC64rr, ADC64ri32)
5876 FROM_TO(SBB64rr, SBB64ri32)
5877 FROM_TO(AND64rr, AND64ri32)
5878 FROM_TO(OR64rr, OR64ri32)
5879 FROM_TO(XOR64rr, XOR64ri32)
5880 FROM_TO(SHR64rCL, SHR64ri)
5881 FROM_TO(SHL64rCL, SHL64ri)
5882 FROM_TO(SAR64rCL, SAR64ri)
5883 FROM_TO(ROL64rCL, ROL64ri)
5884 FROM_TO(ROR64rCL, ROR64ri)
5885 FROM_TO(RCL64rCL, RCL64ri)
5886 FROM_TO(RCR64rCL, RCR64ri)
5887 FROM_TO(ADD32rr, ADD32ri)
5888 FROM_TO(ADC32rr, ADC32ri)
5889 FROM_TO(SUB32rr, SUB32ri)
5890 FROM_TO(SBB32rr, SBB32ri)
5891 FROM_TO(AND32rr, AND32ri)
5892 FROM_TO(OR32rr, OR32ri)
5893 FROM_TO(XOR32rr, XOR32ri)
5894 FROM_TO(SHR32rCL, SHR32ri)
5895 FROM_TO(SHL32rCL, SHL32ri)
5896 FROM_TO(SAR32rCL, SAR32ri)
5897 FROM_TO(ROL32rCL, ROL32ri)
5898 FROM_TO(ROR32rCL, ROR32ri)
5899 FROM_TO(RCL32rCL, RCL32ri)
5900 FROM_TO(RCR32rCL, RCR32ri)
5901#undef FROM_TO
5902#define FROM_TO(FROM, TO) \
5903 case X86::FROM: \
5904 return X86::TO;
5905 FROM_TO(ADD64rr, ADD64ri32)
5906 FROM_TO(SUB64rr, SUB64ri32)
5907 FROM_TO(TEST64rr, TEST64ri32)
5908 FROM_TO(CTEST64rr, CTEST64ri32)
5909 FROM_TO(CMP64rr, CMP64ri32)
5910 FROM_TO(CCMP64rr, CCMP64ri32)
5911 FROM_TO(TEST32rr, TEST32ri)
5912 FROM_TO(CTEST32rr, CTEST32ri)
5913 FROM_TO(CMP32rr, CMP32ri)
5914 FROM_TO(CCMP32rr, CCMP32ri)
5915#undef FROM_TO
5916 case X86::ADD64rr_ND:
5917 return X86::ADD64ri32_ND;
5918 case X86::SUB64rr_ND:
5919 return X86::SUB64ri32_ND;
5920 }
5921}
5922
5923/// Reg is assigned ImmVal in DefMI, and is used in UseMI.
5924/// If MakeChange is true, this function tries to replace Reg by ImmVal in
5925/// UseMI. If MakeChange is false, just check if folding is possible.
5926//
5927/// \returns true if folding is successful or possible.
5928bool X86InstrInfo::foldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI,
5929 Register Reg, int64_t ImmVal,
5930 MachineRegisterInfo *MRI,
5931 bool MakeChange) const {
5932 bool Modified = false;
5933
5934 // 64 bit operations accept sign extended 32 bit immediates.
5935 // 32 bit operations accept all 32 bit immediates, so we don't need to check
5936 // them.
5937 const TargetRegisterClass *RC = nullptr;
5938 if (Reg.isVirtual())
5939 RC = MRI->getRegClass(Reg);
5940 if ((Reg.isPhysical() && X86::GR64RegClass.contains(Reg)) ||
5941 (Reg.isVirtual() && X86::GR64RegClass.hasSubClassEq(RC))) {
5942 if (!isInt<32>(x: ImmVal))
5943 return false;
5944 }
5945
5946 if (UseMI.findRegisterUseOperand(Reg, /*TRI=*/nullptr)->getSubReg())
5947 return false;
5948 // Immediate has larger code size than register. So avoid folding the
5949 // immediate if it has more than 1 use and we are optimizing for size.
5950 if (UseMI.getMF()->getFunction().hasOptSize() && Reg.isVirtual() &&
5951 !MRI->hasOneNonDBGUse(RegNo: Reg))
5952 return false;
5953
5954 unsigned Opc = UseMI.getOpcode();
5955 unsigned NewOpc;
5956 if (Opc == TargetOpcode::COPY) {
5957 Register ToReg = UseMI.getOperand(i: 0).getReg();
5958 const TargetRegisterClass *RC = nullptr;
5959 if (ToReg.isVirtual())
5960 RC = MRI->getRegClass(Reg: ToReg);
5961 bool GR32Reg = (ToReg.isVirtual() && X86::GR32RegClass.hasSubClassEq(RC)) ||
5962 (ToReg.isPhysical() && X86::GR32RegClass.contains(Reg: ToReg));
5963 bool GR64Reg = (ToReg.isVirtual() && X86::GR64RegClass.hasSubClassEq(RC)) ||
5964 (ToReg.isPhysical() && X86::GR64RegClass.contains(Reg: ToReg));
5965 bool GR8Reg = (ToReg.isVirtual() && X86::GR8RegClass.hasSubClassEq(RC)) ||
5966 (ToReg.isPhysical() && X86::GR8RegClass.contains(Reg: ToReg));
5967
5968 if (ImmVal == 0) {
5969 // We have MOV32r0 only.
5970 if (!GR32Reg)
5971 return false;
5972 }
5973
5974 if (GR64Reg) {
5975 if (isUInt<32>(x: ImmVal))
5976 NewOpc = X86::MOV32ri64;
5977 else
5978 NewOpc = X86::MOV64ri;
5979 } else if (GR32Reg) {
5980 NewOpc = X86::MOV32ri;
5981 if (ImmVal == 0) {
5982 // MOV32r0 clobbers EFLAGS.
5983 const TargetRegisterInfo *TRI = &getRegisterInfo();
5984 if (UseMI.getParent()->computeRegisterLiveness(
5985 TRI, Reg: X86::EFLAGS, Before: UseMI) != MachineBasicBlock::LQR_Dead)
5986 return false;
5987
5988 // MOV32r0 is different than other cases because it doesn't encode the
5989 // immediate in the instruction. So we directly modify it here.
5990 if (!MakeChange)
5991 return true;
5992 UseMI.setDesc(get(Opcode: X86::MOV32r0));
5993 UseMI.removeOperand(
5994 OpNo: UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr));
5995 UseMI.addOperand(Op: MachineOperand::CreateReg(Reg: X86::EFLAGS, /*isDef=*/true,
5996 /*isImp=*/true,
5997 /*isKill=*/false,
5998 /*isDead=*/true));
5999 Modified = true;
6000 }
6001 } else if (GR8Reg)
6002 NewOpc = X86::MOV8ri;
6003 else
6004 return false;
6005 } else
6006 NewOpc = convertALUrr2ALUri(Opc);
6007
6008 if (!NewOpc)
6009 return false;
6010
6011 // For SUB instructions the immediate can only be the second source operand.
6012 if ((NewOpc == X86::SUB64ri32 || NewOpc == X86::SUB32ri ||
6013 NewOpc == X86::SBB64ri32 || NewOpc == X86::SBB32ri ||
6014 NewOpc == X86::SUB64ri32_ND || NewOpc == X86::SUB32ri_ND ||
6015 NewOpc == X86::SBB64ri32_ND || NewOpc == X86::SBB32ri_ND) &&
6016 UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr) != 2)
6017 return false;
6018 // For CMP instructions the immediate can only be at index 1.
6019 if (((NewOpc == X86::CMP64ri32 || NewOpc == X86::CMP32ri) ||
6020 (NewOpc == X86::CCMP64ri32 || NewOpc == X86::CCMP32ri)) &&
6021 UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr) != 1)
6022 return false;
6023
6024 using namespace X86;
6025 if (isSHL(Opcode: Opc) || isSHR(Opcode: Opc) || isSAR(Opcode: Opc) || isROL(Opcode: Opc) || isROR(Opcode: Opc) ||
6026 isRCL(Opcode: Opc) || isRCR(Opcode: Opc)) {
6027 unsigned RegIdx = UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr);
6028 if (RegIdx < 2)
6029 return false;
6030 if (!isInt<8>(x: ImmVal))
6031 return false;
6032 assert(Reg == X86::CL);
6033
6034 if (!MakeChange)
6035 return true;
6036 UseMI.setDesc(get(Opcode: NewOpc));
6037 UseMI.removeOperand(OpNo: RegIdx);
6038 UseMI.addOperand(Op: MachineOperand::CreateImm(Val: ImmVal));
6039 // Reg is physical register $cl, so we don't know if DefMI is dead through
6040 // MRI. Let the caller handle it, or pass dead-mi-elimination can delete
6041 // the dead physical register define instruction.
6042 return true;
6043 }
6044
6045 if (!MakeChange)
6046 return true;
6047
6048 if (!Modified) {
6049 // Modify the instruction.
6050 if (ImmVal == 0 && canConvert2Copy(Opc: NewOpc) &&
6051 UseMI.registerDefIsDead(Reg: X86::EFLAGS, /*TRI=*/nullptr)) {
6052 // %100 = add %101, 0
6053 // ==>
6054 // %100 = COPY %101
6055 UseMI.setDesc(get(Opcode: TargetOpcode::COPY));
6056 UseMI.removeOperand(
6057 OpNo: UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr));
6058 UseMI.removeOperand(
6059 OpNo: UseMI.findRegisterDefOperandIdx(Reg: X86::EFLAGS, /*TRI=*/nullptr));
6060 UseMI.untieRegOperand(OpIdx: 0);
6061 UseMI.clearFlag(Flag: MachineInstr::MIFlag::NoSWrap);
6062 UseMI.clearFlag(Flag: MachineInstr::MIFlag::NoUWrap);
6063 } else {
6064 unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
6065 unsigned ImmOpNum = 2;
6066 if (!UseMI.getOperand(i: 0).isDef()) {
6067 Op1 = 0; // TEST, CMP, CTEST, CCMP
6068 ImmOpNum = 1;
6069 }
6070 if (Opc == TargetOpcode::COPY)
6071 ImmOpNum = 1;
6072 if (findCommutedOpIndices(MI: UseMI, SrcOpIdx1&: Op1, SrcOpIdx2&: Op2) &&
6073 UseMI.getOperand(i: Op1).getReg() == Reg)
6074 commuteInstruction(MI&: UseMI);
6075
6076 assert(UseMI.getOperand(ImmOpNum).getReg() == Reg);
6077 UseMI.setDesc(get(Opcode: NewOpc));
6078 UseMI.getOperand(i: ImmOpNum).ChangeToImmediate(ImmVal);
6079 }
6080 }
6081
6082 if (Reg.isVirtual() && MRI->use_nodbg_empty(RegNo: Reg))
6083 DefMI->eraseFromBundle();
6084
6085 return true;
6086}
6087
6088/// foldImmediate - 'Reg' is known to be defined by a move immediate
6089/// instruction, try to fold the immediate into the use instruction.
6090bool X86InstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
6091 Register Reg, MachineRegisterInfo *MRI) const {
6092 int64_t ImmVal;
6093 if (!getConstValDefinedInReg(MI: DefMI, Reg, ImmVal))
6094 return false;
6095
6096 return foldImmediateImpl(UseMI, DefMI: &DefMI, Reg, ImmVal, MRI, MakeChange: true);
6097}
6098
6099/// Expand a single-def pseudo instruction to a two-addr
6100/// instruction with two undef reads of the register being defined.
6101/// This is used for mapping:
6102/// %xmm4 = V_SET0
6103/// to:
6104/// %xmm4 = PXORrr undef %xmm4, undef %xmm4
6105///
6106static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
6107 const MCInstrDesc &Desc) {
6108 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
6109 Register Reg = MIB.getReg(Idx: 0);
6110 MIB->setDesc(Desc);
6111
6112 // MachineInstr::addOperand() will insert explicit operands before any
6113 // implicit operands.
6114 MIB.addReg(RegNo: Reg, Flags: RegState::Undef).addReg(RegNo: Reg, Flags: RegState::Undef);
6115 // But we don't trust that.
6116 assert(MIB.getReg(1) == Reg && MIB.getReg(2) == Reg && "Misplaced operand");
6117 return true;
6118}
6119
6120/// Expand a single-def pseudo instruction to a two-addr
6121/// instruction with two %k0 reads.
6122/// This is used for mapping:
6123/// %k4 = K_SET1
6124/// to:
6125/// %k4 = KXNORrr %k0, %k0
6126static bool Expand2AddrKreg(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
6127 Register Reg) {
6128 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
6129 MIB->setDesc(Desc);
6130 MIB.addReg(RegNo: Reg, Flags: RegState::Undef).addReg(RegNo: Reg, Flags: RegState::Undef);
6131 return true;
6132}
6133
6134static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
6135 bool MinusOne) {
6136 MachineBasicBlock &MBB = *MIB->getParent();
6137 const DebugLoc &DL = MIB->getDebugLoc();
6138 Register Reg = MIB.getReg(Idx: 0);
6139
6140 // Insert the XOR.
6141 BuildMI(BB&: MBB, I: MIB.getInstr(), MIMD: DL, MCID: TII.get(Opcode: X86::XOR32rr), DestReg: Reg)
6142 .addReg(RegNo: Reg, Flags: RegState::Undef)
6143 .addReg(RegNo: Reg, Flags: RegState::Undef);
6144
6145 // Turn the pseudo into an INC or DEC.
6146 MIB->setDesc(TII.get(Opcode: MinusOne ? X86::DEC32r : X86::INC32r));
6147 MIB.addReg(RegNo: Reg);
6148
6149 return true;
6150}
6151
6152static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
6153 const TargetInstrInfo &TII,
6154 const X86Subtarget &Subtarget) {
6155 MachineBasicBlock &MBB = *MIB->getParent();
6156 const DebugLoc &DL = MIB->getDebugLoc();
6157 int64_t Imm = MIB->getOperand(i: 1).getImm();
6158 assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
6159 MachineBasicBlock::iterator I = MIB.getInstr();
6160
6161 int StackAdjustment;
6162
6163 if (Subtarget.is64Bit()) {
6164 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
6165 MIB->getOpcode() == X86::MOV32ImmSExti8);
6166
6167 // Can't use push/pop lowering if the function might write to the red zone.
6168 X86MachineFunctionInfo *X86FI =
6169 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
6170 if (X86FI->getUsesRedZone()) {
6171 MIB->setDesc(TII.get(Opcode: MIB->getOpcode() == X86::MOV32ImmSExti8
6172 ? X86::MOV32ri
6173 : X86::MOV64ri));
6174 return true;
6175 }
6176
6177 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
6178 // widen the register if necessary.
6179 StackAdjustment = 8;
6180 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII.get(Opcode: X86::PUSH64i32)).addImm(Val: Imm);
6181 MIB->setDesc(TII.get(Opcode: X86::POP64r));
6182 MIB->getOperand(i: 0).setReg(getX86SubSuperRegister(Reg: MIB.getReg(Idx: 0), Size: 64));
6183 } else {
6184 assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
6185 StackAdjustment = 4;
6186 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII.get(Opcode: X86::PUSH32i)).addImm(Val: Imm);
6187 MIB->setDesc(TII.get(Opcode: X86::POP32r));
6188 }
6189 MIB->removeOperand(OpNo: 1);
6190 MIB->addImplicitDefUseOperands(MF&: *MBB.getParent());
6191
6192 // Build CFI if necessary.
6193 MachineFunction &MF = *MBB.getParent();
6194 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
6195 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo().usesWindowsCFI();
6196 bool NeedsDwarfCFI = !IsWin64Prologue && MF.needsFrameMoves();
6197 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
6198 if (EmitCFI) {
6199 TFL->BuildCFI(
6200 MBB, MBBI: I, DL,
6201 CFIInst: MCCFIInstruction::createAdjustCfaOffset(L: nullptr, Adjustment: StackAdjustment));
6202 TFL->BuildCFI(
6203 MBB, MBBI: std::next(x: I), DL,
6204 CFIInst: MCCFIInstruction::createAdjustCfaOffset(L: nullptr, Adjustment: -StackAdjustment));
6205 }
6206
6207 return true;
6208}
6209
6210// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
6211// code sequence is needed for other targets.
6212static void expandLoadStackGuard(MachineInstrBuilder &MIB,
6213 const TargetInstrInfo &TII) {
6214 MachineBasicBlock &MBB = *MIB->getParent();
6215 const DebugLoc &DL = MIB->getDebugLoc();
6216 Register Reg = MIB.getReg(Idx: 0);
6217 const GlobalValue *GV =
6218 cast<GlobalValue>(Val: (*MIB->memoperands_begin())->getValue());
6219 auto Flags = MachineMemOperand::MOLoad |
6220 MachineMemOperand::MODereferenceable |
6221 MachineMemOperand::MOInvariant;
6222 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
6223 PtrInfo: MachinePointerInfo::getGOT(MF&: *MBB.getParent()), F: Flags, Size: 8, BaseAlignment: Align(8));
6224 MachineBasicBlock::iterator I = MIB.getInstr();
6225
6226 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII.get(Opcode: X86::MOV64rm), DestReg: Reg)
6227 .addReg(RegNo: X86::RIP)
6228 .addImm(Val: 1)
6229 .addReg(RegNo: 0)
6230 .addGlobalAddress(GV, Offset: 0, TargetFlags: X86II::MO_GOTPCREL)
6231 .addReg(RegNo: 0)
6232 .addMemOperand(MMO);
6233 MIB->setDebugLoc(DL);
6234 MIB->setDesc(TII.get(Opcode: X86::MOV64rm));
6235 MIB.addReg(RegNo: Reg, Flags: RegState::Kill).addImm(Val: 1).addReg(RegNo: 0).addImm(Val: 0).addReg(RegNo: 0);
6236}
6237
6238static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
6239 MachineBasicBlock &MBB = *MIB->getParent();
6240 MachineFunction &MF = *MBB.getParent();
6241 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
6242 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
6243 unsigned XorOp =
6244 MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
6245 MIB->setDesc(TII.get(Opcode: XorOp));
6246 MIB.addReg(RegNo: TRI->getFrameRegister(MF), Flags: RegState::Undef);
6247 return true;
6248}
6249
6250// This is used to handle spills for 128/256-bit registers when we have AVX512,
6251// but not VLX. If it uses an extended register we need to use an instruction
6252// that loads the lower 128/256-bit, but is available with only AVX512F.
6253static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
6254 const TargetRegisterInfo *TRI,
6255 const MCInstrDesc &LoadDesc,
6256 const MCInstrDesc &BroadcastDesc, unsigned SubIdx) {
6257 Register DestReg = MIB.getReg(Idx: 0);
6258 // Check if DestReg is XMM16-31 or YMM16-31.
6259 if (TRI->getEncodingValue(Reg: DestReg) < 16) {
6260 // We can use a normal VEX encoded load.
6261 MIB->setDesc(LoadDesc);
6262 } else {
6263 // Use a 128/256-bit VBROADCAST instruction.
6264 MIB->setDesc(BroadcastDesc);
6265 // Change the destination to a 512-bit register.
6266 DestReg = TRI->getMatchingSuperReg(Reg: DestReg, SubIdx, RC: &X86::VR512RegClass);
6267 MIB->getOperand(i: 0).setReg(DestReg);
6268 }
6269 return true;
6270}
6271
6272// This is used to handle spills for 128/256-bit registers when we have AVX512,
6273// but not VLX. If it uses an extended register we need to use an instruction
6274// that stores the lower 128/256-bit, but is available with only AVX512F.
6275static bool expandNOVLXStore(MachineInstrBuilder &MIB,
6276 const TargetRegisterInfo *TRI,
6277 const MCInstrDesc &StoreDesc,
6278 const MCInstrDesc &ExtractDesc, unsigned SubIdx) {
6279 Register SrcReg = MIB.getReg(Idx: X86::AddrNumOperands);
6280 // Check if DestReg is XMM16-31 or YMM16-31.
6281 if (TRI->getEncodingValue(Reg: SrcReg) < 16) {
6282 // We can use a normal VEX encoded store.
6283 MIB->setDesc(StoreDesc);
6284 } else {
6285 // Use a VEXTRACTF instruction.
6286 MIB->setDesc(ExtractDesc);
6287 // Change the destination to a 512-bit register.
6288 SrcReg = TRI->getMatchingSuperReg(Reg: SrcReg, SubIdx, RC: &X86::VR512RegClass);
6289 MIB->getOperand(i: X86::AddrNumOperands).setReg(SrcReg);
6290 MIB.addImm(Val: 0x0); // Append immediate to extract from the lower bits.
6291 }
6292
6293 return true;
6294}
6295
6296static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
6297 MIB->setDesc(Desc);
6298 int64_t ShiftAmt = MIB->getOperand(i: 2).getImm();
6299 // Temporarily remove the immediate so we can add another source register.
6300 MIB->removeOperand(OpNo: 2);
6301 // Add the register. Don't copy the kill flag if there is one.
6302 MIB.addReg(RegNo: MIB.getReg(Idx: 1), Flags: getUndefRegState(B: MIB->getOperand(i: 1).isUndef()));
6303 // Add back the immediate.
6304 MIB.addImm(Val: ShiftAmt);
6305 return true;
6306}
6307
6308static bool expandMOVSHP(MachineInstrBuilder &MIB, MachineInstr &MI,
6309 const TargetInstrInfo &TII, bool HasAVX) {
6310 unsigned NewOpc;
6311 if (MI.getOpcode() == X86::MOVSHPrm) {
6312 NewOpc = HasAVX ? X86::VMOVSSrm : X86::MOVSSrm;
6313 Register Reg = MI.getOperand(i: 0).getReg();
6314 if (Reg > X86::XMM15)
6315 NewOpc = X86::VMOVSSZrm;
6316 } else {
6317 NewOpc = HasAVX ? X86::VMOVSSmr : X86::MOVSSmr;
6318 Register Reg = MI.getOperand(i: 5).getReg();
6319 if (Reg > X86::XMM15)
6320 NewOpc = X86::VMOVSSZmr;
6321 }
6322
6323 MIB->setDesc(TII.get(Opcode: NewOpc));
6324 return true;
6325}
6326
6327bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
6328 bool HasAVX = Subtarget.hasAVX();
6329 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
6330 switch (MI.getOpcode()) {
6331 case X86::MOV32r0:
6332 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::XOR32rr));
6333 case X86::MOV32r1:
6334 return expandMOV32r1(MIB, TII: *this, /*MinusOne=*/false);
6335 case X86::MOV32r_1:
6336 return expandMOV32r1(MIB, TII: *this, /*MinusOne=*/true);
6337 case X86::MOV32ImmSExti8:
6338 case X86::MOV64ImmSExti8:
6339 return ExpandMOVImmSExti8(MIB, TII: *this, Subtarget);
6340 case X86::SETB_C32r:
6341 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::SBB32rr));
6342 case X86::SETB_C64r:
6343 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::SBB64rr));
6344 case X86::MMX_SET0:
6345 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::MMX_PXORrr));
6346 case X86::V_SET0:
6347 case X86::FsFLD0SS:
6348 case X86::FsFLD0SD:
6349 case X86::FsFLD0SH:
6350 case X86::FsFLD0F128:
6351 return Expand2AddrUndef(MIB, Desc: get(Opcode: HasAVX ? X86::VXORPSrr : X86::XORPSrr));
6352 case X86::AVX512_128_SET0:
6353 case X86::AVX512_FsFLD0SH:
6354 case X86::AVX512_FsFLD0SS:
6355 case X86::AVX512_FsFLD0SD:
6356 case X86::AVX512_FsFLD0F128: {
6357 bool HasVLX = Subtarget.hasVLX();
6358 Register SrcReg = MIB.getReg(Idx: 0);
6359 const TargetRegisterInfo *TRI = &getRegisterInfo();
6360 if (HasVLX || TRI->getEncodingValue(Reg: SrcReg) < 16)
6361 return Expand2AddrUndef(MIB,
6362 Desc: get(Opcode: HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
6363 // Extended register without VLX. Use a larger XOR.
6364 SrcReg =
6365 TRI->getMatchingSuperReg(Reg: SrcReg, SubIdx: X86::sub_xmm, RC: &X86::VR512RegClass);
6366 MIB->getOperand(i: 0).setReg(SrcReg);
6367 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::VPXORDZrr));
6368 }
6369 case X86::MOVSHPmr:
6370 case X86::MOVSHPrm:
6371 return expandMOVSHP(MIB, MI, TII: *this, HasAVX: Subtarget.hasAVX());
6372 case X86::V_SETALLONES:
6373 return Expand2AddrUndef(MIB,
6374 Desc: get(Opcode: HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
6375 case X86::AVX2_SETALLONES:
6376 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::VPCMPEQDYrr));
6377 case X86::AVX1_SETALLONES: {
6378 Register Reg = MIB.getReg(Idx: 0);
6379 // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
6380 MIB->setDesc(get(Opcode: X86::VCMPPSYrri));
6381 MIB.addReg(RegNo: Reg, Flags: RegState::Undef).addReg(RegNo: Reg, Flags: RegState::Undef).addImm(Val: 0xf);
6382 return true;
6383 }
6384 case X86::AVX512_128_SETALLONES:
6385 case X86::AVX512_256_SETALLONES:
6386 case X86::AVX512_512_SETALLONES: {
6387 Register Reg = MIB.getReg(Idx: 0);
6388 unsigned Opc;
6389 switch (MI.getOpcode()) {
6390 case X86::AVX512_128_SETALLONES: {
6391 if (X86::VR128RegClass.contains(Reg))
6392 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::VPCMPEQDrr));
6393
6394 Opc = X86::VPTERNLOGDZ128rri;
6395 break;
6396 }
6397 case X86::AVX512_256_SETALLONES: {
6398 if (X86::VR256RegClass.contains(Reg))
6399 return Expand2AddrUndef(MIB, Desc: get(Opcode: X86::VPCMPEQDYrr));
6400
6401 Opc = X86::VPTERNLOGDZ256rri;
6402 break;
6403 }
6404 case X86::AVX512_512_SETALLONES:
6405 Opc = X86::VPTERNLOGDZrri;
6406 break;
6407 }
6408 MIB->setDesc(get(Opcode: Opc));
6409 // VPTERNLOGD needs 3 register inputs and an immediate.
6410 // 0xff will return 1s for any input.
6411 MIB.addReg(RegNo: Reg, Flags: RegState::Undef)
6412 .addReg(RegNo: Reg, Flags: RegState::Undef)
6413 .addReg(RegNo: Reg, Flags: RegState::Undef)
6414 .addImm(Val: 0xff);
6415 return true;
6416 }
6417 case X86::AVX512_512_SEXT_MASK_32:
6418 case X86::AVX512_512_SEXT_MASK_64: {
6419 Register Reg = MIB.getReg(Idx: 0);
6420 Register MaskReg = MIB.getReg(Idx: 1);
6421 RegState MaskState = getRegState(RegOp: MIB->getOperand(i: 1));
6422 unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64)
6423 ? X86::VPTERNLOGQZrrikz
6424 : X86::VPTERNLOGDZrrikz;
6425 MI.removeOperand(OpNo: 1);
6426 MIB->setDesc(get(Opcode: Opc));
6427 // VPTERNLOG needs 3 register inputs and an immediate.
6428 // 0xff will return 1s for any input.
6429 MIB.addReg(RegNo: Reg, Flags: RegState::Undef)
6430 .addReg(RegNo: MaskReg, Flags: MaskState)
6431 .addReg(RegNo: Reg, Flags: RegState::Undef)
6432 .addReg(RegNo: Reg, Flags: RegState::Undef)
6433 .addImm(Val: 0xff);
6434 return true;
6435 }
6436 case X86::VMOVAPSZ128rm_NOVLX:
6437 return expandNOVLXLoad(MIB, TRI: &getRegisterInfo(), LoadDesc: get(Opcode: X86::VMOVAPSrm),
6438 BroadcastDesc: get(Opcode: X86::VBROADCASTF32X4Zrm), SubIdx: X86::sub_xmm);
6439 case X86::VMOVUPSZ128rm_NOVLX:
6440 return expandNOVLXLoad(MIB, TRI: &getRegisterInfo(), LoadDesc: get(Opcode: X86::VMOVUPSrm),
6441 BroadcastDesc: get(Opcode: X86::VBROADCASTF32X4Zrm), SubIdx: X86::sub_xmm);
6442 case X86::VMOVAPSZ256rm_NOVLX:
6443 return expandNOVLXLoad(MIB, TRI: &getRegisterInfo(), LoadDesc: get(Opcode: X86::VMOVAPSYrm),
6444 BroadcastDesc: get(Opcode: X86::VBROADCASTF64X4Zrm), SubIdx: X86::sub_ymm);
6445 case X86::VMOVUPSZ256rm_NOVLX:
6446 return expandNOVLXLoad(MIB, TRI: &getRegisterInfo(), LoadDesc: get(Opcode: X86::VMOVUPSYrm),
6447 BroadcastDesc: get(Opcode: X86::VBROADCASTF64X4Zrm), SubIdx: X86::sub_ymm);
6448 case X86::VMOVAPSZ128mr_NOVLX:
6449 return expandNOVLXStore(MIB, TRI: &getRegisterInfo(), StoreDesc: get(Opcode: X86::VMOVAPSmr),
6450 ExtractDesc: get(Opcode: X86::VEXTRACTF32X4Zmri), SubIdx: X86::sub_xmm);
6451 case X86::VMOVUPSZ128mr_NOVLX:
6452 return expandNOVLXStore(MIB, TRI: &getRegisterInfo(), StoreDesc: get(Opcode: X86::VMOVUPSmr),
6453 ExtractDesc: get(Opcode: X86::VEXTRACTF32X4Zmri), SubIdx: X86::sub_xmm);
6454 case X86::VMOVAPSZ256mr_NOVLX:
6455 return expandNOVLXStore(MIB, TRI: &getRegisterInfo(), StoreDesc: get(Opcode: X86::VMOVAPSYmr),
6456 ExtractDesc: get(Opcode: X86::VEXTRACTF64X4Zmri), SubIdx: X86::sub_ymm);
6457 case X86::VMOVUPSZ256mr_NOVLX:
6458 return expandNOVLXStore(MIB, TRI: &getRegisterInfo(), StoreDesc: get(Opcode: X86::VMOVUPSYmr),
6459 ExtractDesc: get(Opcode: X86::VEXTRACTF64X4Zmri), SubIdx: X86::sub_ymm);
6460 case X86::MOV32ri64: {
6461 Register Reg = MIB.getReg(Idx: 0);
6462 Register Reg32 = RI.getSubReg(Reg, Idx: X86::sub_32bit);
6463 MI.setDesc(get(Opcode: X86::MOV32ri));
6464 MIB->getOperand(i: 0).setReg(Reg32);
6465 MIB.addReg(RegNo: Reg, Flags: RegState::ImplicitDefine);
6466 return true;
6467 }
6468
6469 case X86::RDFLAGS32:
6470 case X86::RDFLAGS64: {
6471 unsigned Is64Bit = MI.getOpcode() == X86::RDFLAGS64;
6472 MachineBasicBlock &MBB = *MIB->getParent();
6473
6474 MachineInstr *NewMI = BuildMI(BB&: MBB, I&: MI, MIMD: MIB->getDebugLoc(),
6475 MCID: get(Opcode: Is64Bit ? X86::PUSHF64 : X86::PUSHF32))
6476 .getInstr();
6477
6478 // Permit reads of the EFLAGS and DF registers without them being defined.
6479 // This intrinsic exists to read external processor state in flags, such as
6480 // the trap flag, interrupt flag, and direction flag, none of which are
6481 // modeled by the backend.
6482 assert(NewMI->getOperand(2).getReg() == X86::EFLAGS &&
6483 "Unexpected register in operand! Should be EFLAGS.");
6484 NewMI->getOperand(i: 2).setIsUndef();
6485 assert(NewMI->getOperand(3).getReg() == X86::DF &&
6486 "Unexpected register in operand! Should be DF.");
6487 NewMI->getOperand(i: 3).setIsUndef();
6488
6489 MIB->setDesc(get(Opcode: Is64Bit ? X86::POP64r : X86::POP32r));
6490 return true;
6491 }
6492
6493 case X86::WRFLAGS32:
6494 case X86::WRFLAGS64: {
6495 unsigned Is64Bit = MI.getOpcode() == X86::WRFLAGS64;
6496 MachineBasicBlock &MBB = *MIB->getParent();
6497
6498 BuildMI(BB&: MBB, I&: MI, MIMD: MIB->getDebugLoc(),
6499 MCID: get(Opcode: Is64Bit ? X86::PUSH64r : X86::PUSH32r))
6500 .addReg(RegNo: MI.getOperand(i: 0).getReg());
6501 BuildMI(BB&: MBB, I&: MI, MIMD: MIB->getDebugLoc(),
6502 MCID: get(Opcode: Is64Bit ? X86::POPF64 : X86::POPF32));
6503 MI.eraseFromParent();
6504 return true;
6505 }
6506
6507 // KNL does not recognize dependency-breaking idioms for mask registers,
6508 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
6509 // Using %k0 as the undef input register is a performance heuristic based
6510 // on the assumption that %k0 is used less frequently than the other mask
6511 // registers, since it is not usable as a write mask.
6512 // FIXME: A more advanced approach would be to choose the best input mask
6513 // register based on context.
6514 case X86::KSET0B:
6515 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXORBkk), Reg: X86::K0);
6516 case X86::KSET0W:
6517 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXORWkk), Reg: X86::K0);
6518 case X86::KSET0D:
6519 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXORDkk), Reg: X86::K0);
6520 case X86::KSET0Q:
6521 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXORQkk), Reg: X86::K0);
6522 case X86::KSET1B:
6523 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXNORBkk), Reg: X86::K0);
6524 case X86::KSET1W:
6525 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXNORWkk), Reg: X86::K0);
6526 case X86::KSET1D:
6527 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXNORDkk), Reg: X86::K0);
6528 case X86::KSET1Q:
6529 return Expand2AddrKreg(MIB, Desc: get(Opcode: X86::KXNORQkk), Reg: X86::K0);
6530 case TargetOpcode::LOAD_STACK_GUARD:
6531 expandLoadStackGuard(MIB, TII: *this);
6532 return true;
6533 case X86::XOR64_FP:
6534 case X86::XOR32_FP:
6535 return expandXorFP(MIB, TII: *this);
6536 case X86::SHLDROT32ri:
6537 return expandSHXDROT(MIB, Desc: get(Opcode: X86::SHLD32rri8));
6538 case X86::SHLDROT64ri:
6539 return expandSHXDROT(MIB, Desc: get(Opcode: X86::SHLD64rri8));
6540 case X86::SHRDROT32ri:
6541 return expandSHXDROT(MIB, Desc: get(Opcode: X86::SHRD32rri8));
6542 case X86::SHRDROT64ri:
6543 return expandSHXDROT(MIB, Desc: get(Opcode: X86::SHRD64rri8));
6544 case X86::ADD8rr_DB:
6545 MIB->setDesc(get(Opcode: X86::OR8rr));
6546 break;
6547 case X86::ADD16rr_DB:
6548 MIB->setDesc(get(Opcode: X86::OR16rr));
6549 break;
6550 case X86::ADD32rr_DB:
6551 MIB->setDesc(get(Opcode: X86::OR32rr));
6552 break;
6553 case X86::ADD64rr_DB:
6554 MIB->setDesc(get(Opcode: X86::OR64rr));
6555 break;
6556 case X86::ADD8ri_DB:
6557 MIB->setDesc(get(Opcode: X86::OR8ri));
6558 break;
6559 case X86::ADD16ri_DB:
6560 MIB->setDesc(get(Opcode: X86::OR16ri));
6561 break;
6562 case X86::ADD32ri_DB:
6563 MIB->setDesc(get(Opcode: X86::OR32ri));
6564 break;
6565 case X86::ADD64ri32_DB:
6566 MIB->setDesc(get(Opcode: X86::OR64ri32));
6567 break;
6568 }
6569 return false;
6570}
6571
6572/// Return true for all instructions that only update
6573/// the first 32 or 64-bits of the destination register and leave the rest
6574/// unmodified. This can be used to avoid folding loads if the instructions
6575/// only update part of the destination register, and the non-updated part is
6576/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
6577/// instructions breaks the partial register dependency and it can improve
6578/// performance. e.g.:
6579///
6580/// movss (%rdi), %xmm0
6581/// cvtss2sd %xmm0, %xmm0
6582///
6583/// Instead of
6584/// cvtss2sd (%rdi), %xmm0
6585///
6586/// FIXME: This should be turned into a TSFlags.
6587///
6588static bool hasPartialRegUpdate(unsigned Opcode, const X86Subtarget &Subtarget,
6589 bool ForLoadFold = false) {
6590 switch (Opcode) {
6591 case X86::CVTSI2SSrr:
6592 case X86::CVTSI2SSrm:
6593 case X86::CVTSI642SSrr:
6594 case X86::CVTSI642SSrm:
6595 case X86::CVTSI2SDrr:
6596 case X86::CVTSI2SDrm:
6597 case X86::CVTSI642SDrr:
6598 case X86::CVTSI642SDrm:
6599 // Load folding won't effect the undef register update since the input is
6600 // a GPR.
6601 return !ForLoadFold;
6602 case X86::CVTSD2SSrr:
6603 case X86::CVTSD2SSrm:
6604 case X86::CVTSS2SDrr:
6605 case X86::CVTSS2SDrm:
6606 case X86::MOVHPDrm:
6607 case X86::MOVHPSrm:
6608 case X86::MOVLPDrm:
6609 case X86::MOVLPSrm:
6610 case X86::RCPSSr:
6611 case X86::RCPSSm:
6612 case X86::RCPSSr_Int:
6613 case X86::RCPSSm_Int:
6614 case X86::ROUNDSDri:
6615 case X86::ROUNDSDmi:
6616 case X86::ROUNDSSri:
6617 case X86::ROUNDSSmi:
6618 case X86::RSQRTSSr:
6619 case X86::RSQRTSSm:
6620 case X86::RSQRTSSr_Int:
6621 case X86::RSQRTSSm_Int:
6622 case X86::SQRTSSr:
6623 case X86::SQRTSSm:
6624 case X86::SQRTSSr_Int:
6625 case X86::SQRTSSm_Int:
6626 case X86::SQRTSDr:
6627 case X86::SQRTSDm:
6628 case X86::SQRTSDr_Int:
6629 case X86::SQRTSDm_Int:
6630 return true;
6631 case X86::VFCMULCPHZ128rm:
6632 case X86::VFCMULCPHZ128rmb:
6633 case X86::VFCMULCPHZ128rmbkz:
6634 case X86::VFCMULCPHZ128rmkz:
6635 case X86::VFCMULCPHZ128rr:
6636 case X86::VFCMULCPHZ128rrkz:
6637 case X86::VFCMULCPHZ256rm:
6638 case X86::VFCMULCPHZ256rmb:
6639 case X86::VFCMULCPHZ256rmbkz:
6640 case X86::VFCMULCPHZ256rmkz:
6641 case X86::VFCMULCPHZ256rr:
6642 case X86::VFCMULCPHZ256rrkz:
6643 case X86::VFCMULCPHZrm:
6644 case X86::VFCMULCPHZrmb:
6645 case X86::VFCMULCPHZrmbkz:
6646 case X86::VFCMULCPHZrmkz:
6647 case X86::VFCMULCPHZrr:
6648 case X86::VFCMULCPHZrrb:
6649 case X86::VFCMULCPHZrrbkz:
6650 case X86::VFCMULCPHZrrkz:
6651 case X86::VFMULCPHZ128rm:
6652 case X86::VFMULCPHZ128rmb:
6653 case X86::VFMULCPHZ128rmbkz:
6654 case X86::VFMULCPHZ128rmkz:
6655 case X86::VFMULCPHZ128rr:
6656 case X86::VFMULCPHZ128rrkz:
6657 case X86::VFMULCPHZ256rm:
6658 case X86::VFMULCPHZ256rmb:
6659 case X86::VFMULCPHZ256rmbkz:
6660 case X86::VFMULCPHZ256rmkz:
6661 case X86::VFMULCPHZ256rr:
6662 case X86::VFMULCPHZ256rrkz:
6663 case X86::VFMULCPHZrm:
6664 case X86::VFMULCPHZrmb:
6665 case X86::VFMULCPHZrmbkz:
6666 case X86::VFMULCPHZrmkz:
6667 case X86::VFMULCPHZrr:
6668 case X86::VFMULCPHZrrb:
6669 case X86::VFMULCPHZrrbkz:
6670 case X86::VFMULCPHZrrkz:
6671 case X86::VFCMULCSHZrm:
6672 case X86::VFCMULCSHZrmkz:
6673 case X86::VFCMULCSHZrr:
6674 case X86::VFCMULCSHZrrb:
6675 case X86::VFCMULCSHZrrbkz:
6676 case X86::VFCMULCSHZrrkz:
6677 case X86::VFMULCSHZrm:
6678 case X86::VFMULCSHZrmkz:
6679 case X86::VFMULCSHZrr:
6680 case X86::VFMULCSHZrrb:
6681 case X86::VFMULCSHZrrbkz:
6682 case X86::VFMULCSHZrrkz:
6683 return Subtarget.hasMULCFalseDeps();
6684 case X86::VPERMDYrm:
6685 case X86::VPERMDYrr:
6686 case X86::VPERMQYmi:
6687 case X86::VPERMQYri:
6688 case X86::VPERMPSYrm:
6689 case X86::VPERMPSYrr:
6690 case X86::VPERMPDYmi:
6691 case X86::VPERMPDYri:
6692 case X86::VPERMDZ256rm:
6693 case X86::VPERMDZ256rmb:
6694 case X86::VPERMDZ256rmbkz:
6695 case X86::VPERMDZ256rmkz:
6696 case X86::VPERMDZ256rr:
6697 case X86::VPERMDZ256rrkz:
6698 case X86::VPERMDZrm:
6699 case X86::VPERMDZrmb:
6700 case X86::VPERMDZrmbkz:
6701 case X86::VPERMDZrmkz:
6702 case X86::VPERMDZrr:
6703 case X86::VPERMDZrrkz:
6704 case X86::VPERMQZ256mbi:
6705 case X86::VPERMQZ256mbikz:
6706 case X86::VPERMQZ256mi:
6707 case X86::VPERMQZ256mikz:
6708 case X86::VPERMQZ256ri:
6709 case X86::VPERMQZ256rikz:
6710 case X86::VPERMQZ256rm:
6711 case X86::VPERMQZ256rmb:
6712 case X86::VPERMQZ256rmbkz:
6713 case X86::VPERMQZ256rmkz:
6714 case X86::VPERMQZ256rr:
6715 case X86::VPERMQZ256rrkz:
6716 case X86::VPERMQZmbi:
6717 case X86::VPERMQZmbikz:
6718 case X86::VPERMQZmi:
6719 case X86::VPERMQZmikz:
6720 case X86::VPERMQZri:
6721 case X86::VPERMQZrikz:
6722 case X86::VPERMQZrm:
6723 case X86::VPERMQZrmb:
6724 case X86::VPERMQZrmbkz:
6725 case X86::VPERMQZrmkz:
6726 case X86::VPERMQZrr:
6727 case X86::VPERMQZrrkz:
6728 case X86::VPERMPSZ256rm:
6729 case X86::VPERMPSZ256rmb:
6730 case X86::VPERMPSZ256rmbkz:
6731 case X86::VPERMPSZ256rmkz:
6732 case X86::VPERMPSZ256rr:
6733 case X86::VPERMPSZ256rrkz:
6734 case X86::VPERMPSZrm:
6735 case X86::VPERMPSZrmb:
6736 case X86::VPERMPSZrmbkz:
6737 case X86::VPERMPSZrmkz:
6738 case X86::VPERMPSZrr:
6739 case X86::VPERMPSZrrkz:
6740 case X86::VPERMPDZ256mbi:
6741 case X86::VPERMPDZ256mbikz:
6742 case X86::VPERMPDZ256mi:
6743 case X86::VPERMPDZ256mikz:
6744 case X86::VPERMPDZ256ri:
6745 case X86::VPERMPDZ256rikz:
6746 case X86::VPERMPDZ256rm:
6747 case X86::VPERMPDZ256rmb:
6748 case X86::VPERMPDZ256rmbkz:
6749 case X86::VPERMPDZ256rmkz:
6750 case X86::VPERMPDZ256rr:
6751 case X86::VPERMPDZ256rrkz:
6752 case X86::VPERMPDZmbi:
6753 case X86::VPERMPDZmbikz:
6754 case X86::VPERMPDZmi:
6755 case X86::VPERMPDZmikz:
6756 case X86::VPERMPDZri:
6757 case X86::VPERMPDZrikz:
6758 case X86::VPERMPDZrm:
6759 case X86::VPERMPDZrmb:
6760 case X86::VPERMPDZrmbkz:
6761 case X86::VPERMPDZrmkz:
6762 case X86::VPERMPDZrr:
6763 case X86::VPERMPDZrrkz:
6764 return Subtarget.hasPERMFalseDeps();
6765 case X86::VRANGEPDZ128rmbi:
6766 case X86::VRANGEPDZ128rmbikz:
6767 case X86::VRANGEPDZ128rmi:
6768 case X86::VRANGEPDZ128rmikz:
6769 case X86::VRANGEPDZ128rri:
6770 case X86::VRANGEPDZ128rrikz:
6771 case X86::VRANGEPDZ256rmbi:
6772 case X86::VRANGEPDZ256rmbikz:
6773 case X86::VRANGEPDZ256rmi:
6774 case X86::VRANGEPDZ256rmikz:
6775 case X86::VRANGEPDZ256rri:
6776 case X86::VRANGEPDZ256rrikz:
6777 case X86::VRANGEPDZrmbi:
6778 case X86::VRANGEPDZrmbikz:
6779 case X86::VRANGEPDZrmi:
6780 case X86::VRANGEPDZrmikz:
6781 case X86::VRANGEPDZrri:
6782 case X86::VRANGEPDZrrib:
6783 case X86::VRANGEPDZrribkz:
6784 case X86::VRANGEPDZrrikz:
6785 case X86::VRANGEPSZ128rmbi:
6786 case X86::VRANGEPSZ128rmbikz:
6787 case X86::VRANGEPSZ128rmi:
6788 case X86::VRANGEPSZ128rmikz:
6789 case X86::VRANGEPSZ128rri:
6790 case X86::VRANGEPSZ128rrikz:
6791 case X86::VRANGEPSZ256rmbi:
6792 case X86::VRANGEPSZ256rmbikz:
6793 case X86::VRANGEPSZ256rmi:
6794 case X86::VRANGEPSZ256rmikz:
6795 case X86::VRANGEPSZ256rri:
6796 case X86::VRANGEPSZ256rrikz:
6797 case X86::VRANGEPSZrmbi:
6798 case X86::VRANGEPSZrmbikz:
6799 case X86::VRANGEPSZrmi:
6800 case X86::VRANGEPSZrmikz:
6801 case X86::VRANGEPSZrri:
6802 case X86::VRANGEPSZrrib:
6803 case X86::VRANGEPSZrribkz:
6804 case X86::VRANGEPSZrrikz:
6805 case X86::VRANGESDZrmi:
6806 case X86::VRANGESDZrmikz:
6807 case X86::VRANGESDZrri:
6808 case X86::VRANGESDZrrib:
6809 case X86::VRANGESDZrribkz:
6810 case X86::VRANGESDZrrikz:
6811 case X86::VRANGESSZrmi:
6812 case X86::VRANGESSZrmikz:
6813 case X86::VRANGESSZrri:
6814 case X86::VRANGESSZrrib:
6815 case X86::VRANGESSZrribkz:
6816 case X86::VRANGESSZrrikz:
6817 return Subtarget.hasRANGEFalseDeps();
6818 case X86::VGETMANTSSZrmi:
6819 case X86::VGETMANTSSZrmikz:
6820 case X86::VGETMANTSSZrri:
6821 case X86::VGETMANTSSZrrib:
6822 case X86::VGETMANTSSZrribkz:
6823 case X86::VGETMANTSSZrrikz:
6824 case X86::VGETMANTSDZrmi:
6825 case X86::VGETMANTSDZrmikz:
6826 case X86::VGETMANTSDZrri:
6827 case X86::VGETMANTSDZrrib:
6828 case X86::VGETMANTSDZrribkz:
6829 case X86::VGETMANTSDZrrikz:
6830 case X86::VGETMANTSHZrmi:
6831 case X86::VGETMANTSHZrmikz:
6832 case X86::VGETMANTSHZrri:
6833 case X86::VGETMANTSHZrrib:
6834 case X86::VGETMANTSHZrribkz:
6835 case X86::VGETMANTSHZrrikz:
6836 case X86::VGETMANTPSZ128rmbi:
6837 case X86::VGETMANTPSZ128rmbikz:
6838 case X86::VGETMANTPSZ128rmi:
6839 case X86::VGETMANTPSZ128rmikz:
6840 case X86::VGETMANTPSZ256rmbi:
6841 case X86::VGETMANTPSZ256rmbikz:
6842 case X86::VGETMANTPSZ256rmi:
6843 case X86::VGETMANTPSZ256rmikz:
6844 case X86::VGETMANTPSZrmbi:
6845 case X86::VGETMANTPSZrmbikz:
6846 case X86::VGETMANTPSZrmi:
6847 case X86::VGETMANTPSZrmikz:
6848 case X86::VGETMANTPDZ128rmbi:
6849 case X86::VGETMANTPDZ128rmbikz:
6850 case X86::VGETMANTPDZ128rmi:
6851 case X86::VGETMANTPDZ128rmikz:
6852 case X86::VGETMANTPDZ256rmbi:
6853 case X86::VGETMANTPDZ256rmbikz:
6854 case X86::VGETMANTPDZ256rmi:
6855 case X86::VGETMANTPDZ256rmikz:
6856 case X86::VGETMANTPDZrmbi:
6857 case X86::VGETMANTPDZrmbikz:
6858 case X86::VGETMANTPDZrmi:
6859 case X86::VGETMANTPDZrmikz:
6860 return Subtarget.hasGETMANTFalseDeps();
6861 case X86::VPMULLQZ128rm:
6862 case X86::VPMULLQZ128rmb:
6863 case X86::VPMULLQZ128rmbkz:
6864 case X86::VPMULLQZ128rmkz:
6865 case X86::VPMULLQZ128rr:
6866 case X86::VPMULLQZ128rrkz:
6867 case X86::VPMULLQZ256rm:
6868 case X86::VPMULLQZ256rmb:
6869 case X86::VPMULLQZ256rmbkz:
6870 case X86::VPMULLQZ256rmkz:
6871 case X86::VPMULLQZ256rr:
6872 case X86::VPMULLQZ256rrkz:
6873 case X86::VPMULLQZrm:
6874 case X86::VPMULLQZrmb:
6875 case X86::VPMULLQZrmbkz:
6876 case X86::VPMULLQZrmkz:
6877 case X86::VPMULLQZrr:
6878 case X86::VPMULLQZrrkz:
6879 return Subtarget.hasMULLQFalseDeps();
6880 case X86::VPCOMPRESSBZ128rrkz:
6881 case X86::VPCOMPRESSBZ256rrkz:
6882 case X86::VPCOMPRESSBZrrkz:
6883 case X86::VPCOMPRESSWZ128rrkz:
6884 case X86::VPCOMPRESSWZ256rrkz:
6885 case X86::VPCOMPRESSWZrrkz:
6886 case X86::VPCOMPRESSDZ128rrkz:
6887 case X86::VPCOMPRESSDZ256rrkz:
6888 case X86::VPCOMPRESSDZrrkz:
6889 case X86::VPCOMPRESSQZ128rrkz:
6890 case X86::VPCOMPRESSQZ256rrkz:
6891 case X86::VPCOMPRESSQZrrkz:
6892 case X86::VCOMPRESSPSZ128rrkz:
6893 case X86::VCOMPRESSPSZ256rrkz:
6894 case X86::VCOMPRESSPSZrrkz:
6895 case X86::VCOMPRESSPDZ128rrkz:
6896 case X86::VCOMPRESSPDZ256rrkz:
6897 case X86::VCOMPRESSPDZrrkz:
6898 return Subtarget.hasCOMPRESSFalseDeps();
6899 case X86::VPEXPANDBZ128rmkz:
6900 case X86::VPEXPANDBZ128rrkz:
6901 case X86::VPEXPANDBZ256rmkz:
6902 case X86::VPEXPANDBZ256rrkz:
6903 case X86::VPEXPANDBZrmkz:
6904 case X86::VPEXPANDBZrrkz:
6905 case X86::VPEXPANDWZ128rmkz:
6906 case X86::VPEXPANDWZ128rrkz:
6907 case X86::VPEXPANDWZ256rmkz:
6908 case X86::VPEXPANDWZ256rrkz:
6909 case X86::VPEXPANDWZrmkz:
6910 case X86::VPEXPANDWZrrkz:
6911 case X86::VPEXPANDDZ128rmkz:
6912 case X86::VPEXPANDDZ128rrkz:
6913 case X86::VPEXPANDDZ256rmkz:
6914 case X86::VPEXPANDDZ256rrkz:
6915 case X86::VPEXPANDDZrmkz:
6916 case X86::VPEXPANDDZrrkz:
6917 case X86::VPEXPANDQZ128rmkz:
6918 case X86::VPEXPANDQZ128rrkz:
6919 case X86::VPEXPANDQZ256rmkz:
6920 case X86::VPEXPANDQZ256rrkz:
6921 case X86::VPEXPANDQZrmkz:
6922 case X86::VPEXPANDQZrrkz:
6923 case X86::VEXPANDPSZ128rmkz:
6924 case X86::VEXPANDPSZ128rrkz:
6925 case X86::VEXPANDPSZ256rmkz:
6926 case X86::VEXPANDPSZ256rrkz:
6927 case X86::VEXPANDPSZrmkz:
6928 case X86::VEXPANDPSZrrkz:
6929 case X86::VEXPANDPDZ128rmkz:
6930 case X86::VEXPANDPDZ128rrkz:
6931 case X86::VEXPANDPDZ256rmkz:
6932 case X86::VEXPANDPDZ256rrkz:
6933 case X86::VEXPANDPDZrmkz:
6934 case X86::VEXPANDPDZrrkz:
6935 return Subtarget.hasEXPANDFalseDeps();
6936 // GPR
6937 case X86::POPCNT32rm:
6938 case X86::POPCNT32rr:
6939 case X86::POPCNT64rm:
6940 case X86::POPCNT64rr:
6941 return Subtarget.hasPOPCNTFalseDeps();
6942 case X86::LZCNT32rm:
6943 case X86::LZCNT32rr:
6944 case X86::LZCNT64rm:
6945 case X86::LZCNT64rr:
6946 return Subtarget.hasLZCNTFalseDeps();
6947 case X86::TZCNT32rm:
6948 case X86::TZCNT32rr:
6949 case X86::TZCNT64rm:
6950 case X86::TZCNT64rr:
6951 return Subtarget.hasTZCNTFalseDeps();
6952 case X86::BLSR32rr:
6953 case X86::BLSR32rm:
6954 case X86::BLSR64rr:
6955 case X86::BLSR64rm:
6956 case X86::BLSI32rr:
6957 case X86::BLSI32rm:
6958 case X86::BLSI64rr:
6959 case X86::BLSI64rm:
6960 case X86::BLSMSK32rr:
6961 case X86::BLSMSK32rm:
6962 case X86::BLSMSK64rr:
6963 case X86::BLSMSK64rm:
6964 return Subtarget.hasBLSFalseDeps() && !ForLoadFold; // Preserve load folding
6965 }
6966
6967 return false;
6968}
6969
6970/// Inform the BreakFalseDeps pass how many idle
6971/// instructions we would like before a partial register update.
6972unsigned X86InstrInfo::getPartialRegUpdateClearance(const MachineInstr &MI,
6973 unsigned OpNum) const {
6974
6975 if (OpNum != 0)
6976 return 0;
6977
6978 // NDD ops with 8/16b results may appear to be partial register
6979 // updates after register allocation.
6980 bool HasNDDPartialWrite = false;
6981 if (X86II::hasNewDataDest(TSFlags: MI.getDesc().TSFlags)) {
6982 Register Reg = MI.getOperand(i: 0).getReg();
6983 if (!Reg.isVirtual())
6984 HasNDDPartialWrite =
6985 X86::GR8RegClass.contains(Reg) || X86::GR16RegClass.contains(Reg);
6986 }
6987
6988 if (!(HasNDDPartialWrite || hasPartialRegUpdate(Opcode: MI.getOpcode(), Subtarget)))
6989 return 0;
6990
6991 // Check if the result register is also used as a source.
6992 // For non-NDD ops, this means a partial update is wanted, hence we return 0.
6993 // For NDD ops, this means it is possible to compress the instruction
6994 // to a legacy form in CompressEVEX, which would create an unwanted partial
6995 // update, so we return the clearance.
6996 const MachineOperand &MO = MI.getOperand(i: 0);
6997 Register Reg = MO.getReg();
6998 bool ReadsReg = false;
6999 if (Reg.isVirtual())
7000 ReadsReg = (MO.readsReg() || MI.readsVirtualRegister(Reg));
7001 else
7002 ReadsReg = MI.readsRegister(Reg, TRI: &RI);
7003 if (ReadsReg != HasNDDPartialWrite)
7004 return 0;
7005
7006 // If any instructions in the clearance range are reading Reg, insert a
7007 // dependency breaking instruction, which is inexpensive and is likely to
7008 // be hidden in other instruction's cycles.
7009 return Subtarget.getCLOpts().partial_reg_update_clearance;
7010}
7011
7012// Return true for any instruction the copies the high bits of the first source
7013// operand into the unused high bits of the destination operand.
7014// Also returns true for instructions that have two inputs where one may
7015// be undef and we want it to use the same register as the other input.
7016static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
7017 bool ForLoadFold = false) {
7018 // Set the OpNum parameter to the first source operand.
7019 switch (Opcode) {
7020 case X86::MMX_PUNPCKHBWrr:
7021 case X86::MMX_PUNPCKHWDrr:
7022 case X86::MMX_PUNPCKHDQrr:
7023 case X86::MMX_PUNPCKLBWrr:
7024 case X86::MMX_PUNPCKLWDrr:
7025 case X86::MMX_PUNPCKLDQrr:
7026 case X86::MOVHLPSrr:
7027 case X86::PACKSSWBrr:
7028 case X86::PACKUSWBrr:
7029 case X86::PACKSSDWrr:
7030 case X86::PACKUSDWrr:
7031 case X86::PUNPCKHBWrr:
7032 case X86::PUNPCKLBWrr:
7033 case X86::PUNPCKHWDrr:
7034 case X86::PUNPCKLWDrr:
7035 case X86::PUNPCKHDQrr:
7036 case X86::PUNPCKLDQrr:
7037 case X86::PUNPCKHQDQrr:
7038 case X86::PUNPCKLQDQrr:
7039 case X86::SHUFPDrri:
7040 case X86::SHUFPSrri:
7041 // These instructions are sometimes used with an undef first or second
7042 // source. Return true here so BreakFalseDeps will assign this source to the
7043 // same register as the first source to avoid a false dependency.
7044 // Operand 1 of these instructions is tied so they're separate from their
7045 // VEX counterparts.
7046 return OpNum == 2 && !ForLoadFold;
7047
7048 case X86::VMOVLHPSrr:
7049 case X86::VMOVLHPSZrr:
7050 case X86::VPACKSSWBrr:
7051 case X86::VPACKUSWBrr:
7052 case X86::VPACKSSDWrr:
7053 case X86::VPACKUSDWrr:
7054 case X86::VPACKSSWBZ128rr:
7055 case X86::VPACKUSWBZ128rr:
7056 case X86::VPACKSSDWZ128rr:
7057 case X86::VPACKUSDWZ128rr:
7058 case X86::VPERM2F128rri:
7059 case X86::VPERM2I128rri:
7060 case X86::VSHUFF32X4Z256rri:
7061 case X86::VSHUFF32X4Zrri:
7062 case X86::VSHUFF64X2Z256rri:
7063 case X86::VSHUFF64X2Zrri:
7064 case X86::VSHUFI32X4Z256rri:
7065 case X86::VSHUFI32X4Zrri:
7066 case X86::VSHUFI64X2Z256rri:
7067 case X86::VSHUFI64X2Zrri:
7068 case X86::VPUNPCKHBWrr:
7069 case X86::VPUNPCKLBWrr:
7070 case X86::VPUNPCKHBWYrr:
7071 case X86::VPUNPCKLBWYrr:
7072 case X86::VPUNPCKHBWZ128rr:
7073 case X86::VPUNPCKLBWZ128rr:
7074 case X86::VPUNPCKHBWZ256rr:
7075 case X86::VPUNPCKLBWZ256rr:
7076 case X86::VPUNPCKHBWZrr:
7077 case X86::VPUNPCKLBWZrr:
7078 case X86::VPUNPCKHWDrr:
7079 case X86::VPUNPCKLWDrr:
7080 case X86::VPUNPCKHWDYrr:
7081 case X86::VPUNPCKLWDYrr:
7082 case X86::VPUNPCKHWDZ128rr:
7083 case X86::VPUNPCKLWDZ128rr:
7084 case X86::VPUNPCKHWDZ256rr:
7085 case X86::VPUNPCKLWDZ256rr:
7086 case X86::VPUNPCKHWDZrr:
7087 case X86::VPUNPCKLWDZrr:
7088 case X86::VPUNPCKHDQrr:
7089 case X86::VPUNPCKLDQrr:
7090 case X86::VPUNPCKHDQYrr:
7091 case X86::VPUNPCKLDQYrr:
7092 case X86::VPUNPCKHDQZ128rr:
7093 case X86::VPUNPCKLDQZ128rr:
7094 case X86::VPUNPCKHDQZ256rr:
7095 case X86::VPUNPCKLDQZ256rr:
7096 case X86::VPUNPCKHDQZrr:
7097 case X86::VPUNPCKLDQZrr:
7098 case X86::VPUNPCKHQDQrr:
7099 case X86::VPUNPCKLQDQrr:
7100 case X86::VPUNPCKHQDQYrr:
7101 case X86::VPUNPCKLQDQYrr:
7102 case X86::VPUNPCKHQDQZ128rr:
7103 case X86::VPUNPCKLQDQZ128rr:
7104 case X86::VPUNPCKHQDQZ256rr:
7105 case X86::VPUNPCKLQDQZ256rr:
7106 case X86::VPUNPCKHQDQZrr:
7107 case X86::VPUNPCKLQDQZrr:
7108 // These instructions are sometimes used with an undef first or second
7109 // source. Return true here so BreakFalseDeps will assign this source to the
7110 // same register as the first source to avoid a false dependency.
7111 return (OpNum == 1 || OpNum == 2) && !ForLoadFold;
7112
7113 case X86::VCVTSI2SSrr:
7114 case X86::VCVTSI2SSrm:
7115 case X86::VCVTSI2SSrr_Int:
7116 case X86::VCVTSI2SSrm_Int:
7117 case X86::VCVTSI642SSrr:
7118 case X86::VCVTSI642SSrm:
7119 case X86::VCVTSI642SSrr_Int:
7120 case X86::VCVTSI642SSrm_Int:
7121 case X86::VCVTSI2SDrr:
7122 case X86::VCVTSI2SDrm:
7123 case X86::VCVTSI2SDrr_Int:
7124 case X86::VCVTSI2SDrm_Int:
7125 case X86::VCVTSI642SDrr:
7126 case X86::VCVTSI642SDrm:
7127 case X86::VCVTSI642SDrr_Int:
7128 case X86::VCVTSI642SDrm_Int:
7129 // AVX-512
7130 case X86::VCVTSI2SSZrr:
7131 case X86::VCVTSI2SSZrm:
7132 case X86::VCVTSI2SSZrr_Int:
7133 case X86::VCVTSI2SSZrrb_Int:
7134 case X86::VCVTSI2SSZrm_Int:
7135 case X86::VCVTSI642SSZrr:
7136 case X86::VCVTSI642SSZrm:
7137 case X86::VCVTSI642SSZrr_Int:
7138 case X86::VCVTSI642SSZrrb_Int:
7139 case X86::VCVTSI642SSZrm_Int:
7140 case X86::VCVTSI2SDZrr:
7141 case X86::VCVTSI2SDZrm:
7142 case X86::VCVTSI2SDZrr_Int:
7143 case X86::VCVTSI2SDZrm_Int:
7144 case X86::VCVTSI642SDZrr:
7145 case X86::VCVTSI642SDZrm:
7146 case X86::VCVTSI642SDZrr_Int:
7147 case X86::VCVTSI642SDZrrb_Int:
7148 case X86::VCVTSI642SDZrm_Int:
7149 case X86::VCVTUSI2SSZrr:
7150 case X86::VCVTUSI2SSZrm:
7151 case X86::VCVTUSI2SSZrr_Int:
7152 case X86::VCVTUSI2SSZrrb_Int:
7153 case X86::VCVTUSI2SSZrm_Int:
7154 case X86::VCVTUSI642SSZrr:
7155 case X86::VCVTUSI642SSZrm:
7156 case X86::VCVTUSI642SSZrr_Int:
7157 case X86::VCVTUSI642SSZrrb_Int:
7158 case X86::VCVTUSI642SSZrm_Int:
7159 case X86::VCVTUSI2SDZrr:
7160 case X86::VCVTUSI2SDZrm:
7161 case X86::VCVTUSI2SDZrr_Int:
7162 case X86::VCVTUSI2SDZrm_Int:
7163 case X86::VCVTUSI642SDZrr:
7164 case X86::VCVTUSI642SDZrm:
7165 case X86::VCVTUSI642SDZrr_Int:
7166 case X86::VCVTUSI642SDZrrb_Int:
7167 case X86::VCVTUSI642SDZrm_Int:
7168 case X86::VCVTSI2SHZrr:
7169 case X86::VCVTSI2SHZrm:
7170 case X86::VCVTSI2SHZrr_Int:
7171 case X86::VCVTSI2SHZrrb_Int:
7172 case X86::VCVTSI2SHZrm_Int:
7173 case X86::VCVTSI642SHZrr:
7174 case X86::VCVTSI642SHZrm:
7175 case X86::VCVTSI642SHZrr_Int:
7176 case X86::VCVTSI642SHZrrb_Int:
7177 case X86::VCVTSI642SHZrm_Int:
7178 case X86::VCVTUSI2SHZrr:
7179 case X86::VCVTUSI2SHZrm:
7180 case X86::VCVTUSI2SHZrr_Int:
7181 case X86::VCVTUSI2SHZrrb_Int:
7182 case X86::VCVTUSI2SHZrm_Int:
7183 case X86::VCVTUSI642SHZrr:
7184 case X86::VCVTUSI642SHZrm:
7185 case X86::VCVTUSI642SHZrr_Int:
7186 case X86::VCVTUSI642SHZrrb_Int:
7187 case X86::VCVTUSI642SHZrm_Int:
7188 // Load folding won't effect the undef register update since the input is
7189 // a GPR.
7190 return OpNum == 1 && !ForLoadFold;
7191 case X86::VCVTSD2SSrr:
7192 case X86::VCVTSD2SSrm:
7193 case X86::VCVTSD2SSrr_Int:
7194 case X86::VCVTSD2SSrm_Int:
7195 case X86::VCVTSS2SDrr:
7196 case X86::VCVTSS2SDrm:
7197 case X86::VCVTSS2SDrr_Int:
7198 case X86::VCVTSS2SDrm_Int:
7199 case X86::VRCPSSr:
7200 case X86::VRCPSSr_Int:
7201 case X86::VRCPSSm:
7202 case X86::VRCPSSm_Int:
7203 case X86::VROUNDSDri:
7204 case X86::VROUNDSDmi:
7205 case X86::VROUNDSDri_Int:
7206 case X86::VROUNDSDmi_Int:
7207 case X86::VROUNDSSri:
7208 case X86::VROUNDSSmi:
7209 case X86::VROUNDSSri_Int:
7210 case X86::VROUNDSSmi_Int:
7211 case X86::VRSQRTSSr:
7212 case X86::VRSQRTSSr_Int:
7213 case X86::VRSQRTSSm:
7214 case X86::VRSQRTSSm_Int:
7215 case X86::VSQRTSSr:
7216 case X86::VSQRTSSr_Int:
7217 case X86::VSQRTSSm:
7218 case X86::VSQRTSSm_Int:
7219 case X86::VSQRTSDr:
7220 case X86::VSQRTSDr_Int:
7221 case X86::VSQRTSDm:
7222 case X86::VSQRTSDm_Int:
7223 // AVX-512
7224 case X86::VCVTSD2SSZrr:
7225 case X86::VCVTSD2SSZrr_Int:
7226 case X86::VCVTSD2SSZrrb_Int:
7227 case X86::VCVTSD2SSZrm:
7228 case X86::VCVTSD2SSZrm_Int:
7229 case X86::VCVTSS2SDZrr:
7230 case X86::VCVTSS2SDZrr_Int:
7231 case X86::VCVTSS2SDZrrb_Int:
7232 case X86::VCVTSS2SDZrm:
7233 case X86::VCVTSS2SDZrm_Int:
7234 case X86::VGETEXPSDZr:
7235 case X86::VGETEXPSDZrb:
7236 case X86::VGETEXPSDZm:
7237 case X86::VGETEXPSSZr:
7238 case X86::VGETEXPSSZrb:
7239 case X86::VGETEXPSSZm:
7240 case X86::VGETMANTSDZrri:
7241 case X86::VGETMANTSDZrrib:
7242 case X86::VGETMANTSDZrmi:
7243 case X86::VGETMANTSSZrri:
7244 case X86::VGETMANTSSZrrib:
7245 case X86::VGETMANTSSZrmi:
7246 case X86::VRNDSCALESDZrri:
7247 case X86::VRNDSCALESDZrri_Int:
7248 case X86::VRNDSCALESDZrrib_Int:
7249 case X86::VRNDSCALESDZrmi:
7250 case X86::VRNDSCALESDZrmi_Int:
7251 case X86::VRNDSCALESSZrri:
7252 case X86::VRNDSCALESSZrri_Int:
7253 case X86::VRNDSCALESSZrrib_Int:
7254 case X86::VRNDSCALESSZrmi:
7255 case X86::VRNDSCALESSZrmi_Int:
7256 case X86::VRCP14SDZrr:
7257 case X86::VRCP14SDZrm:
7258 case X86::VRCP14SSZrr:
7259 case X86::VRCP14SSZrm:
7260 case X86::VRCPSHZrr:
7261 case X86::VRCPSHZrm:
7262 case X86::VRSQRTSHZrr:
7263 case X86::VRSQRTSHZrm:
7264 case X86::VREDUCESHZrmi:
7265 case X86::VREDUCESHZrri:
7266 case X86::VREDUCESHZrrib:
7267 case X86::VGETEXPSHZr:
7268 case X86::VGETEXPSHZrb:
7269 case X86::VGETEXPSHZm:
7270 case X86::VGETMANTSHZrri:
7271 case X86::VGETMANTSHZrrib:
7272 case X86::VGETMANTSHZrmi:
7273 case X86::VRNDSCALESHZrri:
7274 case X86::VRNDSCALESHZrri_Int:
7275 case X86::VRNDSCALESHZrrib_Int:
7276 case X86::VRNDSCALESHZrmi:
7277 case X86::VRNDSCALESHZrmi_Int:
7278 case X86::VSQRTSHZr:
7279 case X86::VSQRTSHZr_Int:
7280 case X86::VSQRTSHZrb_Int:
7281 case X86::VSQRTSHZm:
7282 case X86::VSQRTSHZm_Int:
7283 case X86::VRCP28SDZr:
7284 case X86::VRCP28SDZrb:
7285 case X86::VRCP28SDZm:
7286 case X86::VRCP28SSZr:
7287 case X86::VRCP28SSZrb:
7288 case X86::VRCP28SSZm:
7289 case X86::VREDUCESSZrmi:
7290 case X86::VREDUCESSZrri:
7291 case X86::VREDUCESSZrrib:
7292 case X86::VRSQRT14SDZrr:
7293 case X86::VRSQRT14SDZrm:
7294 case X86::VRSQRT14SSZrr:
7295 case X86::VRSQRT14SSZrm:
7296 case X86::VRSQRT28SDZr:
7297 case X86::VRSQRT28SDZrb:
7298 case X86::VRSQRT28SDZm:
7299 case X86::VRSQRT28SSZr:
7300 case X86::VRSQRT28SSZrb:
7301 case X86::VRSQRT28SSZm:
7302 case X86::VSQRTSSZr:
7303 case X86::VSQRTSSZr_Int:
7304 case X86::VSQRTSSZrb_Int:
7305 case X86::VSQRTSSZm:
7306 case X86::VSQRTSSZm_Int:
7307 case X86::VSQRTSDZr:
7308 case X86::VSQRTSDZr_Int:
7309 case X86::VSQRTSDZrb_Int:
7310 case X86::VSQRTSDZm:
7311 case X86::VSQRTSDZm_Int:
7312 case X86::VCVTSD2SHZrr:
7313 case X86::VCVTSD2SHZrr_Int:
7314 case X86::VCVTSD2SHZrrb_Int:
7315 case X86::VCVTSD2SHZrm:
7316 case X86::VCVTSD2SHZrm_Int:
7317 case X86::VCVTSS2SHZrr:
7318 case X86::VCVTSS2SHZrr_Int:
7319 case X86::VCVTSS2SHZrrb_Int:
7320 case X86::VCVTSS2SHZrm:
7321 case X86::VCVTSS2SHZrm_Int:
7322 case X86::VCVTSH2SDZrr:
7323 case X86::VCVTSH2SDZrr_Int:
7324 case X86::VCVTSH2SDZrrb_Int:
7325 case X86::VCVTSH2SDZrm:
7326 case X86::VCVTSH2SDZrm_Int:
7327 case X86::VCVTSH2SSZrr:
7328 case X86::VCVTSH2SSZrr_Int:
7329 case X86::VCVTSH2SSZrrb_Int:
7330 case X86::VCVTSH2SSZrm:
7331 case X86::VCVTSH2SSZrm_Int:
7332 return OpNum == 1;
7333 case X86::VMOVSSZrrk:
7334 case X86::VMOVSDZrrk:
7335 return OpNum == 3 && !ForLoadFold;
7336 case X86::VMOVSSZrrkz:
7337 case X86::VMOVSDZrrkz:
7338 return OpNum == 2 && !ForLoadFold;
7339 }
7340
7341 return false;
7342}
7343
7344/// Inform the BreakFalseDeps pass how many idle instructions we would like
7345/// before certain undef register reads.
7346///
7347/// This catches the VCVTSI2SD family of instructions:
7348///
7349/// vcvtsi2sdq %rax, undef %xmm0, %xmm14
7350///
7351/// We should to be careful *not* to catch VXOR idioms which are presumably
7352/// handled specially in the pipeline:
7353///
7354/// vxorps undef %xmm1, undef %xmm1, %xmm1
7355///
7356/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
7357/// high bits that are passed-through are not live.
7358unsigned X86InstrInfo::getUndefRegClearance(const MachineInstr &MI,
7359 unsigned OpNum) const {
7360 const MachineOperand &MO = MI.getOperand(i: OpNum);
7361 if (MO.getReg().isPhysical() && hasUndefRegUpdate(Opcode: MI.getOpcode(), OpNum))
7362 return Subtarget.getCLOpts().undef_reg_clearance;
7363
7364 return 0;
7365}
7366
7367void X86InstrInfo::breakPartialRegDependency(MachineInstr &MI,
7368 unsigned OpNum) const {
7369 Register Reg = MI.getOperand(i: OpNum).getReg();
7370 // If MI kills this register, the false dependence is already broken.
7371 if (MI.killsRegister(Reg, TRI: &RI))
7372 return;
7373
7374 if (X86::VR128RegClass.contains(Reg)) {
7375 // These instructions are all floating point domain, so xorps is the best
7376 // choice.
7377 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
7378 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Opc), DestReg: Reg)
7379 .addReg(RegNo: Reg, Flags: RegState::Undef)
7380 .addReg(RegNo: Reg, Flags: RegState::Undef);
7381 MI.addRegisterKilled(IncomingReg: Reg, RegInfo: &RI, AddIfNotFound: true);
7382 } else if (X86::VR256RegClass.contains(Reg)) {
7383 // Use vxorps to clear the full ymm register.
7384 // It wants to read and write the xmm sub-register.
7385 Register XReg = RI.getSubReg(Reg, Idx: X86::sub_xmm);
7386 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::VXORPSrr), DestReg: XReg)
7387 .addReg(RegNo: XReg, Flags: RegState::Undef)
7388 .addReg(RegNo: XReg, Flags: RegState::Undef)
7389 .addReg(RegNo: Reg, Flags: RegState::ImplicitDefine);
7390 MI.addRegisterKilled(IncomingReg: Reg, RegInfo: &RI, AddIfNotFound: true);
7391 } else if (X86::VR128XRegClass.contains(Reg)) {
7392 // Only handle VLX targets.
7393 if (!Subtarget.hasVLX())
7394 return;
7395 // Since vxorps requires AVX512DQ, vpxord should be the best choice.
7396 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::VPXORDZ128rr), DestReg: Reg)
7397 .addReg(RegNo: Reg, Flags: RegState::Undef)
7398 .addReg(RegNo: Reg, Flags: RegState::Undef);
7399 MI.addRegisterKilled(IncomingReg: Reg, RegInfo: &RI, AddIfNotFound: true);
7400 } else if (X86::VR256XRegClass.contains(Reg) ||
7401 X86::VR512RegClass.contains(Reg)) {
7402 // Only handle VLX targets.
7403 if (!Subtarget.hasVLX())
7404 return;
7405 // Use vpxord to clear the full ymm/zmm register.
7406 // It wants to read and write the xmm sub-register.
7407 Register XReg = RI.getSubReg(Reg, Idx: X86::sub_xmm);
7408 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::VPXORDZ128rr), DestReg: XReg)
7409 .addReg(RegNo: XReg, Flags: RegState::Undef)
7410 .addReg(RegNo: XReg, Flags: RegState::Undef)
7411 .addReg(RegNo: Reg, Flags: RegState::ImplicitDefine);
7412 MI.addRegisterKilled(IncomingReg: Reg, RegInfo: &RI, AddIfNotFound: true);
7413 } else if (X86::GR64RegClass.contains(Reg)) {
7414 // Using XOR32rr because it has shorter encoding and zeros up the upper bits
7415 // as well.
7416 Register XReg = RI.getSubReg(Reg, Idx: X86::sub_32bit);
7417 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::XOR32rr), DestReg: XReg)
7418 .addReg(RegNo: XReg, Flags: RegState::Undef)
7419 .addReg(RegNo: XReg, Flags: RegState::Undef)
7420 .addReg(RegNo: Reg, Flags: RegState::ImplicitDefine);
7421 MI.addRegisterKilled(IncomingReg: Reg, RegInfo: &RI, AddIfNotFound: true);
7422 } else if (X86::GR32RegClass.contains(Reg)) {
7423 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: X86::XOR32rr), DestReg: Reg)
7424 .addReg(RegNo: Reg, Flags: RegState::Undef)
7425 .addReg(RegNo: Reg, Flags: RegState::Undef);
7426 MI.addRegisterKilled(IncomingReg: Reg, RegInfo: &RI, AddIfNotFound: true);
7427 } else if ((X86::GR16RegClass.contains(Reg) ||
7428 X86::GR8RegClass.contains(Reg)) &&
7429 X86II::hasNewDataDest(TSFlags: MI.getDesc().TSFlags)) {
7430 // This case is only expected for NDD ops which appear to be partial
7431 // writes, but are not due to the zeroing of the upper part. Here
7432 // we add an implicit def of the superegister, which prevents
7433 // CompressEVEX from converting this to a legacy form.
7434 Register SuperReg = getX86SubSuperRegister(Reg, Size: 64);
7435 MachineInstrBuilder BuildMI(*MI.getParent()->getParent(), &MI);
7436 if (!MI.definesRegister(Reg: SuperReg, /*TRI=*/nullptr))
7437 BuildMI.addReg(RegNo: SuperReg, Flags: RegState::ImplicitDefine);
7438 }
7439}
7440
7441static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
7442 int PtrOffset = 0) {
7443 unsigned NumAddrOps = MOs.size();
7444
7445 if (NumAddrOps < 4) {
7446 // FrameIndex only - add an immediate offset (whether its zero or not).
7447 for (unsigned i = 0; i != NumAddrOps; ++i)
7448 MIB.add(MO: MOs[i]);
7449 addOffset(MIB, Offset: PtrOffset);
7450 } else {
7451 // General Memory Addressing - we need to add any offset to an existing
7452 // offset.
7453 assert(MOs.size() == 5 && "Unexpected memory operand list length");
7454 for (unsigned i = 0; i != NumAddrOps; ++i) {
7455 const MachineOperand &MO = MOs[i];
7456 if (i == 3 && PtrOffset != 0) {
7457 MIB.addDisp(Disp: MO, off: PtrOffset);
7458 } else {
7459 MIB.add(MO);
7460 }
7461 }
7462 }
7463}
7464
7465static void updateOperandRegConstraints(MachineFunction &MF,
7466 MachineInstr &NewMI,
7467 const TargetInstrInfo &TII) {
7468 MachineRegisterInfo &MRI = MF.getRegInfo();
7469
7470 for (int Idx : llvm::seq<int>(Begin: 0, End: NewMI.getNumOperands())) {
7471 MachineOperand &MO = NewMI.getOperand(i: Idx);
7472 // We only need to update constraints on virtual register operands.
7473 if (!MO.isReg())
7474 continue;
7475 Register Reg = MO.getReg();
7476 if (!Reg.isVirtual())
7477 continue;
7478
7479 auto *NewRC =
7480 MRI.constrainRegClass(Reg, RC: TII.getRegClass(MCID: NewMI.getDesc(), OpNum: Idx));
7481 if (!NewRC) {
7482 LLVM_DEBUG(
7483 dbgs() << "WARNING: Unable to update register constraint for operand "
7484 << Idx << " of instruction:\n";
7485 NewMI.dump(); dbgs() << "\n");
7486 }
7487 }
7488}
7489
7490static MachineInstr *fuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
7491 ArrayRef<MachineOperand> MOs,
7492 MachineBasicBlock::iterator InsertPt,
7493 MachineInstr &MI,
7494 const TargetInstrInfo &TII) {
7495 // Create the base instruction with the memory operand as the first part.
7496 // Omit the implicit operands, something BuildMI can't do.
7497 MachineInstr *NewMI =
7498 MF.CreateMachineInstr(MCID: TII.get(Opcode), DL: MI.getDebugLoc(), NoImplicit: true);
7499 MachineInstrBuilder MIB(MF, NewMI);
7500 addOperands(MIB, MOs);
7501
7502 // Loop over the rest of the ri operands, converting them over.
7503 unsigned NumOps = MI.getDesc().getNumOperands() - 2;
7504 for (unsigned i = 0; i != NumOps; ++i) {
7505 MachineOperand &MO = MI.getOperand(i: i + 2);
7506 MIB.add(MO);
7507 }
7508 for (const MachineOperand &MO : llvm::drop_begin(RangeOrContainer: MI.operands(), N: NumOps + 2))
7509 MIB.add(MO);
7510
7511 updateOperandRegConstraints(MF, NewMI&: *NewMI, TII);
7512
7513 MachineBasicBlock *MBB = InsertPt->getParent();
7514 MBB->insert(I: InsertPt, MI: NewMI);
7515
7516 return MIB;
7517}
7518
7519static MachineInstr *fuseInst(MachineFunction &MF, unsigned Opcode,
7520 unsigned OpNo, ArrayRef<MachineOperand> MOs,
7521 MachineBasicBlock::iterator InsertPt,
7522 MachineInstr &MI, const TargetInstrInfo &TII,
7523 int PtrOffset = 0) {
7524 // Omit the implicit operands, something BuildMI can't do.
7525 MachineInstr *NewMI =
7526 MF.CreateMachineInstr(MCID: TII.get(Opcode), DL: MI.getDebugLoc(), NoImplicit: true);
7527 MachineInstrBuilder MIB(MF, NewMI);
7528
7529 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
7530 MachineOperand &MO = MI.getOperand(i);
7531 if (i == OpNo) {
7532 assert(MO.isReg() && "Expected to fold into reg operand!");
7533 addOperands(MIB, MOs, PtrOffset);
7534 } else {
7535 MIB.add(MO);
7536 }
7537 }
7538
7539 updateOperandRegConstraints(MF, NewMI&: *NewMI, TII);
7540
7541 // Copy the NoFPExcept flag from the instruction we're fusing.
7542 if (MI.getFlag(Flag: MachineInstr::MIFlag::NoFPExcept))
7543 NewMI->setFlag(MachineInstr::MIFlag::NoFPExcept);
7544
7545 MachineBasicBlock *MBB = InsertPt->getParent();
7546 MBB->insert(I: InsertPt, MI: NewMI);
7547
7548 return MIB;
7549}
7550
7551static MachineInstr *makeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
7552 ArrayRef<MachineOperand> MOs,
7553 MachineBasicBlock::iterator InsertPt,
7554 MachineInstr &MI) {
7555 MachineInstrBuilder MIB = BuildMI(BB&: *InsertPt->getParent(), I: InsertPt,
7556 MIMD: MI.getDebugLoc(), MCID: TII.get(Opcode));
7557 addOperands(MIB, MOs);
7558 return MIB.addImm(Val: 0);
7559}
7560
7561MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
7562 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
7563 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
7564 unsigned Size, Align Alignment) const {
7565 switch (MI.getOpcode()) {
7566 case X86::INSERTPSrri:
7567 case X86::VINSERTPSrri:
7568 case X86::VINSERTPSZrri:
7569 // Attempt to convert the load of inserted vector into a fold load
7570 // of a single float.
7571 if (OpNum == 2) {
7572 unsigned Imm = MI.getOperand(i: MI.getNumOperands() - 1).getImm();
7573 unsigned ZMask = Imm & 15;
7574 unsigned DstIdx = (Imm >> 4) & 3;
7575 unsigned SrcIdx = (Imm >> 6) & 3;
7576
7577 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7578 const TargetRegisterClass *RC = getRegClass(MCID: MI.getDesc(), OpNum);
7579 unsigned RCSize = TRI.getRegSizeInBits(RC: *RC) / 8;
7580 if ((Size == 0 || Size >= 16) && RCSize >= 16 &&
7581 (MI.getOpcode() != X86::INSERTPSrri || Alignment >= Align(4))) {
7582 int PtrOffset = SrcIdx * 4;
7583 unsigned NewImm = (DstIdx << 4) | ZMask;
7584 unsigned NewOpCode =
7585 (MI.getOpcode() == X86::VINSERTPSZrri) ? X86::VINSERTPSZrmi
7586 : (MI.getOpcode() == X86::VINSERTPSrri) ? X86::VINSERTPSrmi
7587 : X86::INSERTPSrmi;
7588 MachineInstr *NewMI =
7589 fuseInst(MF, Opcode: NewOpCode, OpNo: OpNum, MOs, InsertPt, MI, TII: *this, PtrOffset);
7590 NewMI->getOperand(i: NewMI->getNumOperands() - 1).setImm(NewImm);
7591 return NewMI;
7592 }
7593 }
7594 break;
7595 case X86::MOVHLPSrr:
7596 case X86::VMOVHLPSrr:
7597 case X86::VMOVHLPSZrr:
7598 // Move the upper 64-bits of the second operand to the lower 64-bits.
7599 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
7600 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
7601 if (OpNum == 2) {
7602 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7603 const TargetRegisterClass *RC = getRegClass(MCID: MI.getDesc(), OpNum);
7604 unsigned RCSize = TRI.getRegSizeInBits(RC: *RC) / 8;
7605 if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(8)) {
7606 unsigned NewOpCode =
7607 (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm
7608 : (MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm
7609 : X86::MOVLPSrm;
7610 MachineInstr *NewMI =
7611 fuseInst(MF, Opcode: NewOpCode, OpNo: OpNum, MOs, InsertPt, MI, TII: *this, PtrOffset: 8);
7612 return NewMI;
7613 }
7614 }
7615 break;
7616 case X86::UNPCKLPDrr:
7617 // If we won't be able to fold this to the memory form of UNPCKL, use
7618 // MOVHPD instead. Done as custom because we can't have this in the load
7619 // table twice.
7620 if (OpNum == 2) {
7621 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7622 const TargetRegisterClass *RC = getRegClass(MCID: MI.getDesc(), OpNum);
7623 unsigned RCSize = TRI.getRegSizeInBits(RC: *RC) / 8;
7624 if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment < Align(16)) {
7625 MachineInstr *NewMI =
7626 fuseInst(MF, Opcode: X86::MOVHPDrm, OpNo: OpNum, MOs, InsertPt, MI, TII: *this);
7627 return NewMI;
7628 }
7629 }
7630 break;
7631 case X86::MOV32r0:
7632 if (auto *NewMI =
7633 makeM0Inst(TII: *this, Opcode: (Size == 4) ? X86::MOV32mi : X86::MOV64mi32, MOs,
7634 InsertPt, MI))
7635 return NewMI;
7636 break;
7637 }
7638
7639 return nullptr;
7640}
7641
7642static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
7643 MachineInstr &MI) {
7644 if (!hasUndefRegUpdate(Opcode: MI.getOpcode(), OpNum: 1, /*ForLoadFold*/ true) ||
7645 !MI.getOperand(i: 1).isReg())
7646 return false;
7647
7648 // The are two cases we need to handle depending on where in the pipeline
7649 // the folding attempt is being made.
7650 // -Register has the undef flag set.
7651 // -Register is produced by the IMPLICIT_DEF instruction.
7652
7653 if (MI.getOperand(i: 1).isUndef())
7654 return true;
7655
7656 MachineRegisterInfo &RegInfo = MF.getRegInfo();
7657 MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(Reg: MI.getOperand(i: 1).getReg());
7658 return VRegDef && VRegDef->isImplicitDef();
7659}
7660
7661unsigned X86InstrInfo::commuteOperandsForFold(MachineInstr &MI,
7662 unsigned Idx1) const {
7663 unsigned Idx2 = CommuteAnyOperandIndex;
7664 if (!findCommutedOpIndices(MI, SrcOpIdx1&: Idx1, SrcOpIdx2&: Idx2))
7665 return Idx1;
7666
7667 bool HasDef = MI.getDesc().getNumDefs();
7668 Register Reg0 = HasDef ? MI.getOperand(i: 0).getReg() : Register();
7669 Register Reg1 = MI.getOperand(i: Idx1).getReg();
7670 Register Reg2 = MI.getOperand(i: Idx2).getReg();
7671 bool Tied1 = 0 == MI.getDesc().getOperandConstraint(OpNum: Idx1, Constraint: MCOI::TIED_TO);
7672 bool Tied2 = 0 == MI.getDesc().getOperandConstraint(OpNum: Idx2, Constraint: MCOI::TIED_TO);
7673
7674 // If either of the commutable operands are tied to the destination
7675 // then we can not commute + fold.
7676 if ((HasDef && Reg0 == Reg1 && Tied1) || (HasDef && Reg0 == Reg2 && Tied2))
7677 return Idx1;
7678
7679 return commuteInstruction(MI, NewMI: false, OpIdx1: Idx1, OpIdx2: Idx2) ? Idx2 : Idx1;
7680}
7681
7682static void printFailMsgforFold(const MachineInstr &MI, unsigned Idx) {
7683 const X86Subtarget &ST = MI.getMF()->getSubtarget<X86Subtarget>();
7684 if (ST.getCLOpts().print_failed_fuse_candidates && !MI.isCopy())
7685 dbgs() << "We failed to fuse operand " << Idx << " in " << MI;
7686}
7687
7688MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
7689 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
7690 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
7691 unsigned Size, Align Alignment, bool AllowCommute, MachineInstr *&CopyMI,
7692 VirtRegMap *VRM) const {
7693 bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
7694 bool isSlowIndirectCall = Subtarget.slowIndirectCall();
7695 unsigned Opc = MI.getOpcode();
7696
7697 // For CPUs that favor the register form of a call,
7698 // do not fold loads into calls, unless optimizing for size aggressively.
7699 if ((isSlowTwoMemOps || isSlowIndirectCall) &&
7700 !MF.getFunction().hasMinSize() &&
7701 (Opc == X86::CALL32r || Opc == X86::CALL64r ||
7702 Opc == X86::CALL64r_ImpCall))
7703 return nullptr;
7704
7705 // For CPUs that favor the register form of a push,
7706 // do not fold loads into pushes, unless optimizing for size aggressively.
7707 if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
7708 (Opc == X86::PUSH16r || Opc == X86::PUSH32r || Opc == X86::PUSH64r))
7709 return nullptr;
7710
7711 // Avoid partial and undef register update stalls unless optimizing for size.
7712 if (!MF.getFunction().hasOptSize() &&
7713 (hasPartialRegUpdate(Opcode: Opc, Subtarget, /*ForLoadFold*/ true) ||
7714 shouldPreventUndefRegUpdateMemFold(MF, MI)))
7715 return nullptr;
7716
7717 unsigned NumOps = MI.getDesc().getNumOperands();
7718 bool IsTwoAddr = NumOps > 1 && OpNum < 2 && MI.getOperand(i: 0).isReg() &&
7719 MI.getOperand(i: 1).isReg() &&
7720 MI.getOperand(i: 0).getReg() == MI.getOperand(i: 1).getReg();
7721
7722 // FIXME: AsmPrinter doesn't know how to handle
7723 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
7724 if (Opc == X86::ADD32ri &&
7725 MI.getOperand(i: 2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
7726 return nullptr;
7727
7728 // GOTTPOFF relocation loads can only be folded into add instructions.
7729 // FIXME: Need to exclude other relocations that only support specific
7730 // instructions.
7731 if (MOs.size() == X86::AddrNumOperands &&
7732 MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
7733 Opc != X86::ADD64rr)
7734 return nullptr;
7735
7736 // Don't fold loads into indirect calls that need a KCFI check as we'll
7737 // have to unfold these in X86TargetLowering::EmitKCFICheck anyway.
7738 if (MI.isCall() && MI.getCFIType())
7739 return nullptr;
7740
7741 // Attempt to fold any custom cases we have.
7742 if (auto *CustomMI = foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt,
7743 Size, Alignment))
7744 return CustomMI;
7745
7746 // Folding a memory location into the two-address part of a two-address
7747 // instruction is different than folding it other places. It requires
7748 // replacing the *two* registers with the memory location.
7749 //
7750 // Utilize the mapping NonNDD -> RMW for the NDD variant.
7751 unsigned NonNDOpc = Subtarget.hasNDD() ? X86::getNonNDVariant(Opc) : 0U;
7752 // Utilize the mapping NonNDD if NDD memory variant is not preferred.
7753 bool NoNDDM = NonNDOpc && !Subtarget.hasNDDM();
7754
7755 MachineRegisterInfo &MRI = MF.getRegInfo();
7756 if (NoNDDM && !IsTwoAddr && !MRI.isSSA()) {
7757 // Bail out if dst has subreg. It happens during register-coalescer from
7758 // 704B %19:gr32 = SUB32rr_ND killed %0:gr32, killed %7:gr32, ...
7759 // 752B undef %23.sub_32bit:gr64 = COPY killed %19:gr32
7760 // 768B %25:gr32 = LEA64_32r killed %23:gr64, 1, killed %21:gr64_nosp, ...
7761 // to
7762 // 704B undef %23.sub_32bit:gr64_with_sub_8bit = SUB32rr_ND %0:gr32, ...
7763 // 768B %25:gr32 = LEA64_32r %23:gr64_with_sub_8bit, 1, %21:gr64_nosp, ...
7764 // Machine verifier fails if we try to tie %23 to the source.
7765 if (MI.getOperand(i: 0).getSubReg())
7766 return nullptr;
7767
7768 // Bail out if dst has been assigned a physical register. Otherwise, we
7769 // cannot update LiveRegMatrix properly.
7770 Register Dst = MI.getOperand(i: 0).getReg();
7771 if (VRM && Dst != MI.getOperand(i: 1).getReg() &&
7772 (!Dst.isVirtual() || VRM->getPhys(virtReg: Dst)))
7773 return nullptr;
7774 }
7775
7776 const X86FoldTableEntry *I =
7777 IsTwoAddr ? lookupTwoAddrFoldTable(RegOp: NonNDOpc ? NonNDOpc : Opc)
7778 : lookupFoldTable(RegOp: NoNDDM ? NonNDOpc : Opc, OpNum);
7779
7780 MachineInstr *NewMI = nullptr;
7781 if (I) {
7782 unsigned Opcode = I->DstOp;
7783 if (Alignment <
7784 Align(1ULL << ((I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT)))
7785 return nullptr;
7786 bool NarrowToMOV32rm = false;
7787 if (Size) {
7788 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7789 const TargetRegisterClass *RC = getRegClass(MCID: MI.getDesc(), OpNum);
7790 unsigned RCSize = TRI.getRegSizeInBits(RC: *RC) / 8;
7791 // Check if it's safe to fold the load. If the size of the object is
7792 // narrower than the load width, then it's not.
7793 // FIXME: Allow scalar intrinsic instructions like ADDSSrm_Int.
7794 if ((I->Flags & TB_FOLDED_LOAD) && Size < RCSize) {
7795 // If this is a 64-bit load, but the spill slot is 32, then we can do
7796 // a 32-bit load which is implicitly zero-extended. This likely is
7797 // due to live interval analysis remat'ing a load from stack slot.
7798 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
7799 return nullptr;
7800 if (MI.getOperand(i: 0).getSubReg() || MI.getOperand(i: 1).getSubReg())
7801 return nullptr;
7802 Opcode = X86::MOV32rm;
7803 NarrowToMOV32rm = true;
7804 }
7805 // For stores, make sure the size of the object is equal to the size of
7806 // the store. If the object is larger, the extra bits would be garbage. If
7807 // the object is smaller we might overwrite another object or fault.
7808 if ((I->Flags & TB_FOLDED_STORE) && Size != RCSize)
7809 return nullptr;
7810 }
7811
7812 NewMI = IsTwoAddr ? fuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, TII: *this)
7813 : fuseInst(MF, Opcode, OpNo: OpNum, MOs, InsertPt, MI, TII: *this);
7814
7815 if (NarrowToMOV32rm) {
7816 // If this is the special case where we use a MOV32rm to load a 32-bit
7817 // value and zero-extend the top bits. Change the destination register
7818 // to a 32-bit one.
7819 Register DstReg = NewMI->getOperand(i: 0).getReg();
7820 if (DstReg.isPhysical())
7821 NewMI->getOperand(i: 0).setReg(RI.getSubReg(Reg: DstReg, Idx: X86::sub_32bit));
7822 else
7823 NewMI->getOperand(i: 0).setSubReg(X86::sub_32bit);
7824 }
7825
7826 if (NoNDDM && !IsTwoAddr) {
7827 Register SrcReg = MI.getOperand(i: 1).getReg();
7828 unsigned SrcSub = MI.getOperand(i: 1).getSubReg();
7829 if (MI.killsRegister(Reg: SrcReg, /*TRI=*/nullptr) ||
7830 MI.getOperand(i: 0).getReg() == SrcReg)
7831 return NewMI;
7832
7833 Register NewSrc = MI.getOperand(i: 0).getReg();
7834 if (MRI.isSSA())
7835 NewSrc = MRI.createVirtualRegister(RegClass: getRegClass(MCID: NewMI->getDesc(), OpNum: 1));
7836
7837 CopyMI = BuildMI(BB&: *NewMI->getParent(), I&: *NewMI, MIMD: MI.getDebugLoc(),
7838 MCID: get(Opcode: TargetOpcode::COPY))
7839 .addDef(RegNo: NewSrc)
7840 .addReg(RegNo: SrcReg, Flags: {}, SubReg: SrcSub);
7841 NewMI->getOperand(i: 1).setReg(NewSrc);
7842 NewMI->getOperand(i: 1).setSubReg(0);
7843 }
7844 return NewMI;
7845 }
7846
7847 if (AllowCommute) {
7848 // If the instruction and target operand are commutable, commute the
7849 // instruction and try again.
7850 unsigned CommuteOpIdx2 = commuteOperandsForFold(MI, Idx1: OpNum);
7851 if (CommuteOpIdx2 == OpNum) {
7852 printFailMsgforFold(MI, Idx: OpNum);
7853 return nullptr;
7854 }
7855 // Attempt to fold with the commuted version of the instruction.
7856 NewMI = foldMemoryOperandImpl(MF, MI, OpNum: CommuteOpIdx2, MOs, InsertPt, Size,
7857 Alignment, /*AllowCommute=*/false, CopyMI);
7858 if (NewMI)
7859 return NewMI;
7860 // Folding failed again - undo the commute before returning.
7861 commuteInstruction(MI, NewMI: false, OpIdx1: OpNum, OpIdx2: CommuteOpIdx2);
7862 }
7863
7864 printFailMsgforFold(MI, Idx: OpNum);
7865 return nullptr;
7866}
7867
7868MachineInstr *
7869X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
7870 ArrayRef<unsigned> Ops, int FrameIndex,
7871 MachineInstr *&CopyMI, LiveIntervals *LIS,
7872 VirtRegMap *VRM) const {
7873 MachineBasicBlock::iterator InsertPt = MI;
7874 // Check switch flag
7875 if (Subtarget.getCLOpts().disable_spill_fusing)
7876 return nullptr;
7877
7878 // Avoid partial and undef register update stalls unless optimizing for size.
7879 if (!MF.getFunction().hasOptSize() &&
7880 (hasPartialRegUpdate(Opcode: MI.getOpcode(), Subtarget, /*ForLoadFold*/ true) ||
7881 shouldPreventUndefRegUpdateMemFold(MF, MI)))
7882 return nullptr;
7883
7884 // Don't fold subreg spills, or reloads that use a high subreg.
7885 for (auto Op : Ops) {
7886 MachineOperand &MO = MI.getOperand(i: Op);
7887 auto SubReg = MO.getSubReg();
7888 // MOV32r0 is special b/c it's used to clear a 64-bit register too.
7889 // (See patterns for MOV32r0 in TD files).
7890 if (MI.getOpcode() == X86::MOV32r0 && SubReg == X86::sub_32bit)
7891 continue;
7892 if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
7893 return nullptr;
7894 }
7895
7896 const MachineFrameInfo &MFI = MF.getFrameInfo();
7897 unsigned Size = MFI.getObjectSize(ObjectIdx: FrameIndex);
7898 Align Alignment = MFI.getObjectAlign(ObjectIdx: FrameIndex);
7899 // If the function stack isn't realigned we don't want to fold instructions
7900 // that need increased alignment.
7901 if (!RI.hasStackRealignment(MF))
7902 Alignment =
7903 std::min(a: Alignment, b: Subtarget.getFrameLowering()->getStackAlign());
7904
7905 auto Impl = [&]() {
7906 return foldMemoryOperandImpl(
7907 MF, MI, OpNum: Ops[0], MOs: MachineOperand::CreateFI(Idx: FrameIndex), InsertPt, Size,
7908 Alignment, /*AllowCommute=*/true, CopyMI, VRM);
7909 };
7910 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
7911 unsigned NewOpc = 0;
7912 unsigned RCSize = 0;
7913 unsigned Opc = MI.getOpcode();
7914 switch (Opc) {
7915 default:
7916 // NDD can be folded into RMW though its Op0 and Op1 are not tied.
7917 return (Subtarget.hasNDD() ? X86::getNonNDVariant(Opc) : 0U) ? Impl()
7918 : nullptr;
7919 case X86::TEST8rr:
7920 NewOpc = X86::CMP8ri;
7921 RCSize = 1;
7922 break;
7923 case X86::TEST16rr:
7924 NewOpc = X86::CMP16ri;
7925 RCSize = 2;
7926 break;
7927 case X86::TEST32rr:
7928 NewOpc = X86::CMP32ri;
7929 RCSize = 4;
7930 break;
7931 case X86::TEST64rr:
7932 NewOpc = X86::CMP64ri32;
7933 RCSize = 8;
7934 break;
7935 }
7936 // Check if it's safe to fold the load. If the size of the object is
7937 // narrower than the load width, then it's not.
7938 if (Size < RCSize)
7939 return nullptr;
7940 // Change to CMPXXri r, 0 first.
7941 MI.setDesc(get(Opcode: NewOpc));
7942 MI.getOperand(i: 1).ChangeToImmediate(ImmVal: 0);
7943 } else if (Ops.size() != 1)
7944 return nullptr;
7945
7946 return Impl();
7947}
7948
7949/// Check if \p LoadMI is a partial register load that we can't fold into \p MI
7950/// because the latter uses contents that wouldn't be defined in the folded
7951/// version. For instance, this transformation isn't legal:
7952/// movss (%rdi), %xmm0
7953/// addps %xmm0, %xmm0
7954/// ->
7955/// addps (%rdi), %xmm0
7956///
7957/// But this one is:
7958/// movss (%rdi), %xmm0
7959/// addss %xmm0, %xmm0
7960/// ->
7961/// addss (%rdi), %xmm0
7962///
7963static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
7964 const MachineInstr &UserMI,
7965 const MachineFunction &MF) {
7966 unsigned Opc = LoadMI.getOpcode();
7967 unsigned UserOpc = UserMI.getOpcode();
7968 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7969 const TargetRegisterClass *RC =
7970 MF.getRegInfo().getRegClass(Reg: LoadMI.getOperand(i: 0).getReg());
7971 unsigned RegSize = TRI.getRegSizeInBits(RC: *RC);
7972
7973 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm ||
7974 Opc == X86::MOVSSrm_alt || Opc == X86::VMOVSSrm_alt ||
7975 Opc == X86::VMOVSSZrm_alt) &&
7976 RegSize > 32) {
7977 // These instructions only load 32 bits, we can't fold them if the
7978 // destination register is wider than 32 bits (4 bytes), and its user
7979 // instruction isn't scalar (SS).
7980 switch (UserOpc) {
7981 case X86::CVTSS2SDrr_Int:
7982 case X86::VCVTSS2SDrr_Int:
7983 case X86::VCVTSS2SDZrr_Int:
7984 case X86::VCVTSS2SDZrrk_Int:
7985 case X86::VCVTSS2SDZrrkz_Int:
7986 case X86::CVTSS2SIrr_Int:
7987 case X86::CVTSS2SI64rr_Int:
7988 case X86::VCVTSS2SIrr_Int:
7989 case X86::VCVTSS2SI64rr_Int:
7990 case X86::VCVTSS2SIZrr_Int:
7991 case X86::VCVTSS2SI64Zrr_Int:
7992 case X86::CVTTSS2SIrr_Int:
7993 case X86::CVTTSS2SI64rr_Int:
7994 case X86::VCVTTSS2SIrr_Int:
7995 case X86::VCVTTSS2SI64rr_Int:
7996 case X86::VCVTTSS2SIZrr_Int:
7997 case X86::VCVTTSS2SI64Zrr_Int:
7998 case X86::VCVTSS2USIZrr_Int:
7999 case X86::VCVTSS2USI64Zrr_Int:
8000 case X86::VCVTTSS2USIZrr_Int:
8001 case X86::VCVTTSS2USI64Zrr_Int:
8002 case X86::RCPSSr_Int:
8003 case X86::VRCPSSr_Int:
8004 case X86::RSQRTSSr_Int:
8005 case X86::VRSQRTSSr_Int:
8006 case X86::ROUNDSSri_Int:
8007 case X86::VROUNDSSri_Int:
8008 case X86::COMISSrr_Int:
8009 case X86::VCOMISSrr_Int:
8010 case X86::VCOMISSZrr_Int:
8011 case X86::UCOMISSrr_Int:
8012 case X86::VUCOMISSrr_Int:
8013 case X86::VUCOMISSZrr_Int:
8014 case X86::ADDSSrr_Int:
8015 case X86::VADDSSrr_Int:
8016 case X86::VADDSSZrr_Int:
8017 case X86::CMPSSrri_Int:
8018 case X86::VCMPSSrri_Int:
8019 case X86::VCMPSSZrri_Int:
8020 case X86::DIVSSrr_Int:
8021 case X86::VDIVSSrr_Int:
8022 case X86::VDIVSSZrr_Int:
8023 case X86::MAXSSrr_Int:
8024 case X86::VMAXSSrr_Int:
8025 case X86::VMAXSSZrr_Int:
8026 case X86::MINSSrr_Int:
8027 case X86::VMINSSrr_Int:
8028 case X86::VMINSSZrr_Int:
8029 case X86::MULSSrr_Int:
8030 case X86::VMULSSrr_Int:
8031 case X86::VMULSSZrr_Int:
8032 case X86::SQRTSSr_Int:
8033 case X86::VSQRTSSr_Int:
8034 case X86::VSQRTSSZr_Int:
8035 case X86::SUBSSrr_Int:
8036 case X86::VSUBSSrr_Int:
8037 case X86::VSUBSSZrr_Int:
8038 case X86::VADDSSZrrk_Int:
8039 case X86::VADDSSZrrkz_Int:
8040 case X86::VCMPSSZrrik_Int:
8041 case X86::VDIVSSZrrk_Int:
8042 case X86::VDIVSSZrrkz_Int:
8043 case X86::VMAXSSZrrk_Int:
8044 case X86::VMAXSSZrrkz_Int:
8045 case X86::VMINSSZrrk_Int:
8046 case X86::VMINSSZrrkz_Int:
8047 case X86::VMULSSZrrk_Int:
8048 case X86::VMULSSZrrkz_Int:
8049 case X86::VSQRTSSZrk_Int:
8050 case X86::VSQRTSSZrkz_Int:
8051 case X86::VSUBSSZrrk_Int:
8052 case X86::VSUBSSZrrkz_Int:
8053 case X86::VFMADDSS4rr_Int:
8054 case X86::VFNMADDSS4rr_Int:
8055 case X86::VFMSUBSS4rr_Int:
8056 case X86::VFNMSUBSS4rr_Int:
8057 case X86::VFMADD132SSr_Int:
8058 case X86::VFNMADD132SSr_Int:
8059 case X86::VFMADD213SSr_Int:
8060 case X86::VFNMADD213SSr_Int:
8061 case X86::VFMADD231SSr_Int:
8062 case X86::VFNMADD231SSr_Int:
8063 case X86::VFMSUB132SSr_Int:
8064 case X86::VFNMSUB132SSr_Int:
8065 case X86::VFMSUB213SSr_Int:
8066 case X86::VFNMSUB213SSr_Int:
8067 case X86::VFMSUB231SSr_Int:
8068 case X86::VFNMSUB231SSr_Int:
8069 case X86::VFMADD132SSZr_Int:
8070 case X86::VFNMADD132SSZr_Int:
8071 case X86::VFMADD213SSZr_Int:
8072 case X86::VFNMADD213SSZr_Int:
8073 case X86::VFMADD231SSZr_Int:
8074 case X86::VFNMADD231SSZr_Int:
8075 case X86::VFMSUB132SSZr_Int:
8076 case X86::VFNMSUB132SSZr_Int:
8077 case X86::VFMSUB213SSZr_Int:
8078 case X86::VFNMSUB213SSZr_Int:
8079 case X86::VFMSUB231SSZr_Int:
8080 case X86::VFNMSUB231SSZr_Int:
8081 case X86::VFMADD132SSZrk_Int:
8082 case X86::VFNMADD132SSZrk_Int:
8083 case X86::VFMADD213SSZrk_Int:
8084 case X86::VFNMADD213SSZrk_Int:
8085 case X86::VFMADD231SSZrk_Int:
8086 case X86::VFNMADD231SSZrk_Int:
8087 case X86::VFMSUB132SSZrk_Int:
8088 case X86::VFNMSUB132SSZrk_Int:
8089 case X86::VFMSUB213SSZrk_Int:
8090 case X86::VFNMSUB213SSZrk_Int:
8091 case X86::VFMSUB231SSZrk_Int:
8092 case X86::VFNMSUB231SSZrk_Int:
8093 case X86::VFMADD132SSZrkz_Int:
8094 case X86::VFNMADD132SSZrkz_Int:
8095 case X86::VFMADD213SSZrkz_Int:
8096 case X86::VFNMADD213SSZrkz_Int:
8097 case X86::VFMADD231SSZrkz_Int:
8098 case X86::VFNMADD231SSZrkz_Int:
8099 case X86::VFMSUB132SSZrkz_Int:
8100 case X86::VFNMSUB132SSZrkz_Int:
8101 case X86::VFMSUB213SSZrkz_Int:
8102 case X86::VFNMSUB213SSZrkz_Int:
8103 case X86::VFMSUB231SSZrkz_Int:
8104 case X86::VFNMSUB231SSZrkz_Int:
8105 case X86::VFIXUPIMMSSZrri:
8106 case X86::VFIXUPIMMSSZrrik:
8107 case X86::VFIXUPIMMSSZrrikz:
8108 case X86::VFPCLASSSSZri:
8109 case X86::VFPCLASSSSZrik:
8110 case X86::VGETEXPSSZr:
8111 case X86::VGETEXPSSZrk:
8112 case X86::VGETEXPSSZrkz:
8113 case X86::VGETMANTSSZrri:
8114 case X86::VGETMANTSSZrrik:
8115 case X86::VGETMANTSSZrrikz:
8116 case X86::VRANGESSZrri:
8117 case X86::VRANGESSZrrik:
8118 case X86::VRANGESSZrrikz:
8119 case X86::VRCP14SSZrr:
8120 case X86::VRCP14SSZrrk:
8121 case X86::VRCP14SSZrrkz:
8122 case X86::VRCP28SSZr:
8123 case X86::VRCP28SSZrk:
8124 case X86::VRCP28SSZrkz:
8125 case X86::VREDUCESSZrri:
8126 case X86::VREDUCESSZrrik:
8127 case X86::VREDUCESSZrrikz:
8128 case X86::VRNDSCALESSZrri_Int:
8129 case X86::VRNDSCALESSZrrik_Int:
8130 case X86::VRNDSCALESSZrrikz_Int:
8131 case X86::VRSQRT14SSZrr:
8132 case X86::VRSQRT14SSZrrk:
8133 case X86::VRSQRT14SSZrrkz:
8134 case X86::VRSQRT28SSZr:
8135 case X86::VRSQRT28SSZrk:
8136 case X86::VRSQRT28SSZrkz:
8137 case X86::VSCALEFSSZrr:
8138 case X86::VSCALEFSSZrrk:
8139 case X86::VSCALEFSSZrrkz:
8140 return false;
8141 default:
8142 return true;
8143 }
8144 }
8145
8146 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm ||
8147 Opc == X86::MOVSDrm_alt || Opc == X86::VMOVSDrm_alt ||
8148 Opc == X86::VMOVSDZrm_alt) &&
8149 RegSize > 64) {
8150 // These instructions only load 64 bits, we can't fold them if the
8151 // destination register is wider than 64 bits (8 bytes), and its user
8152 // instruction isn't scalar (SD).
8153 switch (UserOpc) {
8154 case X86::CVTSD2SSrr_Int:
8155 case X86::VCVTSD2SSrr_Int:
8156 case X86::VCVTSD2SSZrr_Int:
8157 case X86::VCVTSD2SSZrrk_Int:
8158 case X86::VCVTSD2SSZrrkz_Int:
8159 case X86::CVTSD2SIrr_Int:
8160 case X86::CVTSD2SI64rr_Int:
8161 case X86::VCVTSD2SIrr_Int:
8162 case X86::VCVTSD2SI64rr_Int:
8163 case X86::VCVTSD2SIZrr_Int:
8164 case X86::VCVTSD2SI64Zrr_Int:
8165 case X86::CVTTSD2SIrr_Int:
8166 case X86::CVTTSD2SI64rr_Int:
8167 case X86::VCVTTSD2SIrr_Int:
8168 case X86::VCVTTSD2SI64rr_Int:
8169 case X86::VCVTTSD2SIZrr_Int:
8170 case X86::VCVTTSD2SI64Zrr_Int:
8171 case X86::VCVTSD2USIZrr_Int:
8172 case X86::VCVTSD2USI64Zrr_Int:
8173 case X86::VCVTTSD2USIZrr_Int:
8174 case X86::VCVTTSD2USI64Zrr_Int:
8175 case X86::ROUNDSDri_Int:
8176 case X86::VROUNDSDri_Int:
8177 case X86::COMISDrr_Int:
8178 case X86::VCOMISDrr_Int:
8179 case X86::VCOMISDZrr_Int:
8180 case X86::UCOMISDrr_Int:
8181 case X86::VUCOMISDrr_Int:
8182 case X86::VUCOMISDZrr_Int:
8183 case X86::ADDSDrr_Int:
8184 case X86::VADDSDrr_Int:
8185 case X86::VADDSDZrr_Int:
8186 case X86::CMPSDrri_Int:
8187 case X86::VCMPSDrri_Int:
8188 case X86::VCMPSDZrri_Int:
8189 case X86::DIVSDrr_Int:
8190 case X86::VDIVSDrr_Int:
8191 case X86::VDIVSDZrr_Int:
8192 case X86::MAXSDrr_Int:
8193 case X86::VMAXSDrr_Int:
8194 case X86::VMAXSDZrr_Int:
8195 case X86::MINSDrr_Int:
8196 case X86::VMINSDrr_Int:
8197 case X86::VMINSDZrr_Int:
8198 case X86::MULSDrr_Int:
8199 case X86::VMULSDrr_Int:
8200 case X86::VMULSDZrr_Int:
8201 case X86::SQRTSDr_Int:
8202 case X86::VSQRTSDr_Int:
8203 case X86::VSQRTSDZr_Int:
8204 case X86::SUBSDrr_Int:
8205 case X86::VSUBSDrr_Int:
8206 case X86::VSUBSDZrr_Int:
8207 case X86::VADDSDZrrk_Int:
8208 case X86::VADDSDZrrkz_Int:
8209 case X86::VCMPSDZrrik_Int:
8210 case X86::VDIVSDZrrk_Int:
8211 case X86::VDIVSDZrrkz_Int:
8212 case X86::VMAXSDZrrk_Int:
8213 case X86::VMAXSDZrrkz_Int:
8214 case X86::VMINSDZrrk_Int:
8215 case X86::VMINSDZrrkz_Int:
8216 case X86::VMULSDZrrk_Int:
8217 case X86::VMULSDZrrkz_Int:
8218 case X86::VSQRTSDZrk_Int:
8219 case X86::VSQRTSDZrkz_Int:
8220 case X86::VSUBSDZrrk_Int:
8221 case X86::VSUBSDZrrkz_Int:
8222 case X86::VFMADDSD4rr_Int:
8223 case X86::VFNMADDSD4rr_Int:
8224 case X86::VFMSUBSD4rr_Int:
8225 case X86::VFNMSUBSD4rr_Int:
8226 case X86::VFMADD132SDr_Int:
8227 case X86::VFNMADD132SDr_Int:
8228 case X86::VFMADD213SDr_Int:
8229 case X86::VFNMADD213SDr_Int:
8230 case X86::VFMADD231SDr_Int:
8231 case X86::VFNMADD231SDr_Int:
8232 case X86::VFMSUB132SDr_Int:
8233 case X86::VFNMSUB132SDr_Int:
8234 case X86::VFMSUB213SDr_Int:
8235 case X86::VFNMSUB213SDr_Int:
8236 case X86::VFMSUB231SDr_Int:
8237 case X86::VFNMSUB231SDr_Int:
8238 case X86::VFMADD132SDZr_Int:
8239 case X86::VFNMADD132SDZr_Int:
8240 case X86::VFMADD213SDZr_Int:
8241 case X86::VFNMADD213SDZr_Int:
8242 case X86::VFMADD231SDZr_Int:
8243 case X86::VFNMADD231SDZr_Int:
8244 case X86::VFMSUB132SDZr_Int:
8245 case X86::VFNMSUB132SDZr_Int:
8246 case X86::VFMSUB213SDZr_Int:
8247 case X86::VFNMSUB213SDZr_Int:
8248 case X86::VFMSUB231SDZr_Int:
8249 case X86::VFNMSUB231SDZr_Int:
8250 case X86::VFMADD132SDZrk_Int:
8251 case X86::VFNMADD132SDZrk_Int:
8252 case X86::VFMADD213SDZrk_Int:
8253 case X86::VFNMADD213SDZrk_Int:
8254 case X86::VFMADD231SDZrk_Int:
8255 case X86::VFNMADD231SDZrk_Int:
8256 case X86::VFMSUB132SDZrk_Int:
8257 case X86::VFNMSUB132SDZrk_Int:
8258 case X86::VFMSUB213SDZrk_Int:
8259 case X86::VFNMSUB213SDZrk_Int:
8260 case X86::VFMSUB231SDZrk_Int:
8261 case X86::VFNMSUB231SDZrk_Int:
8262 case X86::VFMADD132SDZrkz_Int:
8263 case X86::VFNMADD132SDZrkz_Int:
8264 case X86::VFMADD213SDZrkz_Int:
8265 case X86::VFNMADD213SDZrkz_Int:
8266 case X86::VFMADD231SDZrkz_Int:
8267 case X86::VFNMADD231SDZrkz_Int:
8268 case X86::VFMSUB132SDZrkz_Int:
8269 case X86::VFNMSUB132SDZrkz_Int:
8270 case X86::VFMSUB213SDZrkz_Int:
8271 case X86::VFNMSUB213SDZrkz_Int:
8272 case X86::VFMSUB231SDZrkz_Int:
8273 case X86::VFNMSUB231SDZrkz_Int:
8274 case X86::VFIXUPIMMSDZrri:
8275 case X86::VFIXUPIMMSDZrrik:
8276 case X86::VFIXUPIMMSDZrrikz:
8277 case X86::VFPCLASSSDZri:
8278 case X86::VFPCLASSSDZrik:
8279 case X86::VGETEXPSDZr:
8280 case X86::VGETEXPSDZrk:
8281 case X86::VGETEXPSDZrkz:
8282 case X86::VGETMANTSDZrri:
8283 case X86::VGETMANTSDZrrik:
8284 case X86::VGETMANTSDZrrikz:
8285 case X86::VRANGESDZrri:
8286 case X86::VRANGESDZrrik:
8287 case X86::VRANGESDZrrikz:
8288 case X86::VRCP14SDZrr:
8289 case X86::VRCP14SDZrrk:
8290 case X86::VRCP14SDZrrkz:
8291 case X86::VRCP28SDZr:
8292 case X86::VRCP28SDZrk:
8293 case X86::VRCP28SDZrkz:
8294 case X86::VREDUCESDZrri:
8295 case X86::VREDUCESDZrrik:
8296 case X86::VREDUCESDZrrikz:
8297 case X86::VRNDSCALESDZrri_Int:
8298 case X86::VRNDSCALESDZrrik_Int:
8299 case X86::VRNDSCALESDZrrikz_Int:
8300 case X86::VRSQRT14SDZrr:
8301 case X86::VRSQRT14SDZrrk:
8302 case X86::VRSQRT14SDZrrkz:
8303 case X86::VRSQRT28SDZr:
8304 case X86::VRSQRT28SDZrk:
8305 case X86::VRSQRT28SDZrkz:
8306 case X86::VSCALEFSDZrr:
8307 case X86::VSCALEFSDZrrk:
8308 case X86::VSCALEFSDZrrkz:
8309 return false;
8310 default:
8311 return true;
8312 }
8313 }
8314
8315 if ((Opc == X86::VMOVSHZrm || Opc == X86::VMOVSHZrm_alt) && RegSize > 16) {
8316 // These instructions only load 16 bits, we can't fold them if the
8317 // destination register is wider than 16 bits (2 bytes), and its user
8318 // instruction isn't scalar (SH).
8319 switch (UserOpc) {
8320 case X86::VADDSHZrr_Int:
8321 case X86::VCMPSHZrri_Int:
8322 case X86::VDIVSHZrr_Int:
8323 case X86::VMAXSHZrr_Int:
8324 case X86::VMINSHZrr_Int:
8325 case X86::VMULSHZrr_Int:
8326 case X86::VSUBSHZrr_Int:
8327 case X86::VADDSHZrrk_Int:
8328 case X86::VADDSHZrrkz_Int:
8329 case X86::VCMPSHZrrik_Int:
8330 case X86::VDIVSHZrrk_Int:
8331 case X86::VDIVSHZrrkz_Int:
8332 case X86::VMAXSHZrrk_Int:
8333 case X86::VMAXSHZrrkz_Int:
8334 case X86::VMINSHZrrk_Int:
8335 case X86::VMINSHZrrkz_Int:
8336 case X86::VMULSHZrrk_Int:
8337 case X86::VMULSHZrrkz_Int:
8338 case X86::VSUBSHZrrk_Int:
8339 case X86::VSUBSHZrrkz_Int:
8340 case X86::VFMADD132SHZr_Int:
8341 case X86::VFNMADD132SHZr_Int:
8342 case X86::VFMADD213SHZr_Int:
8343 case X86::VFNMADD213SHZr_Int:
8344 case X86::VFMADD231SHZr_Int:
8345 case X86::VFNMADD231SHZr_Int:
8346 case X86::VFMSUB132SHZr_Int:
8347 case X86::VFNMSUB132SHZr_Int:
8348 case X86::VFMSUB213SHZr_Int:
8349 case X86::VFNMSUB213SHZr_Int:
8350 case X86::VFMSUB231SHZr_Int:
8351 case X86::VFNMSUB231SHZr_Int:
8352 case X86::VFMADD132SHZrk_Int:
8353 case X86::VFNMADD132SHZrk_Int:
8354 case X86::VFMADD213SHZrk_Int:
8355 case X86::VFNMADD213SHZrk_Int:
8356 case X86::VFMADD231SHZrk_Int:
8357 case X86::VFNMADD231SHZrk_Int:
8358 case X86::VFMSUB132SHZrk_Int:
8359 case X86::VFNMSUB132SHZrk_Int:
8360 case X86::VFMSUB213SHZrk_Int:
8361 case X86::VFNMSUB213SHZrk_Int:
8362 case X86::VFMSUB231SHZrk_Int:
8363 case X86::VFNMSUB231SHZrk_Int:
8364 case X86::VFMADD132SHZrkz_Int:
8365 case X86::VFNMADD132SHZrkz_Int:
8366 case X86::VFMADD213SHZrkz_Int:
8367 case X86::VFNMADD213SHZrkz_Int:
8368 case X86::VFMADD231SHZrkz_Int:
8369 case X86::VFNMADD231SHZrkz_Int:
8370 case X86::VFMSUB132SHZrkz_Int:
8371 case X86::VFNMSUB132SHZrkz_Int:
8372 case X86::VFMSUB213SHZrkz_Int:
8373 case X86::VFNMSUB213SHZrkz_Int:
8374 case X86::VFMSUB231SHZrkz_Int:
8375 case X86::VFNMSUB231SHZrkz_Int:
8376 return false;
8377 default:
8378 return true;
8379 }
8380 }
8381
8382 return false;
8383}
8384
8385MachineInstr *
8386X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
8387 ArrayRef<unsigned> Ops,
8388 MachineInstr &LoadMI, MachineInstr *&CopyMI,
8389 LiveIntervals *LIS, VirtRegMap *VRM) const {
8390 MachineBasicBlock::iterator InsertPt = MI;
8391
8392 // If LoadMI is a masked load, check MI having the same mask.
8393 const MCInstrDesc &MCID = get(Opcode: LoadMI.getOpcode());
8394 unsigned NumOps = MCID.getNumOperands();
8395 if (NumOps >= 3) {
8396 Register MaskReg;
8397 const MachineOperand &Op1 = LoadMI.getOperand(i: 1);
8398 const MachineOperand &Op2 = LoadMI.getOperand(i: 2);
8399
8400 auto IsVKWMClass = [](const TargetRegisterClass *RC) {
8401 return RC == &X86::VK2WMRegClass || RC == &X86::VK4WMRegClass ||
8402 RC == &X86::VK8WMRegClass || RC == &X86::VK16WMRegClass ||
8403 RC == &X86::VK32WMRegClass || RC == &X86::VK64WMRegClass;
8404 };
8405
8406 if (Op1.isReg() && IsVKWMClass(getRegClass(MCID, OpNum: 1)))
8407 MaskReg = Op1.getReg();
8408 else if (Op2.isReg() && IsVKWMClass(getRegClass(MCID, OpNum: 2)))
8409 MaskReg = Op2.getReg();
8410
8411 if (MaskReg) {
8412 // Some instructions are invalid to fold into even with the same mask.
8413 // Folding is unsafe if an active destination element may read from a
8414 // source element that is masked off.
8415 if (isNonFoldableWithSameMask(RegOp: MI.getOpcode()))
8416 return nullptr;
8417 bool HasSameMask = false;
8418 for (unsigned I = 1, E = MI.getDesc().getNumOperands(); I < E; ++I) {
8419 const MachineOperand &Op = MI.getOperand(i: I);
8420 if (Op.isReg() && Op.getReg() == MaskReg) {
8421 HasSameMask = true;
8422 break;
8423 }
8424 }
8425 if (!HasSameMask)
8426 return nullptr;
8427 }
8428 }
8429
8430 // TODO: Support the case where LoadMI loads a wide register, but MI
8431 // only uses a subreg.
8432 for (auto Op : Ops) {
8433 if (MI.getOperand(i: Op).getSubReg())
8434 return nullptr;
8435 }
8436
8437 // If loading from a FrameIndex, fold directly from the FrameIndex.
8438 int FrameIndex;
8439 if (isLoadFromStackSlot(MI: LoadMI, FrameIndex)) {
8440 if (isNonFoldablePartialRegisterLoad(LoadMI, UserMI: MI, MF))
8441 return nullptr;
8442 return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex, CopyMI, LIS, VRM);
8443 }
8444
8445 // Check switch flag
8446 if (Subtarget.getCLOpts().disable_spill_fusing)
8447 return nullptr;
8448
8449 // Avoid partial and undef register update stalls unless optimizing for size.
8450 if (!MF.getFunction().hasOptSize() &&
8451 (hasPartialRegUpdate(Opcode: MI.getOpcode(), Subtarget, /*ForLoadFold*/ true) ||
8452 shouldPreventUndefRegUpdateMemFold(MF, MI)))
8453 return nullptr;
8454
8455 // Do not fold a NDD instruction and a memory instruction with relocation to
8456 // avoid emit APX relocation when the flag is disabled for backward
8457 // compatibility.
8458 uint64_t TSFlags = MI.getDesc().TSFlags;
8459 if (!Subtarget.getCLOpts().enable_apx_for_relocation &&
8460 isMemInstrWithGOTPCREL(MI: LoadMI) && X86II::hasNewDataDest(TSFlags))
8461 return nullptr;
8462
8463 // Determine the alignment of the load.
8464 Align Alignment;
8465 unsigned LoadOpc = LoadMI.getOpcode();
8466 if (LoadMI.hasOneMemOperand())
8467 Alignment = (*LoadMI.memoperands_begin())->getAlign();
8468 else
8469 switch (LoadOpc) {
8470 case X86::AVX512_512_SETALLONES:
8471 Alignment = Align(64);
8472 break;
8473 case X86::AVX2_SETALLONES:
8474 case X86::AVX1_SETALLONES:
8475 case X86::AVX512_256_SETALLONES:
8476 Alignment = Align(32);
8477 break;
8478 case X86::V_SET0:
8479 case X86::V_SETALLONES:
8480 case X86::AVX512_128_SET0:
8481 case X86::FsFLD0F128:
8482 case X86::AVX512_FsFLD0F128:
8483 case X86::AVX512_128_SETALLONES:
8484 Alignment = Align(16);
8485 break;
8486 case X86::MMX_SET0:
8487 case X86::FsFLD0SD:
8488 case X86::AVX512_FsFLD0SD:
8489 Alignment = Align(8);
8490 break;
8491 case X86::FsFLD0SS:
8492 case X86::AVX512_FsFLD0SS:
8493 Alignment = Align(4);
8494 break;
8495 case X86::FsFLD0SH:
8496 case X86::AVX512_FsFLD0SH:
8497 Alignment = Align(2);
8498 break;
8499 default:
8500 return nullptr;
8501 }
8502 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
8503 unsigned NewOpc = 0;
8504 switch (MI.getOpcode()) {
8505 default:
8506 return nullptr;
8507 case X86::TEST8rr:
8508 NewOpc = X86::CMP8ri;
8509 break;
8510 case X86::TEST16rr:
8511 NewOpc = X86::CMP16ri;
8512 break;
8513 case X86::TEST32rr:
8514 NewOpc = X86::CMP32ri;
8515 break;
8516 case X86::TEST64rr:
8517 NewOpc = X86::CMP64ri32;
8518 break;
8519 }
8520 // Change to CMPXXri r, 0 first.
8521 MI.setDesc(get(Opcode: NewOpc));
8522 MI.getOperand(i: 1).ChangeToImmediate(ImmVal: 0);
8523 } else if (Ops.size() != 1)
8524 return nullptr;
8525
8526 // Make sure the subregisters match.
8527 // Otherwise we risk changing the size of the load.
8528 if (LoadMI.getOperand(i: 0).getSubReg() != MI.getOperand(i: Ops[0]).getSubReg())
8529 return nullptr;
8530
8531 SmallVector<MachineOperand, X86::AddrNumOperands> MOs;
8532 switch (LoadOpc) {
8533 case X86::MMX_SET0:
8534 case X86::V_SET0:
8535 case X86::V_SETALLONES:
8536 case X86::AVX2_SETALLONES:
8537 case X86::AVX1_SETALLONES:
8538 case X86::AVX512_128_SET0:
8539 case X86::AVX512_128_SETALLONES:
8540 case X86::AVX512_256_SETALLONES:
8541 case X86::AVX512_512_SETALLONES:
8542 case X86::FsFLD0SH:
8543 case X86::AVX512_FsFLD0SH:
8544 case X86::FsFLD0SD:
8545 case X86::AVX512_FsFLD0SD:
8546 case X86::FsFLD0SS:
8547 case X86::AVX512_FsFLD0SS:
8548 case X86::FsFLD0F128:
8549 case X86::AVX512_FsFLD0F128: {
8550 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
8551 // Create a constant-pool entry and operands to load from it.
8552
8553 // Large code model can't fold loads this way.
8554 if (MF.getTarget().getCodeModel() == CodeModel::Large)
8555 return nullptr;
8556
8557 // x86-32 PIC requires a PIC base register for constant pools.
8558 unsigned PICBase = 0;
8559 // Since we're using Small or Kernel code model, we can always use
8560 // RIP-relative addressing for a smaller encoding.
8561 if (Subtarget.is64Bit()) {
8562 PICBase = X86::RIP;
8563 } else if (MF.getTarget().isPositionIndependent()) {
8564 // FIXME: PICBase = getGlobalBaseReg(&MF);
8565 // This doesn't work for several reasons.
8566 // 1. GlobalBaseReg may have been spilled.
8567 // 2. It may not be live at MI.
8568 return nullptr;
8569 }
8570
8571 // Create a constant-pool entry.
8572 MachineConstantPool &MCP = *MF.getConstantPool();
8573 Type *Ty;
8574 bool IsAllOnes = false;
8575 switch (LoadOpc) {
8576 case X86::FsFLD0SS:
8577 case X86::AVX512_FsFLD0SS:
8578 Ty = Type::getFloatTy(C&: MF.getFunction().getContext());
8579 break;
8580 case X86::FsFLD0SD:
8581 case X86::AVX512_FsFLD0SD:
8582 Ty = Type::getDoubleTy(C&: MF.getFunction().getContext());
8583 break;
8584 case X86::FsFLD0F128:
8585 case X86::AVX512_FsFLD0F128:
8586 Ty = Type::getFP128Ty(C&: MF.getFunction().getContext());
8587 break;
8588 case X86::FsFLD0SH:
8589 case X86::AVX512_FsFLD0SH:
8590 Ty = Type::getHalfTy(C&: MF.getFunction().getContext());
8591 break;
8592 case X86::AVX512_512_SETALLONES:
8593 IsAllOnes = true;
8594 Ty = FixedVectorType::get(ElementType: Type::getInt32Ty(C&: MF.getFunction().getContext()),
8595 NumElts: 16);
8596 break;
8597 case X86::AVX1_SETALLONES:
8598 case X86::AVX2_SETALLONES:
8599 case X86::AVX512_256_SETALLONES:
8600 IsAllOnes = true;
8601 Ty = FixedVectorType::get(ElementType: Type::getInt32Ty(C&: MF.getFunction().getContext()),
8602 NumElts: 8);
8603
8604 break;
8605 case X86::MMX_SET0:
8606 Ty = FixedVectorType::get(ElementType: Type::getInt32Ty(C&: MF.getFunction().getContext()),
8607 NumElts: 2);
8608 break;
8609 case X86::V_SETALLONES:
8610 case X86::AVX512_128_SETALLONES:
8611 IsAllOnes = true;
8612 [[fallthrough]];
8613 case X86::V_SET0:
8614 case X86::AVX512_128_SET0:
8615 Ty = FixedVectorType::get(ElementType: Type::getInt32Ty(C&: MF.getFunction().getContext()),
8616 NumElts: 4);
8617 break;
8618 }
8619
8620 const Constant *C =
8621 IsAllOnes ? Constant::getAllOnesValue(Ty) : Constant::getNullValue(Ty);
8622 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
8623
8624 // Create operands to load from the constant pool entry.
8625 MOs.push_back(Elt: MachineOperand::CreateReg(Reg: PICBase, isDef: false));
8626 MOs.push_back(Elt: MachineOperand::CreateImm(Val: 1));
8627 MOs.push_back(Elt: MachineOperand::CreateReg(Reg: 0, isDef: false));
8628 MOs.push_back(Elt: MachineOperand::CreateCPI(Idx: CPI, Offset: 0));
8629 MOs.push_back(Elt: MachineOperand::CreateReg(Reg: 0, isDef: false));
8630 break;
8631 }
8632 case X86::VPBROADCASTBZ128rm:
8633 case X86::VPBROADCASTBZ256rm:
8634 case X86::VPBROADCASTBZrm:
8635 case X86::VBROADCASTF32X2Z256rm:
8636 case X86::VBROADCASTF32X2Zrm:
8637 case X86::VBROADCASTI32X2Z128rm:
8638 case X86::VBROADCASTI32X2Z256rm:
8639 case X86::VBROADCASTI32X2Zrm:
8640 // No instructions currently fuse with 8bits or 32bits x 2.
8641 return nullptr;
8642
8643#define FOLD_BROADCAST(SIZE) \
8644 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands, \
8645 LoadMI.operands_begin() + NumOps); \
8646 return foldMemoryBroadcast(MF, MI, Ops[0], MOs, InsertPt, /*Size=*/SIZE, \
8647 /*AllowCommute=*/true);
8648 case X86::VPBROADCASTWZ128rm:
8649 case X86::VPBROADCASTWZ256rm:
8650 case X86::VPBROADCASTWZrm:
8651 FOLD_BROADCAST(16);
8652 case X86::VPBROADCASTDZ128rm:
8653 case X86::VPBROADCASTDZ256rm:
8654 case X86::VPBROADCASTDZrm:
8655 case X86::VBROADCASTSSZ128rm:
8656 case X86::VBROADCASTSSZ256rm:
8657 case X86::VBROADCASTSSZrm:
8658 FOLD_BROADCAST(32);
8659 case X86::VPBROADCASTQZ128rm:
8660 case X86::VPBROADCASTQZ256rm:
8661 case X86::VPBROADCASTQZrm:
8662 case X86::VBROADCASTSDZ256rm:
8663 case X86::VBROADCASTSDZrm:
8664 FOLD_BROADCAST(64);
8665 default: {
8666 if (isNonFoldablePartialRegisterLoad(LoadMI, UserMI: MI, MF))
8667 return nullptr;
8668
8669 // Folding a normal load. Just copy the load's address operands.
8670 MOs.append(in_start: LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
8671 in_end: LoadMI.operands_begin() + NumOps);
8672 break;
8673 }
8674 }
8675 return foldMemoryOperandImpl(MF, MI, OpNum: Ops[0], MOs, InsertPt,
8676 /*Size=*/0, Alignment, /*AllowCommute=*/true,
8677 CopyMI, VRM);
8678}
8679
8680MachineInstr *
8681X86InstrInfo::foldMemoryBroadcast(MachineFunction &MF, MachineInstr &MI,
8682 unsigned OpNum, ArrayRef<MachineOperand> MOs,
8683 MachineBasicBlock::iterator InsertPt,
8684 unsigned BitsSize, bool AllowCommute) const {
8685
8686 if (auto *I = lookupBroadcastFoldTable(RegOp: MI.getOpcode(), OpNum))
8687 return matchBroadcastSize(Entry: *I, BroadcastBits: BitsSize)
8688 ? fuseInst(MF, Opcode: I->DstOp, OpNo: OpNum, MOs, InsertPt, MI, TII: *this)
8689 : nullptr;
8690
8691 if (AllowCommute) {
8692 // If the instruction and target operand are commutable, commute the
8693 // instruction and try again.
8694 unsigned CommuteOpIdx2 = commuteOperandsForFold(MI, Idx1: OpNum);
8695 if (CommuteOpIdx2 == OpNum) {
8696 printFailMsgforFold(MI, Idx: OpNum);
8697 return nullptr;
8698 }
8699 MachineInstr *NewMI =
8700 foldMemoryBroadcast(MF, MI, OpNum: CommuteOpIdx2, MOs, InsertPt, BitsSize,
8701 /*AllowCommute=*/false);
8702 if (NewMI)
8703 return NewMI;
8704 // Folding failed again - undo the commute before returning.
8705 commuteInstruction(MI, NewMI: false, OpIdx1: OpNum, OpIdx2: CommuteOpIdx2);
8706 }
8707
8708 printFailMsgforFold(MI, Idx: OpNum);
8709 return nullptr;
8710}
8711
8712static SmallVector<MachineMemOperand *, 2>
8713extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
8714 SmallVector<MachineMemOperand *, 2> LoadMMOs;
8715
8716 for (MachineMemOperand *MMO : MMOs) {
8717 if (!MMO->isLoad())
8718 continue;
8719
8720 if (!MMO->isStore()) {
8721 // Reuse the MMO.
8722 LoadMMOs.push_back(Elt: MMO);
8723 } else {
8724 // Clone the MMO and unset the store flag.
8725 LoadMMOs.push_back(Elt: MF.getMachineMemOperand(
8726 MMO, Flags: MMO->getFlags() & ~MachineMemOperand::MOStore));
8727 }
8728 }
8729
8730 return LoadMMOs;
8731}
8732
8733static SmallVector<MachineMemOperand *, 2>
8734extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
8735 SmallVector<MachineMemOperand *, 2> StoreMMOs;
8736
8737 for (MachineMemOperand *MMO : MMOs) {
8738 if (!MMO->isStore())
8739 continue;
8740
8741 if (!MMO->isLoad()) {
8742 // Reuse the MMO.
8743 StoreMMOs.push_back(Elt: MMO);
8744 } else {
8745 // Clone the MMO and unset the load flag.
8746 StoreMMOs.push_back(Elt: MF.getMachineMemOperand(
8747 MMO, Flags: MMO->getFlags() & ~MachineMemOperand::MOLoad));
8748 }
8749 }
8750
8751 return StoreMMOs;
8752}
8753
8754static unsigned getBroadcastOpcode(const X86FoldTableEntry *I,
8755 const TargetRegisterClass *RC,
8756 const X86Subtarget &STI) {
8757 assert(STI.hasAVX512() && "Expected at least AVX512!");
8758 unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(RC: *RC);
8759 assert((SpillSize == 64 || STI.hasVLX()) &&
8760 "Can't broadcast less than 64 bytes without AVX512VL!");
8761
8762#define CASE_BCAST_TYPE_OPC(TYPE, OP16, OP32, OP64) \
8763 case TYPE: \
8764 switch (SpillSize) { \
8765 default: \
8766 llvm_unreachable("Unknown spill size"); \
8767 case 16: \
8768 return X86::OP16; \
8769 case 32: \
8770 return X86::OP32; \
8771 case 64: \
8772 return X86::OP64; \
8773 } \
8774 break;
8775
8776 switch (I->Flags & TB_BCAST_MASK) {
8777 default:
8778 llvm_unreachable("Unexpected broadcast type!");
8779 CASE_BCAST_TYPE_OPC(TB_BCAST_W, VPBROADCASTWZ128rm, VPBROADCASTWZ256rm,
8780 VPBROADCASTWZrm)
8781 CASE_BCAST_TYPE_OPC(TB_BCAST_D, VPBROADCASTDZ128rm, VPBROADCASTDZ256rm,
8782 VPBROADCASTDZrm)
8783 CASE_BCAST_TYPE_OPC(TB_BCAST_Q, VPBROADCASTQZ128rm, VPBROADCASTQZ256rm,
8784 VPBROADCASTQZrm)
8785 CASE_BCAST_TYPE_OPC(TB_BCAST_SH, VPBROADCASTWZ128rm, VPBROADCASTWZ256rm,
8786 VPBROADCASTWZrm)
8787 CASE_BCAST_TYPE_OPC(TB_BCAST_SS, VBROADCASTSSZ128rm, VBROADCASTSSZ256rm,
8788 VBROADCASTSSZrm)
8789 CASE_BCAST_TYPE_OPC(TB_BCAST_SD, VMOVDDUPZ128rm, VBROADCASTSDZ256rm,
8790 VBROADCASTSDZrm)
8791 }
8792}
8793
8794bool X86InstrInfo::unfoldMemoryOperand(
8795 MachineFunction &MF, MachineInstr &MI, Register Reg, bool UnfoldLoad,
8796 bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
8797 const X86FoldTableEntry *I = lookupUnfoldTable(MemOp: MI.getOpcode());
8798 if (I == nullptr)
8799 return false;
8800 unsigned Opc = I->DstOp;
8801 unsigned Index = I->Flags & TB_INDEX_MASK;
8802 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
8803 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
8804 if (UnfoldLoad && !FoldedLoad)
8805 return false;
8806 UnfoldLoad &= FoldedLoad;
8807 if (UnfoldStore && !FoldedStore)
8808 return false;
8809 UnfoldStore &= FoldedStore;
8810
8811 const MCInstrDesc &MCID = get(Opcode: Opc);
8812
8813 const TargetRegisterClass *RC = getRegClass(MCID, OpNum: Index);
8814 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
8815 // TODO: Check if 32-byte or greater accesses are slow too?
8816 if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
8817 Subtarget.isUnalignedMem16Slow())
8818 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
8819 // conservatively assume the address is unaligned. That's bad for
8820 // performance.
8821 return false;
8822 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
8823 SmallVector<MachineOperand, 2> BeforeOps;
8824 SmallVector<MachineOperand, 2> AfterOps;
8825 SmallVector<MachineOperand, 4> ImpOps;
8826 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
8827 MachineOperand &Op = MI.getOperand(i);
8828 if (i >= Index && i < Index + X86::AddrNumOperands)
8829 AddrOps.push_back(Elt: Op);
8830 else if (Op.isReg() && Op.isImplicit())
8831 ImpOps.push_back(Elt: Op);
8832 else if (i < Index)
8833 BeforeOps.push_back(Elt: Op);
8834 else if (i > Index)
8835 AfterOps.push_back(Elt: Op);
8836 }
8837
8838 // Emit the load or broadcast instruction.
8839 if (UnfoldLoad) {
8840 auto MMOs = extractLoadMMOs(MMOs: MI.memoperands(), MF);
8841
8842 unsigned Opc;
8843 if (I->Flags & TB_BCAST_MASK) {
8844 Opc = getBroadcastOpcode(I, RC, STI: Subtarget);
8845 } else {
8846 unsigned Alignment = std::max<uint32_t>(a: TRI.getSpillSize(RC: *RC), b: 16);
8847 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
8848 Opc = getLoadRegOpcode(DestReg: Reg, RC, IsStackAligned: isAligned, STI: Subtarget);
8849 }
8850
8851 DebugLoc DL;
8852 MachineInstrBuilder MIB = BuildMI(MF, MIMD: DL, MCID: get(Opcode: Opc), DestReg: Reg);
8853 for (const MachineOperand &AddrOp : AddrOps)
8854 MIB.add(MO: AddrOp);
8855 MIB.setMemRefs(MMOs);
8856 NewMIs.push_back(Elt: MIB);
8857
8858 if (UnfoldStore) {
8859 // Address operands cannot be marked isKill.
8860 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
8861 MachineOperand &MO = NewMIs[0]->getOperand(i);
8862 if (MO.isReg())
8863 MO.setIsKill(false);
8864 }
8865 }
8866 }
8867
8868 // Emit the data processing instruction.
8869 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, DL: MI.getDebugLoc(), NoImplicit: true);
8870 MachineInstrBuilder MIB(MF, DataMI);
8871
8872 if (FoldedStore)
8873 MIB.addReg(RegNo: Reg, Flags: RegState::Define);
8874 for (MachineOperand &BeforeOp : BeforeOps)
8875 MIB.add(MO: BeforeOp);
8876 if (FoldedLoad)
8877 MIB.addReg(RegNo: Reg);
8878 for (MachineOperand &AfterOp : AfterOps)
8879 MIB.add(MO: AfterOp);
8880 for (MachineOperand &ImpOp : ImpOps) {
8881 MIB.addReg(RegNo: ImpOp.getReg(), Flags: getDefRegState(B: ImpOp.isDef()) |
8882 RegState::Implicit |
8883 getKillRegState(B: ImpOp.isKill()) |
8884 getDeadRegState(B: ImpOp.isDead()) |
8885 getUndefRegState(B: ImpOp.isUndef()));
8886 }
8887 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
8888 switch (DataMI->getOpcode()) {
8889 default:
8890 break;
8891 case X86::CMP64ri32:
8892 case X86::CMP32ri:
8893 case X86::CMP16ri:
8894 case X86::CMP8ri: {
8895 MachineOperand &MO0 = DataMI->getOperand(i: 0);
8896 MachineOperand &MO1 = DataMI->getOperand(i: 1);
8897 if (MO1.isImm() && MO1.getImm() == 0) {
8898 unsigned NewOpc;
8899 switch (DataMI->getOpcode()) {
8900 default:
8901 llvm_unreachable("Unreachable!");
8902 case X86::CMP64ri32:
8903 NewOpc = X86::TEST64rr;
8904 break;
8905 case X86::CMP32ri:
8906 NewOpc = X86::TEST32rr;
8907 break;
8908 case X86::CMP16ri:
8909 NewOpc = X86::TEST16rr;
8910 break;
8911 case X86::CMP8ri:
8912 NewOpc = X86::TEST8rr;
8913 break;
8914 }
8915 DataMI->setDesc(get(Opcode: NewOpc));
8916 MO1.ChangeToRegister(Reg: MO0.getReg(), isDef: false);
8917 }
8918 }
8919 }
8920 NewMIs.push_back(Elt: DataMI);
8921
8922 // Emit the store instruction.
8923 if (UnfoldStore) {
8924 const TargetRegisterClass *DstRC = getRegClass(MCID, OpNum: 0);
8925 auto MMOs = extractStoreMMOs(MMOs: MI.memoperands(), MF);
8926 unsigned Alignment = std::max<uint32_t>(a: TRI.getSpillSize(RC: *DstRC), b: 16);
8927 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
8928 unsigned Opc = getStoreRegOpcode(SrcReg: Reg, RC: DstRC, IsStackAligned: isAligned, STI: Subtarget);
8929 DebugLoc DL;
8930 MachineInstrBuilder MIB = BuildMI(MF, MIMD: DL, MCID: get(Opcode: Opc));
8931 for (const MachineOperand &AddrOp : AddrOps)
8932 MIB.add(MO: AddrOp);
8933 MIB.addReg(RegNo: Reg, Flags: RegState::Kill);
8934 MIB.setMemRefs(MMOs);
8935 NewMIs.push_back(Elt: MIB);
8936 }
8937
8938 return true;
8939}
8940
8941bool X86InstrInfo::unfoldMemoryOperand(
8942 SelectionDAG &DAG, SDNode *N, SmallVectorImpl<SDNode *> &NewNodes) const {
8943 if (!N->isMachineOpcode())
8944 return false;
8945
8946 const X86FoldTableEntry *I = lookupUnfoldTable(MemOp: N->getMachineOpcode());
8947 if (I == nullptr)
8948 return false;
8949 unsigned Opc = I->DstOp;
8950 unsigned Index = I->Flags & TB_INDEX_MASK;
8951 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
8952 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
8953 const MCInstrDesc &MCID = get(Opcode: Opc);
8954 MachineFunction &MF = DAG.getMachineFunction();
8955 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
8956 const TargetRegisterClass *RC = getRegClass(MCID, OpNum: Index);
8957 unsigned NumDefs = MCID.NumDefs;
8958 std::vector<SDValue> AddrOps;
8959 std::vector<SDValue> BeforeOps;
8960 std::vector<SDValue> AfterOps;
8961 SDLoc dl(N);
8962 unsigned NumOps = N->getNumOperands();
8963 for (unsigned i = 0; i != NumOps - 1; ++i) {
8964 SDValue Op = N->getOperand(Num: i);
8965 if (i >= Index - NumDefs && i < Index - NumDefs + X86::AddrNumOperands)
8966 AddrOps.push_back(x: Op);
8967 else if (i < Index - NumDefs)
8968 BeforeOps.push_back(x: Op);
8969 else if (i > Index - NumDefs)
8970 AfterOps.push_back(x: Op);
8971 }
8972 SDValue Chain = N->getOperand(Num: NumOps - 1);
8973 AddrOps.push_back(x: Chain);
8974
8975 // Emit the load instruction.
8976 SDNode *Load = nullptr;
8977 if (FoldedLoad) {
8978 EVT VT = *TRI.legalclasstypes_begin(RC: *RC);
8979 auto MMOs = extractLoadMMOs(MMOs: cast<MachineSDNode>(Val: N)->memoperands(), MF);
8980 if (MMOs.empty() && RC == &X86::VR128RegClass &&
8981 Subtarget.isUnalignedMem16Slow())
8982 // Do not introduce a slow unaligned load.
8983 return false;
8984 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
8985 // memory access is slow above.
8986
8987 unsigned Opc;
8988 if (I->Flags & TB_BCAST_MASK) {
8989 Opc = getBroadcastOpcode(I, RC, STI: Subtarget);
8990 } else {
8991 unsigned Alignment = std::max<uint32_t>(a: TRI.getSpillSize(RC: *RC), b: 16);
8992 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
8993 Opc = getLoadRegOpcode(DestReg: 0, RC, IsStackAligned: isAligned, STI: Subtarget);
8994 }
8995
8996 Load = DAG.getMachineNode(Opcode: Opc, dl, VT1: VT, VT2: MVT::Other, Ops: AddrOps);
8997 NewNodes.push_back(Elt: Load);
8998
8999 // Preserve memory reference information.
9000 DAG.setNodeMemRefs(N: cast<MachineSDNode>(Val: Load), NewMemRefs: MMOs);
9001 }
9002
9003 // Emit the data processing instruction.
9004 std::vector<EVT> VTs;
9005 const TargetRegisterClass *DstRC = nullptr;
9006 if (MCID.getNumDefs() > 0) {
9007 DstRC = getRegClass(MCID, OpNum: 0);
9008 VTs.push_back(x: *TRI.legalclasstypes_begin(RC: *DstRC));
9009 }
9010 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
9011 EVT VT = N->getValueType(ResNo: i);
9012 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
9013 VTs.push_back(x: VT);
9014 }
9015 if (Load)
9016 BeforeOps.push_back(x: SDValue(Load, 0));
9017 llvm::append_range(C&: BeforeOps, R&: AfterOps);
9018 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
9019 switch (Opc) {
9020 default:
9021 break;
9022 case X86::CMP64ri32:
9023 case X86::CMP32ri:
9024 case X86::CMP16ri:
9025 case X86::CMP8ri:
9026 if (isNullConstant(V: BeforeOps[1])) {
9027 switch (Opc) {
9028 default:
9029 llvm_unreachable("Unreachable!");
9030 case X86::CMP64ri32:
9031 Opc = X86::TEST64rr;
9032 break;
9033 case X86::CMP32ri:
9034 Opc = X86::TEST32rr;
9035 break;
9036 case X86::CMP16ri:
9037 Opc = X86::TEST16rr;
9038 break;
9039 case X86::CMP8ri:
9040 Opc = X86::TEST8rr;
9041 break;
9042 }
9043 BeforeOps[1] = BeforeOps[0];
9044 }
9045 }
9046 SDNode *NewNode = DAG.getMachineNode(Opcode: Opc, dl, ResultTys: VTs, Ops: BeforeOps);
9047 NewNodes.push_back(Elt: NewNode);
9048
9049 // Emit the store instruction.
9050 if (FoldedStore) {
9051 AddrOps.pop_back();
9052 AddrOps.push_back(x: SDValue(NewNode, 0));
9053 AddrOps.push_back(x: Chain);
9054 auto MMOs = extractStoreMMOs(MMOs: cast<MachineSDNode>(Val: N)->memoperands(), MF);
9055 if (MMOs.empty() && RC == &X86::VR128RegClass &&
9056 Subtarget.isUnalignedMem16Slow())
9057 // Do not introduce a slow unaligned store.
9058 return false;
9059 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
9060 // memory access is slow above.
9061 unsigned Alignment = std::max<uint32_t>(a: TRI.getSpillSize(RC: *RC), b: 16);
9062 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
9063 SDNode *Store =
9064 DAG.getMachineNode(Opcode: getStoreRegOpcode(SrcReg: 0, RC: DstRC, IsStackAligned: isAligned, STI: Subtarget),
9065 dl, VT: MVT::Other, Ops: AddrOps);
9066 NewNodes.push_back(Elt: Store);
9067
9068 // Preserve memory reference information.
9069 DAG.setNodeMemRefs(N: cast<MachineSDNode>(Val: Store), NewMemRefs: MMOs);
9070 }
9071
9072 return true;
9073}
9074
9075unsigned
9076X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad,
9077 bool UnfoldStore,
9078 unsigned *LoadRegIndex) const {
9079 const X86FoldTableEntry *I = lookupUnfoldTable(MemOp: Opc);
9080 if (I == nullptr)
9081 return 0;
9082 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
9083 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
9084 if (UnfoldLoad && !FoldedLoad)
9085 return 0;
9086 if (UnfoldStore && !FoldedStore)
9087 return 0;
9088 if (LoadRegIndex)
9089 *LoadRegIndex = I->Flags & TB_INDEX_MASK;
9090 return I->DstOp;
9091}
9092
9093bool X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
9094 int64_t &Offset1,
9095 int64_t &Offset2) const {
9096 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
9097 return false;
9098
9099 auto IsLoadOpcode = [&](unsigned Opcode) {
9100 switch (Opcode) {
9101 default:
9102 return false;
9103 case X86::MOV8rm:
9104 case X86::MOV16rm:
9105 case X86::MOV32rm:
9106 case X86::MOV64rm:
9107 case X86::LD_Fp32m:
9108 case X86::LD_Fp64m:
9109 case X86::LD_Fp80m:
9110 case X86::MOVSSrm:
9111 case X86::MOVSSrm_alt:
9112 case X86::MOVSDrm:
9113 case X86::MOVSDrm_alt:
9114 case X86::MMX_MOVD64rm:
9115 case X86::MMX_MOVQ64rm:
9116 case X86::MOVAPSrm:
9117 case X86::MOVUPSrm:
9118 case X86::MOVAPDrm:
9119 case X86::MOVUPDrm:
9120 case X86::MOVDQArm:
9121 case X86::MOVDQUrm:
9122 // AVX load instructions
9123 case X86::VMOVSSrm:
9124 case X86::VMOVSSrm_alt:
9125 case X86::VMOVSDrm:
9126 case X86::VMOVSDrm_alt:
9127 case X86::VMOVAPSrm:
9128 case X86::VMOVUPSrm:
9129 case X86::VMOVAPDrm:
9130 case X86::VMOVUPDrm:
9131 case X86::VMOVDQArm:
9132 case X86::VMOVDQUrm:
9133 case X86::VMOVAPSYrm:
9134 case X86::VMOVUPSYrm:
9135 case X86::VMOVAPDYrm:
9136 case X86::VMOVUPDYrm:
9137 case X86::VMOVDQAYrm:
9138 case X86::VMOVDQUYrm:
9139 // AVX512 load instructions
9140 case X86::VMOVSSZrm:
9141 case X86::VMOVSSZrm_alt:
9142 case X86::VMOVSDZrm:
9143 case X86::VMOVSDZrm_alt:
9144 case X86::VMOVAPSZ128rm:
9145 case X86::VMOVUPSZ128rm:
9146 case X86::VMOVAPSZ128rm_NOVLX:
9147 case X86::VMOVUPSZ128rm_NOVLX:
9148 case X86::VMOVAPDZ128rm:
9149 case X86::VMOVUPDZ128rm:
9150 case X86::VMOVDQU8Z128rm:
9151 case X86::VMOVDQU16Z128rm:
9152 case X86::VMOVDQA32Z128rm:
9153 case X86::VMOVDQU32Z128rm:
9154 case X86::VMOVDQA64Z128rm:
9155 case X86::VMOVDQU64Z128rm:
9156 case X86::VMOVAPSZ256rm:
9157 case X86::VMOVUPSZ256rm:
9158 case X86::VMOVAPSZ256rm_NOVLX:
9159 case X86::VMOVUPSZ256rm_NOVLX:
9160 case X86::VMOVAPDZ256rm:
9161 case X86::VMOVUPDZ256rm:
9162 case X86::VMOVDQU8Z256rm:
9163 case X86::VMOVDQU16Z256rm:
9164 case X86::VMOVDQA32Z256rm:
9165 case X86::VMOVDQU32Z256rm:
9166 case X86::VMOVDQA64Z256rm:
9167 case X86::VMOVDQU64Z256rm:
9168 case X86::VMOVAPSZrm:
9169 case X86::VMOVUPSZrm:
9170 case X86::VMOVAPDZrm:
9171 case X86::VMOVUPDZrm:
9172 case X86::VMOVDQU8Zrm:
9173 case X86::VMOVDQU16Zrm:
9174 case X86::VMOVDQA32Zrm:
9175 case X86::VMOVDQU32Zrm:
9176 case X86::VMOVDQA64Zrm:
9177 case X86::VMOVDQU64Zrm:
9178 case X86::KMOVBkm:
9179 case X86::KMOVBkm_EVEX:
9180 case X86::KMOVWkm:
9181 case X86::KMOVWkm_EVEX:
9182 case X86::KMOVDkm:
9183 case X86::KMOVDkm_EVEX:
9184 case X86::KMOVQkm:
9185 case X86::KMOVQkm_EVEX:
9186 return true;
9187 }
9188 };
9189
9190 if (!IsLoadOpcode(Load1->getMachineOpcode()) ||
9191 !IsLoadOpcode(Load2->getMachineOpcode()))
9192 return false;
9193
9194 // Lambda to check if both the loads have the same value for an operand index.
9195 auto HasSameOp = [&](int I) {
9196 return Load1->getOperand(Num: I) == Load2->getOperand(Num: I);
9197 };
9198
9199 // All operands except the displacement should match.
9200 if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
9201 !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
9202 return false;
9203
9204 // Chain Operand must be the same.
9205 if (!HasSameOp(5))
9206 return false;
9207
9208 // Now let's examine if the displacements are constants.
9209 auto Disp1 = dyn_cast<ConstantSDNode>(Val: Load1->getOperand(Num: X86::AddrDisp));
9210 auto Disp2 = dyn_cast<ConstantSDNode>(Val: Load2->getOperand(Num: X86::AddrDisp));
9211 if (!Disp1 || !Disp2)
9212 return false;
9213
9214 Offset1 = Disp1->getSExtValue();
9215 Offset2 = Disp2->getSExtValue();
9216 return true;
9217}
9218
9219bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
9220 int64_t Offset1, int64_t Offset2,
9221 unsigned NumLoads) const {
9222 assert(Offset2 > Offset1);
9223 if ((Offset2 - Offset1) / 8 > 64)
9224 return false;
9225
9226 unsigned Opc1 = Load1->getMachineOpcode();
9227 unsigned Opc2 = Load2->getMachineOpcode();
9228 if (Opc1 != Opc2)
9229 return false; // FIXME: overly conservative?
9230
9231 switch (Opc1) {
9232 default:
9233 break;
9234 case X86::LD_Fp32m:
9235 case X86::LD_Fp64m:
9236 case X86::LD_Fp80m:
9237 case X86::MMX_MOVD64rm:
9238 case X86::MMX_MOVQ64rm:
9239 return false;
9240 }
9241
9242 EVT VT = Load1->getValueType(ResNo: 0);
9243 switch (VT.getSimpleVT().SimpleTy) {
9244 default:
9245 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
9246 // have 16 of them to play with.
9247 if (Subtarget.is64Bit()) {
9248 if (NumLoads >= 3)
9249 return false;
9250 } else if (NumLoads) {
9251 return false;
9252 }
9253 break;
9254 case MVT::i8:
9255 case MVT::i16:
9256 case MVT::i32:
9257 case MVT::i64:
9258 case MVT::f32:
9259 case MVT::f64:
9260 if (NumLoads)
9261 return false;
9262 break;
9263 }
9264
9265 return true;
9266}
9267
9268bool X86InstrInfo::isSchedulingBoundary(const MachineInstr &MI,
9269 const MachineBasicBlock *MBB,
9270 const MachineFunction &MF) const {
9271
9272 // ENDBR instructions should not be scheduled around.
9273 unsigned Opcode = MI.getOpcode();
9274 if (Opcode == X86::ENDBR64 || Opcode == X86::ENDBR32 ||
9275 Opcode == X86::PLDTILECFGV)
9276 return true;
9277
9278 // Frame setup and destroy can't be scheduled around.
9279 if (MI.getFlag(Flag: MachineInstr::FrameSetup) ||
9280 MI.getFlag(Flag: MachineInstr::FrameDestroy))
9281 return true;
9282
9283 return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF);
9284}
9285
9286bool X86InstrInfo::reverseBranchCondition(
9287 SmallVectorImpl<MachineOperand> &Cond) const {
9288 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
9289 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
9290 Cond[0].setImm(GetOppositeBranchCondition(CC));
9291 return false;
9292}
9293
9294bool X86InstrInfo::isSafeToMoveRegClassDefs(
9295 const TargetRegisterClass *RC) const {
9296 // FIXME: Return false for x87 stack register classes for now. We can't
9297 // allow any loads of these registers before FpGet_ST0_80.
9298 return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
9299 RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
9300 RC == &X86::RFP80RegClass);
9301}
9302
9303/// Return a virtual register initialized with the
9304/// the global base register value. Output instructions required to
9305/// initialize the register in the function entry block, if necessary.
9306///
9307/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
9308///
9309Register X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
9310 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
9311 Register GlobalBaseReg = X86FI->getGlobalBaseReg();
9312 if (GlobalBaseReg)
9313 return GlobalBaseReg;
9314
9315 // Create the register. The code to initialize it is inserted
9316 // later, by the CGBR pass (below).
9317 MachineRegisterInfo &RegInfo = MF->getRegInfo();
9318 GlobalBaseReg = RegInfo.createVirtualRegister(
9319 RegClass: Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
9320 X86FI->setGlobalBaseReg(GlobalBaseReg);
9321 return GlobalBaseReg;
9322}
9323
9324// FIXME: Some shuffle and unpack instructions have equivalents in different
9325// domains, but they require a bit more work than just switching opcodes.
9326
9327static const uint16_t *lookup(unsigned opcode, unsigned domain,
9328 ArrayRef<uint16_t[3]> Table) {
9329 for (const uint16_t(&Row)[3] : Table)
9330 if (Row[domain - 1] == opcode)
9331 return Row;
9332 return nullptr;
9333}
9334
9335static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
9336 ArrayRef<uint16_t[4]> Table) {
9337 // If this is the integer domain make sure to check both integer columns.
9338 for (const uint16_t(&Row)[4] : Table)
9339 if (Row[domain - 1] == opcode || (domain == 3 && Row[3] == opcode))
9340 return Row;
9341 return nullptr;
9342}
9343
9344// Helper to attempt to widen/narrow blend masks.
9345static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
9346 unsigned NewWidth, unsigned *pNewMask = nullptr) {
9347 assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
9348 "Illegal blend mask scale");
9349 unsigned NewMask = 0;
9350
9351 if ((OldWidth % NewWidth) == 0) {
9352 unsigned Scale = OldWidth / NewWidth;
9353 unsigned SubMask = (1u << Scale) - 1;
9354 for (unsigned i = 0; i != NewWidth; ++i) {
9355 unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
9356 if (Sub == SubMask)
9357 NewMask |= (1u << i);
9358 else if (Sub != 0x0)
9359 return false;
9360 }
9361 } else {
9362 unsigned Scale = NewWidth / OldWidth;
9363 unsigned SubMask = (1u << Scale) - 1;
9364 for (unsigned i = 0; i != OldWidth; ++i) {
9365 if (OldMask & (1 << i)) {
9366 NewMask |= (SubMask << (i * Scale));
9367 }
9368 }
9369 }
9370
9371 if (pNewMask)
9372 *pNewMask = NewMask;
9373 return true;
9374}
9375
9376uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
9377 unsigned Opcode = MI.getOpcode();
9378 unsigned NumOperands = MI.getDesc().getNumOperands();
9379
9380 auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
9381 uint16_t validDomains = 0;
9382 if (MI.getOperand(i: NumOperands - 1).isImm()) {
9383 unsigned Imm = MI.getOperand(i: NumOperands - 1).getImm();
9384 if (AdjustBlendMask(OldMask: Imm, OldWidth: ImmWidth, NewWidth: Is256 ? 8 : 4))
9385 validDomains |= 0x2; // PackedSingle
9386 if (AdjustBlendMask(OldMask: Imm, OldWidth: ImmWidth, NewWidth: Is256 ? 4 : 2))
9387 validDomains |= 0x4; // PackedDouble
9388 if (!Is256 || Subtarget.hasAVX2())
9389 validDomains |= 0x8; // PackedInt
9390 }
9391 return validDomains;
9392 };
9393
9394 switch (Opcode) {
9395 case X86::BLENDPDrmi:
9396 case X86::BLENDPDrri:
9397 case X86::VBLENDPDrmi:
9398 case X86::VBLENDPDrri:
9399 return GetBlendDomains(2, false);
9400 case X86::VBLENDPDYrmi:
9401 case X86::VBLENDPDYrri:
9402 return GetBlendDomains(4, true);
9403 case X86::BLENDPSrmi:
9404 case X86::BLENDPSrri:
9405 case X86::VBLENDPSrmi:
9406 case X86::VBLENDPSrri:
9407 case X86::VPBLENDDrmi:
9408 case X86::VPBLENDDrri:
9409 return GetBlendDomains(4, false);
9410 case X86::VBLENDPSYrmi:
9411 case X86::VBLENDPSYrri:
9412 case X86::VPBLENDDYrmi:
9413 case X86::VPBLENDDYrri:
9414 return GetBlendDomains(8, true);
9415 case X86::PBLENDWrmi:
9416 case X86::PBLENDWrri:
9417 case X86::VPBLENDWrmi:
9418 case X86::VPBLENDWrri:
9419 // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
9420 case X86::VPBLENDWYrmi:
9421 case X86::VPBLENDWYrri:
9422 return GetBlendDomains(8, false);
9423 case X86::VPANDDZ128rr:
9424 case X86::VPANDDZ128rm:
9425 case X86::VPANDDZ256rr:
9426 case X86::VPANDDZ256rm:
9427 case X86::VPANDQZ128rr:
9428 case X86::VPANDQZ128rm:
9429 case X86::VPANDQZ256rr:
9430 case X86::VPANDQZ256rm:
9431 case X86::VPANDNDZ128rr:
9432 case X86::VPANDNDZ128rm:
9433 case X86::VPANDNDZ256rr:
9434 case X86::VPANDNDZ256rm:
9435 case X86::VPANDNQZ128rr:
9436 case X86::VPANDNQZ128rm:
9437 case X86::VPANDNQZ256rr:
9438 case X86::VPANDNQZ256rm:
9439 case X86::VPORDZ128rr:
9440 case X86::VPORDZ128rm:
9441 case X86::VPORDZ256rr:
9442 case X86::VPORDZ256rm:
9443 case X86::VPORQZ128rr:
9444 case X86::VPORQZ128rm:
9445 case X86::VPORQZ256rr:
9446 case X86::VPORQZ256rm:
9447 case X86::VPXORDZ128rr:
9448 case X86::VPXORDZ128rm:
9449 case X86::VPXORDZ256rr:
9450 case X86::VPXORDZ256rm:
9451 case X86::VPXORQZ128rr:
9452 case X86::VPXORQZ128rm:
9453 case X86::VPXORQZ256rr:
9454 case X86::VPXORQZ256rm:
9455 // If we don't have DQI see if we can still switch from an EVEX integer
9456 // instruction to a VEX floating point instruction.
9457 if (Subtarget.hasDQI())
9458 return 0;
9459
9460 if (RI.getEncodingValue(Reg: MI.getOperand(i: 0).getReg()) >= 16)
9461 return 0;
9462 if (RI.getEncodingValue(Reg: MI.getOperand(i: 1).getReg()) >= 16)
9463 return 0;
9464 // Register forms will have 3 operands. Memory form will have more.
9465 if (NumOperands == 3 &&
9466 RI.getEncodingValue(Reg: MI.getOperand(i: 2).getReg()) >= 16)
9467 return 0;
9468
9469 // All domains are valid.
9470 return 0xe;
9471 case X86::MOVHLPSrr:
9472 // We can swap domains when both inputs are the same register.
9473 // FIXME: This doesn't catch all the cases we would like. If the input
9474 // register isn't KILLed by the instruction, the two address instruction
9475 // pass puts a COPY on one input. The other input uses the original
9476 // register. This prevents the same physical register from being used by
9477 // both inputs.
9478 if (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 2).getReg() &&
9479 MI.getOperand(i: 0).getSubReg() == 0 &&
9480 MI.getOperand(i: 1).getSubReg() == 0 && MI.getOperand(i: 2).getSubReg() == 0)
9481 return 0x6;
9482 return 0;
9483 case X86::SHUFPDrri:
9484 return 0x6;
9485 }
9486 return 0;
9487}
9488
9489#include "X86ReplaceableInstrs.def"
9490
9491bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
9492 unsigned Domain) const {
9493 assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
9494 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
9495 assert(dom && "Not an SSE instruction");
9496
9497 unsigned Opcode = MI.getOpcode();
9498 unsigned NumOperands = MI.getDesc().getNumOperands();
9499
9500 auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
9501 if (MI.getOperand(i: NumOperands - 1).isImm()) {
9502 unsigned Imm = MI.getOperand(i: NumOperands - 1).getImm() & 255;
9503 Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
9504 unsigned NewImm = Imm;
9505
9506 const uint16_t *table = lookup(opcode: Opcode, domain: dom, Table: ReplaceableBlendInstrs);
9507 if (!table)
9508 table = lookup(opcode: Opcode, domain: dom, Table: ReplaceableBlendAVX2Instrs);
9509
9510 if (Domain == 1) { // PackedSingle
9511 AdjustBlendMask(OldMask: Imm, OldWidth: ImmWidth, NewWidth: Is256 ? 8 : 4, pNewMask: &NewImm);
9512 } else if (Domain == 2) { // PackedDouble
9513 AdjustBlendMask(OldMask: Imm, OldWidth: ImmWidth, NewWidth: Is256 ? 4 : 2, pNewMask: &NewImm);
9514 } else if (Domain == 3) { // PackedInt
9515 if (Subtarget.hasAVX2()) {
9516 // If we are already VPBLENDW use that, else use VPBLENDD.
9517 if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
9518 table = lookup(opcode: Opcode, domain: dom, Table: ReplaceableBlendAVX2Instrs);
9519 AdjustBlendMask(OldMask: Imm, OldWidth: ImmWidth, NewWidth: Is256 ? 8 : 4, pNewMask: &NewImm);
9520 }
9521 } else {
9522 assert(!Is256 && "128-bit vector expected");
9523 AdjustBlendMask(OldMask: Imm, OldWidth: ImmWidth, NewWidth: 8, pNewMask: &NewImm);
9524 }
9525 }
9526
9527 assert(table && table[Domain - 1] && "Unknown domain op");
9528 MI.setDesc(get(Opcode: table[Domain - 1]));
9529 MI.getOperand(i: NumOperands - 1).setImm(NewImm & 255);
9530 }
9531 return true;
9532 };
9533
9534 switch (Opcode) {
9535 case X86::BLENDPDrmi:
9536 case X86::BLENDPDrri:
9537 case X86::VBLENDPDrmi:
9538 case X86::VBLENDPDrri:
9539 return SetBlendDomain(2, false);
9540 case X86::VBLENDPDYrmi:
9541 case X86::VBLENDPDYrri:
9542 return SetBlendDomain(4, true);
9543 case X86::BLENDPSrmi:
9544 case X86::BLENDPSrri:
9545 case X86::VBLENDPSrmi:
9546 case X86::VBLENDPSrri:
9547 case X86::VPBLENDDrmi:
9548 case X86::VPBLENDDrri:
9549 return SetBlendDomain(4, false);
9550 case X86::VBLENDPSYrmi:
9551 case X86::VBLENDPSYrri:
9552 case X86::VPBLENDDYrmi:
9553 case X86::VPBLENDDYrri:
9554 return SetBlendDomain(8, true);
9555 case X86::PBLENDWrmi:
9556 case X86::PBLENDWrri:
9557 case X86::VPBLENDWrmi:
9558 case X86::VPBLENDWrri:
9559 return SetBlendDomain(8, false);
9560 case X86::VPBLENDWYrmi:
9561 case X86::VPBLENDWYrri:
9562 return SetBlendDomain(16, true);
9563 case X86::VPANDDZ128rr:
9564 case X86::VPANDDZ128rm:
9565 case X86::VPANDDZ256rr:
9566 case X86::VPANDDZ256rm:
9567 case X86::VPANDQZ128rr:
9568 case X86::VPANDQZ128rm:
9569 case X86::VPANDQZ256rr:
9570 case X86::VPANDQZ256rm:
9571 case X86::VPANDNDZ128rr:
9572 case X86::VPANDNDZ128rm:
9573 case X86::VPANDNDZ256rr:
9574 case X86::VPANDNDZ256rm:
9575 case X86::VPANDNQZ128rr:
9576 case X86::VPANDNQZ128rm:
9577 case X86::VPANDNQZ256rr:
9578 case X86::VPANDNQZ256rm:
9579 case X86::VPORDZ128rr:
9580 case X86::VPORDZ128rm:
9581 case X86::VPORDZ256rr:
9582 case X86::VPORDZ256rm:
9583 case X86::VPORQZ128rr:
9584 case X86::VPORQZ128rm:
9585 case X86::VPORQZ256rr:
9586 case X86::VPORQZ256rm:
9587 case X86::VPXORDZ128rr:
9588 case X86::VPXORDZ128rm:
9589 case X86::VPXORDZ256rr:
9590 case X86::VPXORDZ256rm:
9591 case X86::VPXORQZ128rr:
9592 case X86::VPXORQZ128rm:
9593 case X86::VPXORQZ256rr:
9594 case X86::VPXORQZ256rm: {
9595 // Without DQI, convert EVEX instructions to VEX instructions.
9596 if (Subtarget.hasDQI())
9597 return false;
9598
9599 const uint16_t *table =
9600 lookupAVX512(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableCustomAVX512LogicInstrs);
9601 assert(table && "Instruction not found in table?");
9602 // Don't change integer Q instructions to D instructions and
9603 // use D intructions if we started with a PS instruction.
9604 if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
9605 Domain = 4;
9606 MI.setDesc(get(Opcode: table[Domain - 1]));
9607 return true;
9608 }
9609 case X86::UNPCKHPDrr:
9610 case X86::MOVHLPSrr:
9611 // We just need to commute the instruction which will switch the domains.
9612 if (Domain != dom && Domain != 3 &&
9613 MI.getOperand(i: 1).getReg() == MI.getOperand(i: 2).getReg() &&
9614 MI.getOperand(i: 0).getSubReg() == 0 &&
9615 MI.getOperand(i: 1).getSubReg() == 0 &&
9616 MI.getOperand(i: 2).getSubReg() == 0) {
9617 commuteInstruction(MI, NewMI: false);
9618 return true;
9619 }
9620 // We must always return true for MOVHLPSrr.
9621 if (Opcode == X86::MOVHLPSrr)
9622 return true;
9623 break;
9624 case X86::SHUFPDrri: {
9625 if (Domain == 1) {
9626 unsigned Imm = MI.getOperand(i: 3).getImm();
9627 unsigned NewImm = 0x44;
9628 if (Imm & 1)
9629 NewImm |= 0x0a;
9630 if (Imm & 2)
9631 NewImm |= 0xa0;
9632 MI.getOperand(i: 3).setImm(NewImm);
9633 MI.setDesc(get(Opcode: X86::SHUFPSrri));
9634 }
9635 return true;
9636 }
9637 }
9638 return false;
9639}
9640
9641std::pair<uint16_t, uint16_t>
9642X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
9643 uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
9644 unsigned opcode = MI.getOpcode();
9645 uint16_t validDomains = 0;
9646 if (domain) {
9647 // Attempt to match for custom instructions.
9648 validDomains = getExecutionDomainCustom(MI);
9649 if (validDomains)
9650 return std::make_pair(x&: domain, y&: validDomains);
9651
9652 if (lookup(opcode, domain, Table: ReplaceableInstrs)) {
9653 validDomains = 0xe;
9654 } else if (lookup(opcode, domain, Table: ReplaceableInstrsAVX2)) {
9655 validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
9656 } else if (lookup(opcode, domain, Table: ReplaceableInstrsFP)) {
9657 validDomains = 0x6;
9658 } else if (lookup(opcode, domain, Table: ReplaceableInstrsAVX2InsertExtract)) {
9659 // Insert/extract instructions should only effect domain if AVX2
9660 // is enabled.
9661 if (!Subtarget.hasAVX2())
9662 return std::make_pair(x: 0, y: 0);
9663 validDomains = 0xe;
9664 } else if (lookupAVX512(opcode, domain, Table: ReplaceableInstrsAVX512)) {
9665 validDomains = 0xe;
9666 } else if (Subtarget.hasDQI() &&
9667 lookupAVX512(opcode, domain, Table: ReplaceableInstrsAVX512DQ)) {
9668 validDomains = 0xe;
9669 } else if (Subtarget.hasDQI()) {
9670 if (const uint16_t *table =
9671 lookupAVX512(opcode, domain, Table: ReplaceableInstrsAVX512DQMasked)) {
9672 if (domain == 1 || (domain == 3 && table[3] == opcode))
9673 validDomains = 0xa;
9674 else
9675 validDomains = 0xc;
9676 }
9677 }
9678 }
9679 return std::make_pair(x&: domain, y&: validDomains);
9680}
9681
9682void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
9683 assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
9684 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
9685 assert(dom && "Not an SSE instruction");
9686
9687 // Attempt to match for custom instructions.
9688 if (setExecutionDomainCustom(MI, Domain))
9689 return;
9690
9691 const uint16_t *table = lookup(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrs);
9692 if (!table) { // try the other table
9693 assert((Subtarget.hasAVX2() || Domain < 3) &&
9694 "256-bit vector operations only available in AVX2");
9695 table = lookup(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrsAVX2);
9696 }
9697 if (!table) { // try the FP table
9698 table = lookup(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrsFP);
9699 assert((!table || Domain < 3) &&
9700 "Can only select PackedSingle or PackedDouble");
9701 }
9702 if (!table) { // try the other table
9703 assert(Subtarget.hasAVX2() &&
9704 "256-bit insert/extract only available in AVX2");
9705 table = lookup(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrsAVX2InsertExtract);
9706 }
9707 if (!table) { // try the AVX512 table
9708 assert(Subtarget.hasAVX512() && "Requires AVX-512");
9709 table = lookupAVX512(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrsAVX512);
9710 // Don't change integer Q instructions to D instructions.
9711 if (table && Domain == 3 && table[3] == MI.getOpcode())
9712 Domain = 4;
9713 }
9714 if (!table) { // try the AVX512DQ table
9715 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
9716 table = lookupAVX512(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrsAVX512DQ);
9717 // Don't change integer Q instructions to D instructions and
9718 // use D instructions if we started with a PS instruction.
9719 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
9720 Domain = 4;
9721 }
9722 if (!table) { // try the AVX512DQMasked table
9723 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
9724 table = lookupAVX512(opcode: MI.getOpcode(), domain: dom, Table: ReplaceableInstrsAVX512DQMasked);
9725 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
9726 Domain = 4;
9727 }
9728 assert(table && "Cannot change domain");
9729 MI.setDesc(get(Opcode: table[Domain - 1]));
9730}
9731
9732void X86InstrInfo::insertNoop(MachineBasicBlock &MBB,
9733 MachineBasicBlock::iterator MI) const {
9734 DebugLoc DL;
9735 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: get(Opcode: X86::NOOP));
9736}
9737
9738/// Return the noop instruction to use for a noop.
9739MCInst X86InstrInfo::getNop() const {
9740 MCInst Nop;
9741 Nop.setOpcode(X86::NOOP);
9742 return Nop;
9743}
9744
9745bool X86InstrInfo::isHighLatencyDef(int opc) const {
9746 switch (opc) {
9747 default:
9748 return false;
9749 case X86::DIVPDrm:
9750 case X86::DIVPDrr:
9751 case X86::DIVPSrm:
9752 case X86::DIVPSrr:
9753 case X86::DIVSDrm:
9754 case X86::DIVSDrm_Int:
9755 case X86::DIVSDrr:
9756 case X86::DIVSDrr_Int:
9757 case X86::DIVSSrm:
9758 case X86::DIVSSrm_Int:
9759 case X86::DIVSSrr:
9760 case X86::DIVSSrr_Int:
9761 case X86::SQRTPDm:
9762 case X86::SQRTPDr:
9763 case X86::SQRTPSm:
9764 case X86::SQRTPSr:
9765 case X86::SQRTSDm:
9766 case X86::SQRTSDm_Int:
9767 case X86::SQRTSDr:
9768 case X86::SQRTSDr_Int:
9769 case X86::SQRTSSm:
9770 case X86::SQRTSSm_Int:
9771 case X86::SQRTSSr:
9772 case X86::SQRTSSr_Int:
9773 // AVX instructions with high latency
9774 case X86::VDIVPDrm:
9775 case X86::VDIVPDrr:
9776 case X86::VDIVPDYrm:
9777 case X86::VDIVPDYrr:
9778 case X86::VDIVPSrm:
9779 case X86::VDIVPSrr:
9780 case X86::VDIVPSYrm:
9781 case X86::VDIVPSYrr:
9782 case X86::VDIVSDrm:
9783 case X86::VDIVSDrm_Int:
9784 case X86::VDIVSDrr:
9785 case X86::VDIVSDrr_Int:
9786 case X86::VDIVSSrm:
9787 case X86::VDIVSSrm_Int:
9788 case X86::VDIVSSrr:
9789 case X86::VDIVSSrr_Int:
9790 case X86::VSQRTPDm:
9791 case X86::VSQRTPDr:
9792 case X86::VSQRTPDYm:
9793 case X86::VSQRTPDYr:
9794 case X86::VSQRTPSm:
9795 case X86::VSQRTPSr:
9796 case X86::VSQRTPSYm:
9797 case X86::VSQRTPSYr:
9798 case X86::VSQRTSDm:
9799 case X86::VSQRTSDm_Int:
9800 case X86::VSQRTSDr:
9801 case X86::VSQRTSDr_Int:
9802 case X86::VSQRTSSm:
9803 case X86::VSQRTSSm_Int:
9804 case X86::VSQRTSSr:
9805 case X86::VSQRTSSr_Int:
9806 // AVX512 instructions with high latency
9807 case X86::VDIVPDZ128rm:
9808 case X86::VDIVPDZ128rmb:
9809 case X86::VDIVPDZ128rmbk:
9810 case X86::VDIVPDZ128rmbkz:
9811 case X86::VDIVPDZ128rmk:
9812 case X86::VDIVPDZ128rmkz:
9813 case X86::VDIVPDZ128rr:
9814 case X86::VDIVPDZ128rrk:
9815 case X86::VDIVPDZ128rrkz:
9816 case X86::VDIVPDZ256rm:
9817 case X86::VDIVPDZ256rmb:
9818 case X86::VDIVPDZ256rmbk:
9819 case X86::VDIVPDZ256rmbkz:
9820 case X86::VDIVPDZ256rmk:
9821 case X86::VDIVPDZ256rmkz:
9822 case X86::VDIVPDZ256rr:
9823 case X86::VDIVPDZ256rrk:
9824 case X86::VDIVPDZ256rrkz:
9825 case X86::VDIVPDZrrb:
9826 case X86::VDIVPDZrrbk:
9827 case X86::VDIVPDZrrbkz:
9828 case X86::VDIVPDZrm:
9829 case X86::VDIVPDZrmb:
9830 case X86::VDIVPDZrmbk:
9831 case X86::VDIVPDZrmbkz:
9832 case X86::VDIVPDZrmk:
9833 case X86::VDIVPDZrmkz:
9834 case X86::VDIVPDZrr:
9835 case X86::VDIVPDZrrk:
9836 case X86::VDIVPDZrrkz:
9837 case X86::VDIVPSZ128rm:
9838 case X86::VDIVPSZ128rmb:
9839 case X86::VDIVPSZ128rmbk:
9840 case X86::VDIVPSZ128rmbkz:
9841 case X86::VDIVPSZ128rmk:
9842 case X86::VDIVPSZ128rmkz:
9843 case X86::VDIVPSZ128rr:
9844 case X86::VDIVPSZ128rrk:
9845 case X86::VDIVPSZ128rrkz:
9846 case X86::VDIVPSZ256rm:
9847 case X86::VDIVPSZ256rmb:
9848 case X86::VDIVPSZ256rmbk:
9849 case X86::VDIVPSZ256rmbkz:
9850 case X86::VDIVPSZ256rmk:
9851 case X86::VDIVPSZ256rmkz:
9852 case X86::VDIVPSZ256rr:
9853 case X86::VDIVPSZ256rrk:
9854 case X86::VDIVPSZ256rrkz:
9855 case X86::VDIVPSZrrb:
9856 case X86::VDIVPSZrrbk:
9857 case X86::VDIVPSZrrbkz:
9858 case X86::VDIVPSZrm:
9859 case X86::VDIVPSZrmb:
9860 case X86::VDIVPSZrmbk:
9861 case X86::VDIVPSZrmbkz:
9862 case X86::VDIVPSZrmk:
9863 case X86::VDIVPSZrmkz:
9864 case X86::VDIVPSZrr:
9865 case X86::VDIVPSZrrk:
9866 case X86::VDIVPSZrrkz:
9867 case X86::VDIVSDZrm:
9868 case X86::VDIVSDZrr:
9869 case X86::VDIVSDZrm_Int:
9870 case X86::VDIVSDZrmk_Int:
9871 case X86::VDIVSDZrmkz_Int:
9872 case X86::VDIVSDZrr_Int:
9873 case X86::VDIVSDZrrk_Int:
9874 case X86::VDIVSDZrrkz_Int:
9875 case X86::VDIVSDZrrb_Int:
9876 case X86::VDIVSDZrrbk_Int:
9877 case X86::VDIVSDZrrbkz_Int:
9878 case X86::VDIVSSZrm:
9879 case X86::VDIVSSZrr:
9880 case X86::VDIVSSZrm_Int:
9881 case X86::VDIVSSZrmk_Int:
9882 case X86::VDIVSSZrmkz_Int:
9883 case X86::VDIVSSZrr_Int:
9884 case X86::VDIVSSZrrk_Int:
9885 case X86::VDIVSSZrrkz_Int:
9886 case X86::VDIVSSZrrb_Int:
9887 case X86::VDIVSSZrrbk_Int:
9888 case X86::VDIVSSZrrbkz_Int:
9889 case X86::VSQRTPDZ128m:
9890 case X86::VSQRTPDZ128mb:
9891 case X86::VSQRTPDZ128mbk:
9892 case X86::VSQRTPDZ128mbkz:
9893 case X86::VSQRTPDZ128mk:
9894 case X86::VSQRTPDZ128mkz:
9895 case X86::VSQRTPDZ128r:
9896 case X86::VSQRTPDZ128rk:
9897 case X86::VSQRTPDZ128rkz:
9898 case X86::VSQRTPDZ256m:
9899 case X86::VSQRTPDZ256mb:
9900 case X86::VSQRTPDZ256mbk:
9901 case X86::VSQRTPDZ256mbkz:
9902 case X86::VSQRTPDZ256mk:
9903 case X86::VSQRTPDZ256mkz:
9904 case X86::VSQRTPDZ256r:
9905 case X86::VSQRTPDZ256rk:
9906 case X86::VSQRTPDZ256rkz:
9907 case X86::VSQRTPDZm:
9908 case X86::VSQRTPDZmb:
9909 case X86::VSQRTPDZmbk:
9910 case X86::VSQRTPDZmbkz:
9911 case X86::VSQRTPDZmk:
9912 case X86::VSQRTPDZmkz:
9913 case X86::VSQRTPDZr:
9914 case X86::VSQRTPDZrb:
9915 case X86::VSQRTPDZrbk:
9916 case X86::VSQRTPDZrbkz:
9917 case X86::VSQRTPDZrk:
9918 case X86::VSQRTPDZrkz:
9919 case X86::VSQRTPSZ128m:
9920 case X86::VSQRTPSZ128mb:
9921 case X86::VSQRTPSZ128mbk:
9922 case X86::VSQRTPSZ128mbkz:
9923 case X86::VSQRTPSZ128mk:
9924 case X86::VSQRTPSZ128mkz:
9925 case X86::VSQRTPSZ128r:
9926 case X86::VSQRTPSZ128rk:
9927 case X86::VSQRTPSZ128rkz:
9928 case X86::VSQRTPSZ256m:
9929 case X86::VSQRTPSZ256mb:
9930 case X86::VSQRTPSZ256mbk:
9931 case X86::VSQRTPSZ256mbkz:
9932 case X86::VSQRTPSZ256mk:
9933 case X86::VSQRTPSZ256mkz:
9934 case X86::VSQRTPSZ256r:
9935 case X86::VSQRTPSZ256rk:
9936 case X86::VSQRTPSZ256rkz:
9937 case X86::VSQRTPSZm:
9938 case X86::VSQRTPSZmb:
9939 case X86::VSQRTPSZmbk:
9940 case X86::VSQRTPSZmbkz:
9941 case X86::VSQRTPSZmk:
9942 case X86::VSQRTPSZmkz:
9943 case X86::VSQRTPSZr:
9944 case X86::VSQRTPSZrb:
9945 case X86::VSQRTPSZrbk:
9946 case X86::VSQRTPSZrbkz:
9947 case X86::VSQRTPSZrk:
9948 case X86::VSQRTPSZrkz:
9949 case X86::VSQRTSDZm:
9950 case X86::VSQRTSDZm_Int:
9951 case X86::VSQRTSDZmk_Int:
9952 case X86::VSQRTSDZmkz_Int:
9953 case X86::VSQRTSDZr:
9954 case X86::VSQRTSDZr_Int:
9955 case X86::VSQRTSDZrk_Int:
9956 case X86::VSQRTSDZrkz_Int:
9957 case X86::VSQRTSDZrb_Int:
9958 case X86::VSQRTSDZrbk_Int:
9959 case X86::VSQRTSDZrbkz_Int:
9960 case X86::VSQRTSSZm:
9961 case X86::VSQRTSSZm_Int:
9962 case X86::VSQRTSSZmk_Int:
9963 case X86::VSQRTSSZmkz_Int:
9964 case X86::VSQRTSSZr:
9965 case X86::VSQRTSSZr_Int:
9966 case X86::VSQRTSSZrk_Int:
9967 case X86::VSQRTSSZrkz_Int:
9968 case X86::VSQRTSSZrb_Int:
9969 case X86::VSQRTSSZrbk_Int:
9970 case X86::VSQRTSSZrbkz_Int:
9971
9972 case X86::VGATHERDPDYrm:
9973 case X86::VGATHERDPDZ128rm:
9974 case X86::VGATHERDPDZ256rm:
9975 case X86::VGATHERDPDZrm:
9976 case X86::VGATHERDPDrm:
9977 case X86::VGATHERDPSYrm:
9978 case X86::VGATHERDPSZ128rm:
9979 case X86::VGATHERDPSZ256rm:
9980 case X86::VGATHERDPSZrm:
9981 case X86::VGATHERDPSrm:
9982 case X86::VGATHERPF0DPDm:
9983 case X86::VGATHERPF0DPSm:
9984 case X86::VGATHERPF0QPDm:
9985 case X86::VGATHERPF0QPSm:
9986 case X86::VGATHERPF1DPDm:
9987 case X86::VGATHERPF1DPSm:
9988 case X86::VGATHERPF1QPDm:
9989 case X86::VGATHERPF1QPSm:
9990 case X86::VGATHERQPDYrm:
9991 case X86::VGATHERQPDZ128rm:
9992 case X86::VGATHERQPDZ256rm:
9993 case X86::VGATHERQPDZrm:
9994 case X86::VGATHERQPDrm:
9995 case X86::VGATHERQPSYrm:
9996 case X86::VGATHERQPSZ128rm:
9997 case X86::VGATHERQPSZ256rm:
9998 case X86::VGATHERQPSZrm:
9999 case X86::VGATHERQPSrm:
10000 case X86::VPGATHERDDYrm:
10001 case X86::VPGATHERDDZ128rm:
10002 case X86::VPGATHERDDZ256rm:
10003 case X86::VPGATHERDDZrm:
10004 case X86::VPGATHERDDrm:
10005 case X86::VPGATHERDQYrm:
10006 case X86::VPGATHERDQZ128rm:
10007 case X86::VPGATHERDQZ256rm:
10008 case X86::VPGATHERDQZrm:
10009 case X86::VPGATHERDQrm:
10010 case X86::VPGATHERQDYrm:
10011 case X86::VPGATHERQDZ128rm:
10012 case X86::VPGATHERQDZ256rm:
10013 case X86::VPGATHERQDZrm:
10014 case X86::VPGATHERQDrm:
10015 case X86::VPGATHERQQYrm:
10016 case X86::VPGATHERQQZ128rm:
10017 case X86::VPGATHERQQZ256rm:
10018 case X86::VPGATHERQQZrm:
10019 case X86::VPGATHERQQrm:
10020 case X86::VSCATTERDPDZ128mr:
10021 case X86::VSCATTERDPDZ256mr:
10022 case X86::VSCATTERDPDZmr:
10023 case X86::VSCATTERDPSZ128mr:
10024 case X86::VSCATTERDPSZ256mr:
10025 case X86::VSCATTERDPSZmr:
10026 case X86::VSCATTERPF0DPDm:
10027 case X86::VSCATTERPF0DPSm:
10028 case X86::VSCATTERPF0QPDm:
10029 case X86::VSCATTERPF0QPSm:
10030 case X86::VSCATTERPF1DPDm:
10031 case X86::VSCATTERPF1DPSm:
10032 case X86::VSCATTERPF1QPDm:
10033 case X86::VSCATTERPF1QPSm:
10034 case X86::VSCATTERQPDZ128mr:
10035 case X86::VSCATTERQPDZ256mr:
10036 case X86::VSCATTERQPDZmr:
10037 case X86::VSCATTERQPSZ128mr:
10038 case X86::VSCATTERQPSZ256mr:
10039 case X86::VSCATTERQPSZmr:
10040 case X86::VPSCATTERDDZ128mr:
10041 case X86::VPSCATTERDDZ256mr:
10042 case X86::VPSCATTERDDZmr:
10043 case X86::VPSCATTERDQZ128mr:
10044 case X86::VPSCATTERDQZ256mr:
10045 case X86::VPSCATTERDQZmr:
10046 case X86::VPSCATTERQDZ128mr:
10047 case X86::VPSCATTERQDZ256mr:
10048 case X86::VPSCATTERQDZmr:
10049 case X86::VPSCATTERQQZ128mr:
10050 case X86::VPSCATTERQQZ256mr:
10051 case X86::VPSCATTERQQZmr:
10052 return true;
10053 }
10054}
10055
10056bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
10057 const MachineRegisterInfo *MRI,
10058 const MachineInstr &DefMI,
10059 unsigned DefIdx,
10060 const MachineInstr &UseMI,
10061 unsigned UseIdx) const {
10062 return isHighLatencyDef(opc: DefMI.getOpcode());
10063}
10064
10065bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
10066 const MachineBasicBlock *MBB) const {
10067 assert(Inst.getNumExplicitOperands() == 3 && Inst.getNumExplicitDefs() == 1 &&
10068 Inst.getNumDefs() <= 2 && "Reassociation needs binary operators");
10069
10070 // Integer binary math/logic instructions have a third source operand:
10071 // the EFLAGS register. That operand must be both defined here and never
10072 // used; ie, it must be dead. If the EFLAGS operand is live, then we can
10073 // not change anything because rearranging the operands could affect other
10074 // instructions that depend on the exact status flags (zero, sign, etc.)
10075 // that are set by using these particular operands with this operation.
10076 const MachineOperand *FlagDef =
10077 Inst.findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
10078 assert((Inst.getNumDefs() == 1 || FlagDef) && "Implicit def isn't flags?");
10079 if (FlagDef && !FlagDef->isDead())
10080 return false;
10081
10082 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
10083}
10084
10085// TODO: There are many more machine instruction opcodes to match:
10086// 1. Other data types (integer, vectors)
10087// 2. Other math / logic operations (xor, or)
10088// 3. Other forms of the same operation (intrinsics and other variants)
10089bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
10090 bool Invert) const {
10091 if (Invert)
10092 return false;
10093 switch (Inst.getOpcode()) {
10094 CASE_ND(ADD8rr)
10095 CASE_ND(ADD16rr)
10096 CASE_ND(ADD32rr)
10097 CASE_ND(ADD64rr)
10098 CASE_ND(AND8rr)
10099 CASE_ND(AND16rr)
10100 CASE_ND(AND32rr)
10101 CASE_ND(AND64rr)
10102 CASE_ND(OR8rr)
10103 CASE_ND(OR16rr)
10104 CASE_ND(OR32rr)
10105 CASE_ND(OR64rr)
10106 CASE_ND(XOR8rr)
10107 CASE_ND(XOR16rr)
10108 CASE_ND(XOR32rr)
10109 CASE_ND(XOR64rr)
10110 CASE_ND(IMUL16rr)
10111 CASE_ND(IMUL32rr)
10112 CASE_ND(IMUL64rr)
10113 case X86::PANDrr:
10114 case X86::PORrr:
10115 case X86::PXORrr:
10116 case X86::ANDPDrr:
10117 case X86::ANDPSrr:
10118 case X86::ORPDrr:
10119 case X86::ORPSrr:
10120 case X86::XORPDrr:
10121 case X86::XORPSrr:
10122 case X86::PADDBrr:
10123 case X86::PADDWrr:
10124 case X86::PADDDrr:
10125 case X86::PADDQrr:
10126 case X86::PMULLWrr:
10127 case X86::PMULLDrr:
10128 case X86::PMAXSBrr:
10129 case X86::PMAXSDrr:
10130 case X86::PMAXSWrr:
10131 case X86::PMAXUBrr:
10132 case X86::PMAXUDrr:
10133 case X86::PMAXUWrr:
10134 case X86::PMINSBrr:
10135 case X86::PMINSDrr:
10136 case X86::PMINSWrr:
10137 case X86::PMINUBrr:
10138 case X86::PMINUDrr:
10139 case X86::PMINUWrr:
10140 case X86::VPANDrr:
10141 case X86::VPANDYrr:
10142 case X86::VPANDDZ128rr:
10143 case X86::VPANDDZ256rr:
10144 case X86::VPANDDZrr:
10145 case X86::VPANDQZ128rr:
10146 case X86::VPANDQZ256rr:
10147 case X86::VPANDQZrr:
10148 case X86::VPORrr:
10149 case X86::VPORYrr:
10150 case X86::VPORDZ128rr:
10151 case X86::VPORDZ256rr:
10152 case X86::VPORDZrr:
10153 case X86::VPORQZ128rr:
10154 case X86::VPORQZ256rr:
10155 case X86::VPORQZrr:
10156 case X86::VPXORrr:
10157 case X86::VPXORYrr:
10158 case X86::VPXORDZ128rr:
10159 case X86::VPXORDZ256rr:
10160 case X86::VPXORDZrr:
10161 case X86::VPXORQZ128rr:
10162 case X86::VPXORQZ256rr:
10163 case X86::VPXORQZrr:
10164 case X86::VANDPDrr:
10165 case X86::VANDPSrr:
10166 case X86::VANDPDYrr:
10167 case X86::VANDPSYrr:
10168 case X86::VANDPDZ128rr:
10169 case X86::VANDPSZ128rr:
10170 case X86::VANDPDZ256rr:
10171 case X86::VANDPSZ256rr:
10172 case X86::VANDPDZrr:
10173 case X86::VANDPSZrr:
10174 case X86::VORPDrr:
10175 case X86::VORPSrr:
10176 case X86::VORPDYrr:
10177 case X86::VORPSYrr:
10178 case X86::VORPDZ128rr:
10179 case X86::VORPSZ128rr:
10180 case X86::VORPDZ256rr:
10181 case X86::VORPSZ256rr:
10182 case X86::VORPDZrr:
10183 case X86::VORPSZrr:
10184 case X86::VXORPDrr:
10185 case X86::VXORPSrr:
10186 case X86::VXORPDYrr:
10187 case X86::VXORPSYrr:
10188 case X86::VXORPDZ128rr:
10189 case X86::VXORPSZ128rr:
10190 case X86::VXORPDZ256rr:
10191 case X86::VXORPSZ256rr:
10192 case X86::VXORPDZrr:
10193 case X86::VXORPSZrr:
10194 case X86::KADDBkk:
10195 case X86::KADDWkk:
10196 case X86::KADDDkk:
10197 case X86::KADDQkk:
10198 case X86::KANDBkk:
10199 case X86::KANDWkk:
10200 case X86::KANDDkk:
10201 case X86::KANDQkk:
10202 case X86::KORBkk:
10203 case X86::KORWkk:
10204 case X86::KORDkk:
10205 case X86::KORQkk:
10206 case X86::KXORBkk:
10207 case X86::KXORWkk:
10208 case X86::KXORDkk:
10209 case X86::KXORQkk:
10210 case X86::VPADDBrr:
10211 case X86::VPADDWrr:
10212 case X86::VPADDDrr:
10213 case X86::VPADDQrr:
10214 case X86::VPADDBYrr:
10215 case X86::VPADDWYrr:
10216 case X86::VPADDDYrr:
10217 case X86::VPADDQYrr:
10218 case X86::VPADDBZ128rr:
10219 case X86::VPADDWZ128rr:
10220 case X86::VPADDDZ128rr:
10221 case X86::VPADDQZ128rr:
10222 case X86::VPADDBZ256rr:
10223 case X86::VPADDWZ256rr:
10224 case X86::VPADDDZ256rr:
10225 case X86::VPADDQZ256rr:
10226 case X86::VPADDBZrr:
10227 case X86::VPADDWZrr:
10228 case X86::VPADDDZrr:
10229 case X86::VPADDQZrr:
10230 case X86::VPMULLWrr:
10231 case X86::VPMULLWYrr:
10232 case X86::VPMULLWZ128rr:
10233 case X86::VPMULLWZ256rr:
10234 case X86::VPMULLWZrr:
10235 case X86::VPMULLDrr:
10236 case X86::VPMULLDYrr:
10237 case X86::VPMULLDZ128rr:
10238 case X86::VPMULLDZ256rr:
10239 case X86::VPMULLDZrr:
10240 case X86::VPMULLQZ128rr:
10241 case X86::VPMULLQZ256rr:
10242 case X86::VPMULLQZrr:
10243 case X86::VPMAXSBrr:
10244 case X86::VPMAXSBYrr:
10245 case X86::VPMAXSBZ128rr:
10246 case X86::VPMAXSBZ256rr:
10247 case X86::VPMAXSBZrr:
10248 case X86::VPMAXSDrr:
10249 case X86::VPMAXSDYrr:
10250 case X86::VPMAXSDZ128rr:
10251 case X86::VPMAXSDZ256rr:
10252 case X86::VPMAXSDZrr:
10253 case X86::VPMAXSQZ128rr:
10254 case X86::VPMAXSQZ256rr:
10255 case X86::VPMAXSQZrr:
10256 case X86::VPMAXSWrr:
10257 case X86::VPMAXSWYrr:
10258 case X86::VPMAXSWZ128rr:
10259 case X86::VPMAXSWZ256rr:
10260 case X86::VPMAXSWZrr:
10261 case X86::VPMAXUBrr:
10262 case X86::VPMAXUBYrr:
10263 case X86::VPMAXUBZ128rr:
10264 case X86::VPMAXUBZ256rr:
10265 case X86::VPMAXUBZrr:
10266 case X86::VPMAXUDrr:
10267 case X86::VPMAXUDYrr:
10268 case X86::VPMAXUDZ128rr:
10269 case X86::VPMAXUDZ256rr:
10270 case X86::VPMAXUDZrr:
10271 case X86::VPMAXUQZ128rr:
10272 case X86::VPMAXUQZ256rr:
10273 case X86::VPMAXUQZrr:
10274 case X86::VPMAXUWrr:
10275 case X86::VPMAXUWYrr:
10276 case X86::VPMAXUWZ128rr:
10277 case X86::VPMAXUWZ256rr:
10278 case X86::VPMAXUWZrr:
10279 case X86::VPMINSBrr:
10280 case X86::VPMINSBYrr:
10281 case X86::VPMINSBZ128rr:
10282 case X86::VPMINSBZ256rr:
10283 case X86::VPMINSBZrr:
10284 case X86::VPMINSDrr:
10285 case X86::VPMINSDYrr:
10286 case X86::VPMINSDZ128rr:
10287 case X86::VPMINSDZ256rr:
10288 case X86::VPMINSDZrr:
10289 case X86::VPMINSQZ128rr:
10290 case X86::VPMINSQZ256rr:
10291 case X86::VPMINSQZrr:
10292 case X86::VPMINSWrr:
10293 case X86::VPMINSWYrr:
10294 case X86::VPMINSWZ128rr:
10295 case X86::VPMINSWZ256rr:
10296 case X86::VPMINSWZrr:
10297 case X86::VPMINUBrr:
10298 case X86::VPMINUBYrr:
10299 case X86::VPMINUBZ128rr:
10300 case X86::VPMINUBZ256rr:
10301 case X86::VPMINUBZrr:
10302 case X86::VPMINUDrr:
10303 case X86::VPMINUDYrr:
10304 case X86::VPMINUDZ128rr:
10305 case X86::VPMINUDZ256rr:
10306 case X86::VPMINUDZrr:
10307 case X86::VPMINUQZ128rr:
10308 case X86::VPMINUQZ256rr:
10309 case X86::VPMINUQZrr:
10310 case X86::VPMINUWrr:
10311 case X86::VPMINUWYrr:
10312 case X86::VPMINUWZ128rr:
10313 case X86::VPMINUWZ256rr:
10314 case X86::VPMINUWZrr:
10315 // Normal min/max instructions are not commutative because of NaN and signed
10316 // zero semantics, but these are. Thus, there's no need to check for global
10317 // relaxed math; the instructions themselves have the properties we need.
10318 case X86::MAXCPDrr:
10319 case X86::MAXCPSrr:
10320 case X86::MAXCSDrr:
10321 case X86::MAXCSSrr:
10322 case X86::MINCPDrr:
10323 case X86::MINCPSrr:
10324 case X86::MINCSDrr:
10325 case X86::MINCSSrr:
10326 case X86::VMAXCPDrr:
10327 case X86::VMAXCPSrr:
10328 case X86::VMAXCPDYrr:
10329 case X86::VMAXCPSYrr:
10330 case X86::VMAXCPDZ128rr:
10331 case X86::VMAXCPSZ128rr:
10332 case X86::VMAXCPDZ256rr:
10333 case X86::VMAXCPSZ256rr:
10334 case X86::VMAXCPDZrr:
10335 case X86::VMAXCPSZrr:
10336 case X86::VMAXCSDrr:
10337 case X86::VMAXCSSrr:
10338 case X86::VMAXCSDZrr:
10339 case X86::VMAXCSSZrr:
10340 case X86::VMINCPDrr:
10341 case X86::VMINCPSrr:
10342 case X86::VMINCPDYrr:
10343 case X86::VMINCPSYrr:
10344 case X86::VMINCPDZ128rr:
10345 case X86::VMINCPSZ128rr:
10346 case X86::VMINCPDZ256rr:
10347 case X86::VMINCPSZ256rr:
10348 case X86::VMINCPDZrr:
10349 case X86::VMINCPSZrr:
10350 case X86::VMINCSDrr:
10351 case X86::VMINCSSrr:
10352 case X86::VMINCSDZrr:
10353 case X86::VMINCSSZrr:
10354 case X86::VMAXCPHZ128rr:
10355 case X86::VMAXCPHZ256rr:
10356 case X86::VMAXCPHZrr:
10357 case X86::VMAXCSHZrr:
10358 case X86::VMINCPHZ128rr:
10359 case X86::VMINCPHZ256rr:
10360 case X86::VMINCPHZrr:
10361 case X86::VMINCSHZrr:
10362 return true;
10363 case X86::ADDPDrr:
10364 case X86::ADDPSrr:
10365 case X86::ADDSDrr:
10366 case X86::ADDSSrr:
10367 case X86::MULPDrr:
10368 case X86::MULPSrr:
10369 case X86::MULSDrr:
10370 case X86::MULSSrr:
10371 case X86::VADDPDrr:
10372 case X86::VADDPSrr:
10373 case X86::VADDPDYrr:
10374 case X86::VADDPSYrr:
10375 case X86::VADDPDZ128rr:
10376 case X86::VADDPSZ128rr:
10377 case X86::VADDPDZ256rr:
10378 case X86::VADDPSZ256rr:
10379 case X86::VADDPDZrr:
10380 case X86::VADDPSZrr:
10381 case X86::VADDSDrr:
10382 case X86::VADDSSrr:
10383 case X86::VADDSDZrr:
10384 case X86::VADDSSZrr:
10385 case X86::VMULPDrr:
10386 case X86::VMULPSrr:
10387 case X86::VMULPDYrr:
10388 case X86::VMULPSYrr:
10389 case X86::VMULPDZ128rr:
10390 case X86::VMULPSZ128rr:
10391 case X86::VMULPDZ256rr:
10392 case X86::VMULPSZ256rr:
10393 case X86::VMULPDZrr:
10394 case X86::VMULPSZrr:
10395 case X86::VMULSDrr:
10396 case X86::VMULSSrr:
10397 case X86::VMULSDZrr:
10398 case X86::VMULSSZrr:
10399 case X86::VADDPHZ128rr:
10400 case X86::VADDPHZ256rr:
10401 case X86::VADDPHZrr:
10402 case X86::VADDSHZrr:
10403 case X86::VMULPHZ128rr:
10404 case X86::VMULPHZ256rr:
10405 case X86::VMULPHZrr:
10406 case X86::VMULSHZrr:
10407 return Inst.getFlag(Flag: MachineInstr::MIFlag::FmReassoc) &&
10408 Inst.getFlag(Flag: MachineInstr::MIFlag::FmNsz);
10409 default:
10410 return false;
10411 }
10412}
10413
10414/// If \p DescribedReg overlaps with the MOVrr instruction's destination
10415/// register then, if possible, describe the value in terms of the source
10416/// register.
10417static std::optional<ParamLoadedValue>
10418describeMOVrrLoadedValue(const MachineInstr &MI, Register DescribedReg,
10419 const TargetRegisterInfo *TRI) {
10420 Register DestReg = MI.getOperand(i: 0).getReg();
10421 Register SrcReg = MI.getOperand(i: 1).getReg();
10422
10423 auto Expr = DIExpression::get(Context&: MI.getMF()->getFunction().getContext(), Elements: {});
10424
10425 // If the described register is the destination, just return the source.
10426 if (DestReg == DescribedReg)
10427 return ParamLoadedValue(MachineOperand::CreateReg(Reg: SrcReg, isDef: false), Expr);
10428
10429 // If the described register is a sub-register of the destination register,
10430 // then pick out the source register's corresponding sub-register.
10431 if (unsigned SubRegIdx = TRI->getSubRegIndex(RegNo: DestReg, SubRegNo: DescribedReg)) {
10432 Register SrcSubReg = TRI->getSubReg(Reg: SrcReg, Idx: SubRegIdx);
10433 return ParamLoadedValue(MachineOperand::CreateReg(Reg: SrcSubReg, isDef: false), Expr);
10434 }
10435
10436 // The remaining case to consider is when the described register is a
10437 // super-register of the destination register. MOV8rr and MOV16rr does not
10438 // write to any of the other bytes in the register, meaning that we'd have to
10439 // describe the value using a combination of the source register and the
10440 // non-overlapping bits in the described register, which is not currently
10441 // possible.
10442 if (MI.getOpcode() == X86::MOV8rr || MI.getOpcode() == X86::MOV16rr ||
10443 !TRI->isSuperRegister(RegA: DestReg, RegB: DescribedReg))
10444 return std::nullopt;
10445
10446 assert(MI.getOpcode() == X86::MOV32rr && "Unexpected super-register case");
10447 return ParamLoadedValue(MachineOperand::CreateReg(Reg: SrcReg, isDef: false), Expr);
10448}
10449
10450std::optional<ParamLoadedValue>
10451X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
10452 const MachineOperand *Op = nullptr;
10453 DIExpression *Expr = nullptr;
10454
10455 const TargetRegisterInfo *TRI = &getRegisterInfo();
10456
10457 switch (MI.getOpcode()) {
10458 case X86::LEA32r:
10459 case X86::LEA64r:
10460 case X86::LEA64_32r: {
10461 // We may need to describe a 64-bit parameter with a 32-bit LEA.
10462 if (!TRI->isSuperRegisterEq(RegA: MI.getOperand(i: 0).getReg(), RegB: Reg))
10463 return std::nullopt;
10464
10465 // Operand 4 could be global address. For now we do not support
10466 // such situation.
10467 if (!MI.getOperand(i: 4).isImm() || !MI.getOperand(i: 2).isImm())
10468 return std::nullopt;
10469
10470 const MachineOperand &Op1 = MI.getOperand(i: 1);
10471 const MachineOperand &Op2 = MI.getOperand(i: 3);
10472 assert(Op2.isReg() &&
10473 (Op2.getReg() == X86::NoRegister || Op2.getReg().isPhysical()));
10474
10475 // Omit situations like:
10476 // %rsi = lea %rsi, 4, ...
10477 if ((Op1.isReg() && Op1.getReg() == MI.getOperand(i: 0).getReg()) ||
10478 Op2.getReg() == MI.getOperand(i: 0).getReg())
10479 return std::nullopt;
10480 else if ((Op1.isReg() && Op1.getReg() != X86::NoRegister &&
10481 TRI->regsOverlap(RegA: Op1.getReg(), RegB: MI.getOperand(i: 0).getReg())) ||
10482 (Op2.getReg() != X86::NoRegister &&
10483 TRI->regsOverlap(RegA: Op2.getReg(), RegB: MI.getOperand(i: 0).getReg())))
10484 return std::nullopt;
10485
10486 int64_t Coef = MI.getOperand(i: 2).getImm();
10487 int64_t Offset = MI.getOperand(i: 4).getImm();
10488 SmallVector<uint64_t, 8> Ops;
10489
10490 if ((Op1.isReg() && Op1.getReg() != X86::NoRegister)) {
10491 Op = &Op1;
10492 } else if (Op1.isFI())
10493 Op = &Op1;
10494
10495 if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) {
10496 Ops.push_back(Elt: dwarf::DW_OP_constu);
10497 Ops.push_back(Elt: Coef + 1);
10498 Ops.push_back(Elt: dwarf::DW_OP_mul);
10499 } else {
10500 if (Op && Op2.getReg() != X86::NoRegister) {
10501 int dwarfReg = TRI->getDwarfRegNum(Reg: Op2.getReg(), isEH: false);
10502 if (dwarfReg < 0)
10503 return std::nullopt;
10504 else if (dwarfReg < 32) {
10505 Ops.push_back(Elt: dwarf::DW_OP_breg0 + dwarfReg);
10506 Ops.push_back(Elt: 0);
10507 } else {
10508 Ops.push_back(Elt: dwarf::DW_OP_bregx);
10509 Ops.push_back(Elt: dwarfReg);
10510 Ops.push_back(Elt: 0);
10511 }
10512 } else if (!Op) {
10513 assert(Op2.getReg() != X86::NoRegister);
10514 Op = &Op2;
10515 }
10516
10517 if (Coef > 1) {
10518 assert(Op2.getReg() != X86::NoRegister);
10519 Ops.push_back(Elt: dwarf::DW_OP_constu);
10520 Ops.push_back(Elt: Coef);
10521 Ops.push_back(Elt: dwarf::DW_OP_mul);
10522 }
10523
10524 if (((Op1.isReg() && Op1.getReg() != X86::NoRegister) || Op1.isFI()) &&
10525 Op2.getReg() != X86::NoRegister) {
10526 Ops.push_back(Elt: dwarf::DW_OP_plus);
10527 }
10528 }
10529
10530 DIExpression::appendOffset(Ops, Offset);
10531 Expr = DIExpression::get(Context&: MI.getMF()->getFunction().getContext(), Elements: Ops);
10532
10533 return ParamLoadedValue(*Op, Expr);
10534 }
10535 case X86::MOV8ri:
10536 case X86::MOV16ri:
10537 // TODO: Handle MOV8ri and MOV16ri.
10538 return std::nullopt;
10539 case X86::MOV32ri:
10540 case X86::MOV64ri:
10541 case X86::MOV64ri32:
10542 // MOV32ri may be used for producing zero-extended 32-bit immediates in
10543 // 64-bit parameters, so we need to consider super-registers.
10544 if (!TRI->isSuperRegisterEq(RegA: MI.getOperand(i: 0).getReg(), RegB: Reg))
10545 return std::nullopt;
10546 return ParamLoadedValue(MI.getOperand(i: 1), Expr);
10547 case X86::MOV8rr:
10548 case X86::MOV16rr:
10549 case X86::MOV32rr:
10550 case X86::MOV64rr:
10551 return describeMOVrrLoadedValue(MI, DescribedReg: Reg, TRI);
10552 case X86::XOR32rr: {
10553 // 64-bit parameters are zero-materialized using XOR32rr, so also consider
10554 // super-registers.
10555 if (!TRI->isSuperRegisterEq(RegA: MI.getOperand(i: 0).getReg(), RegB: Reg))
10556 return std::nullopt;
10557 if (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 2).getReg())
10558 return ParamLoadedValue(MachineOperand::CreateImm(Val: 0), Expr);
10559 return std::nullopt;
10560 }
10561 case X86::MOVSX64rr32: {
10562 // We may need to describe the lower 32 bits of the MOVSX; for example, in
10563 // cases like this:
10564 //
10565 // $ebx = [...]
10566 // $rdi = MOVSX64rr32 $ebx
10567 // $esi = MOV32rr $edi
10568 if (!TRI->isSubRegisterEq(RegA: MI.getOperand(i: 0).getReg(), RegB: Reg))
10569 return std::nullopt;
10570
10571 Expr = DIExpression::get(Context&: MI.getMF()->getFunction().getContext(), Elements: {});
10572
10573 // If the described register is the destination register we need to
10574 // sign-extend the source register from 32 bits. The other case we handle
10575 // is when the described register is the 32-bit sub-register of the
10576 // destination register, in case we just need to return the source
10577 // register.
10578 if (Reg == MI.getOperand(i: 0).getReg())
10579 Expr = DIExpression::appendExt(Expr, FromSize: 32, ToSize: 64, Signed: true);
10580 else
10581 assert(getX86MCRegisterClass(X86::GR32RegClassID).contains(Reg) &&
10582 "Unhandled sub-register case for MOVSX64rr32");
10583
10584 return ParamLoadedValue(MI.getOperand(i: 1), Expr);
10585 }
10586 default:
10587 assert(!MI.isMoveImmediate() && "Unexpected MoveImm instruction");
10588 return TargetInstrInfo::describeLoadedValue(MI, Reg);
10589 }
10590}
10591
10592/// This is an architecture-specific helper function of reassociateOps.
10593/// Set special operand attributes for new instructions after reassociation.
10594void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
10595 MachineInstr &OldMI2,
10596 MachineInstr &NewMI1,
10597 MachineInstr &NewMI2) const {
10598 // Integer instructions may define an implicit EFLAGS dest register operand.
10599 MachineOperand *OldFlagDef1 =
10600 OldMI1.findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
10601 MachineOperand *OldFlagDef2 =
10602 OldMI2.findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
10603
10604 assert(!OldFlagDef1 == !OldFlagDef2 &&
10605 "Unexpected instruction type for reassociation");
10606
10607 if (!OldFlagDef1 || !OldFlagDef2)
10608 return;
10609
10610 assert(OldFlagDef1->isDead() && OldFlagDef2->isDead() &&
10611 "Must have dead EFLAGS operand in reassociable instruction");
10612
10613 MachineOperand *NewFlagDef1 =
10614 NewMI1.findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
10615 MachineOperand *NewFlagDef2 =
10616 NewMI2.findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
10617
10618 assert(NewFlagDef1 && NewFlagDef2 &&
10619 "Unexpected operand in reassociable instruction");
10620
10621 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
10622 // of this pass or other passes. The EFLAGS operands must be dead in these new
10623 // instructions because the EFLAGS operands in the original instructions must
10624 // be dead in order for reassociation to occur.
10625 NewFlagDef1->setIsDead();
10626 NewFlagDef2->setIsDead();
10627}
10628
10629std::pair<unsigned, unsigned>
10630X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
10631 return std::make_pair(x&: TF, y: 0u);
10632}
10633
10634ArrayRef<std::pair<unsigned, const char *>>
10635X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
10636 using namespace X86II;
10637 static const std::pair<unsigned, const char *> TargetFlags[] = {
10638 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
10639 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
10640 {MO_GOT, "x86-got"},
10641 {MO_GOTOFF, "x86-gotoff"},
10642 {MO_GOTPCREL, "x86-gotpcrel"},
10643 {MO_GOTPCREL_NORELAX, "x86-gotpcrel-norelax"},
10644 {MO_PLT, "x86-plt"},
10645 {MO_TLSGD, "x86-tlsgd"},
10646 {MO_TLSLD, "x86-tlsld"},
10647 {MO_TLSLDM, "x86-tlsldm"},
10648 {MO_GOTTPOFF, "x86-gottpoff"},
10649 {MO_INDNTPOFF, "x86-indntpoff"},
10650 {MO_TPOFF, "x86-tpoff"},
10651 {MO_DTPOFF, "x86-dtpoff"},
10652 {MO_NTPOFF, "x86-ntpoff"},
10653 {MO_GOTNTPOFF, "x86-gotntpoff"},
10654 {MO_DLLIMPORT, "x86-dllimport"},
10655 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
10656 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
10657 {MO_TLVP, "x86-tlvp"},
10658 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
10659 {MO_SECREL, "x86-secrel"},
10660 {MO_COFFSTUB, "x86-coffstub"}};
10661 return ArrayRef(TargetFlags);
10662}
10663
10664/// Constants defining how certain sequences should be outlined.
10665///
10666/// \p MachineOutlinerDefault implies that the function is called with a call
10667/// instruction, and a return must be emitted for the outlined function frame.
10668///
10669/// That is,
10670///
10671/// I1 OUTLINED_FUNCTION:
10672/// I2 --> call OUTLINED_FUNCTION I1
10673/// I3 I2
10674/// I3
10675/// ret
10676///
10677/// * Call construction overhead: 1 (call instruction)
10678/// * Frame construction overhead: 1 (return instruction)
10679///
10680/// \p MachineOutlinerTailCall implies that the function is being tail called.
10681/// A jump is emitted instead of a call, and the return is already present in
10682/// the outlined sequence. That is,
10683///
10684/// I1 OUTLINED_FUNCTION:
10685/// I2 --> jmp OUTLINED_FUNCTION I1
10686/// ret I2
10687/// ret
10688///
10689/// * Call construction overhead: 1 (jump instruction)
10690/// * Frame construction overhead: 0 (don't need to return)
10691///
10692enum MachineOutlinerClass { MachineOutlinerDefault, MachineOutlinerTailCall };
10693
10694std::optional<std::unique_ptr<outliner::OutlinedFunction>>
10695X86InstrInfo::getOutliningCandidateInfo(
10696 const MachineModuleInfo &MMI,
10697 std::vector<outliner::Candidate> &RepeatedSequenceLocs,
10698 unsigned MinRepeats) const {
10699 unsigned SequenceSize = 0;
10700 for (auto &MI : RepeatedSequenceLocs[0]) {
10701 // FIXME: x86 doesn't implement getInstSizeInBytes, so
10702 // we can't tell the cost. Just assume each instruction
10703 // is one byte.
10704 if (MI.isDebugInstr() || MI.isKill())
10705 continue;
10706 SequenceSize += 1;
10707 }
10708
10709 // We check to see if CFI Instructions are present, and if they are
10710 // we find the number of CFI Instructions in the candidates.
10711 unsigned CFICount = 0;
10712 for (auto &I : RepeatedSequenceLocs[0]) {
10713 if (I.isCFIInstruction())
10714 CFICount++;
10715 }
10716
10717 // We compare the number of found CFI Instructions to the number of CFI
10718 // instructions in the parent function for each candidate. We must check this
10719 // since if we outline one of the CFI instructions in a function, we have to
10720 // outline them all for correctness. If we do not, the address offsets will be
10721 // incorrect between the two sections of the program.
10722 for (outliner::Candidate &C : RepeatedSequenceLocs) {
10723 std::vector<MCCFIInstruction> CFIInstructions =
10724 C.getMF()->getFrameInstructions();
10725
10726 if (CFICount > 0 && CFICount != CFIInstructions.size())
10727 return std::nullopt;
10728 }
10729
10730 // FIXME: Use real size in bytes for call and ret instructions.
10731 if (RepeatedSequenceLocs[0].back().isTerminator()) {
10732 for (outliner::Candidate &C : RepeatedSequenceLocs)
10733 C.setCallInfo(CID: MachineOutlinerTailCall, CO: 1);
10734
10735 return std::make_unique<outliner::OutlinedFunction>(
10736 args&: RepeatedSequenceLocs, args&: SequenceSize,
10737 args: 0, // Number of bytes to emit frame.
10738 args: MachineOutlinerTailCall // Type of frame.
10739 );
10740 }
10741
10742 if (CFICount > 0)
10743 return std::nullopt;
10744
10745 for (outliner::Candidate &C : RepeatedSequenceLocs)
10746 C.setCallInfo(CID: MachineOutlinerDefault, CO: 1);
10747
10748 return std::make_unique<outliner::OutlinedFunction>(
10749 args&: RepeatedSequenceLocs, args&: SequenceSize, args: 1, args: MachineOutlinerDefault);
10750}
10751
10752bool X86InstrInfo::isFunctionSafeToOutlineFrom(
10753 MachineFunction &MF, bool OutlineFromLinkOnceODRs) const {
10754 const Function &F = MF.getFunction();
10755
10756 // Does the function use a red zone? If it does, then we can't risk messing
10757 // with the stack.
10758 if (Subtarget.getFrameLowering()->has128ByteRedZone(MF)) {
10759 // It could have a red zone. If it does, then we don't want to touch it.
10760 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
10761 if (!X86FI || X86FI->getUsesRedZone())
10762 return false;
10763 }
10764
10765 // If we *don't* want to outline from things that could potentially be deduped
10766 // then return false.
10767 if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
10768 return false;
10769
10770 // This function is viable for outlining, so return true.
10771 return true;
10772}
10773
10774outliner::InstrType
10775X86InstrInfo::getOutliningTypeImpl(const MachineModuleInfo &MMI,
10776 MachineBasicBlock::iterator &MIT,
10777 unsigned Flags) const {
10778 MachineInstr &MI = *MIT;
10779
10780 // Is this a terminator for a basic block?
10781 if (MI.isTerminator())
10782 // TargetInstrInfo::getOutliningType has already filtered out anything
10783 // that would break this, so we can allow it here.
10784 return outliner::InstrType::Legal;
10785
10786 // Don't outline anything that modifies or reads from the stack pointer.
10787 //
10788 // FIXME: There are instructions which are being manually built without
10789 // explicit uses/defs so we also have to check the MCInstrDesc. We should be
10790 // able to remove the extra checks once those are fixed up. For example,
10791 // sometimes we might get something like %rax = POP64r 1. This won't be
10792 // caught by modifiesRegister or readsRegister even though the instruction
10793 // really ought to be formed so that modifiesRegister/readsRegister would
10794 // catch it.
10795 if (MI.modifiesRegister(Reg: X86::RSP, TRI: &RI) || MI.readsRegister(Reg: X86::RSP, TRI: &RI) ||
10796 MI.getDesc().hasImplicitUseOfPhysReg(Reg: X86::RSP) ||
10797 MI.getDesc().hasImplicitDefOfPhysReg(Reg: X86::RSP))
10798 return outliner::InstrType::Illegal;
10799
10800 // Outlined calls change the instruction pointer, so don't read from it.
10801 if (MI.readsRegister(Reg: X86::RIP, TRI: &RI) ||
10802 MI.getDesc().hasImplicitUseOfPhysReg(Reg: X86::RIP) ||
10803 MI.getDesc().hasImplicitDefOfPhysReg(Reg: X86::RIP))
10804 return outliner::InstrType::Illegal;
10805
10806 // Don't outline CFI instructions.
10807 if (MI.isCFIInstruction())
10808 return outliner::InstrType::Illegal;
10809
10810 return outliner::InstrType::Legal;
10811}
10812
10813void X86InstrInfo::buildOutlinedFrame(
10814 MachineBasicBlock &MBB, MachineFunction &MF,
10815 const outliner::OutlinedFunction &OF) const {
10816 // If we're a tail call, we already have a return, so don't do anything.
10817 if (OF.FrameConstructionID == MachineOutlinerTailCall)
10818 return;
10819
10820 // We're a normal call, so our sequence doesn't have a return instruction.
10821 // Add it in.
10822 MachineInstr *retq = BuildMI(MF, MIMD: DebugLoc(), MCID: get(Opcode: X86::RET64));
10823 MBB.insert(I: MBB.end(), MI: retq);
10824}
10825
10826MachineBasicBlock::iterator X86InstrInfo::insertOutlinedCall(
10827 Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It,
10828 MachineFunction &MF, outliner::Candidate &C) const {
10829 // Is it a tail call?
10830 if (C.CallConstructionID == MachineOutlinerTailCall) {
10831 // Yes, just insert a JMP.
10832 It = MBB.insert(I: It, MI: BuildMI(MF, MIMD: DebugLoc(), MCID: get(Opcode: X86::TAILJMPd64))
10833 .addGlobalAddress(GV: M.getNamedValue(Name: MF.getName())));
10834 } else {
10835 // No, insert a call.
10836 It = MBB.insert(I: It, MI: BuildMI(MF, MIMD: DebugLoc(), MCID: get(Opcode: X86::CALL64pcrel32))
10837 .addGlobalAddress(GV: M.getNamedValue(Name: MF.getName())));
10838 }
10839
10840 return It;
10841}
10842
10843void X86InstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB,
10844 MachineBasicBlock::iterator Iter,
10845 DebugLoc &DL,
10846 bool AllowSideEffects) const {
10847 const MachineFunction &MF = *MBB.getParent();
10848 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
10849 const TargetRegisterInfo &TRI = getRegisterInfo();
10850
10851 if (ST.hasMMX() && X86::VR64RegClass.contains(Reg))
10852 // FIXME: Should we ignore MMX registers?
10853 return;
10854
10855 if (TRI.isGeneralPurposeRegister(MF, PhysReg: Reg)) {
10856 // Convert register to the 32-bit version. Both 'movl' and 'xorl' clear the
10857 // upper bits of a 64-bit register automagically.
10858 Reg = getX86SubSuperRegister(Reg, Size: 32);
10859
10860 if (!AllowSideEffects)
10861 // XOR affects flags, so use a MOV instead.
10862 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: X86::MOV32ri), DestReg: Reg).addImm(Val: 0);
10863 else
10864 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: X86::XOR32rr), DestReg: Reg)
10865 .addReg(RegNo: Reg, Flags: RegState::Undef)
10866 .addReg(RegNo: Reg, Flags: RegState::Undef);
10867 } else if (X86::VR128RegClass.contains(Reg)) {
10868 // XMM#
10869 if (!ST.hasSSE1())
10870 return;
10871
10872 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: X86::V_SET0), DestReg: Reg);
10873 } else if (X86::VR256RegClass.contains(Reg)) {
10874 // YMM#
10875 if (!ST.hasAVX())
10876 return;
10877
10878 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: X86::V_SET0), DestReg: TRI.getSubReg(Reg, Idx: X86::sub_xmm));
10879 } else if (X86::VR512RegClass.contains(Reg)) {
10880 // ZMM#
10881 if (!ST.hasAVX512())
10882 return;
10883
10884 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: X86::AVX512_128_SET0),
10885 DestReg: TRI.getSubReg(Reg, Idx: X86::sub_xmm));
10886 } else if (X86::VK1RegClass.contains(Reg) || X86::VK2RegClass.contains(Reg) ||
10887 X86::VK4RegClass.contains(Reg) || X86::VK8RegClass.contains(Reg) ||
10888 X86::VK16RegClass.contains(Reg)) {
10889 if (!ST.hasAVX512())
10890 return;
10891
10892 unsigned Op = ST.hasBWI() ? X86::KSET0Q : X86::KSET0W;
10893 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: Op), DestReg: Reg);
10894 }
10895}
10896
10897bool X86InstrInfo::getMachineCombinerPatterns(
10898 MachineInstr &Root, SmallVectorImpl<unsigned> &Patterns,
10899 bool DoRegPressureReduce) const {
10900 unsigned Opc = Root.getOpcode();
10901 switch (Opc) {
10902 case X86::VPDPWSSDrr:
10903 case X86::VPDPWSSDrm:
10904 case X86::VPDPWSSDYrr:
10905 case X86::VPDPWSSDYrm: {
10906 if (!Subtarget.hasFastDPWSSD()) {
10907 Patterns.push_back(Elt: X86MachineCombinerPattern::DPWSSD);
10908 return true;
10909 }
10910 break;
10911 }
10912 case X86::VPDPWSSDZ128rr:
10913 case X86::VPDPWSSDZ128rm:
10914 case X86::VPDPWSSDZ256rr:
10915 case X86::VPDPWSSDZ256rm:
10916 case X86::VPDPWSSDZrr:
10917 case X86::VPDPWSSDZrm: {
10918 if (Subtarget.hasBWI() && !Subtarget.hasFastDPWSSD()) {
10919 Patterns.push_back(Elt: X86MachineCombinerPattern::DPWSSD);
10920 return true;
10921 }
10922 break;
10923 }
10924 }
10925 return TargetInstrInfo::getMachineCombinerPatterns(Root,
10926 Patterns, DoRegPressureReduce);
10927}
10928
10929static void
10930genAlternativeDpCodeSequence(MachineInstr &Root, const TargetInstrInfo &TII,
10931 SmallVectorImpl<MachineInstr *> &InsInstrs,
10932 SmallVectorImpl<MachineInstr *> &DelInstrs,
10933 DenseMap<Register, unsigned> &InstrIdxForVirtReg) {
10934 MachineFunction *MF = Root.getMF();
10935 MachineRegisterInfo &RegInfo = MF->getRegInfo();
10936
10937 unsigned Opc = Root.getOpcode();
10938 unsigned AddOpc = 0;
10939 unsigned MaddOpc = 0;
10940 switch (Opc) {
10941 default:
10942 assert(false && "It should not reach here");
10943 break;
10944 // vpdpwssd xmm2,xmm3,xmm1
10945 // -->
10946 // vpmaddwd xmm3,xmm3,xmm1
10947 // vpaddd xmm2,xmm2,xmm3
10948 case X86::VPDPWSSDrr:
10949 MaddOpc = X86::VPMADDWDrr;
10950 AddOpc = X86::VPADDDrr;
10951 break;
10952 case X86::VPDPWSSDrm:
10953 MaddOpc = X86::VPMADDWDrm;
10954 AddOpc = X86::VPADDDrr;
10955 break;
10956 case X86::VPDPWSSDZ128rr:
10957 MaddOpc = X86::VPMADDWDZ128rr;
10958 AddOpc = X86::VPADDDZ128rr;
10959 break;
10960 case X86::VPDPWSSDZ128rm:
10961 MaddOpc = X86::VPMADDWDZ128rm;
10962 AddOpc = X86::VPADDDZ128rr;
10963 break;
10964 // vpdpwssd ymm2,ymm3,ymm1
10965 // -->
10966 // vpmaddwd ymm3,ymm3,ymm1
10967 // vpaddd ymm2,ymm2,ymm3
10968 case X86::VPDPWSSDYrr:
10969 MaddOpc = X86::VPMADDWDYrr;
10970 AddOpc = X86::VPADDDYrr;
10971 break;
10972 case X86::VPDPWSSDYrm:
10973 MaddOpc = X86::VPMADDWDYrm;
10974 AddOpc = X86::VPADDDYrr;
10975 break;
10976 case X86::VPDPWSSDZ256rr:
10977 MaddOpc = X86::VPMADDWDZ256rr;
10978 AddOpc = X86::VPADDDZ256rr;
10979 break;
10980 case X86::VPDPWSSDZ256rm:
10981 MaddOpc = X86::VPMADDWDZ256rm;
10982 AddOpc = X86::VPADDDZ256rr;
10983 break;
10984 // vpdpwssd zmm2,zmm3,zmm1
10985 // -->
10986 // vpmaddwd zmm3,zmm3,zmm1
10987 // vpaddd zmm2,zmm2,zmm3
10988 case X86::VPDPWSSDZrr:
10989 MaddOpc = X86::VPMADDWDZrr;
10990 AddOpc = X86::VPADDDZrr;
10991 break;
10992 case X86::VPDPWSSDZrm:
10993 MaddOpc = X86::VPMADDWDZrm;
10994 AddOpc = X86::VPADDDZrr;
10995 break;
10996 }
10997 // Create vpmaddwd.
10998 const TargetRegisterClass *RC =
10999 RegInfo.getRegClass(Reg: Root.getOperand(i: 0).getReg());
11000 Register NewReg = RegInfo.createVirtualRegister(RegClass: RC);
11001 MachineInstr *Madd = Root.getMF()->CloneMachineInstr(Orig: &Root);
11002 Madd->setDesc(TII.get(Opcode: MaddOpc));
11003 Madd->untieRegOperand(OpIdx: 1);
11004 Madd->removeOperand(OpNo: 1);
11005 Madd->getOperand(i: 0).setReg(NewReg);
11006 InstrIdxForVirtReg.insert(KV: std::make_pair(x&: NewReg, y: 0));
11007 // Create vpaddd.
11008 Register DstReg = Root.getOperand(i: 0).getReg();
11009 bool IsKill = Root.getOperand(i: 1).isKill();
11010 MachineInstr *Add =
11011 BuildMI(MF&: *MF, MIMD: MIMetadata(Root), MCID: TII.get(Opcode: AddOpc), DestReg: DstReg)
11012 .addReg(RegNo: Root.getOperand(i: 1).getReg(), Flags: getKillRegState(B: IsKill))
11013 .addReg(RegNo: Madd->getOperand(i: 0).getReg(), Flags: getKillRegState(B: true));
11014 InsInstrs.push_back(Elt: Madd);
11015 InsInstrs.push_back(Elt: Add);
11016 DelInstrs.push_back(Elt: &Root);
11017}
11018
11019void X86InstrInfo::genAlternativeCodeSequence(
11020 MachineInstr &Root, unsigned Pattern,
11021 SmallVectorImpl<MachineInstr *> &InsInstrs,
11022 SmallVectorImpl<MachineInstr *> &DelInstrs,
11023 DenseMap<Register, unsigned> &InstrIdxForVirtReg) const {
11024 switch (Pattern) {
11025 default:
11026 // Reassociate instructions.
11027 TargetInstrInfo::genAlternativeCodeSequence(Root, Pattern, InsInstrs,
11028 DelInstrs, InstIdxForVirtReg&: InstrIdxForVirtReg);
11029 return;
11030 case X86MachineCombinerPattern::DPWSSD:
11031 genAlternativeDpCodeSequence(Root, TII: *this, InsInstrs, DelInstrs,
11032 InstrIdxForVirtReg);
11033 return;
11034 }
11035}
11036
11037// See also: X86DAGToDAGISel::SelectInlineAsmMemoryOperand().
11038void X86InstrInfo::getFrameIndexOperands(SmallVectorImpl<MachineOperand> &Ops,
11039 int FI) const {
11040 X86AddressMode M;
11041 M.BaseType = X86AddressMode::FrameIndexBase;
11042 M.Base.FrameIndex = FI;
11043 M.getFullAddress(MO&: Ops);
11044}
11045
11046MachineInstr *
11047X86InstrInfo::insertCodePrefetchInstr(MachineBasicBlock &MBB,
11048 MachineBasicBlock::iterator InsertBefore,
11049 const GlobalValue *GV) const {
11050 MachineFunction &MF = *MBB.getParent();
11051 MachineInstr *PrefetchInstr = MF.CreateMachineInstr(
11052 MCID: get(Opcode: X86::PREFETCHIT1),
11053 DL: InsertBefore == MBB.instr_end() ? MBB.findPrevDebugLoc(MBBI: InsertBefore)
11054 : InsertBefore->getDebugLoc(),
11055 NoImplicit: true);
11056 MachineInstrBuilder MIB(MF, PrefetchInstr);
11057 MIB.addMemOperand(MMO: MF.getMachineMemOperand(PtrInfo: MachinePointerInfo(GV),
11058 F: MachineMemOperand::MOLoad, /*s=*/Size: 8,
11059 /*base_alignment=*/BaseAlignment: llvm::Align(1)));
11060 MIB.addReg(RegNo: X86::RIP).addImm(Val: 1).addReg(RegNo: X86::NoRegister);
11061 MIB.addGlobalAddress(GV);
11062 MIB.addReg(RegNo: X86::NoRegister);
11063 MBB.insert(I: InsertBefore, MI: PrefetchInstr);
11064 return PrefetchInstr;
11065}
11066
11067#define GET_INSTRINFO_HELPERS
11068#include "X86GenInstrInfo.inc"
11069