1//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations -===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// This pass is added to suppress APX features for relocations. It's used to
11/// keep backward compatibility with old version of linker having no APX
12/// support. It can be removed after APX support is included in the default
13/// linker on OS.
14///
15//===----------------------------------------------------------------------===//
16
17#include "X86.h"
18#include "X86InstrInfo.h"
19#include "X86RegisterInfo.h"
20#include "X86Subtarget.h"
21
22#include "llvm/CodeGen/MachineFunctionPass.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/CodeGen/MachineOperand.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/Passes.h"
27#include "llvm/CodeGen/RegisterClassInfo.h"
28#include "llvm/CodeGen/TargetRegisterInfo.h"
29#include "llvm/Support/ErrorHandling.h"
30
31using namespace llvm;
32
33#define DEBUG_TYPE "x86-suppress-apx-for-relocation"
34
35cl::opt<bool> X86EnableAPXForRelocation(
36 "x86-enable-apx-for-relocation",
37 cl::desc("Enable APX features (EGPR, NDD and NF) for instructions with "
38 "relocations on x86-64 ELF"),
39 cl::init(Val: false));
40
41namespace {
42class X86SuppressAPXForRelocationLegacy : public MachineFunctionPass {
43public:
44 X86SuppressAPXForRelocationLegacy() : MachineFunctionPass(ID) {}
45
46 StringRef getPassName() const override {
47 return "X86 Suppress APX features for relocation";
48 }
49
50 bool runOnMachineFunction(MachineFunction &MF) override;
51
52 void getAnalysisUsage(AnalysisUsage &AU) const override {
53 AU.addPreserved<MachineRegisterClassInfoWrapperPass>();
54 MachineFunctionPass::getAnalysisUsage(AU);
55 }
56
57 static char ID;
58};
59} // namespace
60
61char X86SuppressAPXForRelocationLegacy::ID = 0;
62
63INITIALIZE_PASS_BEGIN(X86SuppressAPXForRelocationLegacy, DEBUG_TYPE,
64 "X86 Suppress APX features for relocation", false, false)
65INITIALIZE_PASS_END(X86SuppressAPXForRelocationLegacy, DEBUG_TYPE,
66 "X86 Suppress APX features for relocation", false, false)
67
68FunctionPass *llvm::createX86SuppressAPXForRelocationLegacyPass() {
69 return new X86SuppressAPXForRelocationLegacy();
70}
71
72static void suppressEGPRRegClass(MachineRegisterInfo *MRI, MachineInstr &MI,
73 const X86Subtarget &ST, unsigned int OpNum) {
74 Register Reg = MI.getOperand(i: OpNum).getReg();
75 if (!Reg.isVirtual()) {
76 assert(!X86II::isApxExtendedReg(Reg) && "APX EGPR is used unexpectedly.");
77 return;
78 }
79 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
80 const X86RegisterInfo *RI = ST.getRegisterInfo();
81 const TargetRegisterClass *NewRC = RI->constrainRegClassToNonRex2(RC);
82 MRI->setRegClass(Reg, RC: NewRC);
83}
84
85// Suppress EGPR in operand 0 of uses to avoid APX relocation types emitted. The
86// register in operand 0 of instruction with relocation may be replaced with
87// operand 0 of uses which may be EGPR. That may lead to emit APX relocation
88// types which breaks the backward compatibility with builtin linkers on
89// existing OS. For example, the register in operand 0 of instruction with
90// relocation is used in PHI instruction, and it may be replaced with operand 0
91// of PHI instruction after PHI elimination and Machine Copy Propagation pass.
92static void suppressEGPRRegClassInRegAndUses(MachineRegisterInfo *MRI,
93 MachineInstr &MI,
94 const X86Subtarget &ST,
95 unsigned int OpNum) {
96 suppressEGPRRegClass(MRI, MI, ST, OpNum);
97 Register Reg = MI.getOperand(i: OpNum).getReg();
98 for (MachineInstr &Use : MRI->use_instructions(Reg))
99 if (Use.getOpcode() == X86::PHI)
100 suppressEGPRRegClass(MRI, MI&: Use, ST, OpNum: 0);
101}
102
103static bool handleInstructionWithEGPR(MachineFunction &MF,
104 const X86Subtarget &ST) {
105 if (!ST.hasEGPR())
106 return false;
107
108 MachineRegisterInfo *MRI = &MF.getRegInfo();
109 auto suppressEGPRInInstrWithReloc = [&](MachineInstr &MI,
110 ArrayRef<unsigned> OpNoArray) {
111 int MemOpNo = X86II::getMemoryOperandIdx(Desc: MI.getDesc());
112 assert(MemOpNo >= 0 && "Expected a memory operand");
113 const MachineOperand &MO = MI.getOperand(i: X86::AddrDisp + MemOpNo);
114 if (MO.getTargetFlags() == X86II::MO_GOTTPOFF ||
115 MO.getTargetFlags() == X86II::MO_GOTPCREL) {
116 LLVM_DEBUG(dbgs() << "Transform instruction with relocation type:\n "
117 << MI);
118 for (unsigned OpNo : OpNoArray)
119 suppressEGPRRegClassInRegAndUses(MRI, MI, ST, OpNum: OpNo);
120 LLVM_DEBUG(dbgs() << "to:\n " << MI << "\n");
121 }
122 };
123
124 for (MachineBasicBlock &MBB : MF) {
125 for (MachineInstr &MI : MBB) {
126 unsigned Opcode = MI.getOpcode();
127 switch (Opcode) {
128 // For GOTPC32_TLSDESC, it's emitted with physical register (EAX/RAX) in
129 // X86AsmPrinter::LowerTlsAddr, and there is no corresponding target
130 // flag for it, so we don't need to handle LEA64r with TLSDESC and EGPR
131 // in this pass (before emitting assembly).
132 case X86::TEST32mr:
133 case X86::TEST64mr: {
134 suppressEGPRInInstrWithReloc(MI, {5});
135 break;
136 }
137 case X86::CMP32rm:
138 case X86::CMP64rm:
139 case X86::MOV32rm:
140 case X86::MOV64rm: {
141 suppressEGPRInInstrWithReloc(MI, {0});
142 break;
143 }
144 case X86::ADC32rm:
145 case X86::ADD32rm:
146 case X86::AND32rm:
147 case X86::OR32rm:
148 case X86::SBB32rm:
149 case X86::SUB32rm:
150 case X86::XOR32rm:
151 case X86::ADC64rm:
152 case X86::ADD64rm:
153 case X86::AND64rm:
154 case X86::OR64rm:
155 case X86::SBB64rm:
156 case X86::SUB64rm:
157 case X86::XOR64rm: {
158 suppressEGPRInInstrWithReloc(MI, {0, 1});
159 break;
160 }
161 }
162 }
163 }
164 return true;
165}
166
167static bool handleNDDOrNFInstructions(MachineFunction &MF,
168 const X86Subtarget &ST) {
169 if (!ST.hasNDD() && !ST.hasNF())
170 return false;
171
172 const X86InstrInfo *TII = ST.getInstrInfo();
173 MachineRegisterInfo *MRI = &MF.getRegInfo();
174 for (MachineBasicBlock &MBB : MF) {
175 for (MachineInstr &MI : llvm::make_early_inc_range(Range&: MBB)) {
176 unsigned Opcode = MI.getOpcode();
177 switch (Opcode) {
178 case X86::ADD64rm_NF:
179 case X86::ADD64mr_NF_ND:
180 case X86::ADD64rm_NF_ND: {
181 int MemOpNo = X86II::getMemoryOperandIdx(Desc: MI.getDesc());
182 assert(MemOpNo >= 0 && "Expected a memory operand");
183 const MachineOperand &MO = MI.getOperand(i: X86::AddrDisp + MemOpNo);
184 if (MO.getTargetFlags() == X86II::MO_GOTTPOFF)
185 llvm_unreachable("Unexpected NF instruction!");
186 break;
187 }
188 case X86::ADD64rm_ND: {
189 int MemOpNo = X86II::getMemoryOperandIdx(Desc: MI.getDesc());
190 assert(MemOpNo >= 0 && "Expected a memory operand");
191 const MachineOperand &MO = MI.getOperand(i: X86::AddrDisp + MemOpNo);
192 if (MO.getTargetFlags() == X86II::MO_GOTTPOFF ||
193 MO.getTargetFlags() == X86II::MO_GOTPCREL) {
194 LLVM_DEBUG(dbgs() << "Transform instruction with relocation type:\n "
195 << MI);
196 Register Reg = MRI->createVirtualRegister(RegClass: &X86::GR64_NOREX2RegClass);
197 [[maybe_unused]] MachineInstrBuilder CopyMIB =
198 BuildMI(BB&: MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: TargetOpcode::COPY),
199 DestReg: Reg)
200 .addReg(RegNo: MI.getOperand(i: 1).getReg());
201 MI.getOperand(i: 1).setReg(Reg);
202 const MCInstrDesc &NewDesc = TII->get(Opcode: X86::ADD64rm);
203 MI.setDesc(NewDesc);
204 suppressEGPRRegClassInRegAndUses(MRI, MI, ST, OpNum: 0);
205 MI.tieOperands(DefIdx: 0, UseIdx: 1);
206 LLVM_DEBUG(dbgs() << "to:\n " << *CopyMIB << "\n");
207 LLVM_DEBUG(dbgs() << " " << MI << "\n");
208 }
209 break;
210 }
211 case X86::ADD64mr_ND: {
212 int MemRefBegin = X86II::getMemoryOperandNo(TSFlags: MI.getDesc().TSFlags);
213 const MachineOperand &MO = MI.getOperand(i: MemRefBegin + X86::AddrDisp);
214 if (MO.getTargetFlags() == X86II::MO_GOTTPOFF) {
215 LLVM_DEBUG(dbgs() << "Transform instruction with relocation type:\n "
216 << MI);
217 suppressEGPRRegClassInRegAndUses(MRI, MI, ST, OpNum: 0);
218 Register Reg = MRI->createVirtualRegister(RegClass: &X86::GR64_NOREX2RegClass);
219 [[maybe_unused]] MachineInstrBuilder CopyMIB =
220 BuildMI(BB&: MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: TargetOpcode::COPY),
221 DestReg: Reg)
222 .addReg(RegNo: MI.getOperand(i: 6).getReg());
223 MachineInstrBuilder NewMIB =
224 BuildMI(BB&: MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: X86::ADD64rm),
225 DestReg: MI.getOperand(i: 0).getReg())
226 .addReg(RegNo: Reg)
227 .addReg(RegNo: MI.getOperand(i: 1).getReg())
228 .addImm(Val: MI.getOperand(i: 2).getImm())
229 .addReg(RegNo: MI.getOperand(i: 3).getReg())
230 .add(MO: MI.getOperand(i: 4))
231 .addReg(RegNo: MI.getOperand(i: 5).getReg());
232 MachineOperand *FlagDef =
233 MI.findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
234 if (FlagDef && FlagDef->isDead()) {
235 MachineOperand *NewFlagDef =
236 NewMIB->findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
237 if (NewFlagDef)
238 NewFlagDef->setIsDead();
239 }
240 MI.eraseFromParent();
241 LLVM_DEBUG(dbgs() << "to:\n " << *CopyMIB << "\n");
242 LLVM_DEBUG(dbgs() << " " << *NewMIB << "\n");
243 }
244 break;
245 }
246 }
247 }
248 }
249 return true;
250}
251
252static bool suppressAPXForRelocation(MachineFunction &MF) {
253 if (X86EnableAPXForRelocation)
254 return false;
255 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
256 bool Changed = handleInstructionWithEGPR(MF, ST);
257 Changed |= handleNDDOrNFInstructions(MF, ST);
258
259 return Changed;
260}
261
262bool X86SuppressAPXForRelocationLegacy::runOnMachineFunction(
263 MachineFunction &MF) {
264 return suppressAPXForRelocation(MF);
265}
266
267PreservedAnalyses
268X86SuppressAPXForRelocationPass::run(MachineFunction &MF,
269 MachineFunctionAnalysisManager &MFAM) {
270 return suppressAPXForRelocation(MF)
271 ? getMachineFunctionPassPreservedAnalyses()
272 .preserveSet<CFGAnalyses>()
273 : PreservedAnalyses::all();
274}
275