1//===- ARMFastISel.cpp - ARM FastISel implementation ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the ARM-specific support for the FastISel class. Some
10// of the target-specific code is generated by tablegen in the file
11// ARMGenFastISel.inc, which is #included here.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARM.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMCallingConv.h"
19#include "ARMConstantPoolValue.h"
20#include "ARMISelLowering.h"
21#include "ARMMachineFunctionInfo.h"
22#include "ARMSubtarget.h"
23#include "ARMTargetMachine.h"
24#include "MCTargetDesc/ARMAddressingModes.h"
25#include "MCTargetDesc/ARMBaseInfo.h"
26#include "Utils/ARMBaseInfo.h"
27#include "llvm/ADT/APFloat.h"
28#include "llvm/ADT/APInt.h"
29#include "llvm/ADT/DenseMap.h"
30#include "llvm/ADT/SmallVector.h"
31#include "llvm/CodeGen/CallingConvLower.h"
32#include "llvm/CodeGen/FastISel.h"
33#include "llvm/CodeGen/FunctionLoweringInfo.h"
34#include "llvm/CodeGen/ISDOpcodes.h"
35#include "llvm/CodeGen/MachineBasicBlock.h"
36#include "llvm/CodeGen/MachineConstantPool.h"
37#include "llvm/CodeGen/MachineFrameInfo.h"
38#include "llvm/CodeGen/MachineFunction.h"
39#include "llvm/CodeGen/MachineInstr.h"
40#include "llvm/CodeGen/MachineInstrBuilder.h"
41#include "llvm/CodeGen/MachineMemOperand.h"
42#include "llvm/CodeGen/MachineOperand.h"
43#include "llvm/CodeGen/MachineRegisterInfo.h"
44#include "llvm/CodeGen/TargetInstrInfo.h"
45#include "llvm/CodeGen/TargetLowering.h"
46#include "llvm/CodeGen/TargetOpcodes.h"
47#include "llvm/CodeGen/TargetRegisterInfo.h"
48#include "llvm/CodeGen/ValueTypes.h"
49#include "llvm/CodeGenTypes/MachineValueType.h"
50#include "llvm/IR/Argument.h"
51#include "llvm/IR/Attributes.h"
52#include "llvm/IR/CallingConv.h"
53#include "llvm/IR/Constant.h"
54#include "llvm/IR/Constants.h"
55#include "llvm/IR/DataLayout.h"
56#include "llvm/IR/DerivedTypes.h"
57#include "llvm/IR/Function.h"
58#include "llvm/IR/GetElementPtrTypeIterator.h"
59#include "llvm/IR/GlobalValue.h"
60#include "llvm/IR/GlobalVariable.h"
61#include "llvm/IR/InstrTypes.h"
62#include "llvm/IR/Instruction.h"
63#include "llvm/IR/Instructions.h"
64#include "llvm/IR/IntrinsicInst.h"
65#include "llvm/IR/Intrinsics.h"
66#include "llvm/IR/Module.h"
67#include "llvm/IR/Operator.h"
68#include "llvm/IR/Type.h"
69#include "llvm/IR/User.h"
70#include "llvm/IR/Value.h"
71#include "llvm/MC/MCInstrDesc.h"
72#include "llvm/Support/Casting.h"
73#include "llvm/Support/Compiler.h"
74#include "llvm/Support/ErrorHandling.h"
75#include "llvm/Support/MathExtras.h"
76#include "llvm/Target/TargetMachine.h"
77#include "llvm/Target/TargetOptions.h"
78#include <cassert>
79#include <cstdint>
80#include <utility>
81
82using namespace llvm;
83
84namespace {
85
86 // All possible address modes, plus some.
87class Address {
88public:
89 enum BaseKind { RegBase, FrameIndexBase };
90
91private:
92 BaseKind Kind = RegBase;
93 union {
94 unsigned Reg;
95 int FI;
96 } Base;
97
98 int Offset = 0;
99
100public:
101 // Innocuous defaults for our address.
102 Address() { Base.Reg = 0; }
103
104 void setKind(BaseKind K) { Kind = K; }
105 BaseKind getKind() const { return Kind; }
106 bool isRegBase() const { return Kind == RegBase; }
107 bool isFIBase() const { return Kind == FrameIndexBase; }
108
109 void setReg(Register Reg) {
110 assert(isRegBase() && "Invalid base register access!");
111 Base.Reg = Reg.id();
112 }
113
114 Register getReg() const {
115 assert(isRegBase() && "Invalid base register access!");
116 return Base.Reg;
117 }
118
119 void setFI(int FI) {
120 assert(isFIBase() && "Invalid base frame index access!");
121 Base.FI = FI;
122 }
123
124 int getFI() const {
125 assert(isFIBase() && "Invalid base frame index access!");
126 return Base.FI;
127 }
128
129 void setOffset(int O) { Offset = O; }
130 int getOffset() { return Offset; }
131};
132
133class ARMFastISel final : public FastISel {
134 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
135 /// make the right decision when generating code for different targets.
136 const ARMSubtarget *Subtarget;
137 Module &M;
138 const ARMBaseInstrInfo &TII;
139 const ARMTargetLowering &TLI;
140 const ARMBaseTargetMachine &TM;
141 ARMFunctionInfo *AFI;
142
143 // Convenience variables to avoid some queries.
144 bool isThumb2;
145 LLVMContext *Context;
146
147 public:
148 explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
149 const TargetLibraryInfo *libInfo,
150 const LibcallLoweringInfo *libcallLowering)
151 : FastISel(funcInfo, libInfo, libcallLowering),
152 Subtarget(&funcInfo.MF->getSubtarget<ARMSubtarget>()),
153 M(const_cast<Module &>(*funcInfo.Fn->getParent())),
154 TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()),
155 TM(TLI.getTM()) {
156 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
157 isThumb2 = AFI->isThumbFunction();
158 Context = &funcInfo.Fn->getContext();
159 }
160
161 private:
162 // Code from FastISel.cpp.
163
164 Register fastEmitInst_r(unsigned MachineInstOpcode,
165 const TargetRegisterClass *RC, Register Op0);
166 Register fastEmitInst_rr(unsigned MachineInstOpcode,
167 const TargetRegisterClass *RC, Register Op0,
168 Register Op1);
169 Register fastEmitInst_ri(unsigned MachineInstOpcode,
170 const TargetRegisterClass *RC, Register Op0,
171 uint64_t Imm);
172 Register fastEmitInst_i(unsigned MachineInstOpcode,
173 const TargetRegisterClass *RC, uint64_t Imm);
174
175 // Backend specific FastISel code.
176
177 bool fastSelectInstruction(const Instruction *I) override;
178 Register fastMaterializeConstant(const Constant *C) override;
179 Register fastMaterializeAlloca(const AllocaInst *AI) override;
180 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
181 const LoadInst *LI) override;
182 bool fastLowerArguments() override;
183
184#include "ARMGenFastISel.inc"
185
186 // Instruction selection routines.
187
188 bool SelectLoad(const Instruction *I);
189 bool SelectStore(const Instruction *I);
190 bool SelectBranch(const Instruction *I);
191 bool SelectIndirectBr(const Instruction *I);
192 bool SelectCmp(const Instruction *I);
193 bool SelectFPExt(const Instruction *I);
194 bool SelectFPTrunc(const Instruction *I);
195 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
196 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
197 bool SelectIToFP(const Instruction *I, bool isSigned);
198 bool SelectFPToI(const Instruction *I, bool isSigned);
199 bool SelectDiv(const Instruction *I, bool isSigned);
200 bool SelectRem(const Instruction *I, bool isSigned);
201 bool SelectCall(const Instruction *I, const char *IntrMemName);
202 bool SelectIntrinsicCall(const IntrinsicInst &I);
203 bool SelectSelect(const Instruction *I);
204 bool SelectRet(const Instruction *I);
205 bool SelectTrunc(const Instruction *I);
206 bool SelectIntExt(const Instruction *I);
207 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
208
209 // Utility routines.
210
211 bool isPositionIndependent() const;
212 bool isTypeLegal(Type *Ty, MVT &VT);
213 bool isLoadTypeLegal(Type *Ty, MVT &VT);
214 bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
215 bool isZExt);
216 bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
217 MaybeAlign Alignment = std::nullopt, bool isZExt = true,
218 bool allocReg = true);
219 bool ARMEmitStore(MVT VT, Register SrcReg, Address &Addr,
220 MaybeAlign Alignment = std::nullopt);
221 bool ARMComputeAddress(const Value *Obj, Address &Addr);
222 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
223 bool ARMIsMemCpySmall(uint64_t Len);
224 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
225 MaybeAlign Alignment);
226 Register ARMEmitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT, bool isZExt);
227 Register ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
228 Register ARMMaterializeInt(const Constant *C, MVT VT);
229 Register ARMMaterializeGV(const GlobalValue *GV, MVT VT);
230 Register ARMMoveToFPReg(MVT VT, Register SrcReg);
231 Register ARMMoveToIntReg(MVT VT, Register SrcReg);
232 unsigned ARMSelectCallOp(bool UseReg);
233 Register ARMLowerPICELF(const GlobalValue *GV, MVT VT);
234
235 const TargetLowering *getTargetLowering() { return &TLI; }
236
237 // Call handling routines.
238
239 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
240 bool Return,
241 bool isVarArg);
242 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
243 SmallVectorImpl<Register> &ArgRegs,
244 SmallVectorImpl<MVT> &ArgVTs,
245 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
246 SmallVectorImpl<Register> &RegArgs,
247 CallingConv::ID CC,
248 unsigned &NumBytes,
249 bool isVarArg);
250 Register getLibcallReg(const Twine &Name);
251 bool FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs,
252 const Instruction *I, CallingConv::ID CC,
253 unsigned &NumBytes, bool isVarArg);
254 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
255
256 // OptionalDef handling routines.
257
258 bool isARMNEONPred(const MachineInstr *MI);
259 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
260 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
261 void AddLoadStoreOperands(MVT VT, Address &Addr,
262 const MachineInstrBuilder &MIB,
263 MachineMemOperand::Flags Flags, bool useAM3);
264};
265
266} // end anonymous namespace
267
268// DefinesOptionalPredicate - This is different from DefinesPredicate in that
269// we don't care about implicit defs here, just places we'll need to add a
270// default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
271bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
272 if (!MI->hasOptionalDef())
273 return false;
274
275 // Look to see if our OptionalDef is defining CPSR or CCR.
276 for (const MachineOperand &MO : MI->operands()) {
277 if (!MO.isReg() || !MO.isDef()) continue;
278 if (MO.getReg() == ARM::CPSR)
279 *CPSR = true;
280 }
281 return true;
282}
283
284bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
285 const MCInstrDesc &MCID = MI->getDesc();
286
287 // If we're a thumb2 or not NEON function we'll be handled via isPredicable.
288 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
289 AFI->isThumb2Function())
290 return MI->isPredicable();
291
292 for (const MCOperandInfo &opInfo : MCID.operands())
293 if (opInfo.isPredicate())
294 return true;
295
296 return false;
297}
298
299// If the machine is predicable go ahead and add the predicate operands, if
300// it needs default CC operands add those.
301// TODO: If we want to support thumb1 then we'll need to deal with optional
302// CPSR defs that need to be added before the remaining operands. See s_cc_out
303// for descriptions why.
304const MachineInstrBuilder &
305ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
306 MachineInstr *MI = &*MIB;
307
308 // Do we use a predicate? or...
309 // Are we NEON in ARM mode and have a predicate operand? If so, I know
310 // we're not predicable but add it anyways.
311 if (isARMNEONPred(MI))
312 MIB.add(MOs: predOps(Pred: ARMCC::AL));
313
314 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
315 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
316 bool CPSR = false;
317 if (DefinesOptionalPredicate(MI, CPSR: &CPSR))
318 MIB.add(MO: CPSR ? t1CondCodeOp() : condCodeOp());
319 return MIB;
320}
321
322Register ARMFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
323 const TargetRegisterClass *RC,
324 Register Op0) {
325 Register ResultReg = createResultReg(RC);
326 const MCInstrDesc &II = TII.get(Opcode: MachineInstOpcode);
327
328 // Make sure the input operand is sufficiently constrained to be legal
329 // for this instruction.
330 Op0 = constrainOperandRegClass(II, Op: Op0, OpNum: 1);
331 if (II.getNumDefs() >= 1) {
332 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II,
333 DestReg: ResultReg).addReg(RegNo: Op0));
334 } else {
335 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II)
336 .addReg(RegNo: Op0));
337 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
338 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: ResultReg)
339 .addReg(RegNo: II.implicit_defs()[0]));
340 }
341 return ResultReg;
342}
343
344Register ARMFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
345 const TargetRegisterClass *RC,
346 Register Op0, Register Op1) {
347 Register ResultReg = createResultReg(RC);
348 const MCInstrDesc &II = TII.get(Opcode: MachineInstOpcode);
349
350 // Make sure the input operands are sufficiently constrained to be legal
351 // for this instruction.
352 Op0 = constrainOperandRegClass(II, Op: Op0, OpNum: 1);
353 Op1 = constrainOperandRegClass(II, Op: Op1, OpNum: 2);
354
355 if (II.getNumDefs() >= 1) {
356 AddOptionalDefs(
357 MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II, DestReg: ResultReg)
358 .addReg(RegNo: Op0)
359 .addReg(RegNo: Op1));
360 } else {
361 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II)
362 .addReg(RegNo: Op0)
363 .addReg(RegNo: Op1));
364 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
365 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: ResultReg)
366 .addReg(RegNo: II.implicit_defs()[0]));
367 }
368 return ResultReg;
369}
370
371Register ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
372 const TargetRegisterClass *RC,
373 Register Op0, uint64_t Imm) {
374 Register ResultReg = createResultReg(RC);
375 const MCInstrDesc &II = TII.get(Opcode: MachineInstOpcode);
376
377 // Make sure the input operand is sufficiently constrained to be legal
378 // for this instruction.
379 Op0 = constrainOperandRegClass(II, Op: Op0, OpNum: 1);
380 if (II.getNumDefs() >= 1) {
381 AddOptionalDefs(
382 MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II, DestReg: ResultReg)
383 .addReg(RegNo: Op0)
384 .addImm(Val: Imm));
385 } else {
386 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II)
387 .addReg(RegNo: Op0)
388 .addImm(Val: Imm));
389 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
390 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: ResultReg)
391 .addReg(RegNo: II.implicit_defs()[0]));
392 }
393 return ResultReg;
394}
395
396Register ARMFastISel::fastEmitInst_i(unsigned MachineInstOpcode,
397 const TargetRegisterClass *RC,
398 uint64_t Imm) {
399 Register ResultReg = createResultReg(RC);
400 const MCInstrDesc &II = TII.get(Opcode: MachineInstOpcode);
401
402 if (II.getNumDefs() >= 1) {
403 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II,
404 DestReg: ResultReg).addImm(Val: Imm));
405 } else {
406 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II)
407 .addImm(Val: Imm));
408 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
409 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: ResultReg)
410 .addReg(RegNo: II.implicit_defs()[0]));
411 }
412 return ResultReg;
413}
414
415// TODO: Don't worry about 64-bit now, but when this is fixed remove the
416// checks from the various callers.
417Register ARMFastISel::ARMMoveToFPReg(MVT VT, Register SrcReg) {
418 if (VT == MVT::f64)
419 return Register();
420
421 Register MoveReg = createResultReg(RC: TLI.getRegClassFor(VT));
422 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
423 MCID: TII.get(Opcode: ARM::VMOVSR), DestReg: MoveReg)
424 .addReg(RegNo: SrcReg));
425 return MoveReg;
426}
427
428Register ARMFastISel::ARMMoveToIntReg(MVT VT, Register SrcReg) {
429 if (VT == MVT::i64)
430 return Register();
431
432 Register MoveReg = createResultReg(RC: TLI.getRegClassFor(VT));
433 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
434 MCID: TII.get(Opcode: ARM::VMOVRS), DestReg: MoveReg)
435 .addReg(RegNo: SrcReg));
436 return MoveReg;
437}
438
439// For double width floating point we need to materialize two constants
440// (the high and the low) into integer registers then use a move to get
441// the combined constant into an FP reg.
442Register ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
443 const APFloat Val = CFP->getValueAPF();
444 bool is64bit = VT == MVT::f64;
445
446 // This checks to see if we can use VFP3 instructions to materialize
447 // a constant, otherwise we have to go through the constant pool.
448 if (TLI.isFPImmLegal(Imm: Val, VT)) {
449 int Imm;
450 unsigned Opc;
451 if (is64bit) {
452 Imm = ARM_AM::getFP64Imm(FPImm: Val);
453 Opc = ARM::FCONSTD;
454 } else {
455 Imm = ARM_AM::getFP32Imm(FPImm: Val);
456 Opc = ARM::FCONSTS;
457 }
458 Register DestReg = createResultReg(RC: TLI.getRegClassFor(VT));
459 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
460 MCID: TII.get(Opcode: Opc), DestReg).addImm(Val: Imm));
461 return DestReg;
462 }
463
464 // Require VFP2 for loading fp constants.
465 if (!Subtarget->hasVFP2Base()) return false;
466
467 // MachineConstantPool wants an explicit alignment.
468 Align Alignment = DL.getPrefTypeAlign(Ty: CFP->getType());
469 unsigned Idx = MCP.getConstantPoolIndex(C: cast<Constant>(Val: CFP), Alignment);
470 Register DestReg = createResultReg(RC: TLI.getRegClassFor(VT));
471 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
472
473 // The extra reg is for addrmode5.
474 AddOptionalDefs(
475 MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg)
476 .addConstantPoolIndex(Idx)
477 .addReg(RegNo: 0));
478 return DestReg;
479}
480
481Register ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
482 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
483 return Register();
484
485 // If we can do this in a single instruction without a constant pool entry
486 // do so now.
487 const ConstantInt *CI = cast<ConstantInt>(Val: C);
488 if (Subtarget->hasV6T2Ops() && isUInt<16>(x: CI->getZExtValue())) {
489 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
490 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
491 &ARM::GPRRegClass;
492 Register ImmReg = createResultReg(RC);
493 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
494 MCID: TII.get(Opcode: Opc), DestReg: ImmReg)
495 .addImm(Val: CI->getZExtValue()));
496 return ImmReg;
497 }
498
499 // Use MVN to emit negative constants.
500 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
501 unsigned Imm = (unsigned)~(CI->getSExtValue());
502 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Arg: Imm) != -1) :
503 (ARM_AM::getSOImmVal(Arg: Imm) != -1);
504 if (UseImm) {
505 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
506 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
507 &ARM::GPRRegClass;
508 Register ImmReg = createResultReg(RC);
509 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
510 MCID: TII.get(Opcode: Opc), DestReg: ImmReg)
511 .addImm(Val: Imm));
512 return ImmReg;
513 }
514 }
515
516 Register ResultReg;
517 if (Subtarget->useMovt())
518 ResultReg = fastEmit_i(VT, RetVT: VT, Opcode: ISD::Constant, imm0: CI->getZExtValue());
519
520 if (ResultReg)
521 return ResultReg;
522
523 // Load from constant pool. For now 32-bit only.
524 if (VT != MVT::i32)
525 return Register();
526
527 // MachineConstantPool wants an explicit alignment.
528 Align Alignment = DL.getPrefTypeAlign(Ty: C->getType());
529 unsigned Idx = MCP.getConstantPoolIndex(C, Alignment);
530 ResultReg = createResultReg(RC: TLI.getRegClassFor(VT));
531 if (isThumb2)
532 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
533 MCID: TII.get(Opcode: ARM::t2LDRpci), DestReg: ResultReg)
534 .addConstantPoolIndex(Idx));
535 else {
536 // The extra immediate is for addrmode2.
537 ResultReg = constrainOperandRegClass(II: TII.get(Opcode: ARM::LDRcp), Op: ResultReg, OpNum: 0);
538 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
539 MCID: TII.get(Opcode: ARM::LDRcp), DestReg: ResultReg)
540 .addConstantPoolIndex(Idx)
541 .addImm(Val: 0));
542 }
543 return ResultReg;
544}
545
546bool ARMFastISel::isPositionIndependent() const {
547 return TLI.isPositionIndependent();
548}
549
550Register ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
551 // For now 32-bit only.
552 if (VT != MVT::i32 || GV->isThreadLocal())
553 return Register();
554
555 // ROPI/RWPI not currently supported.
556 if (Subtarget->isROPI() || Subtarget->isRWPI())
557 return Register();
558
559 bool IsIndirect = Subtarget->isGVIndirectSymbol(GV);
560 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
561 : &ARM::GPRRegClass;
562 Register DestReg = createResultReg(RC);
563
564 // FastISel TLS support on non-MachO is broken, punt to SelectionDAG.
565 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(Val: GV);
566 bool IsThreadLocal = GVar && GVar->isThreadLocal();
567 if (!Subtarget->isTargetMachO() && IsThreadLocal)
568 return Register();
569
570 bool IsPositionIndependent = isPositionIndependent();
571 // Use movw+movt when possible, it avoids constant pool entries.
572 // Non-darwin targets only support static movt relocations in FastISel.
573 if (Subtarget->useMovt() &&
574 (Subtarget->isTargetMachO() || !IsPositionIndependent)) {
575 unsigned Opc;
576 unsigned char TF = 0;
577 if (Subtarget->isTargetMachO())
578 TF = ARMII::MO_NONLAZY;
579
580 if (IsPositionIndependent)
581 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
582 else
583 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
584 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
585 MCID: TII.get(Opcode: Opc), DestReg).addGlobalAddress(GV, Offset: 0, TargetFlags: TF));
586 } else {
587 // MachineConstantPool wants an explicit alignment.
588 Align Alignment = DL.getPrefTypeAlign(Ty: GV->getType());
589
590 if (Subtarget->isTargetELF() && IsPositionIndependent)
591 return ARMLowerPICELF(GV, VT);
592
593 // Grab index.
594 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
595 unsigned Id = AFI->createPICLabelUId();
596 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(C: GV, ID: Id,
597 Kind: ARMCP::CPValue,
598 PCAdj);
599 unsigned Idx = MCP.getConstantPoolIndex(V: CPV, Alignment);
600
601 // Load value.
602 MachineInstrBuilder MIB;
603 if (isThumb2) {
604 unsigned Opc = IsPositionIndependent ? ARM::t2LDRpci_pic : ARM::t2LDRpci;
605 MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc),
606 DestReg).addConstantPoolIndex(Idx);
607 if (IsPositionIndependent)
608 MIB.addImm(Val: Id);
609 AddOptionalDefs(MIB);
610 } else {
611 // The extra immediate is for addrmode2.
612 DestReg = constrainOperandRegClass(II: TII.get(Opcode: ARM::LDRcp), Op: DestReg, OpNum: 0);
613 MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
614 MCID: TII.get(Opcode: ARM::LDRcp), DestReg)
615 .addConstantPoolIndex(Idx)
616 .addImm(Val: 0);
617 AddOptionalDefs(MIB);
618
619 if (IsPositionIndependent) {
620 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
621 Register NewDestReg = createResultReg(RC: TLI.getRegClassFor(VT));
622
623 MachineInstrBuilder MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt,
624 MIMD, MCID: TII.get(Opcode: Opc), DestReg: NewDestReg)
625 .addReg(RegNo: DestReg)
626 .addImm(Val: Id);
627 AddOptionalDefs(MIB);
628 return NewDestReg;
629 }
630 }
631 }
632
633 if ((Subtarget->isTargetELF() && Subtarget->isGVInGOT(GV)) ||
634 (Subtarget->isTargetMachO() && IsIndirect)) {
635 MachineInstrBuilder MIB;
636 Register NewDestReg = createResultReg(RC: TLI.getRegClassFor(VT));
637 if (isThumb2)
638 MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
639 MCID: TII.get(Opcode: ARM::t2LDRi12), DestReg: NewDestReg)
640 .addReg(RegNo: DestReg)
641 .addImm(Val: 0);
642 else
643 MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
644 MCID: TII.get(Opcode: ARM::LDRi12), DestReg: NewDestReg)
645 .addReg(RegNo: DestReg)
646 .addImm(Val: 0);
647 DestReg = NewDestReg;
648 AddOptionalDefs(MIB);
649 }
650
651 return DestReg;
652}
653
654Register ARMFastISel::fastMaterializeConstant(const Constant *C) {
655 EVT CEVT = TLI.getValueType(DL, Ty: C->getType(), AllowUnknown: true);
656
657 // Only handle simple types.
658 if (!CEVT.isSimple())
659 return Register();
660 MVT VT = CEVT.getSimpleVT();
661
662 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Val: C))
663 return ARMMaterializeFP(CFP, VT);
664 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(Val: C))
665 return ARMMaterializeGV(GV, VT);
666 else if (isa<ConstantInt>(Val: C))
667 return ARMMaterializeInt(C, VT);
668
669 return Register();
670}
671
672// TODO: Register ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
673
674Register ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
675 // Don't handle dynamic allocas.
676 if (!FuncInfo.StaticAllocaMap.count(Val: AI))
677 return Register();
678
679 MVT VT;
680 if (!isLoadTypeLegal(Ty: AI->getType(), VT))
681 return Register();
682
683 DenseMap<const AllocaInst*, int>::iterator SI =
684 FuncInfo.StaticAllocaMap.find(Val: AI);
685
686 // This will get lowered later into the correct offsets and registers
687 // via rewriteXFrameIndex.
688 if (SI != FuncInfo.StaticAllocaMap.end()) {
689 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
690 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
691 Register ResultReg = createResultReg(RC);
692 ResultReg = constrainOperandRegClass(II: TII.get(Opcode: Opc), Op: ResultReg, OpNum: 0);
693
694 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
695 MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
696 .addFrameIndex(Idx: SI->second)
697 .addImm(Val: 0));
698 return ResultReg;
699 }
700
701 return Register();
702}
703
704bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
705 EVT evt = TLI.getValueType(DL, Ty, AllowUnknown: true);
706
707 // Only handle simple types.
708 if (evt == MVT::Other || !evt.isSimple()) return false;
709 VT = evt.getSimpleVT();
710
711 // Handle all legal types, i.e. a register that will directly hold this
712 // value.
713 return TLI.isTypeLegal(VT);
714}
715
716bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
717 if (isTypeLegal(Ty, VT)) return true;
718
719 // If this is a type than can be sign or zero-extended to a basic operation
720 // go ahead and accept it now.
721 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
722 return true;
723
724 return false;
725}
726
727// Computes the address to get to an object.
728bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
729 // Some boilerplate from the X86 FastISel.
730 const User *U = nullptr;
731 unsigned Opcode = Instruction::UserOp1;
732 if (const Instruction *I = dyn_cast<Instruction>(Val: Obj)) {
733 // Don't walk into other basic blocks unless the object is an alloca from
734 // another block, otherwise it may not have a virtual register assigned.
735 if (FuncInfo.StaticAllocaMap.count(Val: static_cast<const AllocaInst *>(Obj)) ||
736 FuncInfo.getMBB(BB: I->getParent()) == FuncInfo.MBB) {
737 Opcode = I->getOpcode();
738 U = I;
739 }
740 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Val: Obj)) {
741 Opcode = C->getOpcode();
742 U = C;
743 }
744
745 if (PointerType *Ty = dyn_cast<PointerType>(Val: Obj->getType()))
746 if (Ty->getAddressSpace() > 255)
747 // Fast instruction selection doesn't support the special
748 // address spaces.
749 return false;
750
751 switch (Opcode) {
752 default:
753 break;
754 case Instruction::BitCast:
755 // Look through bitcasts.
756 return ARMComputeAddress(Obj: U->getOperand(i: 0), Addr);
757 case Instruction::IntToPtr:
758 // Look past no-op inttoptrs.
759 if (TLI.getValueType(DL, Ty: U->getOperand(i: 0)->getType()) ==
760 TLI.getPointerTy(DL))
761 return ARMComputeAddress(Obj: U->getOperand(i: 0), Addr);
762 break;
763 case Instruction::PtrToInt:
764 // Look past no-op ptrtoints.
765 if (TLI.getValueType(DL, Ty: U->getType()) == TLI.getPointerTy(DL))
766 return ARMComputeAddress(Obj: U->getOperand(i: 0), Addr);
767 break;
768 case Instruction::GetElementPtr: {
769 Address SavedAddr = Addr;
770 int TmpOffset = Addr.getOffset();
771
772 // Iterate through the GEP folding the constants into offsets where
773 // we can.
774 gep_type_iterator GTI = gep_type_begin(GEP: U);
775 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
776 i != e; ++i, ++GTI) {
777 const Value *Op = *i;
778 if (StructType *STy = GTI.getStructTypeOrNull()) {
779 const StructLayout *SL = DL.getStructLayout(Ty: STy);
780 unsigned Idx = cast<ConstantInt>(Val: Op)->getZExtValue();
781 TmpOffset += SL->getElementOffset(Idx);
782 } else {
783 uint64_t S = GTI.getSequentialElementStride(DL);
784 while (true) {
785 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val: Op)) {
786 // Constant-offset addressing.
787 TmpOffset += CI->getSExtValue() * S;
788 break;
789 }
790 if (canFoldAddIntoGEP(GEP: U, Add: Op)) {
791 // A compatible add with a constant operand. Fold the constant.
792 ConstantInt *CI =
793 cast<ConstantInt>(Val: cast<AddOperator>(Val: Op)->getOperand(i_nocapture: 1));
794 TmpOffset += CI->getSExtValue() * S;
795 // Iterate on the other operand.
796 Op = cast<AddOperator>(Val: Op)->getOperand(i_nocapture: 0);
797 continue;
798 }
799 // Unsupported
800 goto unsupported_gep;
801 }
802 }
803 }
804
805 // Try to grab the base operand now.
806 Addr.setOffset(TmpOffset);
807 if (ARMComputeAddress(Obj: U->getOperand(i: 0), Addr)) return true;
808
809 // We failed, restore everything and try the other options.
810 Addr = SavedAddr;
811
812 unsupported_gep:
813 break;
814 }
815 case Instruction::Alloca: {
816 const AllocaInst *AI = cast<AllocaInst>(Val: Obj);
817 DenseMap<const AllocaInst*, int>::iterator SI =
818 FuncInfo.StaticAllocaMap.find(Val: AI);
819 if (SI != FuncInfo.StaticAllocaMap.end()) {
820 Addr.setKind(Address::FrameIndexBase);
821 Addr.setFI(SI->second);
822 return true;
823 }
824 break;
825 }
826 }
827
828 // Try to get this in a register if nothing else has worked.
829 if (!Addr.getReg())
830 Addr.setReg(getRegForValue(V: Obj));
831 return Addr.getReg();
832}
833
834void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
835 bool needsLowering = false;
836 switch (VT.SimpleTy) {
837 default: llvm_unreachable("Unhandled load/store type!");
838 case MVT::i1:
839 case MVT::i8:
840 case MVT::i16:
841 case MVT::i32:
842 if (!useAM3) {
843 // Integer loads/stores handle 12-bit offsets.
844 needsLowering = ((Addr.getOffset() & 0xfff) != Addr.getOffset());
845 // Handle negative offsets.
846 if (needsLowering && isThumb2)
847 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.getOffset() < 0 &&
848 Addr.getOffset() > -256);
849 } else {
850 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
851 needsLowering = (Addr.getOffset() > 255 || Addr.getOffset() < -255);
852 }
853 break;
854 case MVT::f32:
855 case MVT::f64:
856 // Floating point operands handle 8-bit offsets.
857 needsLowering = ((Addr.getOffset() & 0xff) != Addr.getOffset());
858 break;
859 }
860
861 // If this is a stack pointer and the offset needs to be simplified then
862 // put the alloca address into a register, set the base type back to
863 // register and continue. This should almost never happen.
864 if (needsLowering && Addr.isFIBase()) {
865 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
866 : &ARM::GPRRegClass;
867 Register ResultReg = createResultReg(RC);
868 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
869 AddOptionalDefs(
870 MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
871 .addFrameIndex(Idx: Addr.getFI())
872 .addImm(Val: 0));
873 Addr.setKind(Address::RegBase);
874 Addr.setReg(ResultReg);
875 }
876
877 // Since the offset is too large for the load/store instruction
878 // get the reg+offset into a register.
879 if (needsLowering) {
880 Addr.setReg(fastEmit_ri_(VT: MVT::i32, Opcode: ISD::ADD, Op0: Addr.getReg(),
881 Imm: Addr.getOffset(), ImmType: MVT::i32));
882 Addr.setOffset(0);
883 }
884}
885
886void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
887 const MachineInstrBuilder &MIB,
888 MachineMemOperand::Flags Flags,
889 bool useAM3) {
890 // addrmode5 output depends on the selection dag addressing dividing the
891 // offset by 4 that it then later multiplies. Do this here as well.
892 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
893 Addr.setOffset(Addr.getOffset() / 4);
894
895 // Frame base works a bit differently. Handle it separately.
896 if (Addr.isFIBase()) {
897 int FI = Addr.getFI();
898 int Offset = Addr.getOffset();
899 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
900 PtrInfo: MachinePointerInfo::getFixedStack(MF&: *FuncInfo.MF, FI, Offset), F: Flags,
901 Size: MFI.getObjectSize(ObjectIdx: FI), BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
902 // Now add the rest of the operands.
903 MIB.addFrameIndex(Idx: FI);
904
905 // ARM halfword load/stores and signed byte loads need an additional
906 // operand.
907 if (useAM3) {
908 int Imm = (Addr.getOffset() < 0) ? (0x100 | -Addr.getOffset())
909 : Addr.getOffset();
910 MIB.addReg(RegNo: 0);
911 MIB.addImm(Val: Imm);
912 } else {
913 MIB.addImm(Val: Addr.getOffset());
914 }
915 MIB.addMemOperand(MMO);
916 } else {
917 // Now add the rest of the operands.
918 MIB.addReg(RegNo: Addr.getReg());
919
920 // ARM halfword load/stores and signed byte loads need an additional
921 // operand.
922 if (useAM3) {
923 int Imm = (Addr.getOffset() < 0) ? (0x100 | -Addr.getOffset())
924 : Addr.getOffset();
925 MIB.addReg(RegNo: 0);
926 MIB.addImm(Val: Imm);
927 } else {
928 MIB.addImm(Val: Addr.getOffset());
929 }
930 }
931 AddOptionalDefs(MIB);
932}
933
934bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
935 MaybeAlign Alignment, bool isZExt,
936 bool allocReg) {
937 unsigned Opc;
938 bool useAM3 = false;
939 bool needVMOV = false;
940 const TargetRegisterClass *RC;
941 switch (VT.SimpleTy) {
942 // This is mostly going to be Neon/vector support.
943 default: return false;
944 case MVT::i1:
945 case MVT::i8:
946 if (isThumb2) {
947 if (Addr.getOffset() < 0 && Addr.getOffset() > -256 &&
948 Subtarget->hasV6T2Ops())
949 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
950 else
951 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
952 } else {
953 if (isZExt) {
954 Opc = ARM::LDRBi12;
955 } else {
956 Opc = ARM::LDRSB;
957 useAM3 = true;
958 }
959 }
960 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
961 break;
962 case MVT::i16:
963 if (Alignment && *Alignment < Align(2) &&
964 !Subtarget->allowsUnalignedMem())
965 return false;
966
967 if (isThumb2) {
968 if (Addr.getOffset() < 0 && Addr.getOffset() > -256 &&
969 Subtarget->hasV6T2Ops())
970 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
971 else
972 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
973 } else {
974 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
975 useAM3 = true;
976 }
977 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
978 break;
979 case MVT::i32:
980 if (Alignment && *Alignment < Align(4) &&
981 !Subtarget->allowsUnalignedMem())
982 return false;
983
984 if (isThumb2) {
985 if (Addr.getOffset() < 0 && Addr.getOffset() > -256 &&
986 Subtarget->hasV6T2Ops())
987 Opc = ARM::t2LDRi8;
988 else
989 Opc = ARM::t2LDRi12;
990 } else {
991 Opc = ARM::LDRi12;
992 }
993 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
994 break;
995 case MVT::f32:
996 if (!Subtarget->hasVFP2Base()) return false;
997 // Unaligned loads need special handling. Floats require word-alignment.
998 if (Alignment && *Alignment < Align(4)) {
999 needVMOV = true;
1000 VT = MVT::i32;
1001 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1002 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1003 } else {
1004 Opc = ARM::VLDRS;
1005 RC = TLI.getRegClassFor(VT);
1006 }
1007 break;
1008 case MVT::f64:
1009 // Can load and store double precision even without FeatureFP64
1010 if (!Subtarget->hasVFP2Base()) return false;
1011 // FIXME: Unaligned loads need special handling. Doublewords require
1012 // word-alignment.
1013 if (Alignment && *Alignment < Align(4))
1014 return false;
1015
1016 Opc = ARM::VLDRD;
1017 RC = TLI.getRegClassFor(VT);
1018 break;
1019 }
1020 // Simplify this down to something we can handle.
1021 ARMSimplifyAddress(Addr, VT, useAM3);
1022
1023 // Create the base instruction, then add the operands.
1024 if (allocReg)
1025 ResultReg = createResultReg(RC);
1026 assert(ResultReg.isVirtual() && "Expected an allocated virtual register.");
1027 MachineInstrBuilder MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1028 MCID: TII.get(Opcode: Opc), DestReg: ResultReg);
1029 AddLoadStoreOperands(VT, Addr, MIB, Flags: MachineMemOperand::MOLoad, useAM3);
1030
1031 // If we had an unaligned load of a float we've converted it to an regular
1032 // load. Now we must move from the GRP to the FP register.
1033 if (needVMOV) {
1034 Register MoveReg = createResultReg(RC: TLI.getRegClassFor(VT: MVT::f32));
1035 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1036 MCID: TII.get(Opcode: ARM::VMOVSR), DestReg: MoveReg)
1037 .addReg(RegNo: ResultReg));
1038 ResultReg = MoveReg;
1039 }
1040 return true;
1041}
1042
1043bool ARMFastISel::SelectLoad(const Instruction *I) {
1044 // Atomic loads need special handling.
1045 if (cast<LoadInst>(Val: I)->isAtomic())
1046 return false;
1047
1048 const Value *SV = I->getOperand(i: 0);
1049 if (TLI.supportSwiftError()) {
1050 // Swifterror values can come from either a function parameter with
1051 // swifterror attribute or an alloca with swifterror attribute.
1052 if (const Argument *Arg = dyn_cast<Argument>(Val: SV)) {
1053 if (Arg->hasSwiftErrorAttr())
1054 return false;
1055 }
1056
1057 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(Val: SV)) {
1058 if (Alloca->isSwiftError())
1059 return false;
1060 }
1061 }
1062
1063 // Verify we have a legal type before going any further.
1064 MVT VT;
1065 if (!isLoadTypeLegal(Ty: I->getType(), VT))
1066 return false;
1067
1068 // See if we can handle this address.
1069 Address Addr;
1070 if (!ARMComputeAddress(Obj: I->getOperand(i: 0), Addr)) return false;
1071
1072 Register ResultReg;
1073 if (!ARMEmitLoad(VT, ResultReg, Addr, Alignment: cast<LoadInst>(Val: I)->getAlign()))
1074 return false;
1075 updateValueMap(I, Reg: ResultReg);
1076 return true;
1077}
1078
1079bool ARMFastISel::ARMEmitStore(MVT VT, Register SrcReg, Address &Addr,
1080 MaybeAlign Alignment) {
1081 unsigned StrOpc;
1082 bool useAM3 = false;
1083 switch (VT.SimpleTy) {
1084 // This is mostly going to be Neon/vector support.
1085 default: return false;
1086 case MVT::i1: {
1087 Register Res = createResultReg(RC: isThumb2 ? &ARM::tGPRRegClass
1088 : &ARM::GPRRegClass);
1089 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1090 SrcReg = constrainOperandRegClass(II: TII.get(Opcode: Opc), Op: SrcReg, OpNum: 1);
1091 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1092 MCID: TII.get(Opcode: Opc), DestReg: Res)
1093 .addReg(RegNo: SrcReg).addImm(Val: 1));
1094 SrcReg = Res;
1095 [[fallthrough]];
1096 }
1097 case MVT::i8:
1098 if (isThumb2) {
1099 if (Addr.getOffset() < 0 && Addr.getOffset() > -256 &&
1100 Subtarget->hasV6T2Ops())
1101 StrOpc = ARM::t2STRBi8;
1102 else
1103 StrOpc = ARM::t2STRBi12;
1104 } else {
1105 StrOpc = ARM::STRBi12;
1106 }
1107 break;
1108 case MVT::i16:
1109 if (Alignment && *Alignment < Align(2) &&
1110 !Subtarget->allowsUnalignedMem())
1111 return false;
1112
1113 if (isThumb2) {
1114 if (Addr.getOffset() < 0 && Addr.getOffset() > -256 &&
1115 Subtarget->hasV6T2Ops())
1116 StrOpc = ARM::t2STRHi8;
1117 else
1118 StrOpc = ARM::t2STRHi12;
1119 } else {
1120 StrOpc = ARM::STRH;
1121 useAM3 = true;
1122 }
1123 break;
1124 case MVT::i32:
1125 if (Alignment && *Alignment < Align(4) &&
1126 !Subtarget->allowsUnalignedMem())
1127 return false;
1128
1129 if (isThumb2) {
1130 if (Addr.getOffset() < 0 && Addr.getOffset() > -256 &&
1131 Subtarget->hasV6T2Ops())
1132 StrOpc = ARM::t2STRi8;
1133 else
1134 StrOpc = ARM::t2STRi12;
1135 } else {
1136 StrOpc = ARM::STRi12;
1137 }
1138 break;
1139 case MVT::f32:
1140 if (!Subtarget->hasVFP2Base()) return false;
1141 // Unaligned stores need special handling. Floats require word-alignment.
1142 if (Alignment && *Alignment < Align(4)) {
1143 Register MoveReg = createResultReg(RC: TLI.getRegClassFor(VT: MVT::i32));
1144 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1145 MCID: TII.get(Opcode: ARM::VMOVRS), DestReg: MoveReg)
1146 .addReg(RegNo: SrcReg));
1147 SrcReg = MoveReg;
1148 VT = MVT::i32;
1149 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1150 } else {
1151 StrOpc = ARM::VSTRS;
1152 }
1153 break;
1154 case MVT::f64:
1155 // Can load and store double precision even without FeatureFP64
1156 if (!Subtarget->hasVFP2Base()) return false;
1157 // FIXME: Unaligned stores need special handling. Doublewords require
1158 // word-alignment.
1159 if (Alignment && *Alignment < Align(4))
1160 return false;
1161
1162 StrOpc = ARM::VSTRD;
1163 break;
1164 }
1165 // Simplify this down to something we can handle.
1166 ARMSimplifyAddress(Addr, VT, useAM3);
1167
1168 // Create the base instruction, then add the operands.
1169 SrcReg = constrainOperandRegClass(II: TII.get(Opcode: StrOpc), Op: SrcReg, OpNum: 0);
1170 MachineInstrBuilder MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1171 MCID: TII.get(Opcode: StrOpc))
1172 .addReg(RegNo: SrcReg);
1173 AddLoadStoreOperands(VT, Addr, MIB, Flags: MachineMemOperand::MOStore, useAM3);
1174 return true;
1175}
1176
1177bool ARMFastISel::SelectStore(const Instruction *I) {
1178 Value *Op0 = I->getOperand(i: 0);
1179 Register SrcReg;
1180
1181 // Atomic stores need special handling.
1182 if (cast<StoreInst>(Val: I)->isAtomic())
1183 return false;
1184
1185 const Value *PtrV = I->getOperand(i: 1);
1186 if (TLI.supportSwiftError()) {
1187 // Swifterror values can come from either a function parameter with
1188 // swifterror attribute or an alloca with swifterror attribute.
1189 if (const Argument *Arg = dyn_cast<Argument>(Val: PtrV)) {
1190 if (Arg->hasSwiftErrorAttr())
1191 return false;
1192 }
1193
1194 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(Val: PtrV)) {
1195 if (Alloca->isSwiftError())
1196 return false;
1197 }
1198 }
1199
1200 // Verify we have a legal type before going any further.
1201 MVT VT;
1202 if (!isLoadTypeLegal(Ty: I->getOperand(i: 0)->getType(), VT))
1203 return false;
1204
1205 // Get the value to be stored into a register.
1206 SrcReg = getRegForValue(V: Op0);
1207 if (!SrcReg)
1208 return false;
1209
1210 // See if we can handle this address.
1211 Address Addr;
1212 if (!ARMComputeAddress(Obj: I->getOperand(i: 1), Addr))
1213 return false;
1214
1215 if (!ARMEmitStore(VT, SrcReg, Addr, Alignment: cast<StoreInst>(Val: I)->getAlign()))
1216 return false;
1217 return true;
1218}
1219
1220static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1221 switch (Pred) {
1222 // Needs two compares...
1223 case CmpInst::FCMP_ONE:
1224 case CmpInst::FCMP_UEQ:
1225 default:
1226 // AL is our "false" for now. The other two need more compares.
1227 return ARMCC::AL;
1228 case CmpInst::ICMP_EQ:
1229 case CmpInst::FCMP_OEQ:
1230 return ARMCC::EQ;
1231 case CmpInst::ICMP_SGT:
1232 case CmpInst::FCMP_OGT:
1233 return ARMCC::GT;
1234 case CmpInst::ICMP_SGE:
1235 case CmpInst::FCMP_OGE:
1236 return ARMCC::GE;
1237 case CmpInst::ICMP_UGT:
1238 case CmpInst::FCMP_UGT:
1239 return ARMCC::HI;
1240 case CmpInst::FCMP_OLT:
1241 return ARMCC::MI;
1242 case CmpInst::ICMP_ULE:
1243 case CmpInst::FCMP_OLE:
1244 return ARMCC::LS;
1245 case CmpInst::FCMP_ORD:
1246 return ARMCC::VC;
1247 case CmpInst::FCMP_UNO:
1248 return ARMCC::VS;
1249 case CmpInst::FCMP_UGE:
1250 return ARMCC::PL;
1251 case CmpInst::ICMP_SLT:
1252 case CmpInst::FCMP_ULT:
1253 return ARMCC::LT;
1254 case CmpInst::ICMP_SLE:
1255 case CmpInst::FCMP_ULE:
1256 return ARMCC::LE;
1257 case CmpInst::FCMP_UNE:
1258 case CmpInst::ICMP_NE:
1259 return ARMCC::NE;
1260 case CmpInst::ICMP_UGE:
1261 return ARMCC::HS;
1262 case CmpInst::ICMP_ULT:
1263 return ARMCC::LO;
1264 }
1265}
1266
1267bool ARMFastISel::SelectBranch(const Instruction *I) {
1268 const BranchInst *BI = cast<BranchInst>(Val: I);
1269 MachineBasicBlock *TBB = FuncInfo.getMBB(BB: BI->getSuccessor(i: 0));
1270 MachineBasicBlock *FBB = FuncInfo.getMBB(BB: BI->getSuccessor(i: 1));
1271
1272 // Simple branch support.
1273
1274 // If we can, avoid recomputing the compare - redoing it could lead to wonky
1275 // behavior.
1276 if (const CmpInst *CI = dyn_cast<CmpInst>(Val: BI->getCondition())) {
1277 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1278 // Get the compare predicate.
1279 // Try to take advantage of fallthrough opportunities.
1280 CmpInst::Predicate Predicate = CI->getPredicate();
1281 if (FuncInfo.MBB->isLayoutSuccessor(MBB: TBB)) {
1282 std::swap(a&: TBB, b&: FBB);
1283 Predicate = CmpInst::getInversePredicate(pred: Predicate);
1284 }
1285
1286 ARMCC::CondCodes ARMPred = getComparePred(Pred: Predicate);
1287
1288 // We may not handle every CC for now.
1289 if (ARMPred == ARMCC::AL) return false;
1290
1291 // Emit the compare.
1292 if (!ARMEmitCmp(Src1Value: CI->getOperand(i_nocapture: 0), Src2Value: CI->getOperand(i_nocapture: 1), isZExt: CI->isUnsigned()))
1293 return false;
1294
1295 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1296 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: BrOpc))
1297 .addMBB(MBB: TBB).addImm(Val: ARMPred).addReg(RegNo: ARM::CPSR);
1298 finishCondBranch(BranchBB: BI->getParent(), TrueMBB: TBB, FalseMBB: FBB);
1299 return true;
1300 }
1301 } else if (TruncInst *TI = dyn_cast<TruncInst>(Val: BI->getCondition())) {
1302 MVT SourceVT;
1303 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1304 (isLoadTypeLegal(Ty: TI->getOperand(i_nocapture: 0)->getType(), VT&: SourceVT))) {
1305 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1306 Register OpReg = getRegForValue(V: TI->getOperand(i_nocapture: 0));
1307 OpReg = constrainOperandRegClass(II: TII.get(Opcode: TstOpc), Op: OpReg, OpNum: 0);
1308 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1309 MCID: TII.get(Opcode: TstOpc))
1310 .addReg(RegNo: OpReg).addImm(Val: 1));
1311
1312 unsigned CCMode = ARMCC::NE;
1313 if (FuncInfo.MBB->isLayoutSuccessor(MBB: TBB)) {
1314 std::swap(a&: TBB, b&: FBB);
1315 CCMode = ARMCC::EQ;
1316 }
1317
1318 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1319 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: BrOpc))
1320 .addMBB(MBB: TBB).addImm(Val: CCMode).addReg(RegNo: ARM::CPSR);
1321
1322 finishCondBranch(BranchBB: BI->getParent(), TrueMBB: TBB, FalseMBB: FBB);
1323 return true;
1324 }
1325 } else if (const ConstantInt *CI =
1326 dyn_cast<ConstantInt>(Val: BI->getCondition())) {
1327 uint64_t Imm = CI->getZExtValue();
1328 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1329 fastEmitBranch(MSucc: Target, DbgLoc: MIMD.getDL());
1330 return true;
1331 }
1332
1333 Register CmpReg = getRegForValue(V: BI->getCondition());
1334 if (!CmpReg)
1335 return false;
1336
1337 // We've been divorced from our compare! Our block was split, and
1338 // now our compare lives in a predecessor block. We musn't
1339 // re-compare here, as the children of the compare aren't guaranteed
1340 // live across the block boundary (we *could* check for this).
1341 // Regardless, the compare has been done in the predecessor block,
1342 // and it left a value for us in a virtual register. Ergo, we test
1343 // the one-bit value left in the virtual register.
1344 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1345 CmpReg = constrainOperandRegClass(II: TII.get(Opcode: TstOpc), Op: CmpReg, OpNum: 0);
1346 AddOptionalDefs(
1347 MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: TstOpc))
1348 .addReg(RegNo: CmpReg)
1349 .addImm(Val: 1));
1350
1351 unsigned CCMode = ARMCC::NE;
1352 if (FuncInfo.MBB->isLayoutSuccessor(MBB: TBB)) {
1353 std::swap(a&: TBB, b&: FBB);
1354 CCMode = ARMCC::EQ;
1355 }
1356
1357 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1358 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: BrOpc))
1359 .addMBB(MBB: TBB).addImm(Val: CCMode).addReg(RegNo: ARM::CPSR);
1360 finishCondBranch(BranchBB: BI->getParent(), TrueMBB: TBB, FalseMBB: FBB);
1361 return true;
1362}
1363
1364bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1365 Register AddrReg = getRegForValue(V: I->getOperand(i: 0));
1366 if (!AddrReg)
1367 return false;
1368
1369 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1370 assert(isThumb2 || Subtarget->hasV4TOps());
1371
1372 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1373 MCID: TII.get(Opcode: Opc)).addReg(RegNo: AddrReg));
1374
1375 const IndirectBrInst *IB = cast<IndirectBrInst>(Val: I);
1376 for (const BasicBlock *SuccBB : IB->successors())
1377 FuncInfo.MBB->addSuccessor(Succ: FuncInfo.getMBB(BB: SuccBB));
1378
1379 return true;
1380}
1381
1382bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1383 bool isZExt) {
1384 Type *Ty = Src1Value->getType();
1385 EVT SrcEVT = TLI.getValueType(DL, Ty, AllowUnknown: true);
1386 if (!SrcEVT.isSimple()) return false;
1387 MVT SrcVT = SrcEVT.getSimpleVT();
1388
1389 if (Ty->isFloatTy() && !Subtarget->hasVFP2Base())
1390 return false;
1391
1392 if (Ty->isDoubleTy() && (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()))
1393 return false;
1394
1395 // Check to see if the 2nd operand is a constant that we can encode directly
1396 // in the compare.
1397 int Imm = 0;
1398 bool UseImm = false;
1399 bool isNegativeImm = false;
1400 // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1401 // Thus, Src1Value may be a ConstantInt, but we're missing it.
1402 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Val: Src2Value)) {
1403 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1404 SrcVT == MVT::i1) {
1405 const APInt &CIVal = ConstInt->getValue();
1406 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1407 // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1408 // then a cmn, because there is no way to represent 2147483648 as a
1409 // signed 32-bit int.
1410 if (Imm < 0 && Imm != (int)0x80000000) {
1411 isNegativeImm = true;
1412 Imm = -Imm;
1413 }
1414 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Arg: Imm) != -1) :
1415 (ARM_AM::getSOImmVal(Arg: Imm) != -1);
1416 }
1417 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Val: Src2Value)) {
1418 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1419 if (ConstFP->isZero() && !ConstFP->isNegative())
1420 UseImm = true;
1421 }
1422
1423 unsigned CmpOpc;
1424 bool isICmp = true;
1425 bool needsExt = false;
1426 switch (SrcVT.SimpleTy) {
1427 default: return false;
1428 // TODO: Verify compares.
1429 case MVT::f32:
1430 isICmp = false;
1431 CmpOpc = UseImm ? ARM::VCMPZS : ARM::VCMPS;
1432 break;
1433 case MVT::f64:
1434 isICmp = false;
1435 CmpOpc = UseImm ? ARM::VCMPZD : ARM::VCMPD;
1436 break;
1437 case MVT::i1:
1438 case MVT::i8:
1439 case MVT::i16:
1440 needsExt = true;
1441 [[fallthrough]];
1442 case MVT::i32:
1443 if (isThumb2) {
1444 if (!UseImm)
1445 CmpOpc = ARM::t2CMPrr;
1446 else
1447 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1448 } else {
1449 if (!UseImm)
1450 CmpOpc = ARM::CMPrr;
1451 else
1452 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1453 }
1454 break;
1455 }
1456
1457 Register SrcReg1 = getRegForValue(V: Src1Value);
1458 if (!SrcReg1)
1459 return false;
1460
1461 Register SrcReg2;
1462 if (!UseImm) {
1463 SrcReg2 = getRegForValue(V: Src2Value);
1464 if (!SrcReg2)
1465 return false;
1466 }
1467
1468 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1469 if (needsExt) {
1470 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg: SrcReg1, DestVT: MVT::i32, isZExt);
1471 if (!SrcReg1)
1472 return false;
1473 if (!UseImm) {
1474 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg: SrcReg2, DestVT: MVT::i32, isZExt);
1475 if (!SrcReg2)
1476 return false;
1477 }
1478 }
1479
1480 const MCInstrDesc &II = TII.get(Opcode: CmpOpc);
1481 SrcReg1 = constrainOperandRegClass(II, Op: SrcReg1, OpNum: 0);
1482 if (!UseImm) {
1483 SrcReg2 = constrainOperandRegClass(II, Op: SrcReg2, OpNum: 1);
1484 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II)
1485 .addReg(RegNo: SrcReg1).addReg(RegNo: SrcReg2));
1486 } else {
1487 MachineInstrBuilder MIB;
1488 MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II)
1489 .addReg(RegNo: SrcReg1);
1490
1491 // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1492 if (isICmp)
1493 MIB.addImm(Val: Imm);
1494 AddOptionalDefs(MIB);
1495 }
1496
1497 // For floating point we need to move the result to a comparison register
1498 // that we can then use for branches.
1499 if (Ty->isFloatTy() || Ty->isDoubleTy())
1500 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1501 MCID: TII.get(Opcode: ARM::FMSTAT)));
1502 return true;
1503}
1504
1505bool ARMFastISel::SelectCmp(const Instruction *I) {
1506 const CmpInst *CI = cast<CmpInst>(Val: I);
1507
1508 // Get the compare predicate.
1509 ARMCC::CondCodes ARMPred = getComparePred(Pred: CI->getPredicate());
1510
1511 // We may not handle every CC for now.
1512 if (ARMPred == ARMCC::AL) return false;
1513
1514 // Emit the compare.
1515 if (!ARMEmitCmp(Src1Value: CI->getOperand(i_nocapture: 0), Src2Value: CI->getOperand(i_nocapture: 1), isZExt: CI->isUnsigned()))
1516 return false;
1517
1518 // Now set a register based on the comparison. Explicitly set the predicates
1519 // here.
1520 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1521 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
1522 : &ARM::GPRRegClass;
1523 Register DestReg = createResultReg(RC);
1524 Constant *Zero = ConstantInt::get(Ty: Type::getInt32Ty(C&: *Context), V: 0);
1525 Register ZeroReg = fastMaterializeConstant(C: Zero);
1526 // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1527 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: MovCCOpc), DestReg)
1528 .addReg(RegNo: ZeroReg).addImm(Val: 1)
1529 .addImm(Val: ARMPred).addReg(RegNo: ARM::CPSR);
1530
1531 updateValueMap(I, Reg: DestReg);
1532 return true;
1533}
1534
1535bool ARMFastISel::SelectFPExt(const Instruction *I) {
1536 // Make sure we have VFP and that we're extending float to double.
1537 if (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()) return false;
1538
1539 Value *V = I->getOperand(i: 0);
1540 if (!I->getType()->isDoubleTy() ||
1541 !V->getType()->isFloatTy()) return false;
1542
1543 Register Op = getRegForValue(V);
1544 if (!Op)
1545 return false;
1546
1547 Register Result = createResultReg(RC: &ARM::DPRRegClass);
1548 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1549 MCID: TII.get(Opcode: ARM::VCVTDS), DestReg: Result)
1550 .addReg(RegNo: Op));
1551 updateValueMap(I, Reg: Result);
1552 return true;
1553}
1554
1555bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1556 // Make sure we have VFP and that we're truncating double to float.
1557 if (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()) return false;
1558
1559 Value *V = I->getOperand(i: 0);
1560 if (!(I->getType()->isFloatTy() &&
1561 V->getType()->isDoubleTy())) return false;
1562
1563 Register Op = getRegForValue(V);
1564 if (!Op)
1565 return false;
1566
1567 Register Result = createResultReg(RC: &ARM::SPRRegClass);
1568 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1569 MCID: TII.get(Opcode: ARM::VCVTSD), DestReg: Result)
1570 .addReg(RegNo: Op));
1571 updateValueMap(I, Reg: Result);
1572 return true;
1573}
1574
1575bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1576 // Make sure we have VFP.
1577 if (!Subtarget->hasVFP2Base()) return false;
1578
1579 MVT DstVT;
1580 Type *Ty = I->getType();
1581 if (!isTypeLegal(Ty, VT&: DstVT))
1582 return false;
1583
1584 Value *Src = I->getOperand(i: 0);
1585 EVT SrcEVT = TLI.getValueType(DL, Ty: Src->getType(), AllowUnknown: true);
1586 if (!SrcEVT.isSimple())
1587 return false;
1588 MVT SrcVT = SrcEVT.getSimpleVT();
1589 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1590 return false;
1591
1592 Register SrcReg = getRegForValue(V: Src);
1593 if (!SrcReg)
1594 return false;
1595
1596 // Handle sign-extension.
1597 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1598 SrcReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT: MVT::i32,
1599 /*isZExt*/!isSigned);
1600 if (!SrcReg)
1601 return false;
1602 }
1603
1604 // The conversion routine works on fp-reg to fp-reg and the operand above
1605 // was an integer, move it to the fp registers if possible.
1606 Register FP = ARMMoveToFPReg(VT: MVT::f32, SrcReg);
1607 if (!FP)
1608 return false;
1609
1610 unsigned Opc;
1611 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1612 else if (Ty->isDoubleTy() && Subtarget->hasFP64())
1613 Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1614 else return false;
1615
1616 Register ResultReg = createResultReg(RC: TLI.getRegClassFor(VT: DstVT));
1617 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1618 MCID: TII.get(Opcode: Opc), DestReg: ResultReg).addReg(RegNo: FP));
1619 updateValueMap(I, Reg: ResultReg);
1620 return true;
1621}
1622
1623bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1624 // Make sure we have VFP.
1625 if (!Subtarget->hasVFP2Base()) return false;
1626
1627 MVT DstVT;
1628 Type *RetTy = I->getType();
1629 if (!isTypeLegal(Ty: RetTy, VT&: DstVT))
1630 return false;
1631
1632 Register Op = getRegForValue(V: I->getOperand(i: 0));
1633 if (!Op)
1634 return false;
1635
1636 unsigned Opc;
1637 Type *OpTy = I->getOperand(i: 0)->getType();
1638 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1639 else if (OpTy->isDoubleTy() && Subtarget->hasFP64())
1640 Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1641 else return false;
1642
1643 // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1644 Register ResultReg = createResultReg(RC: TLI.getRegClassFor(VT: MVT::f32));
1645 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1646 MCID: TII.get(Opcode: Opc), DestReg: ResultReg).addReg(RegNo: Op));
1647
1648 // This result needs to be in an integer register, but the conversion only
1649 // takes place in fp-regs.
1650 Register IntReg = ARMMoveToIntReg(VT: DstVT, SrcReg: ResultReg);
1651 if (!IntReg)
1652 return false;
1653
1654 updateValueMap(I, Reg: IntReg);
1655 return true;
1656}
1657
1658bool ARMFastISel::SelectSelect(const Instruction *I) {
1659 MVT VT;
1660 if (!isTypeLegal(Ty: I->getType(), VT))
1661 return false;
1662
1663 // Things need to be register sized for register moves.
1664 if (VT != MVT::i32) return false;
1665
1666 Register CondReg = getRegForValue(V: I->getOperand(i: 0));
1667 if (!CondReg)
1668 return false;
1669 Register Op1Reg = getRegForValue(V: I->getOperand(i: 1));
1670 if (!Op1Reg)
1671 return false;
1672
1673 // Check to see if we can use an immediate in the conditional move.
1674 int Imm = 0;
1675 bool UseImm = false;
1676 bool isNegativeImm = false;
1677 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Val: I->getOperand(i: 2))) {
1678 assert(VT == MVT::i32 && "Expecting an i32.");
1679 Imm = (int)ConstInt->getValue().getZExtValue();
1680 if (Imm < 0) {
1681 isNegativeImm = true;
1682 Imm = ~Imm;
1683 }
1684 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Arg: Imm) != -1) :
1685 (ARM_AM::getSOImmVal(Arg: Imm) != -1);
1686 }
1687
1688 Register Op2Reg;
1689 if (!UseImm) {
1690 Op2Reg = getRegForValue(V: I->getOperand(i: 2));
1691 if (!Op2Reg)
1692 return false;
1693 }
1694
1695 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1696 CondReg = constrainOperandRegClass(II: TII.get(Opcode: TstOpc), Op: CondReg, OpNum: 0);
1697 AddOptionalDefs(
1698 MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: TstOpc))
1699 .addReg(RegNo: CondReg)
1700 .addImm(Val: 1));
1701
1702 unsigned MovCCOpc;
1703 const TargetRegisterClass *RC;
1704 if (!UseImm) {
1705 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1706 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1707 } else {
1708 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1709 if (!isNegativeImm)
1710 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1711 else
1712 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1713 }
1714 Register ResultReg = createResultReg(RC);
1715 if (!UseImm) {
1716 Op2Reg = constrainOperandRegClass(II: TII.get(Opcode: MovCCOpc), Op: Op2Reg, OpNum: 1);
1717 Op1Reg = constrainOperandRegClass(II: TII.get(Opcode: MovCCOpc), Op: Op1Reg, OpNum: 2);
1718 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: MovCCOpc),
1719 DestReg: ResultReg)
1720 .addReg(RegNo: Op2Reg)
1721 .addReg(RegNo: Op1Reg)
1722 .addImm(Val: ARMCC::NE)
1723 .addReg(RegNo: ARM::CPSR);
1724 } else {
1725 Op1Reg = constrainOperandRegClass(II: TII.get(Opcode: MovCCOpc), Op: Op1Reg, OpNum: 1);
1726 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: MovCCOpc),
1727 DestReg: ResultReg)
1728 .addReg(RegNo: Op1Reg)
1729 .addImm(Val: Imm)
1730 .addImm(Val: ARMCC::EQ)
1731 .addReg(RegNo: ARM::CPSR);
1732 }
1733 updateValueMap(I, Reg: ResultReg);
1734 return true;
1735}
1736
1737bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1738 MVT VT;
1739 Type *Ty = I->getType();
1740 if (!isTypeLegal(Ty, VT))
1741 return false;
1742
1743 // If we have integer div support we should have selected this automagically.
1744 // In case we have a real miss go ahead and return false and we'll pick
1745 // it up later.
1746 if (Subtarget->hasDivideInThumbMode())
1747 return false;
1748
1749 // Otherwise emit a libcall.
1750 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1751 if (VT == MVT::i8)
1752 LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1753 else if (VT == MVT::i16)
1754 LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1755 else if (VT == MVT::i32)
1756 LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1757 else if (VT == MVT::i64)
1758 LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1759 else if (VT == MVT::i128)
1760 LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1761 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1762
1763 return ARMEmitLibcall(I, Call: LC);
1764}
1765
1766bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1767 MVT VT;
1768 Type *Ty = I->getType();
1769 if (!isTypeLegal(Ty, VT))
1770 return false;
1771
1772 // Many ABIs do not provide a libcall for standalone remainder, so we need to
1773 // use divrem (see the RTABI 4.3.1). Since FastISel can't handle non-double
1774 // multi-reg returns, we'll have to bail out.
1775 if (!TLI.hasStandaloneRem(VT)) {
1776 return false;
1777 }
1778
1779 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1780 if (VT == MVT::i8)
1781 LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1782 else if (VT == MVT::i16)
1783 LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1784 else if (VT == MVT::i32)
1785 LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1786 else if (VT == MVT::i64)
1787 LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1788 else if (VT == MVT::i128)
1789 LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1790 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1791
1792 return ARMEmitLibcall(I, Call: LC);
1793}
1794
1795bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1796 EVT DestVT = TLI.getValueType(DL, Ty: I->getType(), AllowUnknown: true);
1797
1798 // We can get here in the case when we have a binary operation on a non-legal
1799 // type and the target independent selector doesn't know how to handle it.
1800 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1801 return false;
1802
1803 unsigned Opc;
1804 switch (ISDOpcode) {
1805 default: return false;
1806 case ISD::ADD:
1807 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1808 break;
1809 case ISD::OR:
1810 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1811 break;
1812 case ISD::SUB:
1813 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1814 break;
1815 }
1816
1817 Register SrcReg1 = getRegForValue(V: I->getOperand(i: 0));
1818 if (!SrcReg1)
1819 return false;
1820
1821 // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1822 // in the instruction, rather then materializing the value in a register.
1823 Register SrcReg2 = getRegForValue(V: I->getOperand(i: 1));
1824 if (!SrcReg2)
1825 return false;
1826
1827 Register ResultReg = createResultReg(RC: &ARM::GPRnopcRegClass);
1828 SrcReg1 = constrainOperandRegClass(II: TII.get(Opcode: Opc), Op: SrcReg1, OpNum: 1);
1829 SrcReg2 = constrainOperandRegClass(II: TII.get(Opcode: Opc), Op: SrcReg2, OpNum: 2);
1830 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1831 MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
1832 .addReg(RegNo: SrcReg1).addReg(RegNo: SrcReg2));
1833 updateValueMap(I, Reg: ResultReg);
1834 return true;
1835}
1836
1837bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1838 EVT FPVT = TLI.getValueType(DL, Ty: I->getType(), AllowUnknown: true);
1839 if (!FPVT.isSimple()) return false;
1840 MVT VT = FPVT.getSimpleVT();
1841
1842 // FIXME: Support vector types where possible.
1843 if (VT.isVector())
1844 return false;
1845
1846 // We can get here in the case when we want to use NEON for our fp
1847 // operations, but can't figure out how to. Just use the vfp instructions
1848 // if we have them.
1849 // FIXME: It'd be nice to use NEON instructions.
1850 Type *Ty = I->getType();
1851 if (Ty->isFloatTy() && !Subtarget->hasVFP2Base())
1852 return false;
1853 if (Ty->isDoubleTy() && (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()))
1854 return false;
1855
1856 unsigned Opc;
1857 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1858 switch (ISDOpcode) {
1859 default: return false;
1860 case ISD::FADD:
1861 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1862 break;
1863 case ISD::FSUB:
1864 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1865 break;
1866 case ISD::FMUL:
1867 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1868 break;
1869 }
1870 Register Op1 = getRegForValue(V: I->getOperand(i: 0));
1871 if (!Op1)
1872 return false;
1873
1874 Register Op2 = getRegForValue(V: I->getOperand(i: 1));
1875 if (!Op2)
1876 return false;
1877
1878 Register ResultReg = createResultReg(RC: TLI.getRegClassFor(VT: VT.SimpleTy));
1879 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1880 MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
1881 .addReg(RegNo: Op1).addReg(RegNo: Op2));
1882 updateValueMap(I, Reg: ResultReg);
1883 return true;
1884}
1885
1886// Call Handling Code
1887
1888// This is largely taken directly from CCAssignFnForNode
1889// TODO: We may not support all of this.
1890CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1891 bool Return,
1892 bool isVarArg) {
1893 switch (CC) {
1894 default:
1895 report_fatal_error(reason: "Unsupported calling convention");
1896 case CallingConv::Fast:
1897 if (Subtarget->hasVFP2Base() && !isVarArg) {
1898 if (!TM.isAAPCS_ABI())
1899 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1900 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1901 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1902 }
1903 [[fallthrough]];
1904 case CallingConv::C:
1905 case CallingConv::CXX_FAST_TLS:
1906 // Use target triple & subtarget features to do actual dispatch.
1907 if (TM.isAAPCS_ABI()) {
1908 if (Subtarget->hasFPRegs() &&
1909 TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1910 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1911 else
1912 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1913 } else {
1914 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1915 }
1916 case CallingConv::ARM_AAPCS_VFP:
1917 case CallingConv::Swift:
1918 case CallingConv::SwiftTail:
1919 if (!isVarArg)
1920 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1921 // Fall through to soft float variant, variadic functions don't
1922 // use hard floating point ABI.
1923 [[fallthrough]];
1924 case CallingConv::ARM_AAPCS:
1925 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1926 case CallingConv::ARM_APCS:
1927 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1928 case CallingConv::GHC:
1929 if (Return)
1930 report_fatal_error(reason: "Can't return in GHC call convention");
1931 else
1932 return CC_ARM_APCS_GHC;
1933 case CallingConv::CFGuard_Check:
1934 return (Return ? RetCC_ARM_AAPCS : CC_ARM_Win32_CFGuard_Check);
1935 }
1936}
1937
1938bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1939 SmallVectorImpl<Register> &ArgRegs,
1940 SmallVectorImpl<MVT> &ArgVTs,
1941 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1942 SmallVectorImpl<Register> &RegArgs,
1943 CallingConv::ID CC,
1944 unsigned &NumBytes,
1945 bool isVarArg) {
1946 SmallVector<CCValAssign, 16> ArgLocs;
1947 SmallVector<Type *, 16> OrigTys;
1948 for (Value *Arg : Args)
1949 OrigTys.push_back(Elt: Arg->getType());
1950 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, ArgLocs, *Context);
1951 CCInfo.AnalyzeCallOperands(ArgVTs, Flags&: ArgFlags, OrigTys,
1952 Fn: CCAssignFnForCall(CC, Return: false, isVarArg));
1953
1954 // Check that we can handle all of the arguments. If we can't, then bail out
1955 // now before we add code to the MBB.
1956 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1957 CCValAssign &VA = ArgLocs[i];
1958 MVT ArgVT = ArgVTs[VA.getValNo()];
1959
1960 // We don't handle NEON/vector parameters yet.
1961 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1962 return false;
1963
1964 // Now copy/store arg to correct locations.
1965 if (VA.isRegLoc() && !VA.needsCustom()) {
1966 continue;
1967 } else if (VA.needsCustom()) {
1968 // TODO: We need custom lowering for vector (v2f64) args.
1969 if (VA.getLocVT() != MVT::f64 ||
1970 // TODO: Only handle register args for now.
1971 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1972 return false;
1973 } else {
1974 switch (ArgVT.SimpleTy) {
1975 default:
1976 return false;
1977 case MVT::i1:
1978 case MVT::i8:
1979 case MVT::i16:
1980 case MVT::i32:
1981 break;
1982 case MVT::f32:
1983 if (!Subtarget->hasVFP2Base())
1984 return false;
1985 break;
1986 case MVT::f64:
1987 if (!Subtarget->hasVFP2Base())
1988 return false;
1989 break;
1990 }
1991 }
1992 }
1993
1994 // At the point, we are able to handle the call's arguments in fast isel.
1995
1996 // Get a count of how many bytes are to be pushed on the stack.
1997 NumBytes = CCInfo.getStackSize();
1998
1999 // Issue CALLSEQ_START
2000 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
2001 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2002 MCID: TII.get(Opcode: AdjStackDown))
2003 .addImm(Val: NumBytes).addImm(Val: 0));
2004
2005 // Process the args.
2006 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2007 CCValAssign &VA = ArgLocs[i];
2008 const Value *ArgVal = Args[VA.getValNo()];
2009 Register Arg = ArgRegs[VA.getValNo()];
2010 MVT ArgVT = ArgVTs[VA.getValNo()];
2011
2012 assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
2013 "We don't handle NEON/vector parameters yet.");
2014
2015 // Handle arg promotion, etc.
2016 switch (VA.getLocInfo()) {
2017 case CCValAssign::Full: break;
2018 case CCValAssign::SExt: {
2019 MVT DestVT = VA.getLocVT();
2020 Arg = ARMEmitIntExt(SrcVT: ArgVT, SrcReg: Arg, DestVT, /*isZExt*/false);
2021 assert(Arg && "Failed to emit a sext");
2022 ArgVT = DestVT;
2023 break;
2024 }
2025 case CCValAssign::AExt:
2026 // Intentional fall-through. Handle AExt and ZExt.
2027 case CCValAssign::ZExt: {
2028 MVT DestVT = VA.getLocVT();
2029 Arg = ARMEmitIntExt(SrcVT: ArgVT, SrcReg: Arg, DestVT, /*isZExt*/true);
2030 assert(Arg && "Failed to emit a zext");
2031 ArgVT = DestVT;
2032 break;
2033 }
2034 case CCValAssign::BCvt: {
2035 Register BC = fastEmit_r(VT: ArgVT, RetVT: VA.getLocVT(), Opcode: ISD::BITCAST, Op0: Arg);
2036 assert(BC && "Failed to emit a bitcast!");
2037 Arg = BC;
2038 ArgVT = VA.getLocVT();
2039 break;
2040 }
2041 default: llvm_unreachable("Unknown arg promotion!");
2042 }
2043
2044 // Now copy/store arg to correct locations.
2045 if (VA.isRegLoc() && !VA.needsCustom()) {
2046 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2047 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: VA.getLocReg()).addReg(RegNo: Arg);
2048 RegArgs.push_back(Elt: VA.getLocReg());
2049 } else if (VA.needsCustom()) {
2050 // TODO: We need custom lowering for vector (v2f64) args.
2051 assert(VA.getLocVT() == MVT::f64 &&
2052 "Custom lowering for v2f64 args not available");
2053
2054 // FIXME: ArgLocs[++i] may extend beyond ArgLocs.size()
2055 CCValAssign &NextVA = ArgLocs[++i];
2056
2057 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2058 "We only handle register args!");
2059
2060 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2061 MCID: TII.get(Opcode: ARM::VMOVRRD), DestReg: VA.getLocReg())
2062 .addReg(RegNo: NextVA.getLocReg(), Flags: RegState::Define)
2063 .addReg(RegNo: Arg));
2064 RegArgs.push_back(Elt: VA.getLocReg());
2065 RegArgs.push_back(Elt: NextVA.getLocReg());
2066 } else {
2067 assert(VA.isMemLoc());
2068 // Need to store on the stack.
2069
2070 // Don't emit stores for undef values.
2071 if (isa<UndefValue>(Val: ArgVal))
2072 continue;
2073
2074 Address Addr;
2075 Addr.setKind(Address::RegBase);
2076 Addr.setReg(ARM::SP);
2077 Addr.setOffset(VA.getLocMemOffset());
2078
2079 bool EmitRet = ARMEmitStore(VT: ArgVT, SrcReg: Arg, Addr); (void)EmitRet;
2080 assert(EmitRet && "Could not emit a store for argument!");
2081 }
2082 }
2083
2084 return true;
2085}
2086
2087bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs,
2088 const Instruction *I, CallingConv::ID CC,
2089 unsigned &NumBytes, bool isVarArg) {
2090 // Issue CALLSEQ_END
2091 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2092 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2093 MCID: TII.get(Opcode: AdjStackUp))
2094 .addImm(Val: NumBytes).addImm(Val: -1ULL));
2095
2096 // Now the return value.
2097 if (RetVT != MVT::isVoid) {
2098 SmallVector<CCValAssign, 16> RVLocs;
2099 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2100 CCInfo.AnalyzeCallResult(VT: RetVT, OrigTy: I->getType(),
2101 Fn: CCAssignFnForCall(CC, Return: true, isVarArg));
2102
2103 // Copy all of the result registers out of their specified physreg.
2104 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2105 // For this move we copy into two registers and then move into the
2106 // double fp reg we want.
2107 MVT DestVT = RVLocs[0].getValVT();
2108 const TargetRegisterClass* DstRC = TLI.getRegClassFor(VT: DestVT);
2109 Register ResultReg = createResultReg(RC: DstRC);
2110 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2111 MCID: TII.get(Opcode: ARM::VMOVDRR), DestReg: ResultReg)
2112 .addReg(RegNo: RVLocs[0].getLocReg())
2113 .addReg(RegNo: RVLocs[1].getLocReg()));
2114
2115 UsedRegs.push_back(Elt: RVLocs[0].getLocReg());
2116 UsedRegs.push_back(Elt: RVLocs[1].getLocReg());
2117
2118 // Finally update the result.
2119 updateValueMap(I, Reg: ResultReg);
2120 } else {
2121 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2122 MVT CopyVT = RVLocs[0].getValVT();
2123
2124 // Special handling for extended integers.
2125 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2126 CopyVT = MVT::i32;
2127
2128 const TargetRegisterClass* DstRC = TLI.getRegClassFor(VT: CopyVT);
2129
2130 Register ResultReg = createResultReg(RC: DstRC);
2131 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2132 MCID: TII.get(Opcode: TargetOpcode::COPY),
2133 DestReg: ResultReg).addReg(RegNo: RVLocs[0].getLocReg());
2134 UsedRegs.push_back(Elt: RVLocs[0].getLocReg());
2135
2136 // Finally update the result.
2137 updateValueMap(I, Reg: ResultReg);
2138 }
2139 }
2140
2141 return true;
2142}
2143
2144bool ARMFastISel::SelectRet(const Instruction *I) {
2145 const ReturnInst *Ret = cast<ReturnInst>(Val: I);
2146 const Function &F = *I->getParent()->getParent();
2147 const bool IsCmseNSEntry = F.hasFnAttribute(Kind: "cmse_nonsecure_entry");
2148
2149 if (!FuncInfo.CanLowerReturn)
2150 return false;
2151
2152 if (TLI.supportSwiftError() &&
2153 F.getAttributes().hasAttrSomewhere(Kind: Attribute::SwiftError))
2154 return false;
2155
2156 if (TLI.supportSplitCSR(MF: FuncInfo.MF))
2157 return false;
2158
2159 // Build a list of return value registers.
2160 SmallVector<Register, 4> RetRegs;
2161
2162 CallingConv::ID CC = F.getCallingConv();
2163 if (Ret->getNumOperands() > 0) {
2164 SmallVector<ISD::OutputArg, 4> Outs;
2165 GetReturnInfo(CC, ReturnType: F.getReturnType(), attr: F.getAttributes(), Outs, TLI, DL);
2166
2167 // Analyze operands of the call, assigning locations to each operand.
2168 SmallVector<CCValAssign, 16> ValLocs;
2169 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
2170 CCInfo.AnalyzeReturn(Outs, Fn: CCAssignFnForCall(CC, Return: true /* is Ret */,
2171 isVarArg: F.isVarArg()));
2172
2173 const Value *RV = Ret->getOperand(i_nocapture: 0);
2174 Register Reg = getRegForValue(V: RV);
2175 if (!Reg)
2176 return false;
2177
2178 // Only handle a single return value for now.
2179 if (ValLocs.size() != 1)
2180 return false;
2181
2182 CCValAssign &VA = ValLocs[0];
2183
2184 // Don't bother handling odd stuff for now.
2185 if (VA.getLocInfo() != CCValAssign::Full)
2186 return false;
2187 // Only handle register returns for now.
2188 if (!VA.isRegLoc())
2189 return false;
2190
2191 Register SrcReg = Reg + VA.getValNo();
2192 EVT RVEVT = TLI.getValueType(DL, Ty: RV->getType());
2193 if (!RVEVT.isSimple()) return false;
2194 MVT RVVT = RVEVT.getSimpleVT();
2195 MVT DestVT = VA.getValVT();
2196 // Special handling for extended integers.
2197 if (RVVT != DestVT) {
2198 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2199 return false;
2200
2201 assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2202
2203 // Perform extension if flagged as either zext or sext. Otherwise, do
2204 // nothing.
2205 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2206 SrcReg = ARMEmitIntExt(SrcVT: RVVT, SrcReg, DestVT, isZExt: Outs[0].Flags.isZExt());
2207 if (!SrcReg)
2208 return false;
2209 }
2210 }
2211
2212 // Make the copy.
2213 Register DstReg = VA.getLocReg();
2214 const TargetRegisterClass* SrcRC = MRI.getRegClass(Reg: SrcReg);
2215 // Avoid a cross-class copy. This is very unlikely.
2216 if (!SrcRC->contains(Reg: DstReg))
2217 return false;
2218 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2219 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: DstReg).addReg(RegNo: SrcReg);
2220
2221 // Add register to return instruction.
2222 RetRegs.push_back(Elt: VA.getLocReg());
2223 }
2224
2225 unsigned RetOpc;
2226 if (IsCmseNSEntry)
2227 if (isThumb2)
2228 RetOpc = ARM::tBXNS_RET;
2229 else
2230 llvm_unreachable("CMSE not valid for non-Thumb targets");
2231 else
2232 RetOpc = Subtarget->getReturnOpcode();
2233
2234 MachineInstrBuilder MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2235 MCID: TII.get(Opcode: RetOpc));
2236 AddOptionalDefs(MIB);
2237 for (Register R : RetRegs)
2238 MIB.addReg(RegNo: R, Flags: RegState::Implicit);
2239 return true;
2240}
2241
2242unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2243 if (UseReg)
2244 return isThumb2 ? gettBLXrOpcode(MF: *MF) : getBLXOpcode(MF: *MF);
2245 else
2246 return isThumb2 ? ARM::tBL : ARM::BL;
2247}
2248
2249Register ARMFastISel::getLibcallReg(const Twine &Name) {
2250 // Manually compute the global's type to avoid building it when unnecessary.
2251 Type *GVTy = PointerType::get(C&: *Context, /*AS=*/AddressSpace: 0);
2252 EVT LCREVT = TLI.getValueType(DL, Ty: GVTy);
2253 if (!LCREVT.isSimple())
2254 return Register();
2255
2256 GlobalValue *GV = M.getNamedGlobal(Name: Name.str());
2257 if (!GV)
2258 GV = new GlobalVariable(M, Type::getInt32Ty(C&: *Context), false,
2259 GlobalValue::ExternalLinkage, nullptr, Name);
2260
2261 return ARMMaterializeGV(GV, VT: LCREVT.getSimpleVT());
2262}
2263
2264// A quick function that will emit a call for a named libcall in F with the
2265// vector of passed arguments for the Instruction in I. We can assume that we
2266// can emit a call for any libcall we can produce. This is an abridged version
2267// of the full call infrastructure since we won't need to worry about things
2268// like computed function pointers or strange arguments at call sites.
2269// TODO: Try to unify this and the normal call bits for ARM, then try to unify
2270// with X86.
2271bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2272 RTLIB::LibcallImpl LCImpl = LibcallLowering->getLibcallImpl(Call);
2273 if (LCImpl == RTLIB::Unsupported)
2274 return false;
2275
2276 // Handle *simple* calls for now.
2277 Type *RetTy = I->getType();
2278 MVT RetVT;
2279 if (RetTy->isVoidTy())
2280 RetVT = MVT::isVoid;
2281 else if (!isTypeLegal(Ty: RetTy, VT&: RetVT))
2282 return false;
2283
2284 CallingConv::ID CC = LibcallLowering->getLibcallImplCallingConv(Call: LCImpl);
2285
2286 // Can't handle non-double multi-reg retvals.
2287 if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2288 SmallVector<CCValAssign, 16> RVLocs;
2289 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
2290 CCInfo.AnalyzeCallResult(VT: RetVT, OrigTy: RetTy, Fn: CCAssignFnForCall(CC, Return: true, isVarArg: false));
2291 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2292 return false;
2293 }
2294
2295 // Set up the argument vectors.
2296 SmallVector<Value*, 8> Args;
2297 SmallVector<Register, 8> ArgRegs;
2298 SmallVector<MVT, 8> ArgVTs;
2299 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2300 Args.reserve(N: I->getNumOperands());
2301 ArgRegs.reserve(N: I->getNumOperands());
2302 ArgVTs.reserve(N: I->getNumOperands());
2303 ArgFlags.reserve(N: I->getNumOperands());
2304 for (Value *Op : I->operands()) {
2305 Register Arg = getRegForValue(V: Op);
2306 if (!Arg)
2307 return false;
2308
2309 Type *ArgTy = Op->getType();
2310 MVT ArgVT;
2311 if (!isTypeLegal(Ty: ArgTy, VT&: ArgVT)) return false;
2312
2313 ISD::ArgFlagsTy Flags;
2314 Flags.setOrigAlign(DL.getABITypeAlign(Ty: ArgTy));
2315
2316 Args.push_back(Elt: Op);
2317 ArgRegs.push_back(Elt: Arg);
2318 ArgVTs.push_back(Elt: ArgVT);
2319 ArgFlags.push_back(Elt: Flags);
2320 }
2321
2322 // Handle the arguments now that we've gotten them.
2323 SmallVector<Register, 4> RegArgs;
2324 unsigned NumBytes;
2325 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2326 RegArgs, CC, NumBytes, isVarArg: false))
2327 return false;
2328
2329 StringRef FuncName = RTLIB::RuntimeLibcallsInfo::getLibcallImplName(CallImpl: LCImpl);
2330
2331 Register CalleeReg;
2332 if (Subtarget->genLongCalls()) {
2333 CalleeReg = getLibcallReg(Name: FuncName);
2334 if (!CalleeReg)
2335 return false;
2336 }
2337
2338 // Issue the call.
2339 unsigned CallOpc = ARMSelectCallOp(UseReg: Subtarget->genLongCalls());
2340 MachineInstrBuilder MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt,
2341 MIMD, MCID: TII.get(Opcode: CallOpc));
2342 // BL / BLX don't take a predicate, but tBL / tBLX do.
2343 if (isThumb2)
2344 MIB.add(MOs: predOps(Pred: ARMCC::AL));
2345 if (Subtarget->genLongCalls()) {
2346 CalleeReg =
2347 constrainOperandRegClass(II: TII.get(Opcode: CallOpc), Op: CalleeReg, OpNum: isThumb2 ? 2 : 0);
2348 MIB.addReg(RegNo: CalleeReg);
2349 } else
2350 MIB.addExternalSymbol(FnName: FuncName.data());
2351
2352 // Add implicit physical register uses to the call.
2353 for (Register R : RegArgs)
2354 MIB.addReg(RegNo: R, Flags: RegState::Implicit);
2355
2356 // Add a register mask with the call-preserved registers.
2357 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2358 MIB.addRegMask(Mask: TRI.getCallPreservedMask(MF: *FuncInfo.MF, CC));
2359
2360 // Finish off the call including any return values.
2361 SmallVector<Register, 4> UsedRegs;
2362 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg: false)) return false;
2363
2364 // Set all unused physreg defs as dead.
2365 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2366
2367 return true;
2368}
2369
2370bool ARMFastISel::SelectCall(const Instruction *I,
2371 const char *IntrMemName = nullptr) {
2372 const CallInst *CI = cast<CallInst>(Val: I);
2373 const Value *Callee = CI->getCalledOperand();
2374
2375 // Can't handle inline asm.
2376 if (isa<InlineAsm>(Val: Callee)) return false;
2377
2378 // Allow SelectionDAG isel to handle tail calls.
2379 if (CI->isTailCall()) return false;
2380
2381 // Check the calling convention.
2382 CallingConv::ID CC = CI->getCallingConv();
2383
2384 // TODO: Avoid some calling conventions?
2385
2386 FunctionType *FTy = CI->getFunctionType();
2387 bool isVarArg = FTy->isVarArg();
2388
2389 // Handle *simple* calls for now.
2390 Type *RetTy = I->getType();
2391 MVT RetVT;
2392 if (RetTy->isVoidTy())
2393 RetVT = MVT::isVoid;
2394 else if (!isTypeLegal(Ty: RetTy, VT&: RetVT) && RetVT != MVT::i16 &&
2395 RetVT != MVT::i8 && RetVT != MVT::i1)
2396 return false;
2397
2398 // Can't handle non-double multi-reg retvals.
2399 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2400 RetVT != MVT::i16 && RetVT != MVT::i32) {
2401 SmallVector<CCValAssign, 16> RVLocs;
2402 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2403 CCInfo.AnalyzeCallResult(VT: RetVT, OrigTy: RetTy,
2404 Fn: CCAssignFnForCall(CC, Return: true, isVarArg));
2405 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2406 return false;
2407 }
2408
2409 // Set up the argument vectors.
2410 SmallVector<Value*, 8> Args;
2411 SmallVector<Register, 8> ArgRegs;
2412 SmallVector<MVT, 8> ArgVTs;
2413 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2414 unsigned arg_size = CI->arg_size();
2415 Args.reserve(N: arg_size);
2416 ArgRegs.reserve(N: arg_size);
2417 ArgVTs.reserve(N: arg_size);
2418 ArgFlags.reserve(N: arg_size);
2419 for (auto ArgI = CI->arg_begin(), ArgE = CI->arg_end(); ArgI != ArgE; ++ArgI) {
2420 // If we're lowering a memory intrinsic instead of a regular call, skip the
2421 // last argument, which shouldn't be passed to the underlying function.
2422 if (IntrMemName && ArgE - ArgI <= 1)
2423 break;
2424
2425 ISD::ArgFlagsTy Flags;
2426 unsigned ArgIdx = ArgI - CI->arg_begin();
2427 if (CI->paramHasAttr(ArgNo: ArgIdx, Kind: Attribute::SExt))
2428 Flags.setSExt();
2429 if (CI->paramHasAttr(ArgNo: ArgIdx, Kind: Attribute::ZExt))
2430 Flags.setZExt();
2431
2432 // FIXME: Only handle *easy* calls for now.
2433 if (CI->paramHasAttr(ArgNo: ArgIdx, Kind: Attribute::InReg) ||
2434 CI->paramHasAttr(ArgNo: ArgIdx, Kind: Attribute::StructRet) ||
2435 CI->paramHasAttr(ArgNo: ArgIdx, Kind: Attribute::SwiftSelf) ||
2436 CI->paramHasAttr(ArgNo: ArgIdx, Kind: Attribute::SwiftError) ||
2437 CI->paramHasAttr(ArgNo: ArgIdx, Kind: Attribute::Nest) ||
2438 CI->paramHasAttr(ArgNo: ArgIdx, Kind: Attribute::ByVal))
2439 return false;
2440
2441 Type *ArgTy = (*ArgI)->getType();
2442 MVT ArgVT;
2443 if (!isTypeLegal(Ty: ArgTy, VT&: ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2444 ArgVT != MVT::i1)
2445 return false;
2446
2447 Register Arg = getRegForValue(V: *ArgI);
2448 if (!Arg.isValid())
2449 return false;
2450
2451 Flags.setOrigAlign(DL.getABITypeAlign(Ty: ArgTy));
2452
2453 Args.push_back(Elt: *ArgI);
2454 ArgRegs.push_back(Elt: Arg);
2455 ArgVTs.push_back(Elt: ArgVT);
2456 ArgFlags.push_back(Elt: Flags);
2457 }
2458
2459 // Handle the arguments now that we've gotten them.
2460 SmallVector<Register, 4> RegArgs;
2461 unsigned NumBytes;
2462 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2463 RegArgs, CC, NumBytes, isVarArg))
2464 return false;
2465
2466 bool UseReg = false;
2467 const GlobalValue *GV = dyn_cast<GlobalValue>(Val: Callee);
2468 if (!GV || Subtarget->genLongCalls()) UseReg = true;
2469
2470 Register CalleeReg;
2471 if (UseReg) {
2472 if (IntrMemName)
2473 CalleeReg = getLibcallReg(Name: IntrMemName);
2474 else
2475 CalleeReg = getRegForValue(V: Callee);
2476
2477 if (!CalleeReg)
2478 return false;
2479 }
2480
2481 // Issue the call.
2482 unsigned CallOpc = ARMSelectCallOp(UseReg);
2483 MachineInstrBuilder MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt,
2484 MIMD, MCID: TII.get(Opcode: CallOpc));
2485
2486 // ARM calls don't take a predicate, but tBL / tBLX do.
2487 if(isThumb2)
2488 MIB.add(MOs: predOps(Pred: ARMCC::AL));
2489 if (UseReg) {
2490 CalleeReg =
2491 constrainOperandRegClass(II: TII.get(Opcode: CallOpc), Op: CalleeReg, OpNum: isThumb2 ? 2 : 0);
2492 MIB.addReg(RegNo: CalleeReg);
2493 } else if (!IntrMemName)
2494 MIB.addGlobalAddress(GV, Offset: 0, TargetFlags: 0);
2495 else
2496 MIB.addExternalSymbol(FnName: IntrMemName, TargetFlags: 0);
2497
2498 // Add implicit physical register uses to the call.
2499 for (Register R : RegArgs)
2500 MIB.addReg(RegNo: R, Flags: RegState::Implicit);
2501
2502 // Add a register mask with the call-preserved registers.
2503 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2504 MIB.addRegMask(Mask: TRI.getCallPreservedMask(MF: *FuncInfo.MF, CC));
2505
2506 // Finish off the call including any return values.
2507 SmallVector<Register, 4> UsedRegs;
2508 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2509 return false;
2510
2511 // Set all unused physreg defs as dead.
2512 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2513
2514 diagnoseDontCall(CI: *CI);
2515 return true;
2516}
2517
2518bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2519 return Len <= 16;
2520}
2521
2522bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
2523 MaybeAlign Alignment) {
2524 // Make sure we don't bloat code by inlining very large memcpy's.
2525 if (!ARMIsMemCpySmall(Len))
2526 return false;
2527
2528 while (Len) {
2529 MVT VT;
2530 if (!Alignment || *Alignment >= 4) {
2531 if (Len >= 4)
2532 VT = MVT::i32;
2533 else if (Len >= 2)
2534 VT = MVT::i16;
2535 else {
2536 assert(Len == 1 && "Expected a length of 1!");
2537 VT = MVT::i8;
2538 }
2539 } else {
2540 assert(Alignment && "Alignment is set in this branch");
2541 // Bound based on alignment.
2542 if (Len >= 2 && *Alignment == 2)
2543 VT = MVT::i16;
2544 else {
2545 VT = MVT::i8;
2546 }
2547 }
2548
2549 bool RV;
2550 Register ResultReg;
2551 RV = ARMEmitLoad(VT, ResultReg, Addr&: Src);
2552 assert(RV && "Should be able to handle this load.");
2553 RV = ARMEmitStore(VT, SrcReg: ResultReg, Addr&: Dest);
2554 assert(RV && "Should be able to handle this store.");
2555 (void)RV;
2556
2557 unsigned Size = VT.getSizeInBits()/8;
2558 Len -= Size;
2559 Dest.setOffset(Dest.getOffset() + Size);
2560 Src.setOffset(Src.getOffset() + Size);
2561 }
2562
2563 return true;
2564}
2565
2566bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2567 // FIXME: Handle more intrinsics.
2568 switch (I.getIntrinsicID()) {
2569 default: return false;
2570 case Intrinsic::frameaddress: {
2571 MachineFrameInfo &MFI = FuncInfo.MF->getFrameInfo();
2572 MFI.setFrameAddressIsTaken(true);
2573
2574 unsigned LdrOpc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
2575 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
2576 : &ARM::GPRRegClass;
2577
2578 const ARMBaseRegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2579 Register FramePtr = RegInfo->getFrameRegister(MF: *(FuncInfo.MF));
2580 Register SrcReg = FramePtr;
2581
2582 // Recursively load frame address
2583 // ldr r0 [fp]
2584 // ldr r0 [r0]
2585 // ldr r0 [r0]
2586 // ...
2587 Register DestReg;
2588 unsigned Depth = cast<ConstantInt>(Val: I.getOperand(i_nocapture: 0))->getZExtValue();
2589 while (Depth--) {
2590 DestReg = createResultReg(RC);
2591 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2592 MCID: TII.get(Opcode: LdrOpc), DestReg)
2593 .addReg(RegNo: SrcReg).addImm(Val: 0));
2594 SrcReg = DestReg;
2595 }
2596 updateValueMap(I: &I, Reg: SrcReg);
2597 return true;
2598 }
2599 case Intrinsic::memcpy:
2600 case Intrinsic::memmove: {
2601 const MemTransferInst &MTI = cast<MemTransferInst>(Val: I);
2602 // Don't handle volatile.
2603 if (MTI.isVolatile())
2604 return false;
2605
2606 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2607 // we would emit dead code because we don't currently handle memmoves.
2608 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2609 if (isa<ConstantInt>(Val: MTI.getLength()) && isMemCpy) {
2610 // Small memcpy's are common enough that we want to do them without a call
2611 // if possible.
2612 uint64_t Len = cast<ConstantInt>(Val: MTI.getLength())->getZExtValue();
2613 if (ARMIsMemCpySmall(Len)) {
2614 Address Dest, Src;
2615 if (!ARMComputeAddress(Obj: MTI.getRawDest(), Addr&: Dest) ||
2616 !ARMComputeAddress(Obj: MTI.getRawSource(), Addr&: Src))
2617 return false;
2618 MaybeAlign Alignment;
2619 if (MTI.getDestAlign() || MTI.getSourceAlign())
2620 Alignment = std::min(a: MTI.getDestAlign().valueOrOne(),
2621 b: MTI.getSourceAlign().valueOrOne());
2622 if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2623 return true;
2624 }
2625 }
2626
2627 if (!MTI.getLength()->getType()->isIntegerTy(Bitwidth: 32))
2628 return false;
2629
2630 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2631 return false;
2632
2633 const char *IntrMemName = isa<MemCpyInst>(Val: I) ? "memcpy" : "memmove";
2634 return SelectCall(I: &I, IntrMemName);
2635 }
2636 case Intrinsic::memset: {
2637 const MemSetInst &MSI = cast<MemSetInst>(Val: I);
2638 // Don't handle volatile.
2639 if (MSI.isVolatile())
2640 return false;
2641
2642 if (!MSI.getLength()->getType()->isIntegerTy(Bitwidth: 32))
2643 return false;
2644
2645 if (MSI.getDestAddressSpace() > 255)
2646 return false;
2647
2648 return SelectCall(I: &I, IntrMemName: "memset");
2649 }
2650 case Intrinsic::trap: {
2651 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2652 MCID: TII.get(Opcode: Subtarget->isThumb() ? ARM::tTRAP : ARM::TRAP));
2653 return true;
2654 }
2655 }
2656}
2657
2658bool ARMFastISel::SelectTrunc(const Instruction *I) {
2659 // The high bits for a type smaller than the register size are assumed to be
2660 // undefined.
2661 Value *Op = I->getOperand(i: 0);
2662
2663 EVT SrcVT, DestVT;
2664 SrcVT = TLI.getValueType(DL, Ty: Op->getType(), AllowUnknown: true);
2665 DestVT = TLI.getValueType(DL, Ty: I->getType(), AllowUnknown: true);
2666
2667 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2668 return false;
2669 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2670 return false;
2671
2672 Register SrcReg = getRegForValue(V: Op);
2673 if (!SrcReg) return false;
2674
2675 // Because the high bits are undefined, a truncate doesn't generate
2676 // any code.
2677 updateValueMap(I, Reg: SrcReg);
2678 return true;
2679}
2680
2681Register ARMFastISel::ARMEmitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT,
2682 bool isZExt) {
2683 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2684 return Register();
2685 if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1)
2686 return Register();
2687
2688 // Table of which combinations can be emitted as a single instruction,
2689 // and which will require two.
2690 static const uint8_t isSingleInstrTbl[3][2][2][2] = {
2691 // ARM Thumb
2692 // !hasV6Ops hasV6Ops !hasV6Ops hasV6Ops
2693 // ext: s z s z s z s z
2694 /* 1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } },
2695 /* 8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } },
2696 /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }
2697 };
2698
2699 // Target registers for:
2700 // - For ARM can never be PC.
2701 // - For 16-bit Thumb are restricted to lower 8 registers.
2702 // - For 32-bit Thumb are restricted to non-SP and non-PC.
2703 static const TargetRegisterClass *RCTbl[2][2] = {
2704 // Instructions: Two Single
2705 /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
2706 /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass }
2707 };
2708
2709 // Table governing the instruction(s) to be emitted.
2710 static const struct InstructionTable {
2711 uint32_t Opc : 16;
2712 uint32_t hasS : 1; // Some instructions have an S bit, always set it to 0.
2713 uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi.
2714 uint32_t Imm : 8; // All instructions have either a shift or a mask.
2715 } IT[2][2][3][2] = {
2716 { // Two instructions (first is left shift, second is in this table).
2717 { // ARM Opc S Shift Imm
2718 /* 1 bit sext */ { { .Opc: ARM::MOVsi , .hasS: 1, .Shift: ARM_AM::asr , .Imm: 31 },
2719 /* 1 bit zext */ { .Opc: ARM::MOVsi , .hasS: 1, .Shift: ARM_AM::lsr , .Imm: 31 } },
2720 /* 8 bit sext */ { { .Opc: ARM::MOVsi , .hasS: 1, .Shift: ARM_AM::asr , .Imm: 24 },
2721 /* 8 bit zext */ { .Opc: ARM::MOVsi , .hasS: 1, .Shift: ARM_AM::lsr , .Imm: 24 } },
2722 /* 16 bit sext */ { { .Opc: ARM::MOVsi , .hasS: 1, .Shift: ARM_AM::asr , .Imm: 16 },
2723 /* 16 bit zext */ { .Opc: ARM::MOVsi , .hasS: 1, .Shift: ARM_AM::lsr , .Imm: 16 } }
2724 },
2725 { // Thumb Opc S Shift Imm
2726 /* 1 bit sext */ { { .Opc: ARM::tASRri , .hasS: 0, .Shift: ARM_AM::no_shift, .Imm: 31 },
2727 /* 1 bit zext */ { .Opc: ARM::tLSRri , .hasS: 0, .Shift: ARM_AM::no_shift, .Imm: 31 } },
2728 /* 8 bit sext */ { { .Opc: ARM::tASRri , .hasS: 0, .Shift: ARM_AM::no_shift, .Imm: 24 },
2729 /* 8 bit zext */ { .Opc: ARM::tLSRri , .hasS: 0, .Shift: ARM_AM::no_shift, .Imm: 24 } },
2730 /* 16 bit sext */ { { .Opc: ARM::tASRri , .hasS: 0, .Shift: ARM_AM::no_shift, .Imm: 16 },
2731 /* 16 bit zext */ { .Opc: ARM::tLSRri , .hasS: 0, .Shift: ARM_AM::no_shift, .Imm: 16 } }
2732 }
2733 },
2734 { // Single instruction.
2735 { // ARM Opc S Shift Imm
2736 /* 1 bit sext */ { { .Opc: ARM::KILL , .hasS: 0, .Shift: ARM_AM::no_shift, .Imm: 0 },
2737 /* 1 bit zext */ { .Opc: ARM::ANDri , .hasS: 1, .Shift: ARM_AM::no_shift, .Imm: 1 } },
2738 /* 8 bit sext */ { { .Opc: ARM::SXTB , .hasS: 0, .Shift: ARM_AM::no_shift, .Imm: 0 },
2739 /* 8 bit zext */ { .Opc: ARM::ANDri , .hasS: 1, .Shift: ARM_AM::no_shift, .Imm: 255 } },
2740 /* 16 bit sext */ { { .Opc: ARM::SXTH , .hasS: 0, .Shift: ARM_AM::no_shift, .Imm: 0 },
2741 /* 16 bit zext */ { .Opc: ARM::UXTH , .hasS: 0, .Shift: ARM_AM::no_shift, .Imm: 0 } }
2742 },
2743 { // Thumb Opc S Shift Imm
2744 /* 1 bit sext */ { { .Opc: ARM::KILL , .hasS: 0, .Shift: ARM_AM::no_shift, .Imm: 0 },
2745 /* 1 bit zext */ { .Opc: ARM::t2ANDri, .hasS: 1, .Shift: ARM_AM::no_shift, .Imm: 1 } },
2746 /* 8 bit sext */ { { .Opc: ARM::t2SXTB , .hasS: 0, .Shift: ARM_AM::no_shift, .Imm: 0 },
2747 /* 8 bit zext */ { .Opc: ARM::t2ANDri, .hasS: 1, .Shift: ARM_AM::no_shift, .Imm: 255 } },
2748 /* 16 bit sext */ { { .Opc: ARM::t2SXTH , .hasS: 0, .Shift: ARM_AM::no_shift, .Imm: 0 },
2749 /* 16 bit zext */ { .Opc: ARM::t2UXTH , .hasS: 0, .Shift: ARM_AM::no_shift, .Imm: 0 } }
2750 }
2751 }
2752 };
2753
2754 unsigned SrcBits = SrcVT.getSizeInBits();
2755 unsigned DestBits = DestVT.getSizeInBits();
2756 (void) DestBits;
2757 assert((SrcBits < DestBits) && "can only extend to larger types");
2758 assert((DestBits == 32 || DestBits == 16 || DestBits == 8) &&
2759 "other sizes unimplemented");
2760 assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) &&
2761 "other sizes unimplemented");
2762
2763 bool hasV6Ops = Subtarget->hasV6Ops();
2764 unsigned Bitness = SrcBits / 8; // {1,8,16}=>{0,1,2}
2765 assert((Bitness < 3) && "sanity-check table bounds");
2766
2767 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2768 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
2769 const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2770 unsigned Opc = ITP->Opc;
2771 assert(ARM::KILL != Opc && "Invalid table entry");
2772 unsigned hasS = ITP->hasS;
2773 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2774 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2775 "only MOVsi has shift operand addressing mode");
2776 unsigned Imm = ITP->Imm;
2777
2778 // 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
2779 bool setsCPSR = &ARM::tGPRRegClass == RC;
2780 unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
2781 Register ResultReg;
2782 // MOVsi encodes shift and immediate in shift operand addressing mode.
2783 // The following condition has the same value when emitting two
2784 // instruction sequences: both are shifts.
2785 bool ImmIsSO = (Shift != ARM_AM::no_shift);
2786
2787 // Either one or two instructions are emitted.
2788 // They're always of the form:
2789 // dst = in OP imm
2790 // CPSR is set only by 16-bit Thumb instructions.
2791 // Predicate, if any, is AL.
2792 // S bit, if available, is always 0.
2793 // When two are emitted the first's result will feed as the second's input,
2794 // that value is then dead.
2795 unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2;
2796 for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) {
2797 ResultReg = createResultReg(RC);
2798 bool isLsl = (0 == Instr) && !isSingleInstr;
2799 unsigned Opcode = isLsl ? LSLOpc : Opc;
2800 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
2801 unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShOp: ShiftAM, Imm) : Imm;
2802 bool isKill = 1 == Instr;
2803 MachineInstrBuilder MIB = BuildMI(
2804 BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode), DestReg: ResultReg);
2805 if (setsCPSR)
2806 MIB.addReg(RegNo: ARM::CPSR, Flags: RegState::Define);
2807 SrcReg = constrainOperandRegClass(II: TII.get(Opcode), Op: SrcReg, OpNum: 1 + setsCPSR);
2808 MIB.addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill))
2809 .addImm(Val: ImmEnc)
2810 .add(MOs: predOps(Pred: ARMCC::AL));
2811 if (hasS)
2812 MIB.add(MO: condCodeOp());
2813 // Second instruction consumes the first's result.
2814 SrcReg = ResultReg;
2815 }
2816
2817 return ResultReg;
2818}
2819
2820bool ARMFastISel::SelectIntExt(const Instruction *I) {
2821 // On ARM, in general, integer casts don't involve legal types; this code
2822 // handles promotable integers.
2823 Type *DestTy = I->getType();
2824 Value *Src = I->getOperand(i: 0);
2825 Type *SrcTy = Src->getType();
2826
2827 bool isZExt = isa<ZExtInst>(Val: I);
2828 Register SrcReg = getRegForValue(V: Src);
2829 if (!SrcReg) return false;
2830
2831 EVT SrcEVT, DestEVT;
2832 SrcEVT = TLI.getValueType(DL, Ty: SrcTy, AllowUnknown: true);
2833 DestEVT = TLI.getValueType(DL, Ty: DestTy, AllowUnknown: true);
2834 if (!SrcEVT.isSimple()) return false;
2835 if (!DestEVT.isSimple()) return false;
2836
2837 MVT SrcVT = SrcEVT.getSimpleVT();
2838 MVT DestVT = DestEVT.getSimpleVT();
2839 Register ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2840 if (!ResultReg)
2841 return false;
2842 updateValueMap(I, Reg: ResultReg);
2843 return true;
2844}
2845
2846bool ARMFastISel::SelectShift(const Instruction *I,
2847 ARM_AM::ShiftOpc ShiftTy) {
2848 // We handle thumb2 mode by target independent selector
2849 // or SelectionDAG ISel.
2850 if (isThumb2)
2851 return false;
2852
2853 // Only handle i32 now.
2854 EVT DestVT = TLI.getValueType(DL, Ty: I->getType(), AllowUnknown: true);
2855 if (DestVT != MVT::i32)
2856 return false;
2857
2858 unsigned Opc = ARM::MOVsr;
2859 unsigned ShiftImm;
2860 Value *Src2Value = I->getOperand(i: 1);
2861 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val: Src2Value)) {
2862 ShiftImm = CI->getZExtValue();
2863
2864 // Fall back to selection DAG isel if the shift amount
2865 // is zero or greater than the width of the value type.
2866 if (ShiftImm == 0 || ShiftImm >=32)
2867 return false;
2868
2869 Opc = ARM::MOVsi;
2870 }
2871
2872 Value *Src1Value = I->getOperand(i: 0);
2873 Register Reg1 = getRegForValue(V: Src1Value);
2874 if (!Reg1)
2875 return false;
2876
2877 Register Reg2;
2878 if (Opc == ARM::MOVsr) {
2879 Reg2 = getRegForValue(V: Src2Value);
2880 if (!Reg2)
2881 return false;
2882 }
2883
2884 Register ResultReg = createResultReg(RC: &ARM::GPRnopcRegClass);
2885 if (!ResultReg)
2886 return false;
2887
2888 MachineInstrBuilder MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2889 MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
2890 .addReg(RegNo: Reg1);
2891
2892 if (Opc == ARM::MOVsi)
2893 MIB.addImm(Val: ARM_AM::getSORegOpc(ShOp: ShiftTy, Imm: ShiftImm));
2894 else if (Opc == ARM::MOVsr) {
2895 MIB.addReg(RegNo: Reg2);
2896 MIB.addImm(Val: ARM_AM::getSORegOpc(ShOp: ShiftTy, Imm: 0));
2897 }
2898
2899 AddOptionalDefs(MIB);
2900 updateValueMap(I, Reg: ResultReg);
2901 return true;
2902}
2903
2904// TODO: SoftFP support.
2905bool ARMFastISel::fastSelectInstruction(const Instruction *I) {
2906 switch (I->getOpcode()) {
2907 case Instruction::Load:
2908 return SelectLoad(I);
2909 case Instruction::Store:
2910 return SelectStore(I);
2911 case Instruction::Br:
2912 return SelectBranch(I);
2913 case Instruction::IndirectBr:
2914 return SelectIndirectBr(I);
2915 case Instruction::ICmp:
2916 case Instruction::FCmp:
2917 return SelectCmp(I);
2918 case Instruction::FPExt:
2919 return SelectFPExt(I);
2920 case Instruction::FPTrunc:
2921 return SelectFPTrunc(I);
2922 case Instruction::SIToFP:
2923 return SelectIToFP(I, /*isSigned*/ true);
2924 case Instruction::UIToFP:
2925 return SelectIToFP(I, /*isSigned*/ false);
2926 case Instruction::FPToSI:
2927 return SelectFPToI(I, /*isSigned*/ true);
2928 case Instruction::FPToUI:
2929 return SelectFPToI(I, /*isSigned*/ false);
2930 case Instruction::Add:
2931 return SelectBinaryIntOp(I, ISDOpcode: ISD::ADD);
2932 case Instruction::Or:
2933 return SelectBinaryIntOp(I, ISDOpcode: ISD::OR);
2934 case Instruction::Sub:
2935 return SelectBinaryIntOp(I, ISDOpcode: ISD::SUB);
2936 case Instruction::FAdd:
2937 return SelectBinaryFPOp(I, ISDOpcode: ISD::FADD);
2938 case Instruction::FSub:
2939 return SelectBinaryFPOp(I, ISDOpcode: ISD::FSUB);
2940 case Instruction::FMul:
2941 return SelectBinaryFPOp(I, ISDOpcode: ISD::FMUL);
2942 case Instruction::SDiv:
2943 return SelectDiv(I, /*isSigned*/ true);
2944 case Instruction::UDiv:
2945 return SelectDiv(I, /*isSigned*/ false);
2946 case Instruction::SRem:
2947 return SelectRem(I, /*isSigned*/ true);
2948 case Instruction::URem:
2949 return SelectRem(I, /*isSigned*/ false);
2950 case Instruction::Call:
2951 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(Val: I))
2952 return SelectIntrinsicCall(I: *II);
2953 return SelectCall(I);
2954 case Instruction::Select:
2955 return SelectSelect(I);
2956 case Instruction::Ret:
2957 return SelectRet(I);
2958 case Instruction::Trunc:
2959 return SelectTrunc(I);
2960 case Instruction::ZExt:
2961 case Instruction::SExt:
2962 return SelectIntExt(I);
2963 case Instruction::Shl:
2964 return SelectShift(I, ShiftTy: ARM_AM::lsl);
2965 case Instruction::LShr:
2966 return SelectShift(I, ShiftTy: ARM_AM::lsr);
2967 case Instruction::AShr:
2968 return SelectShift(I, ShiftTy: ARM_AM::asr);
2969 default: break;
2970 }
2971 return false;
2972}
2973
2974// This table describes sign- and zero-extend instructions which can be
2975// folded into a preceding load. All of these extends have an immediate
2976// (sometimes a mask and sometimes a shift) that's applied after
2977// extension.
2978static const struct FoldableLoadExtendsStruct {
2979 uint16_t Opc[2]; // ARM, Thumb.
2980 uint8_t ExpectedImm;
2981 uint8_t isZExt : 1;
2982 uint8_t ExpectedVT : 7;
2983} FoldableLoadExtends[] = {
2984 { .Opc: { ARM::SXTH, ARM::t2SXTH }, .ExpectedImm: 0, .isZExt: 0, .ExpectedVT: MVT::i16 },
2985 { .Opc: { ARM::UXTH, ARM::t2UXTH }, .ExpectedImm: 0, .isZExt: 1, .ExpectedVT: MVT::i16 },
2986 { .Opc: { ARM::ANDri, ARM::t2ANDri }, .ExpectedImm: 255, .isZExt: 1, .ExpectedVT: MVT::i8 },
2987 { .Opc: { ARM::SXTB, ARM::t2SXTB }, .ExpectedImm: 0, .isZExt: 0, .ExpectedVT: MVT::i8 },
2988 { .Opc: { ARM::UXTB, ARM::t2UXTB }, .ExpectedImm: 0, .isZExt: 1, .ExpectedVT: MVT::i8 }
2989};
2990
2991/// The specified machine instr operand is a vreg, and that
2992/// vreg is being provided by the specified load instruction. If possible,
2993/// try to fold the load as an operand to the instruction, returning true if
2994/// successful.
2995bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2996 const LoadInst *LI) {
2997 // Verify we have a legal type before going any further.
2998 MVT VT;
2999 if (!isLoadTypeLegal(Ty: LI->getType(), VT))
3000 return false;
3001
3002 // Combine load followed by zero- or sign-extend.
3003 // ldrb r1, [r0] ldrb r1, [r0]
3004 // uxtb r2, r1 =>
3005 // mov r3, r2 mov r3, r1
3006 if (MI->getNumOperands() < 3 || !MI->getOperand(i: 2).isImm())
3007 return false;
3008 const uint64_t Imm = MI->getOperand(i: 2).getImm();
3009
3010 bool Found = false;
3011 bool isZExt;
3012 for (const FoldableLoadExtendsStruct &FLE : FoldableLoadExtends) {
3013 if (FLE.Opc[isThumb2] == MI->getOpcode() &&
3014 (uint64_t)FLE.ExpectedImm == Imm &&
3015 MVT((MVT::SimpleValueType)FLE.ExpectedVT) == VT) {
3016 Found = true;
3017 isZExt = FLE.isZExt;
3018 }
3019 }
3020 if (!Found) return false;
3021
3022 // See if we can handle this address.
3023 Address Addr;
3024 if (!ARMComputeAddress(Obj: LI->getOperand(i_nocapture: 0), Addr)) return false;
3025
3026 Register ResultReg = MI->getOperand(i: 0).getReg();
3027 if (!ARMEmitLoad(VT, ResultReg, Addr, Alignment: LI->getAlign(), isZExt, allocReg: false))
3028 return false;
3029 MachineBasicBlock::iterator I(MI);
3030 removeDeadCode(I, E: std::next(x: I));
3031 return true;
3032}
3033
3034Register ARMFastISel::ARMLowerPICELF(const GlobalValue *GV, MVT VT) {
3035 bool UseGOT_PREL = !GV->isDSOLocal();
3036 LLVMContext *Context = &MF->getFunction().getContext();
3037 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3038 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
3039 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(
3040 C: GV, ID: ARMPCLabelIndex, Kind: ARMCP::CPValue, PCAdj,
3041 Modifier: UseGOT_PREL ? ARMCP::GOT_PREL : ARMCP::no_modifier,
3042 /*AddCurrentAddress=*/UseGOT_PREL);
3043
3044 Align ConstAlign =
3045 MF->getDataLayout().getPrefTypeAlign(Ty: PointerType::get(C&: *Context, AddressSpace: 0));
3046 unsigned Idx = MF->getConstantPool()->getConstantPoolIndex(V: CPV, Alignment: ConstAlign);
3047 MachineMemOperand *CPMMO =
3048 MF->getMachineMemOperand(PtrInfo: MachinePointerInfo::getConstantPool(MF&: *MF),
3049 F: MachineMemOperand::MOLoad, Size: 4, BaseAlignment: Align(4));
3050
3051 Register TempReg = MF->getRegInfo().createVirtualRegister(RegClass: &ARM::rGPRRegClass);
3052 unsigned Opc = isThumb2 ? ARM::t2LDRpci : ARM::LDRcp;
3053 MachineInstrBuilder MIB =
3054 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: TempReg)
3055 .addConstantPoolIndex(Idx)
3056 .addMemOperand(MMO: CPMMO);
3057 if (Opc == ARM::LDRcp)
3058 MIB.addImm(Val: 0);
3059 MIB.add(MOs: predOps(Pred: ARMCC::AL));
3060
3061 // Fix the address by adding pc.
3062 Register DestReg = createResultReg(RC: TLI.getRegClassFor(VT));
3063 Opc = Subtarget->isThumb() ? ARM::tPICADD : UseGOT_PREL ? ARM::PICLDR
3064 : ARM::PICADD;
3065 DestReg = constrainOperandRegClass(II: TII.get(Opcode: Opc), Op: DestReg, OpNum: 0);
3066 MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg)
3067 .addReg(RegNo: TempReg)
3068 .addImm(Val: ARMPCLabelIndex);
3069
3070 if (!Subtarget->isThumb())
3071 MIB.add(MOs: predOps(Pred: ARMCC::AL));
3072
3073 if (UseGOT_PREL && Subtarget->isThumb()) {
3074 Register NewDestReg = createResultReg(RC: TLI.getRegClassFor(VT));
3075 MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
3076 MCID: TII.get(Opcode: ARM::t2LDRi12), DestReg: NewDestReg)
3077 .addReg(RegNo: DestReg)
3078 .addImm(Val: 0);
3079 DestReg = NewDestReg;
3080 AddOptionalDefs(MIB);
3081 }
3082 return DestReg;
3083}
3084
3085bool ARMFastISel::fastLowerArguments() {
3086 if (!FuncInfo.CanLowerReturn)
3087 return false;
3088
3089 const Function *F = FuncInfo.Fn;
3090 if (F->isVarArg())
3091 return false;
3092
3093 CallingConv::ID CC = F->getCallingConv();
3094 switch (CC) {
3095 default:
3096 return false;
3097 case CallingConv::Fast:
3098 case CallingConv::C:
3099 case CallingConv::ARM_AAPCS_VFP:
3100 case CallingConv::ARM_AAPCS:
3101 case CallingConv::ARM_APCS:
3102 case CallingConv::Swift:
3103 case CallingConv::SwiftTail:
3104 break;
3105 }
3106
3107 // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments
3108 // which are passed in r0 - r3.
3109 for (const Argument &Arg : F->args()) {
3110 if (Arg.getArgNo() >= 4)
3111 return false;
3112
3113 if (Arg.hasAttribute(Kind: Attribute::InReg) ||
3114 Arg.hasAttribute(Kind: Attribute::StructRet) ||
3115 Arg.hasAttribute(Kind: Attribute::SwiftSelf) ||
3116 Arg.hasAttribute(Kind: Attribute::SwiftError) ||
3117 Arg.hasAttribute(Kind: Attribute::ByVal))
3118 return false;
3119
3120 Type *ArgTy = Arg.getType();
3121 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
3122 return false;
3123
3124 EVT ArgVT = TLI.getValueType(DL, Ty: ArgTy);
3125 if (!ArgVT.isSimple()) return false;
3126 switch (ArgVT.getSimpleVT().SimpleTy) {
3127 case MVT::i8:
3128 case MVT::i16:
3129 case MVT::i32:
3130 break;
3131 default:
3132 return false;
3133 }
3134 }
3135
3136 static const MCPhysReg GPRArgRegs[] = {
3137 ARM::R0, ARM::R1, ARM::R2, ARM::R3
3138 };
3139
3140 const TargetRegisterClass *RC = &ARM::rGPRRegClass;
3141 for (const Argument &Arg : F->args()) {
3142 unsigned ArgNo = Arg.getArgNo();
3143 MCRegister SrcReg = GPRArgRegs[ArgNo];
3144 Register DstReg = FuncInfo.MF->addLiveIn(PReg: SrcReg, RC);
3145 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
3146 // Without this, EmitLiveInCopies may eliminate the livein if its only
3147 // use is a bitcast (which isn't turned into an instruction).
3148 Register ResultReg = createResultReg(RC);
3149 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
3150 MCID: TII.get(Opcode: TargetOpcode::COPY),
3151 DestReg: ResultReg).addReg(RegNo: DstReg, Flags: getKillRegState(B: true));
3152 updateValueMap(I: &Arg, Reg: ResultReg);
3153 }
3154
3155 return true;
3156}
3157
3158namespace llvm {
3159
3160FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
3161 const TargetLibraryInfo *libInfo,
3162 const LibcallLoweringInfo *libcallLowering) {
3163 if (funcInfo.MF->getSubtarget<ARMSubtarget>().useFastISel())
3164 return new ARMFastISel(funcInfo, libInfo, libcallLowering);
3165
3166 return nullptr;
3167}
3168
3169} // end namespace llvm
3170