1//===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Mips implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsInstrInfo.h"
14#include "MCTargetDesc/MipsBaseInfo.h"
15#include "MCTargetDesc/MipsMCTargetDesc.h"
16#include "Mips.h"
17#include "MipsSubtarget.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/CodeGen/MachineBasicBlock.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstr.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/CodeGen/MachineOperand.h"
25#include "llvm/CodeGen/TargetOpcodes.h"
26#include "llvm/CodeGen/TargetSubtargetInfo.h"
27#include "llvm/IR/DebugInfoMetadata.h"
28#include "llvm/IR/DebugLoc.h"
29#include "llvm/MC/MCInstBuilder.h"
30#include "llvm/MC/MCInstrDesc.h"
31#include "llvm/Target/TargetMachine.h"
32#include <cassert>
33
34using namespace llvm;
35
36#define GET_INSTRINFO_CTOR_DTOR
37#include "MipsGenInstrInfo.inc"
38
39// Pin the vtable to this file.
40void MipsInstrInfo::anchor() {}
41
42MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI,
43 const MipsRegisterInfo &RI, unsigned UncondBr)
44 : MipsGenInstrInfo(STI, RI, Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
45 Subtarget(STI), UncondBrOpc(UncondBr) {}
46
47const TargetRegisterClass *MipsInstrInfo::getInlineAsmMemoryOperandRegClass(
48 InlineAsm::ConstraintCode C) const {
49 return Subtarget.getABI().ArePtrs64bit() ? &Mips::GPR64RegClass
50 : &Mips::GPR32RegClass;
51}
52
53const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) {
54 if (STI.inMips16Mode())
55 return createMips16InstrInfo(STI);
56
57 return createMipsSEInstrInfo(STI);
58}
59
60bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
61 return op.isImm() && op.getImm() == 0;
62}
63
64MCInst MipsInstrInfo::getNop() const {
65 return MCInstBuilder(Mips::SLL).addReg(Reg: Mips::R0).addReg(Reg: Mips::R0).addImm(Val: 0);
66}
67
68/// insertNoop - If data hazard condition is found insert the target nop
69/// instruction.
70void MipsInstrInfo::
71insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
72{
73 DebugLoc DL;
74 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: get(Opcode: Mips::NOP));
75}
76
77MachineInstrBuilder MipsInstrInfo::insertNop(MachineBasicBlock &MBB,
78 MachineBasicBlock::iterator MI,
79 DebugLoc DL) const {
80 assert(!Subtarget.inMips16Mode() &&
81 "insertNop does not support MIPS16e mode at this time");
82 const unsigned MMOpc =
83 Subtarget.hasMips32r6() ? Mips::SLL_MMR6 : Mips::SLL_MM;
84 const unsigned Opc =
85 Subtarget.inMicroMipsMode() ? MMOpc : (unsigned)Mips::SLL;
86 return BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: get(Opcode: Opc), DestReg: Mips::R0).addReg(RegNo: Mips::R0).addImm(Val: 0);
87}
88
89MachineMemOperand *
90MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
91 MachineMemOperand::Flags Flags) const {
92 MachineFunction &MF = *MBB.getParent();
93 MachineFrameInfo &MFI = MF.getFrameInfo();
94
95 return MF.getMachineMemOperand(PtrInfo: MachinePointerInfo::getFixedStack(MF, FI),
96 F: Flags, Size: MFI.getObjectSize(ObjectIdx: FI),
97 BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
98}
99
100//===----------------------------------------------------------------------===//
101// Branch Analysis
102//===----------------------------------------------------------------------===//
103
104void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
105 MachineBasicBlock *&BB,
106 SmallVectorImpl<MachineOperand> &Cond) const {
107 assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
108 int NumOp = Inst->getNumExplicitOperands();
109
110 // for both int and fp branches, the last explicit operand is the
111 // MBB.
112 BB = Inst->getOperand(i: NumOp-1).getMBB();
113 Cond.push_back(Elt: MachineOperand::CreateImm(Val: Opc));
114
115 for (int i = 0; i < NumOp-1; i++)
116 Cond.push_back(Elt: Inst->getOperand(i));
117}
118
119bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
120 MachineBasicBlock *&TBB,
121 MachineBasicBlock *&FBB,
122 SmallVectorImpl<MachineOperand> &Cond,
123 bool AllowModify) const {
124 SmallVector<MachineInstr*, 2> BranchInstrs;
125 BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
126
127 return (BT == BT_None) || (BT == BT_Indirect);
128}
129
130void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
131 const DebugLoc &DL,
132 ArrayRef<MachineOperand> Cond) const {
133 unsigned Opc = Cond[0].getImm();
134 const MCInstrDesc &MCID = get(Opcode: Opc);
135 MachineInstrBuilder MIB = BuildMI(BB: &MBB, MIMD: DL, MCID);
136
137 for (unsigned i = 1; i < Cond.size(); ++i) {
138 assert((Cond[i].isImm() || Cond[i].isReg()) &&
139 "Cannot copy operand for conditional branch!");
140 MIB.add(MO: Cond[i]);
141 }
142 MIB.addMBB(MBB: TBB);
143 MIB->setImplicitPhysRegDefsDead();
144}
145
146unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB,
147 MachineBasicBlock *TBB,
148 MachineBasicBlock *FBB,
149 ArrayRef<MachineOperand> Cond,
150 const DebugLoc &DL,
151 int *BytesAdded) const {
152 // Shouldn't be a fall through.
153 assert(TBB && "insertBranch must not be told to insert a fallthrough");
154 assert(!BytesAdded && "code size not handled");
155
156 // # of condition operands:
157 // Unconditional branches: 0
158 // Floating point branches: 1 (opc)
159 // Int BranchZero: 2 (opc, reg)
160 // Int Branch: 3 (opc, reg0, reg1)
161 assert((Cond.size() <= 3) &&
162 "# of Mips branch conditions must be <= 3!");
163
164 // Two-way Conditional branch.
165 if (FBB) {
166 BuildCondBr(MBB, TBB, DL, Cond);
167 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: UncondBrOpc))
168 .addMBB(MBB: FBB)
169 ->setImplicitPhysRegDefsDead();
170 return 2;
171 }
172
173 // One way branch.
174 // Unconditional branch.
175 if (Cond.empty()) {
176 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: UncondBrOpc))
177 .addMBB(MBB: TBB)
178 ->setImplicitPhysRegDefsDead();
179 } else {
180 // Conditional branch.
181 BuildCondBr(MBB, TBB, DL, Cond);
182 }
183 return 1;
184}
185
186unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB,
187 int *BytesRemoved) const {
188 assert(!BytesRemoved && "code size not handled");
189
190 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
191 unsigned removed = 0;
192
193 // Up to 2 branches are removed.
194 // Note that indirect branches are not removed.
195 while (I != REnd && removed < 2) {
196 // Skip past debug instructions.
197 if (I->isDebugInstr()) {
198 ++I;
199 continue;
200 }
201 if (!getAnalyzableBrOpc(Opc: I->getOpcode()))
202 break;
203 // Remove the branch.
204 I->eraseFromParent();
205 I = MBB.rbegin();
206 ++removed;
207 }
208
209 return removed;
210}
211
212/// reverseBranchCondition - Return the inverse opcode of the
213/// specified Branch instruction.
214bool MipsInstrInfo::reverseBranchCondition(
215 SmallVectorImpl<MachineOperand> &Cond) const {
216 assert( (Cond.size() && Cond.size() <= 3) &&
217 "Invalid Mips branch condition!");
218 Cond[0].setImm(getOppositeBranchOpc(Opc: Cond[0].getImm()));
219 return false;
220}
221
222MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
223 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
224 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
225 SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
226 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
227
228 // Skip all the debug instructions.
229 while (I != REnd && I->isDebugInstr())
230 ++I;
231
232 if (I == REnd || !isUnpredicatedTerminator(MI: *I)) {
233 // This block ends with no branches (it just falls through to its succ).
234 // Leave TBB/FBB null.
235 TBB = FBB = nullptr;
236 return BT_NoBranch;
237 }
238
239 MachineInstr *LastInst = &*I;
240 unsigned LastOpc = LastInst->getOpcode();
241 BranchInstrs.push_back(Elt: LastInst);
242
243 // Not an analyzable branch (e.g., indirect jump).
244 if (!getAnalyzableBrOpc(Opc: LastOpc))
245 return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
246
247 // Get the second to last instruction in the block.
248 unsigned SecondLastOpc = 0;
249 MachineInstr *SecondLastInst = nullptr;
250
251 // Skip past any debug instruction to see if the second last actual
252 // is a branch.
253 ++I;
254 while (I != REnd && I->isDebugInstr())
255 ++I;
256
257 if (I != REnd) {
258 SecondLastInst = &*I;
259 SecondLastOpc = getAnalyzableBrOpc(Opc: SecondLastInst->getOpcode());
260
261 // Not an analyzable branch (must be an indirect jump).
262 if (isUnpredicatedTerminator(MI: *SecondLastInst) && !SecondLastOpc)
263 return BT_None;
264 }
265
266 // If there is only one terminator instruction, process it.
267 if (!SecondLastOpc) {
268 // Unconditional branch.
269 if (LastInst->isUnconditionalBranch()) {
270 TBB = LastInst->getOperand(i: 0).getMBB();
271 return BT_Uncond;
272 }
273
274 // Conditional branch
275 AnalyzeCondBr(Inst: LastInst, Opc: LastOpc, BB&: TBB, Cond);
276 return BT_Cond;
277 }
278
279 // If we reached here, there are two branches.
280 // If there are three terminators, we don't know what sort of block this is.
281 if (++I != REnd && isUnpredicatedTerminator(MI: *I))
282 return BT_None;
283
284 BranchInstrs.insert(I: BranchInstrs.begin(), Elt: SecondLastInst);
285
286 // If second to last instruction is an unconditional branch,
287 // analyze it and remove the last instruction.
288 if (SecondLastInst->isUnconditionalBranch()) {
289 // Return if the last instruction cannot be removed.
290 if (!AllowModify)
291 return BT_None;
292
293 TBB = SecondLastInst->getOperand(i: 0).getMBB();
294 LastInst->eraseFromParent();
295 BranchInstrs.pop_back();
296 return BT_Uncond;
297 }
298
299 // Conditional branch followed by an unconditional branch.
300 // The last one must be unconditional.
301 if (!LastInst->isUnconditionalBranch())
302 return BT_None;
303
304 AnalyzeCondBr(Inst: SecondLastInst, Opc: SecondLastOpc, BB&: TBB, Cond);
305 FBB = LastInst->getOperand(i: 0).getMBB();
306
307 return BT_CondUncond;
308}
309
310bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc,
311 int64_t BrOffset) const {
312 switch (BranchOpc) {
313 case Mips::B:
314 case Mips::BAL:
315 case Mips::BAL_BR:
316 case Mips::BAL_BR_MM:
317 case Mips::BC1F:
318 case Mips::BC1FL:
319 case Mips::BC1T:
320 case Mips::BC1TL:
321 case Mips::BEQ: case Mips::BEQ64:
322 case Mips::BEQL:
323 case Mips::BGEZ: case Mips::BGEZ64:
324 case Mips::BGEZL:
325 case Mips::BGEZAL:
326 case Mips::BGEZALL:
327 case Mips::BGTZ: case Mips::BGTZ64:
328 case Mips::BGTZL:
329 case Mips::BLEZ: case Mips::BLEZ64:
330 case Mips::BLEZL:
331 case Mips::BLTZ: case Mips::BLTZ64:
332 case Mips::BLTZL:
333 case Mips::BLTZAL:
334 case Mips::BLTZALL:
335 case Mips::BNE: case Mips::BNE64:
336 case Mips::BNEL:
337 return isInt<18>(x: BrOffset);
338
339 // microMIPSr3 branches
340 case Mips::B_MM:
341 case Mips::BC1F_MM:
342 case Mips::BC1T_MM:
343 case Mips::BEQ_MM:
344 case Mips::BGEZ_MM:
345 case Mips::BGEZAL_MM:
346 case Mips::BGTZ_MM:
347 case Mips::BLEZ_MM:
348 case Mips::BLTZ_MM:
349 case Mips::BLTZAL_MM:
350 case Mips::BNE_MM:
351 case Mips::BEQZC_MM:
352 case Mips::BNEZC_MM:
353 return isInt<17>(x: BrOffset);
354
355 // microMIPSR3 short branches.
356 case Mips::B16_MM:
357 return isInt<11>(x: BrOffset);
358
359 case Mips::BEQZ16_MM:
360 case Mips::BNEZ16_MM:
361 return isInt<8>(x: BrOffset);
362
363 // MIPSR6 branches.
364 case Mips::BALC:
365 case Mips::BC:
366 return isInt<28>(x: BrOffset);
367
368 case Mips::BC1EQZ:
369 case Mips::BC1NEZ:
370 case Mips::BC2EQZ:
371 case Mips::BC2NEZ:
372 case Mips::BEQC: case Mips::BEQC64:
373 case Mips::BNEC: case Mips::BNEC64:
374 case Mips::BGEC: case Mips::BGEC64:
375 case Mips::BGEUC: case Mips::BGEUC64:
376 case Mips::BGEZC: case Mips::BGEZC64:
377 case Mips::BGTZC: case Mips::BGTZC64:
378 case Mips::BLEZC: case Mips::BLEZC64:
379 case Mips::BLTC: case Mips::BLTC64:
380 case Mips::BLTUC: case Mips::BLTUC64:
381 case Mips::BLTZC: case Mips::BLTZC64:
382 case Mips::BNVC:
383 case Mips::BOVC:
384 case Mips::BGEZALC:
385 case Mips::BEQZALC:
386 case Mips::BGTZALC:
387 case Mips::BLEZALC:
388 case Mips::BLTZALC:
389 case Mips::BNEZALC:
390 return isInt<18>(x: BrOffset);
391
392 case Mips::BEQZC: case Mips::BEQZC64:
393 case Mips::BNEZC: case Mips::BNEZC64:
394 return isInt<23>(x: BrOffset);
395
396 // microMIPSR6 branches
397 case Mips::BC16_MMR6:
398 return isInt<11>(x: BrOffset);
399
400 case Mips::BEQZC16_MMR6:
401 case Mips::BNEZC16_MMR6:
402 return isInt<8>(x: BrOffset);
403
404 case Mips::BALC_MMR6:
405 case Mips::BC_MMR6:
406 return isInt<27>(x: BrOffset);
407
408 case Mips::BC1EQZC_MMR6:
409 case Mips::BC1NEZC_MMR6:
410 case Mips::BC2EQZC_MMR6:
411 case Mips::BC2NEZC_MMR6:
412 case Mips::BGEZALC_MMR6:
413 case Mips::BEQZALC_MMR6:
414 case Mips::BGTZALC_MMR6:
415 case Mips::BLEZALC_MMR6:
416 case Mips::BLTZALC_MMR6:
417 case Mips::BNEZALC_MMR6:
418 case Mips::BNVC_MMR6:
419 case Mips::BOVC_MMR6:
420 return isInt<17>(x: BrOffset);
421
422 case Mips::BEQC_MMR6:
423 case Mips::BNEC_MMR6:
424 case Mips::BGEC_MMR6:
425 case Mips::BGEUC_MMR6:
426 case Mips::BGEZC_MMR6:
427 case Mips::BGTZC_MMR6:
428 case Mips::BLEZC_MMR6:
429 case Mips::BLTC_MMR6:
430 case Mips::BLTUC_MMR6:
431 case Mips::BLTZC_MMR6:
432 return isInt<18>(x: BrOffset);
433
434 case Mips::BEQZC_MMR6:
435 case Mips::BNEZC_MMR6:
436 return isInt<23>(x: BrOffset);
437
438 // DSP branches.
439 case Mips::BPOSGE32:
440 return isInt<18>(x: BrOffset);
441 case Mips::BPOSGE32_MM:
442 case Mips::BPOSGE32C_MMR3:
443 return isInt<17>(x: BrOffset);
444
445 // cnMIPS branches.
446 case Mips::BBIT0:
447 case Mips::BBIT032:
448 case Mips::BBIT1:
449 case Mips::BBIT132:
450 return isInt<18>(x: BrOffset);
451
452 // MSA branches.
453 case Mips::BZ_B:
454 case Mips::BZ_H:
455 case Mips::BZ_W:
456 case Mips::BZ_D:
457 case Mips::BZ_V:
458 case Mips::BNZ_B:
459 case Mips::BNZ_H:
460 case Mips::BNZ_W:
461 case Mips::BNZ_D:
462 case Mips::BNZ_V:
463 return isInt<18>(x: BrOffset);
464 }
465
466 llvm_unreachable("Unknown branch instruction!");
467}
468
469/// Return the corresponding compact (no delay slot) form of a branch.
470unsigned MipsInstrInfo::getEquivalentCompactForm(
471 const MachineBasicBlock::iterator I) const {
472 unsigned Opcode = I->getOpcode();
473 bool canUseShortMicroMipsCTI = false;
474
475 if (Subtarget.inMicroMipsMode()) {
476 switch (Opcode) {
477 case Mips::BNE:
478 case Mips::BNE_MM:
479 case Mips::BEQ:
480 case Mips::BEQ_MM:
481 // microMIPS has NE,EQ branches that do not have delay slots provided one
482 // of the operands is zero.
483 if (I->getOperand(i: 1).getReg() == Subtarget.getABI().GetZeroReg())
484 canUseShortMicroMipsCTI = true;
485 break;
486 // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
487 // expanded to JR_MM, so they can be replaced with JRC16_MM.
488 case Mips::JR:
489 case Mips::PseudoReturn:
490 case Mips::PseudoIndirectBranch:
491 canUseShortMicroMipsCTI = true;
492 break;
493 }
494 }
495
496 // MIPSR6 forbids both operands being the zero register.
497 if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
498 (I->getOperand(i: 0).isReg() &&
499 (I->getOperand(i: 0).getReg() == Mips::R0 ||
500 I->getOperand(i: 0).getReg() == Mips::R0_64)) &&
501 (I->getOperand(i: 1).isReg() && (I->getOperand(i: 1).getReg() == Mips::R0 ||
502 I->getOperand(i: 1).getReg() == Mips::R0_64)))
503 return 0;
504
505 if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
506 switch (Opcode) {
507 case Mips::B:
508 return Mips::BC;
509 case Mips::BAL:
510 return Mips::BALC;
511 case Mips::BEQ:
512 case Mips::BEQ_MM:
513 if (canUseShortMicroMipsCTI)
514 return Mips::BEQZC_MM;
515 else if (I->getOperand(i: 0).getReg() == I->getOperand(i: 1).getReg())
516 return 0;
517 return Mips::BEQC;
518 case Mips::BNE:
519 case Mips::BNE_MM:
520 if (canUseShortMicroMipsCTI)
521 return Mips::BNEZC_MM;
522 else if (I->getOperand(i: 0).getReg() == I->getOperand(i: 1).getReg())
523 return 0;
524 return Mips::BNEC;
525 case Mips::BGE:
526 if (I->getOperand(i: 0).getReg() == I->getOperand(i: 1).getReg())
527 return 0;
528 return Mips::BGEC;
529 case Mips::BGEU:
530 if (I->getOperand(i: 0).getReg() == I->getOperand(i: 1).getReg())
531 return 0;
532 return Mips::BGEUC;
533 case Mips::BGEZ:
534 return Mips::BGEZC;
535 case Mips::BGTZ:
536 return Mips::BGTZC;
537 case Mips::BLEZ:
538 return Mips::BLEZC;
539 case Mips::BLT:
540 if (I->getOperand(i: 0).getReg() == I->getOperand(i: 1).getReg())
541 return 0;
542 return Mips::BLTC;
543 case Mips::BLTU:
544 if (I->getOperand(i: 0).getReg() == I->getOperand(i: 1).getReg())
545 return 0;
546 return Mips::BLTUC;
547 case Mips::BLTZ:
548 return Mips::BLTZC;
549 case Mips::BEQ64:
550 if (I->getOperand(i: 0).getReg() == I->getOperand(i: 1).getReg())
551 return 0;
552 return Mips::BEQC64;
553 case Mips::BNE64:
554 if (I->getOperand(i: 0).getReg() == I->getOperand(i: 1).getReg())
555 return 0;
556 return Mips::BNEC64;
557 case Mips::BGTZ64:
558 return Mips::BGTZC64;
559 case Mips::BGEZ64:
560 return Mips::BGEZC64;
561 case Mips::BLTZ64:
562 return Mips::BLTZC64;
563 case Mips::BLEZ64:
564 return Mips::BLEZC64;
565 // For MIPSR6, the instruction 'jic' can be used for these cases. Some
566 // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
567 case Mips::JR:
568 case Mips::PseudoIndirectBranchR6:
569 case Mips::PseudoReturn:
570 case Mips::TAILCALLR6REG:
571 if (canUseShortMicroMipsCTI)
572 return Mips::JRC16_MM;
573 return Mips::JIC;
574 case Mips::JALRPseudo:
575 return Mips::JIALC;
576 case Mips::JR64:
577 case Mips::PseudoIndirectBranch64R6:
578 case Mips::PseudoReturn64:
579 case Mips::TAILCALL64R6REG:
580 return Mips::JIC64;
581 case Mips::JALR64Pseudo:
582 return Mips::JIALC64;
583 default:
584 return 0;
585 }
586 }
587
588 return 0;
589}
590
591bool MipsInstrInfo::SafeAfterMflo(const MachineInstr &MI) const {
592 if (IsDIVMULT(MI.getOpcode()))
593 return false;
594
595 return true;
596}
597
598/// Predicate for distingushing between control transfer instructions and all
599/// other instructions for handling forbidden slots. Consider inline assembly
600/// as unsafe as well.
601bool MipsInstrInfo::SafeInForbiddenSlot(const MachineInstr &MI) const {
602 if (MI.isInlineAsm())
603 return false;
604
605 return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
606}
607
608bool MipsInstrInfo::SafeInFPUDelaySlot(const MachineInstr &MIInSlot,
609 const MachineInstr &FPUMI) const {
610 if (MIInSlot.isInlineAsm())
611 return false;
612
613 if (HasFPUDelaySlot(MI: MIInSlot))
614 return false;
615
616 switch (MIInSlot.getOpcode()) {
617 case Mips::BC1F:
618 case Mips::BC1FL:
619 case Mips::BC1T:
620 case Mips::BC1TL:
621 return false;
622 }
623
624 for (const MachineOperand &Op : FPUMI.defs()) {
625 if (!Op.isReg())
626 continue;
627
628 bool Reads, Writes;
629 std::tie(args&: Reads, args&: Writes) = MIInSlot.readsWritesVirtualRegister(Reg: Op.getReg());
630
631 if (Reads || Writes)
632 return false;
633 }
634
635 return true;
636}
637
638/// Predicate for distinguishing instructions that are hazardous in a load delay
639/// slot. Consider inline assembly as unsafe as well.
640bool MipsInstrInfo::SafeInLoadDelaySlot(const MachineInstr &MIInSlot,
641 const MachineInstr &LoadMI) const {
642 if (MIInSlot.isInlineAsm())
643 return false;
644
645 return !llvm::any_of(Range: LoadMI.defs(), P: [&](const MachineOperand &Op) {
646 return Op.isReg() && MIInSlot.readsRegister(Reg: Op.getReg(), /*TRI=*/nullptr) &&
647 !MIInSlot.hasRegisterImplicitUseOperand(Reg: Op.getReg());
648 });
649}
650
651bool MipsInstrInfo::IsMfloOrMfhi(const MachineInstr &MI) const {
652 if (IsMFLOMFHI(MI.getOpcode()))
653 return true;
654
655 return false;
656}
657
658/// Predicate for distingushing instructions that have forbidden slots.
659bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const {
660 return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
661}
662
663/// Predicate for distingushing instructions that have FPU delay slots.
664bool MipsInstrInfo::HasFPUDelaySlot(const MachineInstr &MI) const {
665 switch (MI.getOpcode()) {
666 case Mips::MTC1:
667 case Mips::MFC1:
668 case Mips::MTC1_D64:
669 case Mips::MFC1_D64:
670 case Mips::DMTC1:
671 case Mips::DMFC1:
672 case Mips::FCMP_S32:
673 case Mips::FCMP_D32:
674 case Mips::FCMP_D64:
675 return true;
676
677 default:
678 return false;
679 }
680}
681
682/// Predicate for distingushing instructions that have load delay slots.
683bool MipsInstrInfo::HasLoadDelaySlot(const MachineInstr &MI) const {
684 switch (MI.getOpcode()) {
685 case Mips::LB:
686 case Mips::LBu:
687 case Mips::LH:
688 case Mips::LHu:
689 case Mips::LW:
690 case Mips::LWR:
691 case Mips::LWL:
692 // On MIPS-I, the only float load there is; the rest came with later ISAs.
693 case Mips::LWC1:
694 return true;
695 default:
696 return false;
697 }
698}
699
700bool MipsInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
701 const unsigned Opcode = MI.getOpcode();
702 switch (Opcode) {
703 default:
704 break;
705 case Mips::ADDiu:
706 case Mips::ADDiu_MM:
707 case Mips::DADDiu:
708 return ((MI.getOperand(i: 2).isImm() && MI.getOperand(i: 2).getImm() == 0) ||
709 (MI.getOperand(i: 1).isReg() &&
710 (MI.getOperand(i: 1).getReg() == Mips::R0 ||
711 MI.getOperand(i: 1).getReg() == Mips::R0_64)));
712 }
713 return MI.isAsCheapAsAMove();
714}
715
716/// Return the number of bytes of code the specified instruction may be.
717unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
718 switch (MI.getOpcode()) {
719 default:
720 // Handle non-finalized bundle.
721 if (MI.isBundledWithSucc())
722 return MI.getDesc().getSize() + getInstBundleSize(MI);
723 if (MI.hasDelaySlot()) {
724 // instr + 1 nop
725 return MI.getDesc().getSize() + 4;
726 }
727 return MI.getDesc().getSize();
728 case TargetOpcode::INLINEASM:
729 case TargetOpcode::INLINEASM_BR: { // Inline Asm: Variable size.
730 const MachineFunction *MF = MI.getParent()->getParent();
731 const char *AsmStr = MI.getOperand(i: 0).getSymbolName();
732 return getInlineAsmLength(Str: AsmStr, MAI: MF->getTarget().getMCAsmInfo());
733 }
734 case TargetOpcode::BUNDLE:
735 return getInstBundleSize(MI);
736 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
737 case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
738 case TargetOpcode::PATCHABLE_TAIL_CALL:
739 // Size of xray sled
740 if (Subtarget.isGP64bit()) {
741 // beq + 15 nops
742 return 16 * 4;
743 } else {
744 // beq + 11 nops + addiu
745 return 13 * 4;
746 }
747 case Mips::CONSTPOOL_ENTRY:
748 // If this machine instr is a constant pool entry, its size is recorded as
749 // operand #2.
750 return MI.getOperand(i: 2).getImm();
751 }
752}
753
754MachineInstrBuilder
755MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
756 MachineBasicBlock::iterator I) const {
757 MachineInstrBuilder MIB;
758
759 // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
760 // Pick the zero form of the branch for readable assembly and for greater
761 // branch distance in non-microMIPS mode.
762 // Additional MIPSR6 does not permit the use of register $zero for compact
763 // branches.
764 // FIXME: Certain atomic sequences on mips64 generate 32bit references to
765 // Mips::R0, which is incorrect. This test should be updated to use
766 // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
767 // are fixed.
768 int ZeroOperandPosition = -1;
769 bool BranchWithZeroOperand = false;
770 if (I->isBranch() && !I->isPseudo()) {
771 auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
772 ZeroOperandPosition = I->findRegisterUseOperandIdx(Reg: Mips::R0, TRI, isKill: false);
773 BranchWithZeroOperand = ZeroOperandPosition != -1;
774 }
775
776 if (BranchWithZeroOperand) {
777 switch (NewOpc) {
778 case Mips::BEQC:
779 NewOpc = Mips::BEQZC;
780 break;
781 case Mips::BNEC:
782 NewOpc = Mips::BNEZC;
783 break;
784 case Mips::BGEC:
785 NewOpc = Mips::BGEZC;
786 break;
787 case Mips::BLTC:
788 NewOpc = Mips::BLTZC;
789 break;
790 case Mips::BEQC64:
791 NewOpc = Mips::BEQZC64;
792 break;
793 case Mips::BNEC64:
794 NewOpc = Mips::BNEZC64;
795 break;
796 }
797 }
798
799 MIB = BuildMI(BB&: *I->getParent(), I, MIMD: I->getDebugLoc(), MCID: get(Opcode: NewOpc));
800
801 // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
802 // immediate 0 as an operand and requires the removal of it's implicit-def %ra
803 // implicit operand as copying the implicit operations of the instructio we're
804 // looking at will give us the correct flags.
805 if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
806 NewOpc == Mips::JIALC64) {
807
808 if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
809 MIB->removeOperand(OpNo: 0);
810
811 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
812 MIB.add(MO: I->getOperand(i: J));
813 }
814
815 MIB.addImm(Val: 0);
816
817 // If I has an MCSymbol operand (used by asm printer, to emit R_MIPS_JALR),
818 // add it to the new instruction.
819 for (unsigned J = I->getDesc().getNumOperands(), E = I->getNumOperands();
820 J < E; ++J) {
821 const MachineOperand &MO = I->getOperand(i: J);
822 if (MO.isMCSymbol() && (MO.getTargetFlags() & MipsII::MO_JALR))
823 MIB.addSym(Sym: MO.getMCSymbol(), TargetFlags: MipsII::MO_JALR);
824 }
825
826
827 } else {
828 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
829 if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J)
830 continue;
831
832 MIB.add(MO: I->getOperand(i: J));
833 }
834 }
835
836 MIB.copyImplicitOps(OtherMI: *I);
837 MIB.cloneMemRefs(OtherMI: *I);
838 return MIB;
839}
840
841bool MipsInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
842 unsigned &SrcOpIdx1,
843 unsigned &SrcOpIdx2) const {
844 assert(!MI.isBundle() &&
845 "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
846
847 const MCInstrDesc &MCID = MI.getDesc();
848 if (!MCID.isCommutable())
849 return false;
850
851 switch (MI.getOpcode()) {
852 case Mips::DPADD_U_H:
853 case Mips::DPADD_U_W:
854 case Mips::DPADD_U_D:
855 case Mips::DPADD_S_H:
856 case Mips::DPADD_S_W:
857 case Mips::DPADD_S_D:
858 // The first operand is both input and output, so it should not commute
859 if (!fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1: 2, CommutableOpIdx2: 3))
860 return false;
861
862 if (!MI.getOperand(i: SrcOpIdx1).isReg() || !MI.getOperand(i: SrcOpIdx2).isReg())
863 return false;
864 return true;
865 }
866 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
867}
868
869// ins, ext, dext*, dins have the following constraints:
870// X <= pos < Y
871// X < size <= Y
872// X < pos+size <= Y
873//
874// dinsm and dinsu have the following constraints:
875// X <= pos < Y
876// X <= size <= Y
877// X < pos+size <= Y
878//
879// The callee of verifyInsExtInstruction however gives the bounds of
880// dins[um] like the other (d)ins (d)ext(um) instructions, so that this
881// function doesn't have to vary it's behaviour based on the instruction
882// being checked.
883static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo,
884 const int64_t PosLow, const int64_t PosHigh,
885 const int64_t SizeLow,
886 const int64_t SizeHigh,
887 const int64_t BothLow,
888 const int64_t BothHigh) {
889 MachineOperand MOPos = MI.getOperand(i: 2);
890 if (!MOPos.isImm()) {
891 ErrInfo = "Position is not an immediate!";
892 return false;
893 }
894 int64_t Pos = MOPos.getImm();
895 if (!((PosLow <= Pos) && (Pos < PosHigh))) {
896 ErrInfo = "Position operand is out of range!";
897 return false;
898 }
899
900 MachineOperand MOSize = MI.getOperand(i: 3);
901 if (!MOSize.isImm()) {
902 ErrInfo = "Size operand is not an immediate!";
903 return false;
904 }
905 int64_t Size = MOSize.getImm();
906 if (!((SizeLow < Size) && (Size <= SizeHigh))) {
907 ErrInfo = "Size operand is out of range!";
908 return false;
909 }
910
911 if (!((BothLow < (Pos + Size)) && ((Pos + Size) <= BothHigh))) {
912 ErrInfo = "Position + Size is out of range!";
913 return false;
914 }
915
916 return true;
917}
918
919// Perform target specific instruction verification.
920bool MipsInstrInfo::verifyInstruction(const MachineInstr &MI,
921 StringRef &ErrInfo) const {
922 // Verify that ins and ext instructions are well formed.
923 switch (MI.getOpcode()) {
924 case Mips::EXT:
925 case Mips::EXT_MM:
926 case Mips::INS:
927 case Mips::INS_MM:
928 case Mips::DINS:
929 return verifyInsExtInstruction(MI, ErrInfo, PosLow: 0, PosHigh: 32, SizeLow: 0, SizeHigh: 32, BothLow: 0, BothHigh: 32);
930 case Mips::DINSM:
931 // The ISA spec has a subtle difference between dinsm and dextm
932 // in that it says:
933 // 2 <= size <= 64 for 'dinsm' but 'dextm' has 32 < size <= 64.
934 // To make the bounds checks similar, the range 1 < size <= 64 is checked
935 // for 'dinsm'.
936 return verifyInsExtInstruction(MI, ErrInfo, PosLow: 0, PosHigh: 32, SizeLow: 1, SizeHigh: 64, BothLow: 32, BothHigh: 64);
937 case Mips::DINSU:
938 // The ISA spec has a subtle difference between dinsu and dextu in that
939 // the size range of dinsu is specified as 1 <= size <= 32 whereas size
940 // for dextu is 0 < size <= 32. The range checked for dinsu here is
941 // 0 < size <= 32, which is equivalent and similar to dextu.
942 return verifyInsExtInstruction(MI, ErrInfo, PosLow: 32, PosHigh: 64, SizeLow: 0, SizeHigh: 32, BothLow: 32, BothHigh: 64);
943 case Mips::DEXT:
944 return verifyInsExtInstruction(MI, ErrInfo, PosLow: 0, PosHigh: 32, SizeLow: 0, SizeHigh: 32, BothLow: 0, BothHigh: 63);
945 case Mips::DEXTM:
946 return verifyInsExtInstruction(MI, ErrInfo, PosLow: 0, PosHigh: 32, SizeLow: 32, SizeHigh: 64, BothLow: 32, BothHigh: 64);
947 case Mips::DEXTU:
948 return verifyInsExtInstruction(MI, ErrInfo, PosLow: 32, PosHigh: 64, SizeLow: 0, SizeHigh: 32, BothLow: 32, BothHigh: 64);
949 case Mips::TAILCALLREG:
950 case Mips::PseudoIndirectBranch:
951 case Mips::JR:
952 case Mips::JR64:
953 case Mips::JALR:
954 case Mips::JALR64:
955 case Mips::JALRPseudo:
956 if (!Subtarget.useIndirectJumpsHazard())
957 return true;
958
959 ErrInfo = "invalid instruction when using jump guards!";
960 return false;
961 default:
962 return true;
963 }
964
965 return true;
966}
967
968std::pair<unsigned, unsigned>
969MipsInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
970 return std::make_pair(x&: TF, y: 0u);
971}
972
973ArrayRef<std::pair<unsigned, const char*>>
974MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
975 using namespace MipsII;
976
977 static const std::pair<unsigned, const char*> Flags[] = {
978 {MO_GOT, "mips-got"},
979 {MO_GOT_CALL, "mips-got-call"},
980 {MO_GPREL, "mips-gprel"},
981 {MO_ABS_HI, "mips-abs-hi"},
982 {MO_ABS_LO, "mips-abs-lo"},
983 {MO_TLSGD, "mips-tlsgd"},
984 {MO_TLSLDM, "mips-tlsldm"},
985 {MO_DTPREL_HI, "mips-dtprel-hi"},
986 {MO_DTPREL_LO, "mips-dtprel-lo"},
987 {MO_GOTTPREL, "mips-gottprel"},
988 {MO_TPREL_HI, "mips-tprel-hi"},
989 {MO_TPREL_LO, "mips-tprel-lo"},
990 {MO_GPOFF_HI, "mips-gpoff-hi"},
991 {MO_GPOFF_LO, "mips-gpoff-lo"},
992 {MO_GOT_DISP, "mips-got-disp"},
993 {MO_GOT_PAGE, "mips-got-page"},
994 {MO_GOT_OFST, "mips-got-ofst"},
995 {MO_HIGHER, "mips-higher"},
996 {MO_HIGHEST, "mips-highest"},
997 {MO_GOT_HI16, "mips-got-hi16"},
998 {MO_GOT_LO16, "mips-got-lo16"},
999 {MO_CALL_HI16, "mips-call-hi16"},
1000 {MO_CALL_LO16, "mips-call-lo16"},
1001 {MO_JALR, "mips-jalr"}
1002 };
1003 return ArrayRef(Flags);
1004}
1005
1006std::optional<ParamLoadedValue>
1007MipsInstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
1008 DIExpression *Expr =
1009 DIExpression::get(Context&: MI.getMF()->getFunction().getContext(), Elements: {});
1010
1011 // TODO: Special MIPS instructions that need to be described separately.
1012 if (auto RegImm = isAddImmediate(MI, Reg)) {
1013 Register SrcReg = RegImm->Reg;
1014 int64_t Offset = RegImm->Imm;
1015 // When SrcReg is $zero, treat loaded value as immediate only.
1016 // Ex. $a2 = ADDiu $zero, 10
1017 if (SrcReg == Mips::R0 || SrcReg == Mips::R0_64) {
1018 return ParamLoadedValue(MI.getOperand(i: 2), Expr);
1019 }
1020 Expr = DIExpression::prepend(Expr, Flags: DIExpression::ApplyOffset, Offset);
1021 return ParamLoadedValue(MachineOperand::CreateReg(Reg: SrcReg, isDef: false), Expr);
1022 } else if (auto DestSrc = isCopyInstr(MI)) {
1023 const MachineFunction *MF = MI.getMF();
1024 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
1025 Register DestReg = DestSrc->Destination->getReg();
1026 // TODO: Handle cases where the Reg is sub- or super-register of the
1027 // DestReg.
1028 if (TRI->isSuperRegister(RegA: Reg, RegB: DestReg) || TRI->isSubRegister(RegA: Reg, RegB: DestReg))
1029 return std::nullopt;
1030 }
1031
1032 return TargetInstrInfo::describeLoadedValue(MI, Reg);
1033}
1034
1035std::optional<RegImmPair> MipsInstrInfo::isAddImmediate(const MachineInstr &MI,
1036 Register Reg) const {
1037 // TODO: Handle cases where Reg is a super- or sub-register of the
1038 // destination register.
1039 const MachineOperand &Op0 = MI.getOperand(i: 0);
1040 if (!Op0.isReg() || Reg != Op0.getReg())
1041 return std::nullopt;
1042
1043 switch (MI.getOpcode()) {
1044 case Mips::ADDiu:
1045 case Mips::DADDiu: {
1046 const MachineOperand &Dop = MI.getOperand(i: 0);
1047 const MachineOperand &Sop1 = MI.getOperand(i: 1);
1048 const MachineOperand &Sop2 = MI.getOperand(i: 2);
1049 // Value is sum of register and immediate. Immediate value could be
1050 // global string address which is not supported.
1051 if (Dop.isReg() && Sop1.isReg() && Sop2.isImm())
1052 return RegImmPair{Sop1.getReg(), Sop2.getImm()};
1053 // TODO: Handle case where Sop1 is a frame-index.
1054 }
1055 }
1056 return std::nullopt;
1057}
1058