1//===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Mips implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsInstrInfo.h"
14#include "MCTargetDesc/MipsBaseInfo.h"
15#include "MCTargetDesc/MipsMCTargetDesc.h"
16#include "Mips.h"
17#include "MipsSubtarget.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/CodeGen/MachineBasicBlock.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstr.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/CodeGen/MachineOperand.h"
25#include "llvm/CodeGen/TargetOpcodes.h"
26#include "llvm/CodeGen/TargetSubtargetInfo.h"
27#include "llvm/IR/DebugInfoMetadata.h"
28#include "llvm/IR/DebugLoc.h"
29#include "llvm/MC/MCInstBuilder.h"
30#include "llvm/MC/MCInstrDesc.h"
31#include "llvm/Target/TargetMachine.h"
32#include <cassert>
33
34using namespace llvm;
35
36#define GET_INSTRINFO_CTOR_DTOR
37#include "MipsGenInstrInfo.inc"
38
39// Pin the vtable to this file.
40void MipsInstrInfo::anchor() {}
41
42MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI,
43 const MipsRegisterInfo &RI, unsigned UncondBr)
44 : MipsGenInstrInfo(STI, RI, Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
45 Subtarget(STI), UncondBrOpc(UncondBr) {}
46
47const TargetRegisterClass *MipsInstrInfo::getInlineAsmMemoryOperandRegClass(
48 InlineAsm::ConstraintCode C) const {
49 return Subtarget.getABI().ArePtrs64bit() ? &Mips::GPR64RegClass
50 : &Mips::GPR32RegClass;
51}
52
53const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) {
54 if (STI.inMips16Mode())
55 return createMips16InstrInfo(STI);
56
57 return createMipsSEInstrInfo(STI);
58}
59
60bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
61 return op.isImm() && op.getImm() == 0;
62}
63
64MCInst MipsInstrInfo::getNop() const {
65 return MCInstBuilder(Mips::SLL)
66 .addReg(Reg: Mips::ZERO)
67 .addReg(Reg: Mips::ZERO)
68 .addImm(Val: 0);
69}
70
71/// insertNoop - If data hazard condition is found insert the target nop
72/// instruction.
73void MipsInstrInfo::
74insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
75{
76 DebugLoc DL;
77 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: get(Opcode: Mips::NOP));
78}
79
80MachineInstrBuilder MipsInstrInfo::insertNop(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator MI,
82 DebugLoc DL) const {
83 assert(!Subtarget.inMips16Mode() &&
84 "insertNop does not support MIPS16e mode at this time");
85 const unsigned MMOpc =
86 Subtarget.hasMips32r6() ? Mips::SLL_MMR6 : Mips::SLL_MM;
87 const unsigned Opc =
88 Subtarget.inMicroMipsMode() ? MMOpc : (unsigned)Mips::SLL;
89 return BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: get(Opcode: Opc), DestReg: Mips::ZERO)
90 .addReg(RegNo: Mips::ZERO)
91 .addImm(Val: 0);
92}
93
94MachineMemOperand *
95MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
96 MachineMemOperand::Flags Flags) const {
97 MachineFunction &MF = *MBB.getParent();
98 MachineFrameInfo &MFI = MF.getFrameInfo();
99
100 return MF.getMachineMemOperand(PtrInfo: MachinePointerInfo::getFixedStack(MF, FI),
101 F: Flags, Size: MFI.getObjectSize(ObjectIdx: FI),
102 BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
103}
104
105//===----------------------------------------------------------------------===//
106// Branch Analysis
107//===----------------------------------------------------------------------===//
108
109void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
110 MachineBasicBlock *&BB,
111 SmallVectorImpl<MachineOperand> &Cond) const {
112 assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
113 int NumOp = Inst->getNumExplicitOperands();
114
115 // for both int and fp branches, the last explicit operand is the
116 // MBB.
117 BB = Inst->getOperand(i: NumOp-1).getMBB();
118 Cond.push_back(Elt: MachineOperand::CreateImm(Val: Opc));
119
120 for (int i = 0; i < NumOp-1; i++)
121 Cond.push_back(Elt: Inst->getOperand(i));
122}
123
124bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
125 MachineBasicBlock *&TBB,
126 MachineBasicBlock *&FBB,
127 SmallVectorImpl<MachineOperand> &Cond,
128 bool AllowModify) const {
129 SmallVector<MachineInstr*, 2> BranchInstrs;
130 BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
131
132 return (BT == BT_None) || (BT == BT_Indirect);
133}
134
135void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
136 const DebugLoc &DL,
137 ArrayRef<MachineOperand> Cond) const {
138 unsigned Opc = Cond[0].getImm();
139 const MCInstrDesc &MCID = get(Opcode: Opc);
140 MachineInstrBuilder MIB = BuildMI(BB: &MBB, MIMD: DL, MCID);
141
142 for (unsigned i = 1; i < Cond.size(); ++i) {
143 assert((Cond[i].isImm() || Cond[i].isReg()) &&
144 "Cannot copy operand for conditional branch!");
145 MIB.add(MO: Cond[i]);
146 }
147 MIB.addMBB(MBB: TBB);
148}
149
150unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB,
151 MachineBasicBlock *TBB,
152 MachineBasicBlock *FBB,
153 ArrayRef<MachineOperand> Cond,
154 const DebugLoc &DL,
155 int *BytesAdded) const {
156 // Shouldn't be a fall through.
157 assert(TBB && "insertBranch must not be told to insert a fallthrough");
158 assert(!BytesAdded && "code size not handled");
159
160 // # of condition operands:
161 // Unconditional branches: 0
162 // Floating point branches: 1 (opc)
163 // Int BranchZero: 2 (opc, reg)
164 // Int Branch: 3 (opc, reg0, reg1)
165 assert((Cond.size() <= 3) &&
166 "# of Mips branch conditions must be <= 3!");
167
168 // Two-way Conditional branch.
169 if (FBB) {
170 BuildCondBr(MBB, TBB, DL, Cond);
171 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: UncondBrOpc)).addMBB(MBB: FBB);
172 return 2;
173 }
174
175 // One way branch.
176 // Unconditional branch.
177 if (Cond.empty())
178 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: UncondBrOpc)).addMBB(MBB: TBB);
179 else // Conditional branch.
180 BuildCondBr(MBB, TBB, DL, Cond);
181 return 1;
182}
183
184unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB,
185 int *BytesRemoved) const {
186 assert(!BytesRemoved && "code size not handled");
187
188 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
189 unsigned removed = 0;
190
191 // Up to 2 branches are removed.
192 // Note that indirect branches are not removed.
193 while (I != REnd && removed < 2) {
194 // Skip past debug instructions.
195 if (I->isDebugInstr()) {
196 ++I;
197 continue;
198 }
199 if (!getAnalyzableBrOpc(Opc: I->getOpcode()))
200 break;
201 // Remove the branch.
202 I->eraseFromParent();
203 I = MBB.rbegin();
204 ++removed;
205 }
206
207 return removed;
208}
209
210/// reverseBranchCondition - Return the inverse opcode of the
211/// specified Branch instruction.
212bool MipsInstrInfo::reverseBranchCondition(
213 SmallVectorImpl<MachineOperand> &Cond) const {
214 assert( (Cond.size() && Cond.size() <= 3) &&
215 "Invalid Mips branch condition!");
216 Cond[0].setImm(getOppositeBranchOpc(Opc: Cond[0].getImm()));
217 return false;
218}
219
220MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
221 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
222 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
223 SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
224 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
225
226 // Skip all the debug instructions.
227 while (I != REnd && I->isDebugInstr())
228 ++I;
229
230 if (I == REnd || !isUnpredicatedTerminator(MI: *I)) {
231 // This block ends with no branches (it just falls through to its succ).
232 // Leave TBB/FBB null.
233 TBB = FBB = nullptr;
234 return BT_NoBranch;
235 }
236
237 MachineInstr *LastInst = &*I;
238 unsigned LastOpc = LastInst->getOpcode();
239 BranchInstrs.push_back(Elt: LastInst);
240
241 // Not an analyzable branch (e.g., indirect jump).
242 if (!getAnalyzableBrOpc(Opc: LastOpc))
243 return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
244
245 // Get the second to last instruction in the block.
246 unsigned SecondLastOpc = 0;
247 MachineInstr *SecondLastInst = nullptr;
248
249 // Skip past any debug instruction to see if the second last actual
250 // is a branch.
251 ++I;
252 while (I != REnd && I->isDebugInstr())
253 ++I;
254
255 if (I != REnd) {
256 SecondLastInst = &*I;
257 SecondLastOpc = getAnalyzableBrOpc(Opc: SecondLastInst->getOpcode());
258
259 // Not an analyzable branch (must be an indirect jump).
260 if (isUnpredicatedTerminator(MI: *SecondLastInst) && !SecondLastOpc)
261 return BT_None;
262 }
263
264 // If there is only one terminator instruction, process it.
265 if (!SecondLastOpc) {
266 // Unconditional branch.
267 if (LastInst->isUnconditionalBranch()) {
268 TBB = LastInst->getOperand(i: 0).getMBB();
269 return BT_Uncond;
270 }
271
272 // Conditional branch
273 AnalyzeCondBr(Inst: LastInst, Opc: LastOpc, BB&: TBB, Cond);
274 return BT_Cond;
275 }
276
277 // If we reached here, there are two branches.
278 // If there are three terminators, we don't know what sort of block this is.
279 if (++I != REnd && isUnpredicatedTerminator(MI: *I))
280 return BT_None;
281
282 BranchInstrs.insert(I: BranchInstrs.begin(), Elt: SecondLastInst);
283
284 // If second to last instruction is an unconditional branch,
285 // analyze it and remove the last instruction.
286 if (SecondLastInst->isUnconditionalBranch()) {
287 // Return if the last instruction cannot be removed.
288 if (!AllowModify)
289 return BT_None;
290
291 TBB = SecondLastInst->getOperand(i: 0).getMBB();
292 LastInst->eraseFromParent();
293 BranchInstrs.pop_back();
294 return BT_Uncond;
295 }
296
297 // Conditional branch followed by an unconditional branch.
298 // The last one must be unconditional.
299 if (!LastInst->isUnconditionalBranch())
300 return BT_None;
301
302 AnalyzeCondBr(Inst: SecondLastInst, Opc: SecondLastOpc, BB&: TBB, Cond);
303 FBB = LastInst->getOperand(i: 0).getMBB();
304
305 return BT_CondUncond;
306}
307
308bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc,
309 int64_t BrOffset) const {
310 switch (BranchOpc) {
311 case Mips::B:
312 case Mips::BAL:
313 case Mips::BAL_BR:
314 case Mips::BAL_BR_MM:
315 case Mips::BC1F:
316 case Mips::BC1FL:
317 case Mips::BC1T:
318 case Mips::BC1TL:
319 case Mips::BEQ: case Mips::BEQ64:
320 case Mips::BEQL:
321 case Mips::BGEZ: case Mips::BGEZ64:
322 case Mips::BGEZL:
323 case Mips::BGEZAL:
324 case Mips::BGEZALL:
325 case Mips::BGTZ: case Mips::BGTZ64:
326 case Mips::BGTZL:
327 case Mips::BLEZ: case Mips::BLEZ64:
328 case Mips::BLEZL:
329 case Mips::BLTZ: case Mips::BLTZ64:
330 case Mips::BLTZL:
331 case Mips::BLTZAL:
332 case Mips::BLTZALL:
333 case Mips::BNE: case Mips::BNE64:
334 case Mips::BNEL:
335 return isInt<18>(x: BrOffset);
336
337 // microMIPSr3 branches
338 case Mips::B_MM:
339 case Mips::BC1F_MM:
340 case Mips::BC1T_MM:
341 case Mips::BEQ_MM:
342 case Mips::BGEZ_MM:
343 case Mips::BGEZAL_MM:
344 case Mips::BGTZ_MM:
345 case Mips::BLEZ_MM:
346 case Mips::BLTZ_MM:
347 case Mips::BLTZAL_MM:
348 case Mips::BNE_MM:
349 case Mips::BEQZC_MM:
350 case Mips::BNEZC_MM:
351 return isInt<17>(x: BrOffset);
352
353 // microMIPSR3 short branches.
354 case Mips::B16_MM:
355 return isInt<11>(x: BrOffset);
356
357 case Mips::BEQZ16_MM:
358 case Mips::BNEZ16_MM:
359 return isInt<8>(x: BrOffset);
360
361 // MIPSR6 branches.
362 case Mips::BALC:
363 case Mips::BC:
364 return isInt<28>(x: BrOffset);
365
366 case Mips::BC1EQZ:
367 case Mips::BC1NEZ:
368 case Mips::BC2EQZ:
369 case Mips::BC2NEZ:
370 case Mips::BEQC: case Mips::BEQC64:
371 case Mips::BNEC: case Mips::BNEC64:
372 case Mips::BGEC: case Mips::BGEC64:
373 case Mips::BGEUC: case Mips::BGEUC64:
374 case Mips::BGEZC: case Mips::BGEZC64:
375 case Mips::BGTZC: case Mips::BGTZC64:
376 case Mips::BLEZC: case Mips::BLEZC64:
377 case Mips::BLTC: case Mips::BLTC64:
378 case Mips::BLTUC: case Mips::BLTUC64:
379 case Mips::BLTZC: case Mips::BLTZC64:
380 case Mips::BNVC:
381 case Mips::BOVC:
382 case Mips::BGEZALC:
383 case Mips::BEQZALC:
384 case Mips::BGTZALC:
385 case Mips::BLEZALC:
386 case Mips::BLTZALC:
387 case Mips::BNEZALC:
388 return isInt<18>(x: BrOffset);
389
390 case Mips::BEQZC: case Mips::BEQZC64:
391 case Mips::BNEZC: case Mips::BNEZC64:
392 return isInt<23>(x: BrOffset);
393
394 // microMIPSR6 branches
395 case Mips::BC16_MMR6:
396 return isInt<11>(x: BrOffset);
397
398 case Mips::BEQZC16_MMR6:
399 case Mips::BNEZC16_MMR6:
400 return isInt<8>(x: BrOffset);
401
402 case Mips::BALC_MMR6:
403 case Mips::BC_MMR6:
404 return isInt<27>(x: BrOffset);
405
406 case Mips::BC1EQZC_MMR6:
407 case Mips::BC1NEZC_MMR6:
408 case Mips::BC2EQZC_MMR6:
409 case Mips::BC2NEZC_MMR6:
410 case Mips::BGEZALC_MMR6:
411 case Mips::BEQZALC_MMR6:
412 case Mips::BGTZALC_MMR6:
413 case Mips::BLEZALC_MMR6:
414 case Mips::BLTZALC_MMR6:
415 case Mips::BNEZALC_MMR6:
416 case Mips::BNVC_MMR6:
417 case Mips::BOVC_MMR6:
418 return isInt<17>(x: BrOffset);
419
420 case Mips::BEQC_MMR6:
421 case Mips::BNEC_MMR6:
422 case Mips::BGEC_MMR6:
423 case Mips::BGEUC_MMR6:
424 case Mips::BGEZC_MMR6:
425 case Mips::BGTZC_MMR6:
426 case Mips::BLEZC_MMR6:
427 case Mips::BLTC_MMR6:
428 case Mips::BLTUC_MMR6:
429 case Mips::BLTZC_MMR6:
430 return isInt<18>(x: BrOffset);
431
432 case Mips::BEQZC_MMR6:
433 case Mips::BNEZC_MMR6:
434 return isInt<23>(x: BrOffset);
435
436 // DSP branches.
437 case Mips::BPOSGE32:
438 return isInt<18>(x: BrOffset);
439 case Mips::BPOSGE32_MM:
440 case Mips::BPOSGE32C_MMR3:
441 return isInt<17>(x: BrOffset);
442
443 // cnMIPS branches.
444 case Mips::BBIT0:
445 case Mips::BBIT032:
446 case Mips::BBIT1:
447 case Mips::BBIT132:
448 return isInt<18>(x: BrOffset);
449
450 // MSA branches.
451 case Mips::BZ_B:
452 case Mips::BZ_H:
453 case Mips::BZ_W:
454 case Mips::BZ_D:
455 case Mips::BZ_V:
456 case Mips::BNZ_B:
457 case Mips::BNZ_H:
458 case Mips::BNZ_W:
459 case Mips::BNZ_D:
460 case Mips::BNZ_V:
461 return isInt<18>(x: BrOffset);
462 }
463
464 llvm_unreachable("Unknown branch instruction!");
465}
466
467/// Return the corresponding compact (no delay slot) form of a branch.
468unsigned MipsInstrInfo::getEquivalentCompactForm(
469 const MachineBasicBlock::iterator I) const {
470 unsigned Opcode = I->getOpcode();
471 bool canUseShortMicroMipsCTI = false;
472
473 if (Subtarget.inMicroMipsMode()) {
474 switch (Opcode) {
475 case Mips::BNE:
476 case Mips::BNE_MM:
477 case Mips::BEQ:
478 case Mips::BEQ_MM:
479 // microMIPS has NE,EQ branches that do not have delay slots provided one
480 // of the operands is zero.
481 if (I->getOperand(i: 1).getReg() == Subtarget.getABI().GetZeroReg())
482 canUseShortMicroMipsCTI = true;
483 break;
484 // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
485 // expanded to JR_MM, so they can be replaced with JRC16_MM.
486 case Mips::JR:
487 case Mips::PseudoReturn:
488 case Mips::PseudoIndirectBranch:
489 canUseShortMicroMipsCTI = true;
490 break;
491 }
492 }
493
494 // MIPSR6 forbids both operands being the zero register.
495 if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
496 (I->getOperand(i: 0).isReg() &&
497 (I->getOperand(i: 0).getReg() == Mips::ZERO ||
498 I->getOperand(i: 0).getReg() == Mips::ZERO_64)) &&
499 (I->getOperand(i: 1).isReg() &&
500 (I->getOperand(i: 1).getReg() == Mips::ZERO ||
501 I->getOperand(i: 1).getReg() == Mips::ZERO_64)))
502 return 0;
503
504 if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
505 switch (Opcode) {
506 case Mips::B:
507 return Mips::BC;
508 case Mips::BAL:
509 return Mips::BALC;
510 case Mips::BEQ:
511 case Mips::BEQ_MM:
512 if (canUseShortMicroMipsCTI)
513 return Mips::BEQZC_MM;
514 else if (I->getOperand(i: 0).getReg() == I->getOperand(i: 1).getReg())
515 return 0;
516 return Mips::BEQC;
517 case Mips::BNE:
518 case Mips::BNE_MM:
519 if (canUseShortMicroMipsCTI)
520 return Mips::BNEZC_MM;
521 else if (I->getOperand(i: 0).getReg() == I->getOperand(i: 1).getReg())
522 return 0;
523 return Mips::BNEC;
524 case Mips::BGE:
525 if (I->getOperand(i: 0).getReg() == I->getOperand(i: 1).getReg())
526 return 0;
527 return Mips::BGEC;
528 case Mips::BGEU:
529 if (I->getOperand(i: 0).getReg() == I->getOperand(i: 1).getReg())
530 return 0;
531 return Mips::BGEUC;
532 case Mips::BGEZ:
533 return Mips::BGEZC;
534 case Mips::BGTZ:
535 return Mips::BGTZC;
536 case Mips::BLEZ:
537 return Mips::BLEZC;
538 case Mips::BLT:
539 if (I->getOperand(i: 0).getReg() == I->getOperand(i: 1).getReg())
540 return 0;
541 return Mips::BLTC;
542 case Mips::BLTU:
543 if (I->getOperand(i: 0).getReg() == I->getOperand(i: 1).getReg())
544 return 0;
545 return Mips::BLTUC;
546 case Mips::BLTZ:
547 return Mips::BLTZC;
548 case Mips::BEQ64:
549 if (I->getOperand(i: 0).getReg() == I->getOperand(i: 1).getReg())
550 return 0;
551 return Mips::BEQC64;
552 case Mips::BNE64:
553 if (I->getOperand(i: 0).getReg() == I->getOperand(i: 1).getReg())
554 return 0;
555 return Mips::BNEC64;
556 case Mips::BGTZ64:
557 return Mips::BGTZC64;
558 case Mips::BGEZ64:
559 return Mips::BGEZC64;
560 case Mips::BLTZ64:
561 return Mips::BLTZC64;
562 case Mips::BLEZ64:
563 return Mips::BLEZC64;
564 // For MIPSR6, the instruction 'jic' can be used for these cases. Some
565 // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
566 case Mips::JR:
567 case Mips::PseudoIndirectBranchR6:
568 case Mips::PseudoReturn:
569 case Mips::TAILCALLR6REG:
570 if (canUseShortMicroMipsCTI)
571 return Mips::JRC16_MM;
572 return Mips::JIC;
573 case Mips::JALRPseudo:
574 return Mips::JIALC;
575 case Mips::JR64:
576 case Mips::PseudoIndirectBranch64R6:
577 case Mips::PseudoReturn64:
578 case Mips::TAILCALL64R6REG:
579 return Mips::JIC64;
580 case Mips::JALR64Pseudo:
581 return Mips::JIALC64;
582 default:
583 return 0;
584 }
585 }
586
587 return 0;
588}
589
590bool MipsInstrInfo::SafeAfterMflo(const MachineInstr &MI) const {
591 if (IsDIVMULT(MI.getOpcode()))
592 return false;
593
594 return true;
595}
596
597/// Predicate for distingushing between control transfer instructions and all
598/// other instructions for handling forbidden slots. Consider inline assembly
599/// as unsafe as well.
600bool MipsInstrInfo::SafeInForbiddenSlot(const MachineInstr &MI) const {
601 if (MI.isInlineAsm())
602 return false;
603
604 return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
605}
606
607bool MipsInstrInfo::SafeInFPUDelaySlot(const MachineInstr &MIInSlot,
608 const MachineInstr &FPUMI) const {
609 if (MIInSlot.isInlineAsm())
610 return false;
611
612 if (HasFPUDelaySlot(MI: MIInSlot))
613 return false;
614
615 switch (MIInSlot.getOpcode()) {
616 case Mips::BC1F:
617 case Mips::BC1FL:
618 case Mips::BC1T:
619 case Mips::BC1TL:
620 return false;
621 }
622
623 for (const MachineOperand &Op : FPUMI.defs()) {
624 if (!Op.isReg())
625 continue;
626
627 bool Reads, Writes;
628 std::tie(args&: Reads, args&: Writes) = MIInSlot.readsWritesVirtualRegister(Reg: Op.getReg());
629
630 if (Reads || Writes)
631 return false;
632 }
633
634 return true;
635}
636
637/// Predicate for distinguishing instructions that are hazardous in a load delay
638/// slot. Consider inline assembly as unsafe as well.
639bool MipsInstrInfo::SafeInLoadDelaySlot(const MachineInstr &MIInSlot,
640 const MachineInstr &LoadMI) const {
641 if (MIInSlot.isInlineAsm())
642 return false;
643
644 return !llvm::any_of(Range: LoadMI.defs(), P: [&](const MachineOperand &Op) {
645 return Op.isReg() && MIInSlot.readsRegister(Reg: Op.getReg(), /*TRI=*/nullptr) &&
646 !MIInSlot.hasRegisterImplicitUseOperand(Reg: Op.getReg());
647 });
648}
649
650bool MipsInstrInfo::IsMfloOrMfhi(const MachineInstr &MI) const {
651 if (IsMFLOMFHI(MI.getOpcode()))
652 return true;
653
654 return false;
655}
656
657/// Predicate for distingushing instructions that have forbidden slots.
658bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const {
659 return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
660}
661
662/// Predicate for distingushing instructions that have FPU delay slots.
663bool MipsInstrInfo::HasFPUDelaySlot(const MachineInstr &MI) const {
664 switch (MI.getOpcode()) {
665 case Mips::MTC1:
666 case Mips::MFC1:
667 case Mips::MTC1_D64:
668 case Mips::MFC1_D64:
669 case Mips::DMTC1:
670 case Mips::DMFC1:
671 case Mips::FCMP_S32:
672 case Mips::FCMP_D32:
673 case Mips::FCMP_D64:
674 return true;
675
676 default:
677 return false;
678 }
679}
680
681/// Predicate for distingushing instructions that have load delay slots.
682bool MipsInstrInfo::HasLoadDelaySlot(const MachineInstr &MI) const {
683 switch (MI.getOpcode()) {
684 case Mips::LB:
685 case Mips::LBu:
686 case Mips::LH:
687 case Mips::LHu:
688 case Mips::LW:
689 case Mips::LWR:
690 case Mips::LWL:
691 return true;
692 default:
693 return false;
694 }
695}
696
697bool MipsInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
698 const unsigned Opcode = MI.getOpcode();
699 switch (Opcode) {
700 default:
701 break;
702 case Mips::ADDiu:
703 case Mips::ADDiu_MM:
704 case Mips::DADDiu:
705 return ((MI.getOperand(i: 2).isImm() && MI.getOperand(i: 2).getImm() == 0) ||
706 (MI.getOperand(i: 1).isReg() &&
707 (MI.getOperand(i: 1).getReg() == Mips::ZERO ||
708 MI.getOperand(i: 1).getReg() == Mips::ZERO_64)));
709 }
710 return MI.isAsCheapAsAMove();
711}
712
713/// Return the number of bytes of code the specified instruction may be.
714unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
715 switch (MI.getOpcode()) {
716 default:
717 // Handle non-finalized bundle.
718 if (MI.isBundledWithSucc())
719 return MI.getDesc().getSize() + getInstBundleSize(MI);
720 if (MI.hasDelaySlot()) {
721 // instr + 1 nop
722 return MI.getDesc().getSize() + 4;
723 }
724 return MI.getDesc().getSize();
725 case TargetOpcode::INLINEASM:
726 case TargetOpcode::INLINEASM_BR: { // Inline Asm: Variable size.
727 const MachineFunction *MF = MI.getParent()->getParent();
728 const char *AsmStr = MI.getOperand(i: 0).getSymbolName();
729 return getInlineAsmLength(Str: AsmStr, MAI: MF->getTarget().getMCAsmInfo());
730 }
731 case TargetOpcode::BUNDLE:
732 return getInstBundleSize(MI);
733 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
734 case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
735 case TargetOpcode::PATCHABLE_TAIL_CALL:
736 // Size of xray sled
737 if (Subtarget.isGP64bit()) {
738 // beq + 15 nops
739 return 16 * 4;
740 } else {
741 // beq + 11 nops + addiu
742 return 13 * 4;
743 }
744 case Mips::CONSTPOOL_ENTRY:
745 // If this machine instr is a constant pool entry, its size is recorded as
746 // operand #2.
747 return MI.getOperand(i: 2).getImm();
748 }
749}
750
751MachineInstrBuilder
752MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
753 MachineBasicBlock::iterator I) const {
754 MachineInstrBuilder MIB;
755
756 // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
757 // Pick the zero form of the branch for readable assembly and for greater
758 // branch distance in non-microMIPS mode.
759 // Additional MIPSR6 does not permit the use of register $zero for compact
760 // branches.
761 // FIXME: Certain atomic sequences on mips64 generate 32bit references to
762 // Mips::ZERO, which is incorrect. This test should be updated to use
763 // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
764 // are fixed.
765 int ZeroOperandPosition = -1;
766 bool BranchWithZeroOperand = false;
767 if (I->isBranch() && !I->isPseudo()) {
768 auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
769 ZeroOperandPosition = I->findRegisterUseOperandIdx(Reg: Mips::ZERO, TRI, isKill: false);
770 BranchWithZeroOperand = ZeroOperandPosition != -1;
771 }
772
773 if (BranchWithZeroOperand) {
774 switch (NewOpc) {
775 case Mips::BEQC:
776 NewOpc = Mips::BEQZC;
777 break;
778 case Mips::BNEC:
779 NewOpc = Mips::BNEZC;
780 break;
781 case Mips::BGEC:
782 NewOpc = Mips::BGEZC;
783 break;
784 case Mips::BLTC:
785 NewOpc = Mips::BLTZC;
786 break;
787 case Mips::BEQC64:
788 NewOpc = Mips::BEQZC64;
789 break;
790 case Mips::BNEC64:
791 NewOpc = Mips::BNEZC64;
792 break;
793 }
794 }
795
796 MIB = BuildMI(BB&: *I->getParent(), I, MIMD: I->getDebugLoc(), MCID: get(Opcode: NewOpc));
797
798 // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
799 // immediate 0 as an operand and requires the removal of it's implicit-def %ra
800 // implicit operand as copying the implicit operations of the instructio we're
801 // looking at will give us the correct flags.
802 if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
803 NewOpc == Mips::JIALC64) {
804
805 if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
806 MIB->removeOperand(OpNo: 0);
807
808 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
809 MIB.add(MO: I->getOperand(i: J));
810 }
811
812 MIB.addImm(Val: 0);
813
814 // If I has an MCSymbol operand (used by asm printer, to emit R_MIPS_JALR),
815 // add it to the new instruction.
816 for (unsigned J = I->getDesc().getNumOperands(), E = I->getNumOperands();
817 J < E; ++J) {
818 const MachineOperand &MO = I->getOperand(i: J);
819 if (MO.isMCSymbol() && (MO.getTargetFlags() & MipsII::MO_JALR))
820 MIB.addSym(Sym: MO.getMCSymbol(), TargetFlags: MipsII::MO_JALR);
821 }
822
823
824 } else {
825 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
826 if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J)
827 continue;
828
829 MIB.add(MO: I->getOperand(i: J));
830 }
831 }
832
833 MIB.copyImplicitOps(OtherMI: *I);
834 MIB.cloneMemRefs(OtherMI: *I);
835 return MIB;
836}
837
838bool MipsInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
839 unsigned &SrcOpIdx1,
840 unsigned &SrcOpIdx2) const {
841 assert(!MI.isBundle() &&
842 "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
843
844 const MCInstrDesc &MCID = MI.getDesc();
845 if (!MCID.isCommutable())
846 return false;
847
848 switch (MI.getOpcode()) {
849 case Mips::DPADD_U_H:
850 case Mips::DPADD_U_W:
851 case Mips::DPADD_U_D:
852 case Mips::DPADD_S_H:
853 case Mips::DPADD_S_W:
854 case Mips::DPADD_S_D:
855 // The first operand is both input and output, so it should not commute
856 if (!fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1: 2, CommutableOpIdx2: 3))
857 return false;
858
859 if (!MI.getOperand(i: SrcOpIdx1).isReg() || !MI.getOperand(i: SrcOpIdx2).isReg())
860 return false;
861 return true;
862 }
863 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
864}
865
866// ins, ext, dext*, dins have the following constraints:
867// X <= pos < Y
868// X < size <= Y
869// X < pos+size <= Y
870//
871// dinsm and dinsu have the following constraints:
872// X <= pos < Y
873// X <= size <= Y
874// X < pos+size <= Y
875//
876// The callee of verifyInsExtInstruction however gives the bounds of
877// dins[um] like the other (d)ins (d)ext(um) instructions, so that this
878// function doesn't have to vary it's behaviour based on the instruction
879// being checked.
880static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo,
881 const int64_t PosLow, const int64_t PosHigh,
882 const int64_t SizeLow,
883 const int64_t SizeHigh,
884 const int64_t BothLow,
885 const int64_t BothHigh) {
886 MachineOperand MOPos = MI.getOperand(i: 2);
887 if (!MOPos.isImm()) {
888 ErrInfo = "Position is not an immediate!";
889 return false;
890 }
891 int64_t Pos = MOPos.getImm();
892 if (!((PosLow <= Pos) && (Pos < PosHigh))) {
893 ErrInfo = "Position operand is out of range!";
894 return false;
895 }
896
897 MachineOperand MOSize = MI.getOperand(i: 3);
898 if (!MOSize.isImm()) {
899 ErrInfo = "Size operand is not an immediate!";
900 return false;
901 }
902 int64_t Size = MOSize.getImm();
903 if (!((SizeLow < Size) && (Size <= SizeHigh))) {
904 ErrInfo = "Size operand is out of range!";
905 return false;
906 }
907
908 if (!((BothLow < (Pos + Size)) && ((Pos + Size) <= BothHigh))) {
909 ErrInfo = "Position + Size is out of range!";
910 return false;
911 }
912
913 return true;
914}
915
916// Perform target specific instruction verification.
917bool MipsInstrInfo::verifyInstruction(const MachineInstr &MI,
918 StringRef &ErrInfo) const {
919 // Verify that ins and ext instructions are well formed.
920 switch (MI.getOpcode()) {
921 case Mips::EXT:
922 case Mips::EXT_MM:
923 case Mips::INS:
924 case Mips::INS_MM:
925 case Mips::DINS:
926 return verifyInsExtInstruction(MI, ErrInfo, PosLow: 0, PosHigh: 32, SizeLow: 0, SizeHigh: 32, BothLow: 0, BothHigh: 32);
927 case Mips::DINSM:
928 // The ISA spec has a subtle difference between dinsm and dextm
929 // in that it says:
930 // 2 <= size <= 64 for 'dinsm' but 'dextm' has 32 < size <= 64.
931 // To make the bounds checks similar, the range 1 < size <= 64 is checked
932 // for 'dinsm'.
933 return verifyInsExtInstruction(MI, ErrInfo, PosLow: 0, PosHigh: 32, SizeLow: 1, SizeHigh: 64, BothLow: 32, BothHigh: 64);
934 case Mips::DINSU:
935 // The ISA spec has a subtle difference between dinsu and dextu in that
936 // the size range of dinsu is specified as 1 <= size <= 32 whereas size
937 // for dextu is 0 < size <= 32. The range checked for dinsu here is
938 // 0 < size <= 32, which is equivalent and similar to dextu.
939 return verifyInsExtInstruction(MI, ErrInfo, PosLow: 32, PosHigh: 64, SizeLow: 0, SizeHigh: 32, BothLow: 32, BothHigh: 64);
940 case Mips::DEXT:
941 return verifyInsExtInstruction(MI, ErrInfo, PosLow: 0, PosHigh: 32, SizeLow: 0, SizeHigh: 32, BothLow: 0, BothHigh: 63);
942 case Mips::DEXTM:
943 return verifyInsExtInstruction(MI, ErrInfo, PosLow: 0, PosHigh: 32, SizeLow: 32, SizeHigh: 64, BothLow: 32, BothHigh: 64);
944 case Mips::DEXTU:
945 return verifyInsExtInstruction(MI, ErrInfo, PosLow: 32, PosHigh: 64, SizeLow: 0, SizeHigh: 32, BothLow: 32, BothHigh: 64);
946 case Mips::TAILCALLREG:
947 case Mips::PseudoIndirectBranch:
948 case Mips::JR:
949 case Mips::JR64:
950 case Mips::JALR:
951 case Mips::JALR64:
952 case Mips::JALRPseudo:
953 if (!Subtarget.useIndirectJumpsHazard())
954 return true;
955
956 ErrInfo = "invalid instruction when using jump guards!";
957 return false;
958 default:
959 return true;
960 }
961
962 return true;
963}
964
965std::pair<unsigned, unsigned>
966MipsInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
967 return std::make_pair(x&: TF, y: 0u);
968}
969
970ArrayRef<std::pair<unsigned, const char*>>
971MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
972 using namespace MipsII;
973
974 static const std::pair<unsigned, const char*> Flags[] = {
975 {MO_GOT, "mips-got"},
976 {MO_GOT_CALL, "mips-got-call"},
977 {MO_GPREL, "mips-gprel"},
978 {MO_ABS_HI, "mips-abs-hi"},
979 {MO_ABS_LO, "mips-abs-lo"},
980 {MO_TLSGD, "mips-tlsgd"},
981 {MO_TLSLDM, "mips-tlsldm"},
982 {MO_DTPREL_HI, "mips-dtprel-hi"},
983 {MO_DTPREL_LO, "mips-dtprel-lo"},
984 {MO_GOTTPREL, "mips-gottprel"},
985 {MO_TPREL_HI, "mips-tprel-hi"},
986 {MO_TPREL_LO, "mips-tprel-lo"},
987 {MO_GPOFF_HI, "mips-gpoff-hi"},
988 {MO_GPOFF_LO, "mips-gpoff-lo"},
989 {MO_GOT_DISP, "mips-got-disp"},
990 {MO_GOT_PAGE, "mips-got-page"},
991 {MO_GOT_OFST, "mips-got-ofst"},
992 {MO_HIGHER, "mips-higher"},
993 {MO_HIGHEST, "mips-highest"},
994 {MO_GOT_HI16, "mips-got-hi16"},
995 {MO_GOT_LO16, "mips-got-lo16"},
996 {MO_CALL_HI16, "mips-call-hi16"},
997 {MO_CALL_LO16, "mips-call-lo16"},
998 {MO_JALR, "mips-jalr"}
999 };
1000 return ArrayRef(Flags);
1001}
1002
1003std::optional<ParamLoadedValue>
1004MipsInstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
1005 DIExpression *Expr =
1006 DIExpression::get(Context&: MI.getMF()->getFunction().getContext(), Elements: {});
1007
1008 // TODO: Special MIPS instructions that need to be described separately.
1009 if (auto RegImm = isAddImmediate(MI, Reg)) {
1010 Register SrcReg = RegImm->Reg;
1011 int64_t Offset = RegImm->Imm;
1012 // When SrcReg is $zero, treat loaded value as immediate only.
1013 // Ex. $a2 = ADDiu $zero, 10
1014 if (SrcReg == Mips::ZERO || SrcReg == Mips::ZERO_64) {
1015 return ParamLoadedValue(MI.getOperand(i: 2), Expr);
1016 }
1017 Expr = DIExpression::prepend(Expr, Flags: DIExpression::ApplyOffset, Offset);
1018 return ParamLoadedValue(MachineOperand::CreateReg(Reg: SrcReg, isDef: false), Expr);
1019 } else if (auto DestSrc = isCopyInstr(MI)) {
1020 const MachineFunction *MF = MI.getMF();
1021 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
1022 Register DestReg = DestSrc->Destination->getReg();
1023 // TODO: Handle cases where the Reg is sub- or super-register of the
1024 // DestReg.
1025 if (TRI->isSuperRegister(RegA: Reg, RegB: DestReg) || TRI->isSubRegister(RegA: Reg, RegB: DestReg))
1026 return std::nullopt;
1027 }
1028
1029 return TargetInstrInfo::describeLoadedValue(MI, Reg);
1030}
1031
1032std::optional<RegImmPair> MipsInstrInfo::isAddImmediate(const MachineInstr &MI,
1033 Register Reg) const {
1034 // TODO: Handle cases where Reg is a super- or sub-register of the
1035 // destination register.
1036 const MachineOperand &Op0 = MI.getOperand(i: 0);
1037 if (!Op0.isReg() || Reg != Op0.getReg())
1038 return std::nullopt;
1039
1040 switch (MI.getOpcode()) {
1041 case Mips::ADDiu:
1042 case Mips::DADDiu: {
1043 const MachineOperand &Dop = MI.getOperand(i: 0);
1044 const MachineOperand &Sop1 = MI.getOperand(i: 1);
1045 const MachineOperand &Sop2 = MI.getOperand(i: 2);
1046 // Value is sum of register and immediate. Immediate value could be
1047 // global string address which is not supported.
1048 if (Dop.isReg() && Sop1.isReg() && Sop2.isImm())
1049 return RegImmPair{Sop1.getReg(), Sop2.getImm()};
1050 // TODO: Handle case where Sop1 is a frame-index.
1051 }
1052 }
1053 return std::nullopt;
1054}
1055