1//===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that Mips uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsISelLowering.h"
15#include "MCTargetDesc/MipsBaseInfo.h"
16#include "MCTargetDesc/MipsInstPrinter.h"
17#include "MCTargetDesc/MipsMCTargetDesc.h"
18#include "MipsCCState.h"
19#include "MipsInstrInfo.h"
20#include "MipsMachineFunction.h"
21#include "MipsRegisterInfo.h"
22#include "MipsSubtarget.h"
23#include "MipsTargetMachine.h"
24#include "MipsTargetObjectFile.h"
25#include "llvm/ADT/APFloat.h"
26#include "llvm/ADT/ArrayRef.h"
27#include "llvm/ADT/SmallVector.h"
28#include "llvm/ADT/Statistic.h"
29#include "llvm/ADT/StringRef.h"
30#include "llvm/ADT/StringSwitch.h"
31#include "llvm/CodeGen/CallingConvLower.h"
32#include "llvm/CodeGen/FunctionLoweringInfo.h"
33#include "llvm/CodeGen/ISDOpcodes.h"
34#include "llvm/CodeGen/MachineBasicBlock.h"
35#include "llvm/CodeGen/MachineFrameInfo.h"
36#include "llvm/CodeGen/MachineFunction.h"
37#include "llvm/CodeGen/MachineInstr.h"
38#include "llvm/CodeGen/MachineInstrBuilder.h"
39#include "llvm/CodeGen/MachineJumpTableInfo.h"
40#include "llvm/CodeGen/MachineMemOperand.h"
41#include "llvm/CodeGen/MachineOperand.h"
42#include "llvm/CodeGen/MachineRegisterInfo.h"
43#include "llvm/CodeGen/SelectionDAG.h"
44#include "llvm/CodeGen/SelectionDAGNodes.h"
45#include "llvm/CodeGen/TargetFrameLowering.h"
46#include "llvm/CodeGen/TargetInstrInfo.h"
47#include "llvm/CodeGen/TargetRegisterInfo.h"
48#include "llvm/CodeGen/ValueTypes.h"
49#include "llvm/CodeGenTypes/MachineValueType.h"
50#include "llvm/IR/CallingConv.h"
51#include "llvm/IR/Constants.h"
52#include "llvm/IR/DataLayout.h"
53#include "llvm/IR/DebugLoc.h"
54#include "llvm/IR/DerivedTypes.h"
55#include "llvm/IR/Function.h"
56#include "llvm/IR/GlobalValue.h"
57#include "llvm/IR/Module.h"
58#include "llvm/IR/Type.h"
59#include "llvm/IR/Value.h"
60#include "llvm/MC/MCContext.h"
61#include "llvm/Support/Casting.h"
62#include "llvm/Support/CodeGen.h"
63#include "llvm/Support/CommandLine.h"
64#include "llvm/Support/Compiler.h"
65#include "llvm/Support/ErrorHandling.h"
66#include "llvm/Support/MathExtras.h"
67#include "llvm/Target/TargetMachine.h"
68#include "llvm/Target/TargetOptions.h"
69#include <algorithm>
70#include <cassert>
71#include <cctype>
72#include <cstdint>
73#include <deque>
74#include <iterator>
75#include <utility>
76#include <vector>
77
78using namespace llvm;
79
80#define DEBUG_TYPE "mips-lower"
81
82STATISTIC(NumTailCalls, "Number of tail calls");
83
84static cl::opt<bool>
85NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
86 cl::desc("MIPS: Don't trap on integer division by zero."),
87 cl::init(Val: false));
88
89extern cl::opt<bool> EmitJalrReloc;
90
91static const MCPhysReg Mips64DPRegs[8] = {
92 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
93 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
94};
95
96// The MIPS MSA ABI passes vector arguments in the integer register set.
97// The number of integer registers used is dependant on the ABI used.
98MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
99 CallingConv::ID CC,
100 EVT VT) const {
101 if (!VT.isVector())
102 return getRegisterType(Context, VT);
103
104 if (VT.isPow2VectorType() && VT.getVectorElementType().isRound())
105 return Subtarget.isABI_O32() || VT.getSizeInBits() == 32 ? MVT::i32
106 : MVT::i64;
107 return getRegisterType(Context, VT: VT.getVectorElementType());
108}
109
110unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
111 CallingConv::ID CC,
112 EVT VT) const {
113 if (VT.isVector()) {
114 if (VT.isPow2VectorType() && VT.getVectorElementType().isRound())
115 return divideCeil(Numerator: VT.getSizeInBits(), Denominator: Subtarget.isABI_O32() ? 32 : 64);
116 return VT.getVectorNumElements() *
117 getNumRegisters(Context, VT: VT.getVectorElementType());
118 }
119 return MipsTargetLowering::getNumRegisters(Context, VT);
120}
121
122unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv(
123 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
124 unsigned &NumIntermediates, MVT &RegisterVT) const {
125 if (VT.isPow2VectorType() && VT.getVectorElementType().isRound()) {
126 IntermediateVT = getRegisterTypeForCallingConv(Context, CC, VT);
127 RegisterVT = IntermediateVT.getSimpleVT();
128 NumIntermediates = getNumRegistersForCallingConv(Context, CC, VT);
129 return NumIntermediates;
130 }
131 IntermediateVT = VT.getVectorElementType();
132 NumIntermediates = VT.getVectorNumElements();
133 RegisterVT = getRegisterType(Context, VT: IntermediateVT);
134 return NumIntermediates * getNumRegisters(Context, VT: IntermediateVT);
135}
136
137SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
138 MachineFunction &MF = DAG.getMachineFunction();
139 MipsFunctionInfo *FI = MF.getInfo<MipsFunctionInfo>();
140 return DAG.getRegister(Reg: FI->getGlobalBaseReg(MF), VT: Ty);
141}
142
143SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
144 SelectionDAG &DAG,
145 unsigned Flag) const {
146 return DAG.getTargetGlobalAddress(GV: N->getGlobal(), DL: SDLoc(N), VT: Ty, offset: 0, TargetFlags: Flag);
147}
148
149SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
150 SelectionDAG &DAG,
151 unsigned Flag) const {
152 return DAG.getTargetExternalSymbol(Sym: N->getSymbol(), VT: Ty, TargetFlags: Flag);
153}
154
155SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
156 SelectionDAG &DAG,
157 unsigned Flag) const {
158 return DAG.getTargetBlockAddress(BA: N->getBlockAddress(), VT: Ty, Offset: 0, TargetFlags: Flag);
159}
160
161SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
162 SelectionDAG &DAG,
163 unsigned Flag) const {
164 return DAG.getTargetJumpTable(JTI: N->getIndex(), VT: Ty, TargetFlags: Flag);
165}
166
167SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
168 SelectionDAG &DAG,
169 unsigned Flag) const {
170 return DAG.getTargetConstantPool(C: N->getConstVal(), VT: Ty, Align: N->getAlign(),
171 Offset: N->getOffset(), TargetFlags: Flag);
172}
173
174const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
175 switch ((MipsISD::NodeType)Opcode) {
176 case MipsISD::FIRST_NUMBER: break;
177 case MipsISD::JmpLink: return "MipsISD::JmpLink";
178 case MipsISD::TailCall: return "MipsISD::TailCall";
179 case MipsISD::Highest: return "MipsISD::Highest";
180 case MipsISD::Higher: return "MipsISD::Higher";
181 case MipsISD::Hi: return "MipsISD::Hi";
182 case MipsISD::Lo: return "MipsISD::Lo";
183 case MipsISD::GotHi: return "MipsISD::GotHi";
184 case MipsISD::TlsHi: return "MipsISD::TlsHi";
185 case MipsISD::GPRel: return "MipsISD::GPRel";
186 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
187 case MipsISD::Ret: return "MipsISD::Ret";
188 case MipsISD::ERet: return "MipsISD::ERet";
189 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
190 case MipsISD::FAbs: return "MipsISD::FAbs";
191 case MipsISD::FMS: return "MipsISD::FMS";
192 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
193 case MipsISD::FPCmp: return "MipsISD::FPCmp";
194 case MipsISD::FSELECT: return "MipsISD::FSELECT";
195 case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64";
196 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
197 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
198 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
199 case MipsISD::MFHI: return "MipsISD::MFHI";
200 case MipsISD::MFLO: return "MipsISD::MFLO";
201 case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
202 case MipsISD::Mult: return "MipsISD::Mult";
203 case MipsISD::Multu: return "MipsISD::Multu";
204 case MipsISD::MAdd: return "MipsISD::MAdd";
205 case MipsISD::MAddu: return "MipsISD::MAddu";
206 case MipsISD::MSub: return "MipsISD::MSub";
207 case MipsISD::MSubu: return "MipsISD::MSubu";
208 case MipsISD::DivRem: return "MipsISD::DivRem";
209 case MipsISD::DivRemU: return "MipsISD::DivRemU";
210 case MipsISD::DivRem16: return "MipsISD::DivRem16";
211 case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
212 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
213 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
214 case MipsISD::Wrapper: return "MipsISD::Wrapper";
215 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
216 case MipsISD::Sync: return "MipsISD::Sync";
217 case MipsISD::Ext: return "MipsISD::Ext";
218 case MipsISD::Ins: return "MipsISD::Ins";
219 case MipsISD::CIns: return "MipsISD::CIns";
220 case MipsISD::LWL: return "MipsISD::LWL";
221 case MipsISD::LWR: return "MipsISD::LWR";
222 case MipsISD::SWL: return "MipsISD::SWL";
223 case MipsISD::SWR: return "MipsISD::SWR";
224 case MipsISD::LDL: return "MipsISD::LDL";
225 case MipsISD::LDR: return "MipsISD::LDR";
226 case MipsISD::SDL: return "MipsISD::SDL";
227 case MipsISD::SDR: return "MipsISD::SDR";
228 case MipsISD::EXTP: return "MipsISD::EXTP";
229 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
230 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
231 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
232 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
233 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
234 case MipsISD::SHILO: return "MipsISD::SHILO";
235 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
236 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH";
237 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL";
238 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR";
239 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL";
240 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR";
241 case MipsISD::DOUBLE_SELECT_I: return "MipsISD::DOUBLE_SELECT_I";
242 case MipsISD::DOUBLE_SELECT_I64: return "MipsISD::DOUBLE_SELECT_I64";
243 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL";
244 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR";
245 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL";
246 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR";
247 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH";
248 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH";
249 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W";
250 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W";
251 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH";
252 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH";
253 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH";
254 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH";
255 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH";
256 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH";
257 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH";
258 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH";
259 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH";
260 case MipsISD::MULT: return "MipsISD::MULT";
261 case MipsISD::MULTU: return "MipsISD::MULTU";
262 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
263 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
264 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
265 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
266 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
267 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
268 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
269 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
270 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
271 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
272 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
273 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
274 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
275 case MipsISD::VCEQ: return "MipsISD::VCEQ";
276 case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
277 case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
278 case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
279 case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
280 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
281 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
282 case MipsISD::VNOR: return "MipsISD::VNOR";
283 case MipsISD::VSHF: return "MipsISD::VSHF";
284 case MipsISD::SHF: return "MipsISD::SHF";
285 case MipsISD::ILVEV: return "MipsISD::ILVEV";
286 case MipsISD::ILVOD: return "MipsISD::ILVOD";
287 case MipsISD::ILVL: return "MipsISD::ILVL";
288 case MipsISD::ILVR: return "MipsISD::ILVR";
289 case MipsISD::PCKEV: return "MipsISD::PCKEV";
290 case MipsISD::PCKOD: return "MipsISD::PCKOD";
291 case MipsISD::INSVE: return "MipsISD::INSVE";
292 }
293 return nullptr;
294}
295
296MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
297 const MipsSubtarget &STI)
298 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
299 // Mips does not have i1 type, so use i32 for
300 // setcc operations results (slt, sgt, ...).
301 setBooleanContents(ZeroOrOneBooleanContent);
302 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
303 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
304 // does. Integer booleans still use 0 and 1.
305 if (Subtarget.hasMips32r6())
306 setBooleanContents(IntTy: ZeroOrOneBooleanContent,
307 FloatTy: ZeroOrNegativeOneBooleanContent);
308
309 // Load extented operations for i1 types must be promoted
310 for (MVT VT : MVT::integer_valuetypes()) {
311 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::i1, Action: Promote);
312 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: VT, MemVT: MVT::i1, Action: Promote);
313 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: VT, MemVT: MVT::i1, Action: Promote);
314 }
315
316 // MIPS doesn't have extending float->double load/store. Set LoadExtAction
317 // for f32, f16
318 for (MVT VT : MVT::fp_valuetypes()) {
319 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::f32, Action: Expand);
320 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::f16, Action: Expand);
321 }
322
323 // Set LoadExtAction for f16 vectors to Expand
324 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) {
325 MVT F16VT = MVT::getVectorVT(VT: MVT::f16, NumElements: VT.getVectorNumElements());
326 if (F16VT.isValid())
327 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: F16VT, Action: Expand);
328 }
329
330 setTruncStoreAction(ValVT: MVT::f32, MemVT: MVT::f16, Action: Expand);
331 setTruncStoreAction(ValVT: MVT::f64, MemVT: MVT::f16, Action: Expand);
332
333 setTruncStoreAction(ValVT: MVT::f64, MemVT: MVT::f32, Action: Expand);
334
335 // Used by legalize types to correctly generate the setcc result.
336 // Without this, every float setcc comes with a AND/OR with the result,
337 // we don't want this, since the fpcmp result goes to a flag register,
338 // which is used implicitly by brcond and select operations.
339 AddPromotedToType(Opc: ISD::SETCC, OrigVT: MVT::i1, DestVT: MVT::i32);
340
341 // Mips Custom Operations
342 setOperationAction(Op: ISD::BR_JT, VT: MVT::Other, Action: Expand);
343 setOperationAction(Op: ISD::GlobalAddress, VT: MVT::i32, Action: Custom);
344 setOperationAction(Op: ISD::BlockAddress, VT: MVT::i32, Action: Custom);
345 setOperationAction(Op: ISD::GlobalTLSAddress, VT: MVT::i32, Action: Custom);
346 setOperationAction(Op: ISD::JumpTable, VT: MVT::i32, Action: Custom);
347 setOperationAction(Op: ISD::ConstantPool, VT: MVT::i32, Action: Custom);
348 setOperationAction(Op: ISD::SELECT, VT: MVT::f32, Action: Custom);
349 setOperationAction(Op: ISD::SELECT, VT: MVT::f64, Action: Custom);
350 setOperationAction(Op: ISD::SELECT, VT: MVT::i32, Action: Custom);
351 setOperationAction(Op: ISD::SETCC, VT: MVT::f32, Action: Custom);
352 setOperationAction(Op: ISD::SETCC, VT: MVT::f64, Action: Custom);
353 setOperationAction(Op: ISD::BRCOND, VT: MVT::Other, Action: Custom);
354 setOperationAction(Op: ISD::FABS, VT: MVT::f32, Action: Custom);
355 setOperationAction(Op: ISD::FABS, VT: MVT::f64, Action: Custom);
356 setOperationAction(Op: ISD::FCOPYSIGN, VT: MVT::f32, Action: Custom);
357 setOperationAction(Op: ISD::FCOPYSIGN, VT: MVT::f64, Action: Custom);
358 setOperationAction(Op: ISD::FP_TO_SINT, VT: MVT::i32, Action: Custom);
359
360 if (Subtarget.hasMips32r2() ||
361 getTargetMachine().getTargetTriple().isOSLinux())
362 setOperationAction(Op: ISD::READCYCLECOUNTER, VT: MVT::i64, Action: Custom);
363
364 // Lower fmin/fmax/fclass operations for MIPS R6.
365 if (Subtarget.hasMips32r6()) {
366 setOperationAction(Op: ISD::FMINNUM_IEEE, VT: MVT::f32, Action: Legal);
367 setOperationAction(Op: ISD::FMAXNUM_IEEE, VT: MVT::f32, Action: Legal);
368 setOperationAction(Op: ISD::FMINNUM, VT: MVT::f32, Action: Legal);
369 setOperationAction(Op: ISD::FMAXNUM, VT: MVT::f32, Action: Legal);
370 setOperationAction(Op: ISD::FMINNUM_IEEE, VT: MVT::f64, Action: Legal);
371 setOperationAction(Op: ISD::FMAXNUM_IEEE, VT: MVT::f64, Action: Legal);
372 setOperationAction(Op: ISD::FMINNUM, VT: MVT::f64, Action: Legal);
373 setOperationAction(Op: ISD::FMAXNUM, VT: MVT::f64, Action: Legal);
374 setOperationAction(Op: ISD::IS_FPCLASS, VT: MVT::f32, Action: Legal);
375 setOperationAction(Op: ISD::IS_FPCLASS, VT: MVT::f64, Action: Legal);
376 } else {
377 setOperationAction(Op: ISD::FCANONICALIZE, VT: MVT::f32, Action: Custom);
378 setOperationAction(Op: ISD::FCANONICALIZE, VT: MVT::f64, Action: Custom);
379 }
380
381 if (Subtarget.isGP64bit()) {
382 setOperationAction(Op: ISD::GlobalAddress, VT: MVT::i64, Action: Custom);
383 setOperationAction(Op: ISD::BlockAddress, VT: MVT::i64, Action: Custom);
384 setOperationAction(Op: ISD::GlobalTLSAddress, VT: MVT::i64, Action: Custom);
385 setOperationAction(Op: ISD::JumpTable, VT: MVT::i64, Action: Custom);
386 setOperationAction(Op: ISD::ConstantPool, VT: MVT::i64, Action: Custom);
387 setOperationAction(Op: ISD::SELECT, VT: MVT::i64, Action: Custom);
388 if (Subtarget.hasMips64r6()) {
389 setOperationAction(Op: ISD::LOAD, VT: MVT::i64, Action: Legal);
390 setOperationAction(Op: ISD::STORE, VT: MVT::i64, Action: Legal);
391 } else {
392 setOperationAction(Op: ISD::LOAD, VT: MVT::i64, Action: Custom);
393 setOperationAction(Op: ISD::STORE, VT: MVT::i64, Action: Custom);
394 }
395 setOperationAction(Op: ISD::FP_TO_SINT, VT: MVT::i64, Action: Custom);
396 setOperationAction(Op: ISD::SHL_PARTS, VT: MVT::i64, Action: Custom);
397 setOperationAction(Op: ISD::SRA_PARTS, VT: MVT::i64, Action: Custom);
398 setOperationAction(Op: ISD::SRL_PARTS, VT: MVT::i64, Action: Custom);
399 }
400
401 if (!Subtarget.isGP64bit()) {
402 setOperationAction(Op: ISD::SHL_PARTS, VT: MVT::i32, Action: Custom);
403 setOperationAction(Op: ISD::SRA_PARTS, VT: MVT::i32, Action: Custom);
404 setOperationAction(Op: ISD::SRL_PARTS, VT: MVT::i32, Action: Custom);
405 }
406
407 setOperationAction(Op: ISD::EH_DWARF_CFA, VT: MVT::i32, Action: Custom);
408 if (Subtarget.isGP64bit())
409 setOperationAction(Op: ISD::EH_DWARF_CFA, VT: MVT::i64, Action: Custom);
410
411 setOperationAction(Op: ISD::SDIV, VT: MVT::i32, Action: Expand);
412 setOperationAction(Op: ISD::SREM, VT: MVT::i32, Action: Expand);
413 setOperationAction(Op: ISD::UDIV, VT: MVT::i32, Action: Expand);
414 setOperationAction(Op: ISD::UREM, VT: MVT::i32, Action: Expand);
415 setOperationAction(Op: ISD::SDIV, VT: MVT::i64, Action: Expand);
416 setOperationAction(Op: ISD::SREM, VT: MVT::i64, Action: Expand);
417 setOperationAction(Op: ISD::UDIV, VT: MVT::i64, Action: Expand);
418 setOperationAction(Op: ISD::UREM, VT: MVT::i64, Action: Expand);
419
420 // Operations not directly supported by Mips.
421 setOperationAction(Op: ISD::BR_CC, VT: MVT::f32, Action: Expand);
422 setOperationAction(Op: ISD::BR_CC, VT: MVT::f64, Action: Expand);
423 setOperationAction(Op: ISD::BR_CC, VT: MVT::i32, Action: Expand);
424 setOperationAction(Op: ISD::BR_CC, VT: MVT::i64, Action: Expand);
425 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i32, Action: Expand);
426 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i64, Action: Expand);
427 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::f32, Action: Expand);
428 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::f64, Action: Expand);
429 setOperationAction(Op: ISD::UINT_TO_FP, VT: MVT::i32, Action: Expand);
430 setOperationAction(Op: ISD::UINT_TO_FP, VT: MVT::i64, Action: Expand);
431 setOperationAction(Op: ISD::FP_TO_UINT, VT: MVT::i32, Action: Expand);
432 setOperationAction(Op: ISD::FP_TO_UINT, VT: MVT::i64, Action: Expand);
433 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i1, Action: Expand);
434 if (Subtarget.hasCnMips()) {
435 setOperationAction(Op: ISD::CTPOP, VT: MVT::i32, Action: Legal);
436 setOperationAction(Op: ISD::CTPOP, VT: MVT::i64, Action: Legal);
437 } else {
438 setOperationAction(Op: ISD::CTPOP, VT: MVT::i32, Action: Expand);
439 setOperationAction(Op: ISD::CTPOP, VT: MVT::i64, Action: Expand);
440 }
441 setOperationAction(Op: ISD::CTTZ, VT: MVT::i32, Action: Expand);
442 setOperationAction(Op: ISD::CTTZ, VT: MVT::i64, Action: Expand);
443 setOperationAction(Op: ISD::ROTL, VT: MVT::i32, Action: Expand);
444 setOperationAction(Op: ISD::ROTL, VT: MVT::i64, Action: Expand);
445 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i32, Action: Expand);
446 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i64, Action: Expand);
447
448 if (!Subtarget.hasMips32r2())
449 setOperationAction(Op: ISD::ROTR, VT: MVT::i32, Action: Expand);
450
451 if (!Subtarget.hasMips64r2())
452 setOperationAction(Op: ISD::ROTR, VT: MVT::i64, Action: Expand);
453
454 setOperationAction(Op: ISD::FSIN, VT: MVT::f32, Action: Expand);
455 setOperationAction(Op: ISD::FSIN, VT: MVT::f64, Action: Expand);
456 setOperationAction(Op: ISD::FCOS, VT: MVT::f32, Action: Expand);
457 setOperationAction(Op: ISD::FCOS, VT: MVT::f64, Action: Expand);
458 setOperationAction(Op: ISD::FSINCOS, VT: MVT::f32, Action: Expand);
459 setOperationAction(Op: ISD::FSINCOS, VT: MVT::f64, Action: Expand);
460 setOperationAction(Op: ISD::FPOW, VT: MVT::f32, Action: Expand);
461 setOperationAction(Op: ISD::FPOW, VT: MVT::f64, Action: Expand);
462 setOperationAction(Op: ISD::FLOG, VT: MVT::f32, Action: Expand);
463 setOperationAction(Op: ISD::FLOG2, VT: MVT::f32, Action: Expand);
464 setOperationAction(Op: ISD::FLOG10, VT: MVT::f32, Action: Expand);
465 setOperationAction(Op: ISD::FEXP, VT: MVT::f32, Action: Expand);
466 setOperationAction(Op: ISD::FMA, VT: MVT::f32, Action: Expand);
467 setOperationAction(Op: ISD::FMA, VT: MVT::f64, Action: Expand);
468 setOperationAction(Op: ISD::FREM, VT: MVT::f32, Action: Expand);
469 setOperationAction(Op: ISD::FREM, VT: MVT::f64, Action: Expand);
470
471 // Lower f16 conversion operations into library calls
472 setOperationAction(Op: ISD::FP16_TO_FP, VT: MVT::f32, Action: Expand);
473 setOperationAction(Op: ISD::FP_TO_FP16, VT: MVT::f32, Action: Expand);
474 setOperationAction(Op: ISD::FP16_TO_FP, VT: MVT::f64, Action: Expand);
475 setOperationAction(Op: ISD::FP_TO_FP16, VT: MVT::f64, Action: Expand);
476
477 setOperationAction(Op: ISD::EH_RETURN, VT: MVT::Other, Action: Custom);
478
479 setOperationAction(Op: ISD::VASTART, VT: MVT::Other, Action: Custom);
480 setOperationAction(Op: ISD::VAARG, VT: MVT::Other, Action: Custom);
481 setOperationAction(Op: ISD::VACOPY, VT: MVT::Other, Action: Expand);
482 setOperationAction(Op: ISD::VAEND, VT: MVT::Other, Action: Expand);
483
484 // Use the default for now
485 setOperationAction(Op: ISD::STACKSAVE, VT: MVT::Other, Action: Expand);
486 setOperationAction(Op: ISD::STACKRESTORE, VT: MVT::Other, Action: Expand);
487
488 if (!Subtarget.isGP64bit()) {
489 setOperationAction(Op: ISD::ATOMIC_LOAD, VT: MVT::i64, Action: Expand);
490 setOperationAction(Op: ISD::ATOMIC_STORE, VT: MVT::i64, Action: Expand);
491 }
492
493 if (!Subtarget.hasMips32r2()) {
494 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i8, Action: Expand);
495 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i16, Action: Expand);
496 }
497
498 // MIPS16 lacks MIPS32's clz and clo instructions.
499 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode())
500 setOperationAction(Op: ISD::CTLZ, VT: MVT::i32, Action: Expand);
501 if (!Subtarget.hasMips64())
502 setOperationAction(Op: ISD::CTLZ, VT: MVT::i64, Action: Expand);
503
504 if (!Subtarget.hasMips32r2())
505 setOperationAction(Op: ISD::BSWAP, VT: MVT::i32, Action: Expand);
506 if (!Subtarget.hasMips64r2())
507 setOperationAction(Op: ISD::BSWAP, VT: MVT::i64, Action: Expand);
508
509 if (Subtarget.isGP64bit() && Subtarget.hasMips64r6()) {
510 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: MVT::i64, MemVT: MVT::i32, Action: Legal);
511 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: MVT::i64, MemVT: MVT::i32, Action: Legal);
512 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: MVT::i64, MemVT: MVT::i32, Action: Legal);
513 setTruncStoreAction(ValVT: MVT::i64, MemVT: MVT::i32, Action: Legal);
514 } else if (Subtarget.isGP64bit()) {
515 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: MVT::i64, MemVT: MVT::i32, Action: Custom);
516 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: MVT::i64, MemVT: MVT::i32, Action: Custom);
517 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: MVT::i64, MemVT: MVT::i32, Action: Custom);
518 setTruncStoreAction(ValVT: MVT::i64, MemVT: MVT::i32, Action: Custom);
519 }
520
521 setOperationAction(Op: ISD::TRAP, VT: MVT::Other, Action: Legal);
522
523 setOperationAction(Op: ISD::ConstantFP, VT: MVT::f32, Action: Custom);
524 setOperationAction(Op: ISD::ConstantFP, VT: MVT::f64, Action: Custom);
525
526 setTargetDAGCombine({ISD::SDIVREM, ISD::UDIVREM, ISD::SELECT, ISD::AND,
527 ISD::OR, ISD::ADD, ISD::SUB, ISD::AssertZext, ISD::SHL,
528 ISD::SIGN_EXTEND});
529
530 if (Subtarget.isGP64bit())
531 setMaxAtomicSizeInBitsSupported(64);
532 else
533 setMaxAtomicSizeInBitsSupported(32);
534
535 setMinFunctionAlignment(Subtarget.isGP64bit() ? Align(8) : Align(4));
536
537 // The arguments on the stack are defined in terms of 4-byte slots on O32
538 // and 8-byte slots on N32/N64.
539 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? Align(8)
540 : Align(4));
541
542 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
543
544 MaxStoresPerMemcpy = 16;
545
546 isMicroMips = Subtarget.inMicroMipsMode();
547}
548
549const MipsTargetLowering *
550MipsTargetLowering::create(const MipsTargetMachine &TM,
551 const MipsSubtarget &STI) {
552 if (STI.inMips16Mode())
553 return createMips16TargetLowering(TM, STI);
554
555 return createMipsSETargetLowering(TM, STI);
556}
557
558// Create a fast isel object.
559FastISel *
560MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
561 const TargetLibraryInfo *libInfo) const {
562 const MipsTargetMachine &TM =
563 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget());
564
565 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs.
566 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() &&
567 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() &&
568 !Subtarget.inMicroMipsMode();
569
570 // Disable if either of the following is true:
571 // We do not generate PIC, the ABI is not O32, XGOT is being used.
572 if (!TM.isPositionIndependent() || !TM.getABI().IsO32() ||
573 Subtarget.useXGOT())
574 UseFastISel = false;
575
576 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr;
577}
578
579EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
580 EVT VT) const {
581 if (!VT.isVector())
582 return MVT::i32;
583 return VT.changeVectorElementTypeToInteger();
584}
585
586static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
587 TargetLowering::DAGCombinerInfo &DCI,
588 const MipsSubtarget &Subtarget) {
589 if (DCI.isBeforeLegalizeOps())
590 return SDValue();
591
592 EVT Ty = N->getValueType(ResNo: 0);
593 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
594 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
595 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
596 MipsISD::DivRemU16;
597 SDLoc DL(N);
598
599 SDValue DivRem = DAG.getNode(Opcode: Opc, DL, VT: MVT::Glue,
600 N1: N->getOperand(Num: 0), N2: N->getOperand(Num: 1));
601 SDValue InChain = DAG.getEntryNode();
602 SDValue InGlue = DivRem;
603
604 // insert MFLO
605 if (N->hasAnyUseOfValue(Value: 0)) {
606 SDValue CopyFromLo = DAG.getCopyFromReg(Chain: InChain, dl: DL, Reg: LO, VT: Ty,
607 Glue: InGlue);
608 DAG.ReplaceAllUsesOfValueWith(From: SDValue(N, 0), To: CopyFromLo);
609 InChain = CopyFromLo.getValue(R: 1);
610 InGlue = CopyFromLo.getValue(R: 2);
611 }
612
613 // insert MFHI
614 if (N->hasAnyUseOfValue(Value: 1)) {
615 SDValue CopyFromHi = DAG.getCopyFromReg(Chain: InChain, dl: DL,
616 Reg: HI, VT: Ty, Glue: InGlue);
617 DAG.ReplaceAllUsesOfValueWith(From: SDValue(N, 1), To: CopyFromHi);
618 }
619
620 return SDValue();
621}
622
623static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
624 switch (CC) {
625 default: llvm_unreachable("Unknown fp condition code!");
626 case ISD::SETEQ:
627 case ISD::SETOEQ: return Mips::FCOND_OEQ;
628 case ISD::SETUNE: return Mips::FCOND_UNE;
629 case ISD::SETLT:
630 case ISD::SETOLT: return Mips::FCOND_OLT;
631 case ISD::SETGT:
632 case ISD::SETOGT: return Mips::FCOND_OGT;
633 case ISD::SETLE:
634 case ISD::SETOLE: return Mips::FCOND_OLE;
635 case ISD::SETGE:
636 case ISD::SETOGE: return Mips::FCOND_OGE;
637 case ISD::SETULT: return Mips::FCOND_ULT;
638 case ISD::SETULE: return Mips::FCOND_ULE;
639 case ISD::SETUGT: return Mips::FCOND_UGT;
640 case ISD::SETUGE: return Mips::FCOND_UGE;
641 case ISD::SETUO: return Mips::FCOND_UN;
642 case ISD::SETO: return Mips::FCOND_OR;
643 case ISD::SETNE:
644 case ISD::SETONE: return Mips::FCOND_ONE;
645 case ISD::SETUEQ: return Mips::FCOND_UEQ;
646 }
647}
648
649/// This function returns true if the floating point conditional branches and
650/// conditional moves which use condition code CC should be inverted.
651static bool invertFPCondCodeUser(Mips::CondCode CC) {
652 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
653 return false;
654
655 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
656 "Illegal Condition Code");
657
658 return true;
659}
660
661// Creates and returns an FPCmp node from a setcc node.
662// Returns Op if setcc is not a floating point comparison.
663static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
664 // must be a SETCC node
665 if (Op.getOpcode() != ISD::SETCC)
666 return Op;
667
668 SDValue LHS = Op.getOperand(i: 0);
669
670 if (!LHS.getValueType().isFloatingPoint())
671 return Op;
672
673 SDValue RHS = Op.getOperand(i: 1);
674 SDLoc DL(Op);
675
676 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
677 // node if necessary.
678 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 2))->get();
679
680 return DAG.getNode(Opcode: MipsISD::FPCmp, DL, VT: MVT::Glue, N1: LHS, N2: RHS,
681 N3: DAG.getConstant(Val: condCodeToFCC(CC), DL, VT: MVT::i32));
682}
683
684// Creates and returns a CMovFPT/F node.
685static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
686 SDValue False, const SDLoc &DL) {
687 ConstantSDNode *CC = cast<ConstantSDNode>(Val: Cond.getOperand(i: 2));
688 bool invert = invertFPCondCodeUser(CC: (Mips::CondCode)CC->getSExtValue());
689 SDValue FCC0 = DAG.getRegister(Reg: Mips::FCC0, VT: MVT::i32);
690
691 return DAG.getNode(Opcode: (invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
692 VT: True.getValueType(), N1: True, N2: FCC0, N3: False, N4: Cond);
693}
694
695static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
696 TargetLowering::DAGCombinerInfo &DCI,
697 const MipsSubtarget &Subtarget) {
698 if (DCI.isBeforeLegalizeOps())
699 return SDValue();
700
701 SDValue SetCC = N->getOperand(Num: 0);
702
703 if ((SetCC.getOpcode() != ISD::SETCC) ||
704 !SetCC.getOperand(i: 0).getValueType().isInteger())
705 return SDValue();
706
707 SDValue False = N->getOperand(Num: 2);
708 EVT FalseTy = False.getValueType();
709
710 if (!FalseTy.isInteger())
711 return SDValue();
712
713 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(Val&: False);
714
715 // If the RHS (False) is 0, we swap the order of the operands
716 // of ISD::SELECT (obviously also inverting the condition) so that we can
717 // take advantage of conditional moves using the $0 register.
718 // Example:
719 // return (a != 0) ? x : 0;
720 // load $reg, x
721 // movz $reg, $0, a
722 if (!FalseC)
723 return SDValue();
724
725 const SDLoc DL(N);
726
727 if (!FalseC->getZExtValue()) {
728 ISD::CondCode CC = cast<CondCodeSDNode>(Val: SetCC.getOperand(i: 2))->get();
729 SDValue True = N->getOperand(Num: 1);
730
731 SetCC = DAG.getSetCC(DL, VT: SetCC.getValueType(), LHS: SetCC.getOperand(i: 0),
732 RHS: SetCC.getOperand(i: 1),
733 Cond: ISD::getSetCCInverse(Operation: CC, Type: SetCC.getValueType()));
734
735 return DAG.getNode(Opcode: ISD::SELECT, DL, VT: FalseTy, N1: SetCC, N2: False, N3: True);
736 }
737
738 // If both operands are integer constants there's a possibility that we
739 // can do some interesting optimizations.
740 SDValue True = N->getOperand(Num: 1);
741 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(Val&: True);
742
743 if (!TrueC || !True.getValueType().isInteger())
744 return SDValue();
745
746 // We'll also ignore MVT::i64 operands as this optimizations proves
747 // to be ineffective because of the required sign extensions as the result
748 // of a SETCC operator is always MVT::i32 for non-vector types.
749 if (True.getValueType() == MVT::i64)
750 return SDValue();
751
752 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
753
754 // 1) (a < x) ? y : y-1
755 // slti $reg1, a, x
756 // addiu $reg2, $reg1, y-1
757 if (Diff == 1)
758 return DAG.getNode(Opcode: ISD::ADD, DL, VT: SetCC.getValueType(), N1: SetCC, N2: False);
759
760 // 2) (a < x) ? y-1 : y
761 // slti $reg1, a, x
762 // xor $reg1, $reg1, 1
763 // addiu $reg2, $reg1, y-1
764 if (Diff == -1) {
765 ISD::CondCode CC = cast<CondCodeSDNode>(Val: SetCC.getOperand(i: 2))->get();
766 SetCC = DAG.getSetCC(DL, VT: SetCC.getValueType(), LHS: SetCC.getOperand(i: 0),
767 RHS: SetCC.getOperand(i: 1),
768 Cond: ISD::getSetCCInverse(Operation: CC, Type: SetCC.getValueType()));
769 return DAG.getNode(Opcode: ISD::ADD, DL, VT: SetCC.getValueType(), N1: SetCC, N2: True);
770 }
771
772 // Could not optimize.
773 return SDValue();
774}
775
776static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
777 TargetLowering::DAGCombinerInfo &DCI,
778 const MipsSubtarget &Subtarget) {
779 if (DCI.isBeforeLegalizeOps())
780 return SDValue();
781
782 SDValue ValueIfTrue = N->getOperand(Num: 0), ValueIfFalse = N->getOperand(Num: 2);
783
784 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(Val&: ValueIfFalse);
785 if (!FalseC || FalseC->getZExtValue())
786 return SDValue();
787
788 // Since RHS (False) is 0, we swap the order of the True/False operands
789 // (obviously also inverting the condition) so that we can
790 // take advantage of conditional moves using the $0 register.
791 // Example:
792 // return (a != 0) ? x : 0;
793 // load $reg, x
794 // movz $reg, $0, a
795 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
796 MipsISD::CMovFP_T;
797
798 SDValue FCC = N->getOperand(Num: 1), Glue = N->getOperand(Num: 3);
799 return DAG.getNode(Opcode: Opc, DL: SDLoc(N), VT: ValueIfFalse.getValueType(),
800 N1: ValueIfFalse, N2: FCC, N3: ValueIfTrue, N4: Glue);
801}
802
803static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
804 TargetLowering::DAGCombinerInfo &DCI,
805 const MipsSubtarget &Subtarget) {
806 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
807 return SDValue();
808
809 SDValue FirstOperand = N->getOperand(Num: 0);
810 unsigned FirstOperandOpc = FirstOperand.getOpcode();
811 SDValue Mask = N->getOperand(Num: 1);
812 EVT ValTy = N->getValueType(ResNo: 0);
813 SDLoc DL(N);
814
815 uint64_t Pos = 0;
816 unsigned SMPos, SMSize;
817 ConstantSDNode *CN;
818 SDValue NewOperand;
819 unsigned Opc;
820
821 // Op's second operand must be a shifted mask.
822 if (!(CN = dyn_cast<ConstantSDNode>(Val&: Mask)) ||
823 !isShiftedMask_64(Value: CN->getZExtValue(), MaskIdx&: SMPos, MaskLen&: SMSize))
824 return SDValue();
825
826 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) {
827 // Pattern match EXT.
828 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
829 // => ext $dst, $src, pos, size
830
831 // The second operand of the shift must be an immediate.
832 if (!(CN = dyn_cast<ConstantSDNode>(Val: FirstOperand.getOperand(i: 1))))
833 return SDValue();
834
835 Pos = CN->getZExtValue();
836
837 // Return if the shifted mask does not start at bit 0 or the sum of its size
838 // and Pos exceeds the word's size.
839 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
840 return SDValue();
841
842 Opc = MipsISD::Ext;
843 NewOperand = FirstOperand.getOperand(i: 0);
844 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) {
845 // Pattern match CINS.
846 // $dst = and (shl $src , pos), mask
847 // => cins $dst, $src, pos, size
848 // mask is a shifted mask with consecutive 1's, pos = shift amount,
849 // size = population count.
850
851 // The second operand of the shift must be an immediate.
852 if (!(CN = dyn_cast<ConstantSDNode>(Val: FirstOperand.getOperand(i: 1))))
853 return SDValue();
854
855 Pos = CN->getZExtValue();
856
857 if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 ||
858 Pos + SMSize > ValTy.getSizeInBits())
859 return SDValue();
860
861 NewOperand = FirstOperand.getOperand(i: 0);
862 // SMSize is 'location' (position) in this case, not size.
863 SMSize--;
864 Opc = MipsISD::CIns;
865 } else {
866 // Pattern match EXT.
867 // $dst = and $src, (2**size - 1) , if size > 16
868 // => ext $dst, $src, pos, size , pos = 0
869
870 // If the mask is <= 0xffff, andi can be used instead.
871 if (CN->getZExtValue() <= 0xffff)
872 return SDValue();
873
874 // Return if the mask doesn't start at position 0.
875 if (SMPos)
876 return SDValue();
877
878 Opc = MipsISD::Ext;
879 NewOperand = FirstOperand;
880 }
881 return DAG.getNode(Opcode: Opc, DL, VT: ValTy, N1: NewOperand,
882 N2: DAG.getConstant(Val: Pos, DL, VT: MVT::i32),
883 N3: DAG.getConstant(Val: SMSize, DL, VT: MVT::i32));
884}
885
886static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
887 TargetLowering::DAGCombinerInfo &DCI,
888 const MipsSubtarget &Subtarget) {
889 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
890 return SDValue();
891
892 SDValue FirstOperand = N->getOperand(Num: 0), SecondOperand = N->getOperand(Num: 1);
893 unsigned SMPos0, SMSize0, SMPos1, SMSize1;
894 ConstantSDNode *CN, *CN1;
895
896 if ((FirstOperand.getOpcode() == ISD::AND &&
897 SecondOperand.getOpcode() == ISD::SHL) ||
898 (FirstOperand.getOpcode() == ISD::SHL &&
899 SecondOperand.getOpcode() == ISD::AND)) {
900 // Pattern match INS.
901 // $dst = or (and $src1, (2**size0 - 1)), (shl $src2, size0)
902 // ==> ins $src1, $src2, pos, size, pos = size0, size = 32 - pos;
903 // Or:
904 // $dst = or (shl $src2, size0), (and $src1, (2**size0 - 1))
905 // ==> ins $src1, $src2, pos, size, pos = size0, size = 32 - pos;
906 SDValue AndOperand0 = FirstOperand.getOpcode() == ISD::AND
907 ? FirstOperand.getOperand(i: 0)
908 : SecondOperand.getOperand(i: 0);
909 SDValue ShlOperand0 = FirstOperand.getOpcode() == ISD::AND
910 ? SecondOperand.getOperand(i: 0)
911 : FirstOperand.getOperand(i: 0);
912 SDValue AndMask = FirstOperand.getOpcode() == ISD::AND
913 ? FirstOperand.getOperand(i: 1)
914 : SecondOperand.getOperand(i: 1);
915 if (!(CN = dyn_cast<ConstantSDNode>(Val&: AndMask)) ||
916 !isShiftedMask_64(Value: CN->getZExtValue(), MaskIdx&: SMPos0, MaskLen&: SMSize0))
917 return SDValue();
918
919 SDValue ShlShift = FirstOperand.getOpcode() == ISD::AND
920 ? SecondOperand.getOperand(i: 1)
921 : FirstOperand.getOperand(i: 1);
922 if (!(CN = dyn_cast<ConstantSDNode>(Val&: ShlShift)))
923 return SDValue();
924 uint64_t ShlShiftValue = CN->getZExtValue();
925
926 if (SMPos0 != 0 || SMSize0 != ShlShiftValue)
927 return SDValue();
928
929 SDLoc DL(N);
930 EVT ValTy = N->getValueType(ResNo: 0);
931 SMPos1 = ShlShiftValue;
932 assert(SMPos1 < ValTy.getSizeInBits());
933 SMSize1 = (ValTy == MVT::i64 ? 64 : 32) - SMPos1;
934 return DAG.getNode(Opcode: MipsISD::Ins, DL, VT: ValTy, N1: ShlOperand0,
935 N2: DAG.getConstant(Val: SMPos1, DL, VT: MVT::i32),
936 N3: DAG.getConstant(Val: SMSize1, DL, VT: MVT::i32), N4: AndOperand0);
937 }
938
939 // See if Op's first operand matches (and $src1 , mask0).
940 if (FirstOperand.getOpcode() != ISD::AND)
941 return SDValue();
942
943 // Pattern match INS.
944 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
945 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
946 // => ins $dst, $src, size, pos, $src1
947 if (!(CN = dyn_cast<ConstantSDNode>(Val: FirstOperand.getOperand(i: 1))) ||
948 !isShiftedMask_64(Value: ~CN->getSExtValue(), MaskIdx&: SMPos0, MaskLen&: SMSize0))
949 return SDValue();
950
951 // See if Op's second operand matches (and (shl $src, pos), mask1).
952 if (SecondOperand.getOpcode() == ISD::AND &&
953 SecondOperand.getOperand(i: 0).getOpcode() == ISD::SHL) {
954
955 if (!(CN = dyn_cast<ConstantSDNode>(Val: SecondOperand.getOperand(i: 1))) ||
956 !isShiftedMask_64(Value: CN->getZExtValue(), MaskIdx&: SMPos1, MaskLen&: SMSize1))
957 return SDValue();
958
959 // The shift masks must have the same position and size.
960 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
961 return SDValue();
962
963 SDValue Shl = SecondOperand.getOperand(i: 0);
964
965 if (!(CN = dyn_cast<ConstantSDNode>(Val: Shl.getOperand(i: 1))))
966 return SDValue();
967
968 unsigned Shamt = CN->getZExtValue();
969
970 // Return if the shift amount and the first bit position of mask are not the
971 // same.
972 EVT ValTy = N->getValueType(ResNo: 0);
973 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
974 return SDValue();
975
976 SDLoc DL(N);
977 return DAG.getNode(Opcode: MipsISD::Ins, DL, VT: ValTy, N1: Shl.getOperand(i: 0),
978 N2: DAG.getConstant(Val: SMPos0, DL, VT: MVT::i32),
979 N3: DAG.getConstant(Val: SMSize0, DL, VT: MVT::i32),
980 N4: FirstOperand.getOperand(i: 0));
981 } else {
982 // Pattern match DINS.
983 // $dst = or (and $src, mask0), mask1
984 // where mask0 = ((1 << SMSize0) -1) << SMPos0
985 // => dins $dst, $src, pos, size
986 if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) &&
987 ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) ||
988 (SMSize0 + SMPos0 <= 32))) {
989 // Check if AND instruction has constant as argument
990 bool isConstCase = SecondOperand.getOpcode() != ISD::AND;
991 if (SecondOperand.getOpcode() == ISD::AND) {
992 if (!(CN1 = dyn_cast<ConstantSDNode>(Val: SecondOperand->getOperand(Num: 1))))
993 return SDValue();
994 } else {
995 if (!(CN1 = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 1))))
996 return SDValue();
997 }
998 // Don't generate INS if constant OR operand doesn't fit into bits
999 // cleared by constant AND operand.
1000 if (CN->getSExtValue() & CN1->getSExtValue())
1001 return SDValue();
1002
1003 SDLoc DL(N);
1004 EVT ValTy = N->getOperand(Num: 0)->getValueType(ResNo: 0);
1005 SDValue Const1;
1006 SDValue SrlX;
1007 if (!isConstCase) {
1008 Const1 = DAG.getConstant(Val: SMPos0, DL, VT: MVT::i32);
1009 SrlX = DAG.getNode(Opcode: ISD::SRL, DL, VT: SecondOperand->getValueType(ResNo: 0),
1010 N1: SecondOperand, N2: Const1);
1011 }
1012 return DAG.getNode(
1013 Opcode: MipsISD::Ins, DL, VT: N->getValueType(ResNo: 0),
1014 N1: isConstCase
1015 ? DAG.getSignedConstant(Val: CN1->getSExtValue() >> SMPos0, DL, VT: ValTy)
1016 : SrlX,
1017 N2: DAG.getConstant(Val: SMPos0, DL, VT: MVT::i32),
1018 N3: DAG.getConstant(Val: ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31
1019 : SMSize0,
1020 DL, VT: MVT::i32),
1021 N4: FirstOperand->getOperand(Num: 0));
1022 }
1023 return SDValue();
1024 }
1025}
1026
1027static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG,
1028 const MipsSubtarget &Subtarget) {
1029 // ROOTNode must have a multiplication as an operand for the match to be
1030 // successful.
1031 if (ROOTNode->getOperand(Num: 0).getOpcode() != ISD::MUL &&
1032 ROOTNode->getOperand(Num: 1).getOpcode() != ISD::MUL)
1033 return SDValue();
1034
1035 // In the case where we have a multiplication as the left operand of
1036 // of a subtraction, we can't combine into a MipsISD::MSub node as the
1037 // the instruction definition of msub(u) places the multiplication on
1038 // on the right.
1039 if (ROOTNode->getOpcode() == ISD::SUB &&
1040 ROOTNode->getOperand(Num: 0).getOpcode() == ISD::MUL)
1041 return SDValue();
1042
1043 // We don't handle vector types here.
1044 if (ROOTNode->getValueType(ResNo: 0).isVector())
1045 return SDValue();
1046
1047 // For MIPS64, madd / msub instructions are inefficent to use with 64 bit
1048 // arithmetic. E.g.
1049 // (add (mul a b) c) =>
1050 // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in
1051 // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32)
1052 // or
1053 // MIPS64R2: (dins (mflo res) (mfhi res) 32 32)
1054 //
1055 // The overhead of setting up the Hi/Lo registers and reassembling the
1056 // result makes this a dubious optimzation for MIPS64. The core of the
1057 // problem is that Hi/Lo contain the upper and lower 32 bits of the
1058 // operand and result.
1059 //
1060 // It requires a chain of 4 add/mul for MIPS64R2 to get better code
1061 // density than doing it naively, 5 for MIPS64. Additionally, using
1062 // madd/msub on MIPS64 requires the operands actually be 32 bit sign
1063 // extended operands, not true 64 bit values.
1064 //
1065 // FIXME: For the moment, disable this completely for MIPS64.
1066 if (Subtarget.hasMips64())
1067 return SDValue();
1068
1069 SDValue Mult = ROOTNode->getOperand(Num: 0).getOpcode() == ISD::MUL
1070 ? ROOTNode->getOperand(Num: 0)
1071 : ROOTNode->getOperand(Num: 1);
1072
1073 SDValue AddOperand = ROOTNode->getOperand(Num: 0).getOpcode() == ISD::MUL
1074 ? ROOTNode->getOperand(Num: 1)
1075 : ROOTNode->getOperand(Num: 0);
1076
1077 // Transform this to a MADD only if the user of this node is the add.
1078 // If there are other users of the mul, this function returns here.
1079 if (!Mult.hasOneUse())
1080 return SDValue();
1081
1082 // maddu and madd are unusual instructions in that on MIPS64 bits 63..31
1083 // must be in canonical form, i.e. sign extended. For MIPS32, the operands
1084 // of the multiply must have 32 or more sign bits, otherwise we cannot
1085 // perform this optimization. We have to check this here as we're performing
1086 // this optimization pre-legalization.
1087 SDValue MultLHS = Mult->getOperand(Num: 0);
1088 SDValue MultRHS = Mult->getOperand(Num: 1);
1089
1090 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND &&
1091 MultRHS->getOpcode() == ISD::SIGN_EXTEND;
1092 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND &&
1093 MultRHS->getOpcode() == ISD::ZERO_EXTEND;
1094
1095 if (!IsSigned && !IsUnsigned)
1096 return SDValue();
1097
1098 // Initialize accumulator.
1099 SDLoc DL(ROOTNode);
1100 SDValue BottomHalf, TopHalf;
1101 std::tie(args&: BottomHalf, args&: TopHalf) =
1102 CurDAG.SplitScalar(N: AddOperand, DL, LoVT: MVT::i32, HiVT: MVT::i32);
1103 SDValue ACCIn =
1104 CurDAG.getNode(Opcode: MipsISD::MTLOHI, DL, VT: MVT::Untyped, N1: BottomHalf, N2: TopHalf);
1105
1106 // Create MipsMAdd(u) / MipsMSub(u) node.
1107 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD;
1108 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd)
1109 : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub);
1110 SDValue MAddOps[3] = {
1111 CurDAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MVT::i32, Operand: Mult->getOperand(Num: 0)),
1112 CurDAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MVT::i32, Operand: Mult->getOperand(Num: 1)), ACCIn};
1113 SDValue MAdd = CurDAG.getNode(Opcode, DL, VT: MVT::Untyped, Ops: MAddOps);
1114
1115 SDValue ResLo = CurDAG.getNode(Opcode: MipsISD::MFLO, DL, VT: MVT::i32, Operand: MAdd);
1116 SDValue ResHi = CurDAG.getNode(Opcode: MipsISD::MFHI, DL, VT: MVT::i32, Operand: MAdd);
1117 SDValue Combined =
1118 CurDAG.getNode(Opcode: ISD::BUILD_PAIR, DL, VT: MVT::i64, N1: ResLo, N2: ResHi);
1119 return Combined;
1120}
1121
1122static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
1123 TargetLowering::DAGCombinerInfo &DCI,
1124 const MipsSubtarget &Subtarget) {
1125 // (sub v0 (mul v1, v2)) => (msub v1, v2, v0)
1126 if (DCI.isBeforeLegalizeOps()) {
1127 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1128 !Subtarget.inMips16Mode() && N->getValueType(ResNo: 0) == MVT::i64)
1129 return performMADD_MSUBCombine(ROOTNode: N, CurDAG&: DAG, Subtarget);
1130
1131 return SDValue();
1132 }
1133
1134 return SDValue();
1135}
1136
1137static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
1138 TargetLowering::DAGCombinerInfo &DCI,
1139 const MipsSubtarget &Subtarget) {
1140 // (add v0 (mul v1, v2)) => (madd v1, v2, v0)
1141 if (DCI.isBeforeLegalizeOps()) {
1142 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1143 !Subtarget.inMips16Mode() && N->getValueType(ResNo: 0) == MVT::i64)
1144 return performMADD_MSUBCombine(ROOTNode: N, CurDAG&: DAG, Subtarget);
1145
1146 return SDValue();
1147 }
1148
1149 // When loading from a jump table, push the Lo node to the position that
1150 // allows folding it into a load immediate.
1151 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
1152 // (add (add abs_lo(tjt), v1), v0) => (add (add v0, v1), abs_lo(tjt))
1153 SDValue InnerAdd = N->getOperand(Num: 1);
1154 SDValue Index = N->getOperand(Num: 0);
1155 if (InnerAdd.getOpcode() != ISD::ADD)
1156 std::swap(a&: InnerAdd, b&: Index);
1157 if (InnerAdd.getOpcode() != ISD::ADD)
1158 return SDValue();
1159
1160 SDValue Lo = InnerAdd.getOperand(i: 0);
1161 SDValue Other = InnerAdd.getOperand(i: 1);
1162 if (Lo.getOpcode() != MipsISD::Lo)
1163 std::swap(a&: Lo, b&: Other);
1164
1165 if ((Lo.getOpcode() != MipsISD::Lo) ||
1166 (Lo.getOperand(i: 0).getOpcode() != ISD::TargetJumpTable))
1167 return SDValue();
1168
1169 EVT ValTy = N->getValueType(ResNo: 0);
1170 SDLoc DL(N);
1171
1172 SDValue Add1 = DAG.getNode(Opcode: ISD::ADD, DL, VT: ValTy, N1: Index, N2: Other);
1173 return DAG.getNode(Opcode: ISD::ADD, DL, VT: ValTy, N1: Add1, N2: Lo);
1174}
1175
1176static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
1177 TargetLowering::DAGCombinerInfo &DCI,
1178 const MipsSubtarget &Subtarget) {
1179 // Pattern match CINS.
1180 // $dst = shl (and $src , imm), pos
1181 // => cins $dst, $src, pos, size
1182
1183 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips())
1184 return SDValue();
1185
1186 SDValue FirstOperand = N->getOperand(Num: 0);
1187 unsigned FirstOperandOpc = FirstOperand.getOpcode();
1188 SDValue SecondOperand = N->getOperand(Num: 1);
1189 EVT ValTy = N->getValueType(ResNo: 0);
1190 SDLoc DL(N);
1191
1192 uint64_t Pos = 0;
1193 unsigned SMPos, SMSize;
1194 ConstantSDNode *CN;
1195 SDValue NewOperand;
1196
1197 // The second operand of the shift must be an immediate.
1198 if (!(CN = dyn_cast<ConstantSDNode>(Val&: SecondOperand)))
1199 return SDValue();
1200
1201 Pos = CN->getZExtValue();
1202
1203 if (Pos >= ValTy.getSizeInBits())
1204 return SDValue();
1205
1206 if (FirstOperandOpc != ISD::AND)
1207 return SDValue();
1208
1209 // AND's second operand must be a shifted mask.
1210 if (!(CN = dyn_cast<ConstantSDNode>(Val: FirstOperand.getOperand(i: 1))) ||
1211 !isShiftedMask_64(Value: CN->getZExtValue(), MaskIdx&: SMPos, MaskLen&: SMSize))
1212 return SDValue();
1213
1214 // Return if the shifted mask does not start at bit 0 or the sum of its size
1215 // and Pos exceeds the word's size.
1216 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits())
1217 return SDValue();
1218
1219 NewOperand = FirstOperand.getOperand(i: 0);
1220 // SMSize is 'location' (position) in this case, not size.
1221 SMSize--;
1222
1223 return DAG.getNode(Opcode: MipsISD::CIns, DL, VT: ValTy, N1: NewOperand,
1224 N2: DAG.getConstant(Val: Pos, DL, VT: MVT::i32),
1225 N3: DAG.getConstant(Val: SMSize, DL, VT: MVT::i32));
1226}
1227
1228static SDValue performSignExtendCombine(SDNode *N, SelectionDAG &DAG,
1229 TargetLowering::DAGCombinerInfo &DCI,
1230 const MipsSubtarget &Subtarget) {
1231 if (DCI.Level != AfterLegalizeDAG || !Subtarget.isGP64bit()) {
1232 return SDValue();
1233 }
1234
1235 SDValue N0 = N->getOperand(Num: 0);
1236 EVT VT = N->getValueType(ResNo: 0);
1237
1238 // Pattern match XOR.
1239 // $dst = sign_extend (xor (trunc $src, i32), imm)
1240 // => $dst = xor (signext_inreg $src, i32), imm
1241 if (N0.getOpcode() == ISD::XOR &&
1242 N0.getOperand(i: 0).getOpcode() == ISD::TRUNCATE &&
1243 N0.getOperand(i: 1).getOpcode() == ISD::Constant) {
1244 SDValue TruncateSource = N0.getOperand(i: 0).getOperand(i: 0);
1245 auto *ConstantOperand = dyn_cast<ConstantSDNode>(Val: N0->getOperand(Num: 1));
1246
1247 SDValue FirstOperand =
1248 DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: SDLoc(N0), VT, N1: TruncateSource,
1249 N2: DAG.getValueType(N0.getOperand(i: 0).getValueType()));
1250
1251 int64_t ConstImm = ConstantOperand->getSExtValue();
1252 return DAG.getNode(Opcode: ISD::XOR, DL: SDLoc(N0), VT, N1: FirstOperand,
1253 N2: DAG.getConstant(Val: ConstImm, DL: SDLoc(N0), VT));
1254 }
1255
1256 return SDValue();
1257}
1258
1259SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
1260 const {
1261 SelectionDAG &DAG = DCI.DAG;
1262 unsigned Opc = N->getOpcode();
1263
1264 switch (Opc) {
1265 default: break;
1266 case ISD::SDIVREM:
1267 case ISD::UDIVREM:
1268 return performDivRemCombine(N, DAG, DCI, Subtarget);
1269 case ISD::SELECT:
1270 return performSELECTCombine(N, DAG, DCI, Subtarget);
1271 case MipsISD::CMovFP_F:
1272 case MipsISD::CMovFP_T:
1273 return performCMovFPCombine(N, DAG, DCI, Subtarget);
1274 case ISD::AND:
1275 return performANDCombine(N, DAG, DCI, Subtarget);
1276 case ISD::OR:
1277 return performORCombine(N, DAG, DCI, Subtarget);
1278 case ISD::ADD:
1279 return performADDCombine(N, DAG, DCI, Subtarget);
1280 case ISD::SHL:
1281 return performSHLCombine(N, DAG, DCI, Subtarget);
1282 case ISD::SUB:
1283 return performSUBCombine(N, DAG, DCI, Subtarget);
1284 case ISD::SIGN_EXTEND:
1285 return performSignExtendCombine(N, DAG, DCI, Subtarget);
1286 }
1287
1288 return SDValue();
1289}
1290
1291bool MipsTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
1292 return Subtarget.hasMips32();
1293}
1294
1295bool MipsTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
1296 return Subtarget.hasMips32();
1297}
1298
1299bool MipsTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
1300 // We can use ANDI+SLTIU as a bit test. Y contains the bit position.
1301 // For MIPSR2 or later, we may be able to use the `ext` instruction or its'
1302 // double-word variants.
1303 if (auto *C = dyn_cast<ConstantSDNode>(Val&: Y))
1304 return C->getAPIntValue().ule(RHS: 15);
1305
1306 return false;
1307}
1308
1309bool MipsTargetLowering::shouldFoldConstantShiftPairToMask(
1310 const SDNode *N, CombineLevel Level) const {
1311 assert(((N->getOpcode() == ISD::SHL &&
1312 N->getOperand(0).getOpcode() == ISD::SRL) ||
1313 (N->getOpcode() == ISD::SRL &&
1314 N->getOperand(0).getOpcode() == ISD::SHL)) &&
1315 "Expected shift-shift mask");
1316
1317 if (N->getOperand(Num: 0).getValueType().isVector())
1318 return false;
1319 return true;
1320}
1321
1322void
1323MipsTargetLowering::ReplaceNodeResults(SDNode *N,
1324 SmallVectorImpl<SDValue> &Results,
1325 SelectionDAG &DAG) const {
1326 return LowerOperationWrapper(N, Results, DAG);
1327}
1328
1329SDValue MipsTargetLowering::
1330LowerOperation(SDValue Op, SelectionDAG &DAG) const
1331{
1332 switch (Op.getOpcode())
1333 {
1334 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
1335 case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
1336 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
1337 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
1338 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
1339 case ISD::JumpTable: return lowerJumpTable(Op, DAG);
1340 case ISD::SELECT: return lowerSELECT(Op, DAG);
1341 case ISD::SETCC: return lowerSETCC(Op, DAG);
1342 case ISD::VASTART: return lowerVASTART(Op, DAG);
1343 case ISD::VAARG: return lowerVAARG(Op, DAG);
1344 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
1345 case ISD::FABS: return lowerFABS(Op, DAG);
1346 case ISD::FCANONICALIZE:
1347 return lowerFCANONICALIZE(Op, DAG);
1348 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
1349 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
1350 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
1351 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
1352 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
1353 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, IsSRA: true);
1354 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, IsSRA: false);
1355 case ISD::LOAD: return lowerLOAD(Op, DAG);
1356 case ISD::STORE: return lowerSTORE(Op, DAG);
1357 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG);
1358 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
1359 case ISD::READCYCLECOUNTER:
1360 return lowerREADCYCLECOUNTER(Op, DAG);
1361 case ISD::ConstantFP:
1362 return lowerConstantFP(Op, DAG);
1363 }
1364 return SDValue();
1365}
1366
1367//===----------------------------------------------------------------------===//
1368// Lower helper functions
1369//===----------------------------------------------------------------------===//
1370
1371// addLiveIn - This helper function adds the specified physical register to the
1372// MachineFunction as a live in value. It also creates a corresponding
1373// virtual register for it.
1374static unsigned
1375addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1376{
1377 Register VReg = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1378 MF.getRegInfo().addLiveIn(Reg: PReg, vreg: VReg);
1379 return VReg;
1380}
1381
1382static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI,
1383 MachineBasicBlock &MBB,
1384 const TargetInstrInfo &TII,
1385 bool Is64Bit, bool IsMicroMips) {
1386 if (NoZeroDivCheck)
1387 return &MBB;
1388
1389 // Insert instruction "teq $divisor_reg, $zero, 7".
1390 MachineBasicBlock::iterator I(MI);
1391 MachineInstrBuilder MIB;
1392 MachineOperand &Divisor = MI.getOperand(i: 2);
1393 MIB = BuildMI(BB&: MBB, I: std::next(x: I), MIMD: MI.getDebugLoc(),
1394 MCID: TII.get(Opcode: IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1395 .addReg(RegNo: Divisor.getReg(), flags: getKillRegState(B: Divisor.isKill()))
1396 .addReg(RegNo: Mips::ZERO)
1397 .addImm(Val: 7);
1398
1399 // Use the 32-bit sub-register if this is a 64-bit division.
1400 if (Is64Bit)
1401 MIB->getOperand(i: 0).setSubReg(Mips::sub_32);
1402
1403 // Clear Divisor's kill flag.
1404 Divisor.setIsKill(false);
1405
1406 // We would normally delete the original instruction here but in this case
1407 // we only needed to inject an additional instruction rather than replace it.
1408
1409 return &MBB;
1410}
1411
1412MachineBasicBlock *
1413MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1414 MachineBasicBlock *BB) const {
1415 switch (MI.getOpcode()) {
1416 default:
1417 llvm_unreachable("Unexpected instr type to insert");
1418 case Mips::ATOMIC_LOAD_ADD_I8:
1419 return emitAtomicBinaryPartword(MI, BB, Size: 1);
1420 case Mips::ATOMIC_LOAD_ADD_I16:
1421 return emitAtomicBinaryPartword(MI, BB, Size: 2);
1422 case Mips::ATOMIC_LOAD_ADD_I32:
1423 return emitAtomicBinary(MI, BB);
1424 case Mips::ATOMIC_LOAD_ADD_I64:
1425 return emitAtomicBinary(MI, BB);
1426
1427 case Mips::ATOMIC_LOAD_AND_I8:
1428 return emitAtomicBinaryPartword(MI, BB, Size: 1);
1429 case Mips::ATOMIC_LOAD_AND_I16:
1430 return emitAtomicBinaryPartword(MI, BB, Size: 2);
1431 case Mips::ATOMIC_LOAD_AND_I32:
1432 return emitAtomicBinary(MI, BB);
1433 case Mips::ATOMIC_LOAD_AND_I64:
1434 return emitAtomicBinary(MI, BB);
1435
1436 case Mips::ATOMIC_LOAD_OR_I8:
1437 return emitAtomicBinaryPartword(MI, BB, Size: 1);
1438 case Mips::ATOMIC_LOAD_OR_I16:
1439 return emitAtomicBinaryPartword(MI, BB, Size: 2);
1440 case Mips::ATOMIC_LOAD_OR_I32:
1441 return emitAtomicBinary(MI, BB);
1442 case Mips::ATOMIC_LOAD_OR_I64:
1443 return emitAtomicBinary(MI, BB);
1444
1445 case Mips::ATOMIC_LOAD_XOR_I8:
1446 return emitAtomicBinaryPartword(MI, BB, Size: 1);
1447 case Mips::ATOMIC_LOAD_XOR_I16:
1448 return emitAtomicBinaryPartword(MI, BB, Size: 2);
1449 case Mips::ATOMIC_LOAD_XOR_I32:
1450 return emitAtomicBinary(MI, BB);
1451 case Mips::ATOMIC_LOAD_XOR_I64:
1452 return emitAtomicBinary(MI, BB);
1453
1454 case Mips::ATOMIC_LOAD_NAND_I8:
1455 return emitAtomicBinaryPartword(MI, BB, Size: 1);
1456 case Mips::ATOMIC_LOAD_NAND_I16:
1457 return emitAtomicBinaryPartword(MI, BB, Size: 2);
1458 case Mips::ATOMIC_LOAD_NAND_I32:
1459 return emitAtomicBinary(MI, BB);
1460 case Mips::ATOMIC_LOAD_NAND_I64:
1461 return emitAtomicBinary(MI, BB);
1462
1463 case Mips::ATOMIC_LOAD_SUB_I8:
1464 return emitAtomicBinaryPartword(MI, BB, Size: 1);
1465 case Mips::ATOMIC_LOAD_SUB_I16:
1466 return emitAtomicBinaryPartword(MI, BB, Size: 2);
1467 case Mips::ATOMIC_LOAD_SUB_I32:
1468 return emitAtomicBinary(MI, BB);
1469 case Mips::ATOMIC_LOAD_SUB_I64:
1470 return emitAtomicBinary(MI, BB);
1471
1472 case Mips::ATOMIC_SWAP_I8:
1473 return emitAtomicBinaryPartword(MI, BB, Size: 1);
1474 case Mips::ATOMIC_SWAP_I16:
1475 return emitAtomicBinaryPartword(MI, BB, Size: 2);
1476 case Mips::ATOMIC_SWAP_I32:
1477 return emitAtomicBinary(MI, BB);
1478 case Mips::ATOMIC_SWAP_I64:
1479 return emitAtomicBinary(MI, BB);
1480
1481 case Mips::ATOMIC_CMP_SWAP_I8:
1482 return emitAtomicCmpSwapPartword(MI, BB, Size: 1);
1483 case Mips::ATOMIC_CMP_SWAP_I16:
1484 return emitAtomicCmpSwapPartword(MI, BB, Size: 2);
1485 case Mips::ATOMIC_CMP_SWAP_I32:
1486 return emitAtomicCmpSwap(MI, BB);
1487 case Mips::ATOMIC_CMP_SWAP_I64:
1488 return emitAtomicCmpSwap(MI, BB);
1489
1490 case Mips::ATOMIC_LOAD_MIN_I8:
1491 return emitAtomicBinaryPartword(MI, BB, Size: 1);
1492 case Mips::ATOMIC_LOAD_MIN_I16:
1493 return emitAtomicBinaryPartword(MI, BB, Size: 2);
1494 case Mips::ATOMIC_LOAD_MIN_I32:
1495 return emitAtomicBinary(MI, BB);
1496 case Mips::ATOMIC_LOAD_MIN_I64:
1497 return emitAtomicBinary(MI, BB);
1498
1499 case Mips::ATOMIC_LOAD_MAX_I8:
1500 return emitAtomicBinaryPartword(MI, BB, Size: 1);
1501 case Mips::ATOMIC_LOAD_MAX_I16:
1502 return emitAtomicBinaryPartword(MI, BB, Size: 2);
1503 case Mips::ATOMIC_LOAD_MAX_I32:
1504 return emitAtomicBinary(MI, BB);
1505 case Mips::ATOMIC_LOAD_MAX_I64:
1506 return emitAtomicBinary(MI, BB);
1507
1508 case Mips::ATOMIC_LOAD_UMIN_I8:
1509 return emitAtomicBinaryPartword(MI, BB, Size: 1);
1510 case Mips::ATOMIC_LOAD_UMIN_I16:
1511 return emitAtomicBinaryPartword(MI, BB, Size: 2);
1512 case Mips::ATOMIC_LOAD_UMIN_I32:
1513 return emitAtomicBinary(MI, BB);
1514 case Mips::ATOMIC_LOAD_UMIN_I64:
1515 return emitAtomicBinary(MI, BB);
1516
1517 case Mips::ATOMIC_LOAD_UMAX_I8:
1518 return emitAtomicBinaryPartword(MI, BB, Size: 1);
1519 case Mips::ATOMIC_LOAD_UMAX_I16:
1520 return emitAtomicBinaryPartword(MI, BB, Size: 2);
1521 case Mips::ATOMIC_LOAD_UMAX_I32:
1522 return emitAtomicBinary(MI, BB);
1523 case Mips::ATOMIC_LOAD_UMAX_I64:
1524 return emitAtomicBinary(MI, BB);
1525
1526 case Mips::PseudoSDIV:
1527 case Mips::PseudoUDIV:
1528 case Mips::DIV:
1529 case Mips::DIVU:
1530 case Mips::MOD:
1531 case Mips::MODU:
1532 return insertDivByZeroTrap(MI, MBB&: *BB, TII: *Subtarget.getInstrInfo(), Is64Bit: false,
1533 IsMicroMips: false);
1534 case Mips::SDIV_MM_Pseudo:
1535 case Mips::UDIV_MM_Pseudo:
1536 case Mips::SDIV_MM:
1537 case Mips::UDIV_MM:
1538 case Mips::DIV_MMR6:
1539 case Mips::DIVU_MMR6:
1540 case Mips::MOD_MMR6:
1541 case Mips::MODU_MMR6:
1542 return insertDivByZeroTrap(MI, MBB&: *BB, TII: *Subtarget.getInstrInfo(), Is64Bit: false, IsMicroMips: true);
1543 case Mips::PseudoDSDIV:
1544 case Mips::PseudoDUDIV:
1545 case Mips::DDIV:
1546 case Mips::DDIVU:
1547 case Mips::DMOD:
1548 case Mips::DMODU:
1549 return insertDivByZeroTrap(MI, MBB&: *BB, TII: *Subtarget.getInstrInfo(), Is64Bit: true, IsMicroMips: false);
1550
1551 case Mips::PseudoSELECT_I:
1552 case Mips::PseudoSELECT_I64:
1553 case Mips::PseudoSELECT_S:
1554 case Mips::PseudoSELECT_D32:
1555 case Mips::PseudoSELECT_D64:
1556 return emitPseudoSELECT(MI, BB, isFPCmp: false, Opc: Mips::BNE);
1557 case Mips::PseudoSELECTFP_F_I:
1558 case Mips::PseudoSELECTFP_F_I64:
1559 case Mips::PseudoSELECTFP_F_S:
1560 case Mips::PseudoSELECTFP_F_D32:
1561 case Mips::PseudoSELECTFP_F_D64:
1562 return emitPseudoSELECT(MI, BB, isFPCmp: true, Opc: Mips::BC1F);
1563 case Mips::PseudoSELECTFP_T_I:
1564 case Mips::PseudoSELECTFP_T_I64:
1565 case Mips::PseudoSELECTFP_T_S:
1566 case Mips::PseudoSELECTFP_T_D32:
1567 case Mips::PseudoSELECTFP_T_D64:
1568 return emitPseudoSELECT(MI, BB, isFPCmp: true, Opc: Mips::BC1T);
1569 case Mips::PseudoD_SELECT_I:
1570 case Mips::PseudoD_SELECT_I64:
1571 return emitPseudoD_SELECT(MI, BB);
1572 case Mips::LDR_W:
1573 return emitLDR_W(MI, BB);
1574 case Mips::LDR_D:
1575 return emitLDR_D(MI, BB);
1576 case Mips::STR_W:
1577 return emitSTR_W(MI, BB);
1578 case Mips::STR_D:
1579 return emitSTR_D(MI, BB);
1580 }
1581}
1582
1583// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1584// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1585MachineBasicBlock *
1586MipsTargetLowering::emitAtomicBinary(MachineInstr &MI,
1587 MachineBasicBlock *BB) const {
1588
1589 MachineFunction *MF = BB->getParent();
1590 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1591 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1592 DebugLoc DL = MI.getDebugLoc();
1593
1594 unsigned AtomicOp;
1595 bool NeedsAdditionalReg = false;
1596 switch (MI.getOpcode()) {
1597 case Mips::ATOMIC_LOAD_ADD_I32:
1598 AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA;
1599 break;
1600 case Mips::ATOMIC_LOAD_SUB_I32:
1601 AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA;
1602 break;
1603 case Mips::ATOMIC_LOAD_AND_I32:
1604 AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA;
1605 break;
1606 case Mips::ATOMIC_LOAD_OR_I32:
1607 AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA;
1608 break;
1609 case Mips::ATOMIC_LOAD_XOR_I32:
1610 AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA;
1611 break;
1612 case Mips::ATOMIC_LOAD_NAND_I32:
1613 AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA;
1614 break;
1615 case Mips::ATOMIC_SWAP_I32:
1616 AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA;
1617 break;
1618 case Mips::ATOMIC_LOAD_ADD_I64:
1619 AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA;
1620 break;
1621 case Mips::ATOMIC_LOAD_SUB_I64:
1622 AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA;
1623 break;
1624 case Mips::ATOMIC_LOAD_AND_I64:
1625 AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA;
1626 break;
1627 case Mips::ATOMIC_LOAD_OR_I64:
1628 AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA;
1629 break;
1630 case Mips::ATOMIC_LOAD_XOR_I64:
1631 AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA;
1632 break;
1633 case Mips::ATOMIC_LOAD_NAND_I64:
1634 AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA;
1635 break;
1636 case Mips::ATOMIC_SWAP_I64:
1637 AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA;
1638 break;
1639 case Mips::ATOMIC_LOAD_MIN_I32:
1640 AtomicOp = Mips::ATOMIC_LOAD_MIN_I32_POSTRA;
1641 NeedsAdditionalReg = true;
1642 break;
1643 case Mips::ATOMIC_LOAD_MAX_I32:
1644 AtomicOp = Mips::ATOMIC_LOAD_MAX_I32_POSTRA;
1645 NeedsAdditionalReg = true;
1646 break;
1647 case Mips::ATOMIC_LOAD_UMIN_I32:
1648 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I32_POSTRA;
1649 NeedsAdditionalReg = true;
1650 break;
1651 case Mips::ATOMIC_LOAD_UMAX_I32:
1652 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I32_POSTRA;
1653 NeedsAdditionalReg = true;
1654 break;
1655 case Mips::ATOMIC_LOAD_MIN_I64:
1656 AtomicOp = Mips::ATOMIC_LOAD_MIN_I64_POSTRA;
1657 NeedsAdditionalReg = true;
1658 break;
1659 case Mips::ATOMIC_LOAD_MAX_I64:
1660 AtomicOp = Mips::ATOMIC_LOAD_MAX_I64_POSTRA;
1661 NeedsAdditionalReg = true;
1662 break;
1663 case Mips::ATOMIC_LOAD_UMIN_I64:
1664 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I64_POSTRA;
1665 NeedsAdditionalReg = true;
1666 break;
1667 case Mips::ATOMIC_LOAD_UMAX_I64:
1668 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I64_POSTRA;
1669 NeedsAdditionalReg = true;
1670 break;
1671 default:
1672 llvm_unreachable("Unknown pseudo atomic for replacement!");
1673 }
1674
1675 Register OldVal = MI.getOperand(i: 0).getReg();
1676 Register Ptr = MI.getOperand(i: 1).getReg();
1677 Register Incr = MI.getOperand(i: 2).getReg();
1678 Register Scratch = RegInfo.createVirtualRegister(RegClass: RegInfo.getRegClass(Reg: OldVal));
1679
1680 MachineBasicBlock::iterator II(MI);
1681
1682 // The scratch registers here with the EarlyClobber | Define | Implicit
1683 // flags is used to persuade the register allocator and the machine
1684 // verifier to accept the usage of this register. This has to be a real
1685 // register which has an UNDEF value but is dead after the instruction which
1686 // is unique among the registers chosen for the instruction.
1687
1688 // The EarlyClobber flag has the semantic properties that the operand it is
1689 // attached to is clobbered before the rest of the inputs are read. Hence it
1690 // must be unique among the operands to the instruction.
1691 // The Define flag is needed to coerce the machine verifier that an Undef
1692 // value isn't a problem.
1693 // The Dead flag is needed as the value in scratch isn't used by any other
1694 // instruction. Kill isn't used as Dead is more precise.
1695 // The implicit flag is here due to the interaction between the other flags
1696 // and the machine verifier.
1697
1698 // For correctness purpose, a new pseudo is introduced here. We need this
1699 // new pseudo, so that FastRegisterAllocator does not see an ll/sc sequence
1700 // that is spread over >1 basic blocks. A register allocator which
1701 // introduces (or any codegen infact) a store, can violate the expectations
1702 // of the hardware.
1703 //
1704 // An atomic read-modify-write sequence starts with a linked load
1705 // instruction and ends with a store conditional instruction. The atomic
1706 // read-modify-write sequence fails if any of the following conditions
1707 // occur between the execution of ll and sc:
1708 // * A coherent store is completed by another process or coherent I/O
1709 // module into the block of synchronizable physical memory containing
1710 // the word. The size and alignment of the block is
1711 // implementation-dependent.
1712 // * A coherent store is executed between an LL and SC sequence on the
1713 // same processor to the block of synchornizable physical memory
1714 // containing the word.
1715 //
1716
1717 Register PtrCopy = RegInfo.createVirtualRegister(RegClass: RegInfo.getRegClass(Reg: Ptr));
1718 Register IncrCopy = RegInfo.createVirtualRegister(RegClass: RegInfo.getRegClass(Reg: Incr));
1719
1720 BuildMI(BB&: *BB, I: II, MIMD: DL, MCID: TII->get(Opcode: Mips::COPY), DestReg: IncrCopy).addReg(RegNo: Incr);
1721 BuildMI(BB&: *BB, I: II, MIMD: DL, MCID: TII->get(Opcode: Mips::COPY), DestReg: PtrCopy).addReg(RegNo: Ptr);
1722
1723 MachineInstrBuilder MIB =
1724 BuildMI(BB&: *BB, I: II, MIMD: DL, MCID: TII->get(Opcode: AtomicOp))
1725 .addReg(RegNo: OldVal, flags: RegState::Define | RegState::EarlyClobber)
1726 .addReg(RegNo: PtrCopy)
1727 .addReg(RegNo: IncrCopy)
1728 .addReg(RegNo: Scratch, flags: RegState::Define | RegState::EarlyClobber |
1729 RegState::Implicit | RegState::Dead);
1730 if (NeedsAdditionalReg) {
1731 Register Scratch2 =
1732 RegInfo.createVirtualRegister(RegClass: RegInfo.getRegClass(Reg: OldVal));
1733 MIB.addReg(RegNo: Scratch2, flags: RegState::Define | RegState::EarlyClobber |
1734 RegState::Implicit | RegState::Dead);
1735 }
1736
1737 MI.eraseFromParent();
1738
1739 return BB;
1740}
1741
1742MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1743 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1744 unsigned SrcReg) const {
1745 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1746 const DebugLoc &DL = MI.getDebugLoc();
1747
1748 if (Subtarget.hasMips32r2() && Size == 1) {
1749 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::SEB), DestReg: DstReg).addReg(RegNo: SrcReg);
1750 return BB;
1751 }
1752
1753 if (Subtarget.hasMips32r2() && Size == 2) {
1754 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::SEH), DestReg: DstReg).addReg(RegNo: SrcReg);
1755 return BB;
1756 }
1757
1758 MachineFunction *MF = BB->getParent();
1759 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1760 const TargetRegisterClass *RC = getRegClassFor(VT: MVT::i32);
1761 Register ScrReg = RegInfo.createVirtualRegister(RegClass: RC);
1762
1763 assert(Size < 32);
1764 int64_t ShiftImm = 32 - (Size * 8);
1765
1766 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::SLL), DestReg: ScrReg).addReg(RegNo: SrcReg).addImm(Val: ShiftImm);
1767 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::SRA), DestReg: DstReg).addReg(RegNo: ScrReg).addImm(Val: ShiftImm);
1768
1769 return BB;
1770}
1771
1772MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1773 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1774 assert((Size == 1 || Size == 2) &&
1775 "Unsupported size for EmitAtomicBinaryPartial.");
1776
1777 MachineFunction *MF = BB->getParent();
1778 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1779 const TargetRegisterClass *RC = getRegClassFor(VT: MVT::i32);
1780 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1781 const TargetRegisterClass *RCp =
1782 getRegClassFor(VT: ArePtrs64bit ? MVT::i64 : MVT::i32);
1783 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1784 DebugLoc DL = MI.getDebugLoc();
1785
1786 Register Dest = MI.getOperand(i: 0).getReg();
1787 Register Ptr = MI.getOperand(i: 1).getReg();
1788 Register Incr = MI.getOperand(i: 2).getReg();
1789
1790 Register AlignedAddr = RegInfo.createVirtualRegister(RegClass: RCp);
1791 Register ShiftAmt = RegInfo.createVirtualRegister(RegClass: RC);
1792 Register Mask = RegInfo.createVirtualRegister(RegClass: RC);
1793 Register Mask2 = RegInfo.createVirtualRegister(RegClass: RC);
1794 Register Incr2 = RegInfo.createVirtualRegister(RegClass: RC);
1795 Register MaskLSB2 = RegInfo.createVirtualRegister(RegClass: RCp);
1796 Register PtrLSB2 = RegInfo.createVirtualRegister(RegClass: RC);
1797 Register MaskUpper = RegInfo.createVirtualRegister(RegClass: RC);
1798 Register Scratch = RegInfo.createVirtualRegister(RegClass: RC);
1799 Register Scratch2 = RegInfo.createVirtualRegister(RegClass: RC);
1800 Register Scratch3 = RegInfo.createVirtualRegister(RegClass: RC);
1801
1802 unsigned AtomicOp = 0;
1803 bool NeedsAdditionalReg = false;
1804 switch (MI.getOpcode()) {
1805 case Mips::ATOMIC_LOAD_NAND_I8:
1806 AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA;
1807 break;
1808 case Mips::ATOMIC_LOAD_NAND_I16:
1809 AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA;
1810 break;
1811 case Mips::ATOMIC_SWAP_I8:
1812 AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA;
1813 break;
1814 case Mips::ATOMIC_SWAP_I16:
1815 AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA;
1816 break;
1817 case Mips::ATOMIC_LOAD_ADD_I8:
1818 AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA;
1819 break;
1820 case Mips::ATOMIC_LOAD_ADD_I16:
1821 AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA;
1822 break;
1823 case Mips::ATOMIC_LOAD_SUB_I8:
1824 AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA;
1825 break;
1826 case Mips::ATOMIC_LOAD_SUB_I16:
1827 AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA;
1828 break;
1829 case Mips::ATOMIC_LOAD_AND_I8:
1830 AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA;
1831 break;
1832 case Mips::ATOMIC_LOAD_AND_I16:
1833 AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA;
1834 break;
1835 case Mips::ATOMIC_LOAD_OR_I8:
1836 AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA;
1837 break;
1838 case Mips::ATOMIC_LOAD_OR_I16:
1839 AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA;
1840 break;
1841 case Mips::ATOMIC_LOAD_XOR_I8:
1842 AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA;
1843 break;
1844 case Mips::ATOMIC_LOAD_XOR_I16:
1845 AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA;
1846 break;
1847 case Mips::ATOMIC_LOAD_MIN_I8:
1848 AtomicOp = Mips::ATOMIC_LOAD_MIN_I8_POSTRA;
1849 NeedsAdditionalReg = true;
1850 break;
1851 case Mips::ATOMIC_LOAD_MIN_I16:
1852 AtomicOp = Mips::ATOMIC_LOAD_MIN_I16_POSTRA;
1853 NeedsAdditionalReg = true;
1854 break;
1855 case Mips::ATOMIC_LOAD_MAX_I8:
1856 AtomicOp = Mips::ATOMIC_LOAD_MAX_I8_POSTRA;
1857 NeedsAdditionalReg = true;
1858 break;
1859 case Mips::ATOMIC_LOAD_MAX_I16:
1860 AtomicOp = Mips::ATOMIC_LOAD_MAX_I16_POSTRA;
1861 NeedsAdditionalReg = true;
1862 break;
1863 case Mips::ATOMIC_LOAD_UMIN_I8:
1864 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I8_POSTRA;
1865 NeedsAdditionalReg = true;
1866 break;
1867 case Mips::ATOMIC_LOAD_UMIN_I16:
1868 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I16_POSTRA;
1869 NeedsAdditionalReg = true;
1870 break;
1871 case Mips::ATOMIC_LOAD_UMAX_I8:
1872 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I8_POSTRA;
1873 NeedsAdditionalReg = true;
1874 break;
1875 case Mips::ATOMIC_LOAD_UMAX_I16:
1876 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I16_POSTRA;
1877 NeedsAdditionalReg = true;
1878 break;
1879 default:
1880 llvm_unreachable("Unknown subword atomic pseudo for expansion!");
1881 }
1882
1883 // insert new blocks after the current block
1884 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1885 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(BB: LLVM_BB);
1886 MachineFunction::iterator It = ++BB->getIterator();
1887 MF->insert(MBBI: It, MBB: exitMBB);
1888
1889 // Transfer the remainder of BB and its successor edges to exitMBB.
1890 exitMBB->splice(Where: exitMBB->begin(), Other: BB,
1891 From: std::next(x: MachineBasicBlock::iterator(MI)), To: BB->end());
1892 exitMBB->transferSuccessorsAndUpdatePHIs(FromMBB: BB);
1893
1894 BB->addSuccessor(Succ: exitMBB, Prob: BranchProbability::getOne());
1895
1896 // thisMBB:
1897 // addiu masklsb2,$0,-4 # 0xfffffffc
1898 // and alignedaddr,ptr,masklsb2
1899 // andi ptrlsb2,ptr,3
1900 // sll shiftamt,ptrlsb2,3
1901 // ori maskupper,$0,255 # 0xff
1902 // sll mask,maskupper,shiftamt
1903 // nor mask2,$0,mask
1904 // sll incr2,incr,shiftamt
1905
1906 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1907 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: ABI.GetPtrAddiuOp()), DestReg: MaskLSB2)
1908 .addReg(RegNo: ABI.GetNullPtr()).addImm(Val: -4);
1909 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: ABI.GetPtrAndOp()), DestReg: AlignedAddr)
1910 .addReg(RegNo: Ptr).addReg(RegNo: MaskLSB2);
1911 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::ANDi), DestReg: PtrLSB2)
1912 .addReg(RegNo: Ptr, flags: 0, SubReg: ArePtrs64bit ? Mips::sub_32 : 0).addImm(Val: 3);
1913 if (Subtarget.isLittle()) {
1914 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::SLL), DestReg: ShiftAmt).addReg(RegNo: PtrLSB2).addImm(Val: 3);
1915 } else {
1916 Register Off = RegInfo.createVirtualRegister(RegClass: RC);
1917 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::XORi), DestReg: Off)
1918 .addReg(RegNo: PtrLSB2).addImm(Val: (Size == 1) ? 3 : 2);
1919 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::SLL), DestReg: ShiftAmt).addReg(RegNo: Off).addImm(Val: 3);
1920 }
1921 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::ORi), DestReg: MaskUpper)
1922 .addReg(RegNo: Mips::ZERO).addImm(Val: MaskImm);
1923 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::SLLV), DestReg: Mask)
1924 .addReg(RegNo: MaskUpper).addReg(RegNo: ShiftAmt);
1925 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::NOR), DestReg: Mask2).addReg(RegNo: Mips::ZERO).addReg(RegNo: Mask);
1926 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::SLLV), DestReg: Incr2).addReg(RegNo: Incr).addReg(RegNo: ShiftAmt);
1927
1928
1929 // The purposes of the flags on the scratch registers is explained in
1930 // emitAtomicBinary. In summary, we need a scratch register which is going to
1931 // be undef, that is unique among registers chosen for the instruction.
1932
1933 MachineInstrBuilder MIB =
1934 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: AtomicOp))
1935 .addReg(RegNo: Dest, flags: RegState::Define | RegState::EarlyClobber)
1936 .addReg(RegNo: AlignedAddr)
1937 .addReg(RegNo: Incr2)
1938 .addReg(RegNo: Mask)
1939 .addReg(RegNo: Mask2)
1940 .addReg(RegNo: ShiftAmt)
1941 .addReg(RegNo: Scratch, flags: RegState::EarlyClobber | RegState::Define |
1942 RegState::Dead | RegState::Implicit)
1943 .addReg(RegNo: Scratch2, flags: RegState::EarlyClobber | RegState::Define |
1944 RegState::Dead | RegState::Implicit)
1945 .addReg(RegNo: Scratch3, flags: RegState::EarlyClobber | RegState::Define |
1946 RegState::Dead | RegState::Implicit);
1947 if (NeedsAdditionalReg) {
1948 Register Scratch4 = RegInfo.createVirtualRegister(RegClass: RC);
1949 MIB.addReg(RegNo: Scratch4, flags: RegState::EarlyClobber | RegState::Define |
1950 RegState::Dead | RegState::Implicit);
1951 }
1952
1953 MI.eraseFromParent(); // The instruction is gone now.
1954
1955 return exitMBB;
1956}
1957
1958// Lower atomic compare and swap to a pseudo instruction, taking care to
1959// define a scratch register for the pseudo instruction's expansion. The
1960// instruction is expanded after the register allocator as to prevent
1961// the insertion of stores between the linked load and the store conditional.
1962
1963MachineBasicBlock *
1964MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI,
1965 MachineBasicBlock *BB) const {
1966
1967 assert((MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ||
1968 MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) &&
1969 "Unsupported atomic pseudo for EmitAtomicCmpSwap.");
1970
1971 const unsigned Size = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8;
1972
1973 MachineFunction *MF = BB->getParent();
1974 MachineRegisterInfo &MRI = MF->getRegInfo();
1975 const TargetRegisterClass *RC = getRegClassFor(VT: MVT::getIntegerVT(BitWidth: Size * 8));
1976 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1977 DebugLoc DL = MI.getDebugLoc();
1978
1979 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32
1980 ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA
1981 : Mips::ATOMIC_CMP_SWAP_I64_POSTRA;
1982 Register Dest = MI.getOperand(i: 0).getReg();
1983 Register Ptr = MI.getOperand(i: 1).getReg();
1984 Register OldVal = MI.getOperand(i: 2).getReg();
1985 Register NewVal = MI.getOperand(i: 3).getReg();
1986
1987 Register Scratch = MRI.createVirtualRegister(RegClass: RC);
1988 MachineBasicBlock::iterator II(MI);
1989
1990 // We need to create copies of the various registers and kill them at the
1991 // atomic pseudo. If the copies are not made, when the atomic is expanded
1992 // after fast register allocation, the spills will end up outside of the
1993 // blocks that their values are defined in, causing livein errors.
1994
1995 Register PtrCopy = MRI.createVirtualRegister(RegClass: MRI.getRegClass(Reg: Ptr));
1996 Register OldValCopy = MRI.createVirtualRegister(RegClass: MRI.getRegClass(Reg: OldVal));
1997 Register NewValCopy = MRI.createVirtualRegister(RegClass: MRI.getRegClass(Reg: NewVal));
1998
1999 BuildMI(BB&: *BB, I: II, MIMD: DL, MCID: TII->get(Opcode: Mips::COPY), DestReg: PtrCopy).addReg(RegNo: Ptr);
2000 BuildMI(BB&: *BB, I: II, MIMD: DL, MCID: TII->get(Opcode: Mips::COPY), DestReg: OldValCopy).addReg(RegNo: OldVal);
2001 BuildMI(BB&: *BB, I: II, MIMD: DL, MCID: TII->get(Opcode: Mips::COPY), DestReg: NewValCopy).addReg(RegNo: NewVal);
2002
2003 // The purposes of the flags on the scratch registers is explained in
2004 // emitAtomicBinary. In summary, we need a scratch register which is going to
2005 // be undef, that is unique among registers chosen for the instruction.
2006
2007 BuildMI(BB&: *BB, I: II, MIMD: DL, MCID: TII->get(Opcode: AtomicOp))
2008 .addReg(RegNo: Dest, flags: RegState::Define | RegState::EarlyClobber)
2009 .addReg(RegNo: PtrCopy, flags: RegState::Kill)
2010 .addReg(RegNo: OldValCopy, flags: RegState::Kill)
2011 .addReg(RegNo: NewValCopy, flags: RegState::Kill)
2012 .addReg(RegNo: Scratch, flags: RegState::EarlyClobber | RegState::Define |
2013 RegState::Dead | RegState::Implicit);
2014
2015 MI.eraseFromParent(); // The instruction is gone now.
2016
2017 return BB;
2018}
2019
2020MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
2021 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
2022 assert((Size == 1 || Size == 2) &&
2023 "Unsupported size for EmitAtomicCmpSwapPartial.");
2024
2025 MachineFunction *MF = BB->getParent();
2026 MachineRegisterInfo &RegInfo = MF->getRegInfo();
2027 const TargetRegisterClass *RC = getRegClassFor(VT: MVT::i32);
2028 const bool ArePtrs64bit = ABI.ArePtrs64bit();
2029 const TargetRegisterClass *RCp =
2030 getRegClassFor(VT: ArePtrs64bit ? MVT::i64 : MVT::i32);
2031 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
2032 DebugLoc DL = MI.getDebugLoc();
2033
2034 Register Dest = MI.getOperand(i: 0).getReg();
2035 Register Ptr = MI.getOperand(i: 1).getReg();
2036 Register CmpVal = MI.getOperand(i: 2).getReg();
2037 Register NewVal = MI.getOperand(i: 3).getReg();
2038
2039 Register AlignedAddr = RegInfo.createVirtualRegister(RegClass: RCp);
2040 Register ShiftAmt = RegInfo.createVirtualRegister(RegClass: RC);
2041 Register Mask = RegInfo.createVirtualRegister(RegClass: RC);
2042 Register Mask2 = RegInfo.createVirtualRegister(RegClass: RC);
2043 Register ShiftedCmpVal = RegInfo.createVirtualRegister(RegClass: RC);
2044 Register ShiftedNewVal = RegInfo.createVirtualRegister(RegClass: RC);
2045 Register MaskLSB2 = RegInfo.createVirtualRegister(RegClass: RCp);
2046 Register PtrLSB2 = RegInfo.createVirtualRegister(RegClass: RC);
2047 Register MaskUpper = RegInfo.createVirtualRegister(RegClass: RC);
2048 Register MaskedCmpVal = RegInfo.createVirtualRegister(RegClass: RC);
2049 Register MaskedNewVal = RegInfo.createVirtualRegister(RegClass: RC);
2050 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8
2051 ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA
2052 : Mips::ATOMIC_CMP_SWAP_I16_POSTRA;
2053
2054 // The scratch registers here with the EarlyClobber | Define | Dead | Implicit
2055 // flags are used to coerce the register allocator and the machine verifier to
2056 // accept the usage of these registers.
2057 // The EarlyClobber flag has the semantic properties that the operand it is
2058 // attached to is clobbered before the rest of the inputs are read. Hence it
2059 // must be unique among the operands to the instruction.
2060 // The Define flag is needed to coerce the machine verifier that an Undef
2061 // value isn't a problem.
2062 // The Dead flag is needed as the value in scratch isn't used by any other
2063 // instruction. Kill isn't used as Dead is more precise.
2064 Register Scratch = RegInfo.createVirtualRegister(RegClass: RC);
2065 Register Scratch2 = RegInfo.createVirtualRegister(RegClass: RC);
2066
2067 // insert new blocks after the current block
2068 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2069 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(BB: LLVM_BB);
2070 MachineFunction::iterator It = ++BB->getIterator();
2071 MF->insert(MBBI: It, MBB: exitMBB);
2072
2073 // Transfer the remainder of BB and its successor edges to exitMBB.
2074 exitMBB->splice(Where: exitMBB->begin(), Other: BB,
2075 From: std::next(x: MachineBasicBlock::iterator(MI)), To: BB->end());
2076 exitMBB->transferSuccessorsAndUpdatePHIs(FromMBB: BB);
2077
2078 BB->addSuccessor(Succ: exitMBB, Prob: BranchProbability::getOne());
2079
2080 // thisMBB:
2081 // addiu masklsb2,$0,-4 # 0xfffffffc
2082 // and alignedaddr,ptr,masklsb2
2083 // andi ptrlsb2,ptr,3
2084 // xori ptrlsb2,ptrlsb2,3 # Only for BE
2085 // sll shiftamt,ptrlsb2,3
2086 // ori maskupper,$0,255 # 0xff
2087 // sll mask,maskupper,shiftamt
2088 // nor mask2,$0,mask
2089 // andi maskedcmpval,cmpval,255
2090 // sll shiftedcmpval,maskedcmpval,shiftamt
2091 // andi maskednewval,newval,255
2092 // sll shiftednewval,maskednewval,shiftamt
2093 int64_t MaskImm = (Size == 1) ? 255 : 65535;
2094 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), DestReg: MaskLSB2)
2095 .addReg(RegNo: ABI.GetNullPtr()).addImm(Val: -4);
2096 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: ArePtrs64bit ? Mips::AND64 : Mips::AND), DestReg: AlignedAddr)
2097 .addReg(RegNo: Ptr).addReg(RegNo: MaskLSB2);
2098 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::ANDi), DestReg: PtrLSB2)
2099 .addReg(RegNo: Ptr, flags: 0, SubReg: ArePtrs64bit ? Mips::sub_32 : 0).addImm(Val: 3);
2100 if (Subtarget.isLittle()) {
2101 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::SLL), DestReg: ShiftAmt).addReg(RegNo: PtrLSB2).addImm(Val: 3);
2102 } else {
2103 Register Off = RegInfo.createVirtualRegister(RegClass: RC);
2104 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::XORi), DestReg: Off)
2105 .addReg(RegNo: PtrLSB2).addImm(Val: (Size == 1) ? 3 : 2);
2106 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::SLL), DestReg: ShiftAmt).addReg(RegNo: Off).addImm(Val: 3);
2107 }
2108 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::ORi), DestReg: MaskUpper)
2109 .addReg(RegNo: Mips::ZERO).addImm(Val: MaskImm);
2110 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::SLLV), DestReg: Mask)
2111 .addReg(RegNo: MaskUpper).addReg(RegNo: ShiftAmt);
2112 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::NOR), DestReg: Mask2).addReg(RegNo: Mips::ZERO).addReg(RegNo: Mask);
2113 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::ANDi), DestReg: MaskedCmpVal)
2114 .addReg(RegNo: CmpVal).addImm(Val: MaskImm);
2115 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::SLLV), DestReg: ShiftedCmpVal)
2116 .addReg(RegNo: MaskedCmpVal).addReg(RegNo: ShiftAmt);
2117 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::ANDi), DestReg: MaskedNewVal)
2118 .addReg(RegNo: NewVal).addImm(Val: MaskImm);
2119 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::SLLV), DestReg: ShiftedNewVal)
2120 .addReg(RegNo: MaskedNewVal).addReg(RegNo: ShiftAmt);
2121
2122 // The purposes of the flags on the scratch registers are explained in
2123 // emitAtomicBinary. In summary, we need a scratch register which is going to
2124 // be undef, that is unique among the register chosen for the instruction.
2125
2126 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: AtomicOp))
2127 .addReg(RegNo: Dest, flags: RegState::Define | RegState::EarlyClobber)
2128 .addReg(RegNo: AlignedAddr)
2129 .addReg(RegNo: Mask)
2130 .addReg(RegNo: ShiftedCmpVal)
2131 .addReg(RegNo: Mask2)
2132 .addReg(RegNo: ShiftedNewVal)
2133 .addReg(RegNo: ShiftAmt)
2134 .addReg(RegNo: Scratch, flags: RegState::EarlyClobber | RegState::Define |
2135 RegState::Dead | RegState::Implicit)
2136 .addReg(RegNo: Scratch2, flags: RegState::EarlyClobber | RegState::Define |
2137 RegState::Dead | RegState::Implicit);
2138
2139 MI.eraseFromParent(); // The instruction is gone now.
2140
2141 return exitMBB;
2142}
2143
2144SDValue MipsTargetLowering::lowerREADCYCLECOUNTER(SDValue Op,
2145 SelectionDAG &DAG) const {
2146 SmallVector<SDValue, 3> Results;
2147 SDLoc DL(Op);
2148 MachineFunction &MF = DAG.getMachineFunction();
2149 unsigned RdhwrOpc, DestReg;
2150 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
2151
2152 if (PtrVT == MVT::i64) {
2153 RdhwrOpc = Mips::RDHWR64;
2154 DestReg = MF.getRegInfo().createVirtualRegister(RegClass: getRegClassFor(VT: MVT::i64));
2155 SDNode *Rdhwr = DAG.getMachineNode(Opcode: RdhwrOpc, dl: DL, VT1: MVT::i64, VT2: MVT::Glue,
2156 Op1: DAG.getRegister(Reg: Mips::HWR2, VT: MVT::i32),
2157 Op2: DAG.getTargetConstant(Val: 0, DL, VT: MVT::i32));
2158 SDValue Chain = DAG.getCopyToReg(Chain: DAG.getEntryNode(), dl: DL, Reg: DestReg,
2159 N: SDValue(Rdhwr, 0), Glue: SDValue(Rdhwr, 1));
2160 SDValue ResNode =
2161 DAG.getCopyFromReg(Chain, dl: DL, Reg: DestReg, VT: MVT::i64, Glue: Chain.getValue(R: 1));
2162 Results.push_back(Elt: ResNode);
2163 Results.push_back(Elt: ResNode.getValue(R: 1));
2164 } else {
2165 RdhwrOpc = Mips::RDHWR;
2166 DestReg = MF.getRegInfo().createVirtualRegister(RegClass: getRegClassFor(VT: MVT::i32));
2167 SDNode *Rdhwr = DAG.getMachineNode(Opcode: RdhwrOpc, dl: DL, VT1: MVT::i32, VT2: MVT::Glue,
2168 Op1: DAG.getRegister(Reg: Mips::HWR2, VT: MVT::i32),
2169 Op2: DAG.getTargetConstant(Val: 0, DL, VT: MVT::i32));
2170 SDValue Chain = DAG.getCopyToReg(Chain: DAG.getEntryNode(), dl: DL, Reg: DestReg,
2171 N: SDValue(Rdhwr, 0), Glue: SDValue(Rdhwr, 1));
2172 SDValue ResNode =
2173 DAG.getCopyFromReg(Chain, dl: DL, Reg: DestReg, VT: MVT::i32, Glue: Chain.getValue(R: 1));
2174 Results.push_back(Elt: DAG.getNode(Opcode: ISD::BUILD_PAIR, DL, VT: MVT::i64, N1: ResNode,
2175 N2: DAG.getConstant(Val: 0, DL, VT: MVT::i32)));
2176 Results.push_back(Elt: ResNode.getValue(R: 1));
2177 }
2178
2179 return DAG.getMergeValues(Ops: Results, dl: DL);
2180}
2181
2182SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
2183 // The first operand is the chain, the second is the condition, the third is
2184 // the block to branch to if the condition is true.
2185 SDValue Chain = Op.getOperand(i: 0);
2186 SDValue Dest = Op.getOperand(i: 2);
2187 SDLoc DL(Op);
2188
2189 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
2190 SDValue CondRes = createFPCmp(DAG, Op: Op.getOperand(i: 1));
2191
2192 // Return if flag is not set by a floating point comparison.
2193 if (CondRes.getOpcode() != MipsISD::FPCmp)
2194 return Op;
2195
2196 SDValue CCNode = CondRes.getOperand(i: 2);
2197 Mips::CondCode CC = (Mips::CondCode)CCNode->getAsZExtVal();
2198 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
2199 SDValue BrCode = DAG.getConstant(Val: Opc, DL, VT: MVT::i32);
2200 SDValue FCC0 = DAG.getRegister(Reg: Mips::FCC0, VT: MVT::i32);
2201 return DAG.getNode(Opcode: MipsISD::FPBrcond, DL, VT: Op.getValueType(), N1: Chain, N2: BrCode,
2202 N3: FCC0, N4: Dest, N5: CondRes);
2203}
2204
2205SDValue MipsTargetLowering::
2206lowerSELECT(SDValue Op, SelectionDAG &DAG) const
2207{
2208 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
2209 SDValue Cond = createFPCmp(DAG, Op: Op.getOperand(i: 0));
2210
2211 // Return if flag is not set by a floating point comparison.
2212 if (Cond.getOpcode() != MipsISD::FPCmp)
2213 return Op;
2214
2215 return createCMovFP(DAG, Cond, True: Op.getOperand(i: 1), False: Op.getOperand(i: 2),
2216 DL: SDLoc(Op));
2217}
2218
2219SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2220 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
2221 SDValue Cond = createFPCmp(DAG, Op);
2222
2223 assert(Cond.getOpcode() == MipsISD::FPCmp &&
2224 "Floating point operand expected.");
2225
2226 SDLoc DL(Op);
2227 SDValue True = DAG.getConstant(Val: 1, DL, VT: MVT::i32);
2228 SDValue False = DAG.getConstant(Val: 0, DL, VT: MVT::i32);
2229
2230 return createCMovFP(DAG, Cond, True, False, DL);
2231}
2232
2233SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
2234 SelectionDAG &DAG) const {
2235 EVT Ty = Op.getValueType();
2236 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Val&: Op);
2237 const GlobalValue *GV = N->getGlobal();
2238
2239 if (GV->hasDLLImportStorageClass()) {
2240 assert(Subtarget.isTargetWindows() &&
2241 "Windows is the only supported COFF target");
2242 return getDllimportVariable(
2243 N, DL: SDLoc(N), Ty, DAG, Chain: DAG.getEntryNode(),
2244 PtrInfo: MachinePointerInfo::getGOT(MF&: DAG.getMachineFunction()));
2245 }
2246
2247 if (!isPositionIndependent()) {
2248 const MipsTargetObjectFile *TLOF =
2249 static_cast<const MipsTargetObjectFile *>(
2250 getTargetMachine().getObjFileLowering());
2251 const GlobalObject *GO = GV->getAliaseeObject();
2252 if (GO && TLOF->IsGlobalInSmallSection(GO, TM: getTargetMachine()))
2253 // %gp_rel relocation
2254 return getAddrGPRel(N, DL: SDLoc(N), Ty, DAG, IsN64: ABI.IsN64());
2255
2256 // %hi/%lo relocation
2257 return Subtarget.hasSym32() ? getAddrNonPIC(N, DL: SDLoc(N), Ty, DAG)
2258 // %highest/%higher/%hi/%lo relocation
2259 : getAddrNonPICSym64(N, DL: SDLoc(N), Ty, DAG);
2260 }
2261
2262 // Every other architecture would use shouldAssumeDSOLocal in here, but
2263 // mips is special.
2264 // * In PIC code mips requires got loads even for local statics!
2265 // * To save on got entries, for local statics the got entry contains the
2266 // page and an additional add instruction takes care of the low bits.
2267 // * It is legal to access a hidden symbol with a non hidden undefined,
2268 // so one cannot guarantee that all access to a hidden symbol will know
2269 // it is hidden.
2270 // * Mips linkers don't support creating a page and a full got entry for
2271 // the same symbol.
2272 // * Given all that, we have to use a full got entry for hidden symbols :-(
2273 if (GV->hasLocalLinkage())
2274 return getAddrLocal(N, DL: SDLoc(N), Ty, DAG, IsN32OrN64: ABI.IsN32() || ABI.IsN64());
2275
2276 if (Subtarget.useXGOT())
2277 return getAddrGlobalLargeGOT(
2278 N, DL: SDLoc(N), Ty, DAG, HiFlag: MipsII::MO_GOT_HI16, LoFlag: MipsII::MO_GOT_LO16,
2279 Chain: DAG.getEntryNode(),
2280 PtrInfo: MachinePointerInfo::getGOT(MF&: DAG.getMachineFunction()));
2281
2282 return getAddrGlobal(
2283 N, DL: SDLoc(N), Ty, DAG,
2284 Flag: (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT,
2285 Chain: DAG.getEntryNode(), PtrInfo: MachinePointerInfo::getGOT(MF&: DAG.getMachineFunction()));
2286}
2287
2288SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
2289 SelectionDAG &DAG) const {
2290 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Val&: Op);
2291 EVT Ty = Op.getValueType();
2292
2293 if (!isPositionIndependent())
2294 return Subtarget.hasSym32() ? getAddrNonPIC(N, DL: SDLoc(N), Ty, DAG)
2295 : getAddrNonPICSym64(N, DL: SDLoc(N), Ty, DAG);
2296
2297 return getAddrLocal(N, DL: SDLoc(N), Ty, DAG, IsN32OrN64: ABI.IsN32() || ABI.IsN64());
2298}
2299
2300SDValue MipsTargetLowering::
2301lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
2302{
2303 // If the relocation model is PIC, use the General Dynamic TLS Model or
2304 // Local Dynamic TLS model, otherwise use the Initial Exec or
2305 // Local Exec TLS Model.
2306
2307 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Val&: Op);
2308 if (DAG.getTarget().useEmulatedTLS())
2309 return LowerToTLSEmulatedModel(GA, DAG);
2310
2311 SDLoc DL(GA);
2312 const GlobalValue *GV = GA->getGlobal();
2313 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
2314
2315 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2316
2317 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2318 // General Dynamic and Local Dynamic TLS Model.
2319 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
2320 : MipsII::MO_TLSGD;
2321
2322 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, VT: PtrVT, offset: 0, TargetFlags: Flag);
2323 SDValue Argument = DAG.getNode(Opcode: MipsISD::Wrapper, DL, VT: PtrVT,
2324 N1: getGlobalReg(DAG, Ty: PtrVT), N2: TGA);
2325 unsigned PtrSize = PtrVT.getSizeInBits();
2326 IntegerType *PtrTy = Type::getIntNTy(C&: *DAG.getContext(), N: PtrSize);
2327
2328 SDValue TlsGetAddr = DAG.getExternalSymbol(Sym: "__tls_get_addr", VT: PtrVT);
2329
2330 ArgListTy Args;
2331 ArgListEntry Entry;
2332 Entry.Node = Argument;
2333 Entry.Ty = PtrTy;
2334 Args.push_back(x: Entry);
2335
2336 TargetLowering::CallLoweringInfo CLI(DAG);
2337 CLI.setDebugLoc(DL)
2338 .setChain(DAG.getEntryNode())
2339 .setLibCallee(CC: CallingConv::C, ResultType: PtrTy, Target: TlsGetAddr, ArgsList: std::move(Args));
2340 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2341
2342 SDValue Ret = CallResult.first;
2343
2344 if (model != TLSModel::LocalDynamic)
2345 return Ret;
2346
2347 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, VT: PtrVT, offset: 0,
2348 TargetFlags: MipsII::MO_DTPREL_HI);
2349 SDValue Hi = DAG.getNode(Opcode: MipsISD::TlsHi, DL, VT: PtrVT, Operand: TGAHi);
2350 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, VT: PtrVT, offset: 0,
2351 TargetFlags: MipsII::MO_DTPREL_LO);
2352 SDValue Lo = DAG.getNode(Opcode: MipsISD::Lo, DL, VT: PtrVT, Operand: TGALo);
2353 SDValue Add = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: Hi, N2: Ret);
2354 return DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: Add, N2: Lo);
2355 }
2356
2357 SDValue Offset;
2358 if (model == TLSModel::InitialExec) {
2359 // Initial Exec TLS Model
2360 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, VT: PtrVT, offset: 0,
2361 TargetFlags: MipsII::MO_GOTTPREL);
2362 TGA = DAG.getNode(Opcode: MipsISD::Wrapper, DL, VT: PtrVT, N1: getGlobalReg(DAG, Ty: PtrVT),
2363 N2: TGA);
2364 Offset =
2365 DAG.getLoad(VT: PtrVT, dl: DL, Chain: DAG.getEntryNode(), Ptr: TGA, PtrInfo: MachinePointerInfo());
2366 } else {
2367 // Local Exec TLS Model
2368 assert(model == TLSModel::LocalExec);
2369 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, VT: PtrVT, offset: 0,
2370 TargetFlags: MipsII::MO_TPREL_HI);
2371 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, VT: PtrVT, offset: 0,
2372 TargetFlags: MipsII::MO_TPREL_LO);
2373 SDValue Hi = DAG.getNode(Opcode: MipsISD::TlsHi, DL, VT: PtrVT, Operand: TGAHi);
2374 SDValue Lo = DAG.getNode(Opcode: MipsISD::Lo, DL, VT: PtrVT, Operand: TGALo);
2375 Offset = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: Hi, N2: Lo);
2376 }
2377
2378 SDValue ThreadPointer = DAG.getNode(Opcode: MipsISD::ThreadPointer, DL, VT: PtrVT);
2379 return DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: ThreadPointer, N2: Offset);
2380}
2381
2382SDValue MipsTargetLowering::
2383lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
2384{
2385 JumpTableSDNode *N = cast<JumpTableSDNode>(Val&: Op);
2386 EVT Ty = Op.getValueType();
2387
2388 if (!isPositionIndependent())
2389 return Subtarget.hasSym32() ? getAddrNonPIC(N, DL: SDLoc(N), Ty, DAG)
2390 : getAddrNonPICSym64(N, DL: SDLoc(N), Ty, DAG);
2391
2392 return getAddrLocal(N, DL: SDLoc(N), Ty, DAG, IsN32OrN64: ABI.IsN32() || ABI.IsN64());
2393}
2394
2395SDValue MipsTargetLowering::
2396lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
2397{
2398 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Val&: Op);
2399 EVT Ty = Op.getValueType();
2400
2401 if (!isPositionIndependent()) {
2402 const MipsTargetObjectFile *TLOF =
2403 static_cast<const MipsTargetObjectFile *>(
2404 getTargetMachine().getObjFileLowering());
2405
2406 if (TLOF->IsConstantInSmallSection(DL: DAG.getDataLayout(), CN: N->getConstVal(),
2407 TM: getTargetMachine()))
2408 // %gp_rel relocation
2409 return getAddrGPRel(N, DL: SDLoc(N), Ty, DAG, IsN64: ABI.IsN64());
2410
2411 return Subtarget.hasSym32() ? getAddrNonPIC(N, DL: SDLoc(N), Ty, DAG)
2412 : getAddrNonPICSym64(N, DL: SDLoc(N), Ty, DAG);
2413 }
2414
2415 return getAddrLocal(N, DL: SDLoc(N), Ty, DAG, IsN32OrN64: ABI.IsN32() || ABI.IsN64());
2416}
2417
2418SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2419 MachineFunction &MF = DAG.getMachineFunction();
2420 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2421
2422 SDLoc DL(Op);
2423 SDValue FI = DAG.getFrameIndex(FI: FuncInfo->getVarArgsFrameIndex(),
2424 VT: getPointerTy(DL: MF.getDataLayout()));
2425
2426 // vastart just stores the address of the VarArgsFrameIndex slot into the
2427 // memory location argument.
2428 const Value *SV = cast<SrcValueSDNode>(Val: Op.getOperand(i: 2))->getValue();
2429 return DAG.getStore(Chain: Op.getOperand(i: 0), dl: DL, Val: FI, Ptr: Op.getOperand(i: 1),
2430 PtrInfo: MachinePointerInfo(SV));
2431}
2432
2433SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2434 SDNode *Node = Op.getNode();
2435 EVT VT = Node->getValueType(ResNo: 0);
2436 SDValue Chain = Node->getOperand(Num: 0);
2437 SDValue VAListPtr = Node->getOperand(Num: 1);
2438 const Align Align =
2439 llvm::MaybeAlign(Node->getConstantOperandVal(Num: 3)).valueOrOne();
2440 const Value *SV = cast<SrcValueSDNode>(Val: Node->getOperand(Num: 2))->getValue();
2441 SDLoc DL(Node);
2442 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
2443
2444 SDValue VAListLoad = DAG.getLoad(VT: getPointerTy(DL: DAG.getDataLayout()), dl: DL, Chain,
2445 Ptr: VAListPtr, PtrInfo: MachinePointerInfo(SV));
2446 SDValue VAList = VAListLoad;
2447
2448 // Re-align the pointer if necessary.
2449 // It should only ever be necessary for 64-bit types on O32 since the minimum
2450 // argument alignment is the same as the maximum type alignment for N32/N64.
2451 //
2452 // FIXME: We currently align too often. The code generator doesn't notice
2453 // when the pointer is still aligned from the last va_arg (or pair of
2454 // va_args for the i64 on O32 case).
2455 if (Align > getMinStackArgumentAlignment()) {
2456 VAList = DAG.getNode(
2457 Opcode: ISD::ADD, DL, VT: VAList.getValueType(), N1: VAList,
2458 N2: DAG.getConstant(Val: Align.value() - 1, DL, VT: VAList.getValueType()));
2459
2460 VAList = DAG.getNode(Opcode: ISD::AND, DL, VT: VAList.getValueType(), N1: VAList,
2461 N2: DAG.getSignedConstant(Val: -(int64_t)Align.value(), DL,
2462 VT: VAList.getValueType()));
2463 }
2464
2465 // Increment the pointer, VAList, to the next vaarg.
2466 auto &TD = DAG.getDataLayout();
2467 unsigned ArgSizeInBytes =
2468 TD.getTypeAllocSize(Ty: VT.getTypeForEVT(Context&: *DAG.getContext()));
2469 SDValue Tmp3 =
2470 DAG.getNode(Opcode: ISD::ADD, DL, VT: VAList.getValueType(), N1: VAList,
2471 N2: DAG.getConstant(Val: alignTo(Value: ArgSizeInBytes, Align: ArgSlotSizeInBytes),
2472 DL, VT: VAList.getValueType()));
2473 // Store the incremented VAList to the legalized pointer
2474 Chain = DAG.getStore(Chain: VAListLoad.getValue(R: 1), dl: DL, Val: Tmp3, Ptr: VAListPtr,
2475 PtrInfo: MachinePointerInfo(SV));
2476
2477 // In big-endian mode we must adjust the pointer when the load size is smaller
2478 // than the argument slot size. We must also reduce the known alignment to
2479 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
2480 // the correct half of the slot, and reduce the alignment from 8 (slot
2481 // alignment) down to 4 (type alignment).
2482 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
2483 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2484 VAList = DAG.getNode(Opcode: ISD::ADD, DL, VT: VAListPtr.getValueType(), N1: VAList,
2485 N2: DAG.getIntPtrConstant(Val: Adjustment, DL));
2486 }
2487 // Load the actual argument out of the pointer VAList
2488 return DAG.getLoad(VT, dl: DL, Chain, Ptr: VAList, PtrInfo: MachinePointerInfo());
2489}
2490
2491static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
2492 bool HasExtractInsert) {
2493 EVT TyX = Op.getOperand(i: 0).getValueType();
2494 EVT TyY = Op.getOperand(i: 1).getValueType();
2495 SDLoc DL(Op);
2496 SDValue Const1 = DAG.getConstant(Val: 1, DL, VT: MVT::i32);
2497 SDValue Const31 = DAG.getConstant(Val: 31, DL, VT: MVT::i32);
2498 SDValue Res;
2499
2500 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2501 // to i32.
2502 SDValue X = (TyX == MVT::f32) ?
2503 DAG.getNode(Opcode: ISD::BITCAST, DL, VT: MVT::i32, Operand: Op.getOperand(i: 0)) :
2504 DAG.getNode(Opcode: MipsISD::ExtractElementF64, DL, VT: MVT::i32, N1: Op.getOperand(i: 0),
2505 N2: Const1);
2506 SDValue Y = (TyY == MVT::f32) ?
2507 DAG.getNode(Opcode: ISD::BITCAST, DL, VT: MVT::i32, Operand: Op.getOperand(i: 1)) :
2508 DAG.getNode(Opcode: MipsISD::ExtractElementF64, DL, VT: MVT::i32, N1: Op.getOperand(i: 1),
2509 N2: Const1);
2510
2511 if (HasExtractInsert) {
2512 // ext E, Y, 31, 1 ; extract bit31 of Y
2513 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
2514 SDValue E = DAG.getNode(Opcode: MipsISD::Ext, DL, VT: MVT::i32, N1: Y, N2: Const31, N3: Const1);
2515 Res = DAG.getNode(Opcode: MipsISD::Ins, DL, VT: MVT::i32, N1: E, N2: Const31, N3: Const1, N4: X);
2516 } else {
2517 // sll SllX, X, 1
2518 // srl SrlX, SllX, 1
2519 // srl SrlY, Y, 31
2520 // sll SllY, SrlX, 31
2521 // or Or, SrlX, SllY
2522 SDValue SllX = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i32, N1: X, N2: Const1);
2523 SDValue SrlX = DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i32, N1: SllX, N2: Const1);
2524 SDValue SrlY = DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i32, N1: Y, N2: Const31);
2525 SDValue SllY = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i32, N1: SrlY, N2: Const31);
2526 Res = DAG.getNode(Opcode: ISD::OR, DL, VT: MVT::i32, N1: SrlX, N2: SllY);
2527 }
2528
2529 if (TyX == MVT::f32)
2530 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: Op.getOperand(i: 0).getValueType(), Operand: Res);
2531
2532 SDValue LowX = DAG.getNode(Opcode: MipsISD::ExtractElementF64, DL, VT: MVT::i32,
2533 N1: Op.getOperand(i: 0),
2534 N2: DAG.getConstant(Val: 0, DL, VT: MVT::i32));
2535 return DAG.getNode(Opcode: MipsISD::BuildPairF64, DL, VT: MVT::f64, N1: LowX, N2: Res);
2536}
2537
2538static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
2539 bool HasExtractInsert) {
2540 unsigned WidthX = Op.getOperand(i: 0).getValueSizeInBits();
2541 unsigned WidthY = Op.getOperand(i: 1).getValueSizeInBits();
2542 EVT TyX = MVT::getIntegerVT(BitWidth: WidthX), TyY = MVT::getIntegerVT(BitWidth: WidthY);
2543 SDLoc DL(Op);
2544 SDValue Const1 = DAG.getConstant(Val: 1, DL, VT: MVT::i32);
2545
2546 // Bitcast to integer nodes.
2547 SDValue X = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: TyX, Operand: Op.getOperand(i: 0));
2548 SDValue Y = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: TyY, Operand: Op.getOperand(i: 1));
2549
2550 if (HasExtractInsert) {
2551 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
2552 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
2553 SDValue E = DAG.getNode(Opcode: MipsISD::Ext, DL, VT: TyY, N1: Y,
2554 N2: DAG.getConstant(Val: WidthY - 1, DL, VT: MVT::i32), N3: Const1);
2555
2556 if (WidthX > WidthY)
2557 E = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: TyX, Operand: E);
2558 else if (WidthY > WidthX)
2559 E = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: TyX, Operand: E);
2560
2561 SDValue I = DAG.getNode(Opcode: MipsISD::Ins, DL, VT: TyX, N1: E,
2562 N2: DAG.getConstant(Val: WidthX - 1, DL, VT: MVT::i32), N3: Const1,
2563 N4: X);
2564 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: Op.getOperand(i: 0).getValueType(), Operand: I);
2565 }
2566
2567 // (d)sll SllX, X, 1
2568 // (d)srl SrlX, SllX, 1
2569 // (d)srl SrlY, Y, width(Y)-1
2570 // (d)sll SllY, SrlX, width(Y)-1
2571 // or Or, SrlX, SllY
2572 SDValue SllX = DAG.getNode(Opcode: ISD::SHL, DL, VT: TyX, N1: X, N2: Const1);
2573 SDValue SrlX = DAG.getNode(Opcode: ISD::SRL, DL, VT: TyX, N1: SllX, N2: Const1);
2574 SDValue SrlY = DAG.getNode(Opcode: ISD::SRL, DL, VT: TyY, N1: Y,
2575 N2: DAG.getConstant(Val: WidthY - 1, DL, VT: MVT::i32));
2576
2577 if (WidthX > WidthY)
2578 SrlY = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: TyX, Operand: SrlY);
2579 else if (WidthY > WidthX)
2580 SrlY = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: TyX, Operand: SrlY);
2581
2582 SDValue SllY = DAG.getNode(Opcode: ISD::SHL, DL, VT: TyX, N1: SrlY,
2583 N2: DAG.getConstant(Val: WidthX - 1, DL, VT: MVT::i32));
2584 SDValue Or = DAG.getNode(Opcode: ISD::OR, DL, VT: TyX, N1: SrlX, N2: SllY);
2585 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: Op.getOperand(i: 0).getValueType(), Operand: Or);
2586}
2587
2588SDValue
2589MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2590 if (Subtarget.isGP64bit())
2591 return lowerFCOPYSIGN64(Op, DAG, HasExtractInsert: Subtarget.hasExtractInsert());
2592
2593 return lowerFCOPYSIGN32(Op, DAG, HasExtractInsert: Subtarget.hasExtractInsert());
2594}
2595
2596SDValue MipsTargetLowering::lowerFABS32(SDValue Op, SelectionDAG &DAG,
2597 bool HasExtractInsert) const {
2598 SDLoc DL(Op);
2599 SDValue Res, Const1 = DAG.getConstant(Val: 1, DL, VT: MVT::i32);
2600
2601 if (DAG.getTarget().Options.NoNaNsFPMath || Subtarget.inAbs2008Mode())
2602 return DAG.getNode(Opcode: MipsISD::FAbs, DL, VT: Op.getValueType(), Operand: Op.getOperand(i: 0));
2603
2604 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2605 // to i32.
2606 SDValue X = (Op.getValueType() == MVT::f32)
2607 ? DAG.getNode(Opcode: ISD::BITCAST, DL, VT: MVT::i32, Operand: Op.getOperand(i: 0))
2608 : DAG.getNode(Opcode: MipsISD::ExtractElementF64, DL, VT: MVT::i32,
2609 N1: Op.getOperand(i: 0), N2: Const1);
2610
2611 // Clear MSB.
2612 if (HasExtractInsert)
2613 Res = DAG.getNode(Opcode: MipsISD::Ins, DL, VT: MVT::i32,
2614 N1: DAG.getRegister(Reg: Mips::ZERO, VT: MVT::i32),
2615 N2: DAG.getConstant(Val: 31, DL, VT: MVT::i32), N3: Const1, N4: X);
2616 else {
2617 // TODO: Provide DAG patterns which transform (and x, cst)
2618 // back to a (shl (srl x (clz cst)) (clz cst)) sequence.
2619 SDValue SllX = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i32, N1: X, N2: Const1);
2620 Res = DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i32, N1: SllX, N2: Const1);
2621 }
2622
2623 if (Op.getValueType() == MVT::f32)
2624 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: MVT::f32, Operand: Res);
2625
2626 // FIXME: For mips32r2, the sequence of (BuildPairF64 (ins (ExtractElementF64
2627 // Op 1), $zero, 31 1) (ExtractElementF64 Op 0)) and the Op has one use, we
2628 // should be able to drop the usage of mfc1/mtc1 and rewrite the register in
2629 // place.
2630 SDValue LowX =
2631 DAG.getNode(Opcode: MipsISD::ExtractElementF64, DL, VT: MVT::i32, N1: Op.getOperand(i: 0),
2632 N2: DAG.getConstant(Val: 0, DL, VT: MVT::i32));
2633 return DAG.getNode(Opcode: MipsISD::BuildPairF64, DL, VT: MVT::f64, N1: LowX, N2: Res);
2634}
2635
2636SDValue MipsTargetLowering::lowerFABS64(SDValue Op, SelectionDAG &DAG,
2637 bool HasExtractInsert) const {
2638 SDLoc DL(Op);
2639 SDValue Res, Const1 = DAG.getConstant(Val: 1, DL, VT: MVT::i32);
2640
2641 if (DAG.getTarget().Options.NoNaNsFPMath || Subtarget.inAbs2008Mode())
2642 return DAG.getNode(Opcode: MipsISD::FAbs, DL, VT: Op.getValueType(), Operand: Op.getOperand(i: 0));
2643
2644 // Bitcast to integer node.
2645 SDValue X = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: MVT::i64, Operand: Op.getOperand(i: 0));
2646
2647 // Clear MSB.
2648 if (HasExtractInsert)
2649 Res = DAG.getNode(Opcode: MipsISD::Ins, DL, VT: MVT::i64,
2650 N1: DAG.getRegister(Reg: Mips::ZERO_64, VT: MVT::i64),
2651 N2: DAG.getConstant(Val: 63, DL, VT: MVT::i32), N3: Const1, N4: X);
2652 else {
2653 SDValue SllX = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i64, N1: X, N2: Const1);
2654 Res = DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i64, N1: SllX, N2: Const1);
2655 }
2656
2657 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: MVT::f64, Operand: Res);
2658}
2659
2660SDValue MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const {
2661 if ((ABI.IsN32() || ABI.IsN64()) && (Op.getValueType() == MVT::f64))
2662 return lowerFABS64(Op, DAG, HasExtractInsert: Subtarget.hasExtractInsert());
2663
2664 return lowerFABS32(Op, DAG, HasExtractInsert: Subtarget.hasExtractInsert());
2665}
2666
2667SDValue MipsTargetLowering::lowerFCANONICALIZE(SDValue Op,
2668 SelectionDAG &DAG) const {
2669 SDLoc DL(Op);
2670 EVT VT = Op.getValueType();
2671 SDValue Operand = Op.getOperand(i: 0);
2672 SDNodeFlags Flags = Op->getFlags();
2673
2674 if (Flags.hasNoNaNs() || DAG.isKnownNeverNaN(Op: Operand))
2675 return Operand;
2676
2677 SDValue Quiet = DAG.getNode(Opcode: ISD::FADD, DL, VT, N1: Operand, N2: Operand);
2678 return DAG.getSelectCC(DL, LHS: Operand, RHS: Operand, True: Quiet, False: Operand, Cond: ISD::SETUO);
2679}
2680
2681SDValue MipsTargetLowering::
2682lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2683 // check the depth
2684 if (Op.getConstantOperandVal(i: 0) != 0) {
2685 DAG.getContext()->emitError(
2686 ErrorStr: "return address can be determined only for current frame");
2687 return SDValue();
2688 }
2689
2690 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2691 MFI.setFrameAddressIsTaken(true);
2692 EVT VT = Op.getValueType();
2693 SDLoc DL(Op);
2694 SDValue FrameAddr = DAG.getCopyFromReg(
2695 Chain: DAG.getEntryNode(), dl: DL, Reg: ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2696 return FrameAddr;
2697}
2698
2699SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2700 SelectionDAG &DAG) const {
2701 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2702 return SDValue();
2703
2704 // check the depth
2705 if (Op.getConstantOperandVal(i: 0) != 0) {
2706 DAG.getContext()->emitError(
2707 ErrorStr: "return address can be determined only for current frame");
2708 return SDValue();
2709 }
2710
2711 MachineFunction &MF = DAG.getMachineFunction();
2712 MachineFrameInfo &MFI = MF.getFrameInfo();
2713 MVT VT = Op.getSimpleValueType();
2714 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2715 MFI.setReturnAddressIsTaken(true);
2716
2717 // Return RA, which contains the return address. Mark it an implicit live-in.
2718 Register Reg = MF.addLiveIn(PReg: RA, RC: getRegClassFor(VT));
2719 return DAG.getCopyFromReg(Chain: DAG.getEntryNode(), dl: SDLoc(Op), Reg, VT);
2720}
2721
2722// An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2723// generated from __builtin_eh_return (offset, handler)
2724// The effect of this is to adjust the stack pointer by "offset"
2725// and then branch to "handler".
2726SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2727 const {
2728 MachineFunction &MF = DAG.getMachineFunction();
2729 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2730
2731 MipsFI->setCallsEhReturn();
2732 SDValue Chain = Op.getOperand(i: 0);
2733 SDValue Offset = Op.getOperand(i: 1);
2734 SDValue Handler = Op.getOperand(i: 2);
2735 SDLoc DL(Op);
2736 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2737
2738 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2739 // EH_RETURN nodes, so that instructions are emitted back-to-back.
2740 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2741 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2742 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: OffsetReg, N: Offset, Glue: SDValue());
2743 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: AddrReg, N: Handler, Glue: Chain.getValue(R: 1));
2744 return DAG.getNode(Opcode: MipsISD::EH_RETURN, DL, VT: MVT::Other, N1: Chain,
2745 N2: DAG.getRegister(Reg: OffsetReg, VT: Ty),
2746 N3: DAG.getRegister(Reg: AddrReg, VT: getPointerTy(DL: MF.getDataLayout())),
2747 N4: Chain.getValue(R: 1));
2748}
2749
2750SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2751 SelectionDAG &DAG) const {
2752 // FIXME: Need pseudo-fence for 'singlethread' fences
2753 // FIXME: Set SType for weaker fences where supported/appropriate.
2754 unsigned SType = 0;
2755 SDLoc DL(Op);
2756 return DAG.getNode(Opcode: MipsISD::Sync, DL, VT: MVT::Other, N1: Op.getOperand(i: 0),
2757 N2: DAG.getConstant(Val: SType, DL, VT: MVT::i32));
2758}
2759
2760SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2761 SelectionDAG &DAG) const {
2762 SDLoc DL(Op);
2763 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2764
2765 SDValue Lo = Op.getOperand(i: 0), Hi = Op.getOperand(i: 1);
2766 SDValue Shamt = Op.getOperand(i: 2);
2767 // if shamt < (VT.bits):
2768 // lo = (shl lo, shamt)
2769 // hi = (or (shl hi, shamt) (srl (srl lo, 1), (xor shamt, (VT.bits-1))))
2770 // else:
2771 // lo = 0
2772 // hi = (shl lo, shamt[4:0])
2773 SDValue Not =
2774 DAG.getNode(Opcode: ISD::XOR, DL, VT: MVT::i32, N1: Shamt,
2775 N2: DAG.getConstant(Val: VT.getSizeInBits() - 1, DL, VT: MVT::i32));
2776 SDValue ShiftRight1Lo = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Lo,
2777 N2: DAG.getConstant(Val: 1, DL, VT));
2778 SDValue ShiftRightLo = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: ShiftRight1Lo, N2: Not);
2779 SDValue ShiftLeftHi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Hi, N2: Shamt);
2780 SDValue Or = DAG.getNode(Opcode: ISD::OR, DL, VT, N1: ShiftLeftHi, N2: ShiftRightLo);
2781 SDValue ShiftLeftLo = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Lo, N2: Shamt);
2782 SDValue Cond = DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i32, N1: Shamt,
2783 N2: DAG.getConstant(Val: VT.getSizeInBits(), DL, VT: MVT::i32));
2784 Lo = DAG.getNode(Opcode: ISD::SELECT, DL, VT, N1: Cond,
2785 N2: DAG.getConstant(Val: 0, DL, VT), N3: ShiftLeftLo);
2786 Hi = DAG.getNode(Opcode: ISD::SELECT, DL, VT, N1: Cond, N2: ShiftLeftLo, N3: Or);
2787
2788 SDValue Ops[2] = {Lo, Hi};
2789 return DAG.getMergeValues(Ops, dl: DL);
2790}
2791
2792SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2793 bool IsSRA) const {
2794 SDLoc DL(Op);
2795 SDValue Lo = Op.getOperand(i: 0), Hi = Op.getOperand(i: 1);
2796 SDValue Shamt = Op.getOperand(i: 2);
2797 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2798
2799 // if shamt < (VT.bits):
2800 // lo = (or (shl (shl hi, 1), (xor shamt, (VT.bits-1))) (srl lo, shamt))
2801 // if isSRA:
2802 // hi = (sra hi, shamt)
2803 // else:
2804 // hi = (srl hi, shamt)
2805 // else:
2806 // if isSRA:
2807 // lo = (sra hi, shamt[4:0])
2808 // hi = (sra hi, 31)
2809 // else:
2810 // lo = (srl hi, shamt[4:0])
2811 // hi = 0
2812 SDValue Not =
2813 DAG.getNode(Opcode: ISD::XOR, DL, VT: MVT::i32, N1: Shamt,
2814 N2: DAG.getConstant(Val: VT.getSizeInBits() - 1, DL, VT: MVT::i32));
2815 SDValue ShiftLeft1Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Hi,
2816 N2: DAG.getConstant(Val: 1, DL, VT));
2817 SDValue ShiftLeftHi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: ShiftLeft1Hi, N2: Not);
2818 SDValue ShiftRightLo = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Lo, N2: Shamt);
2819 SDValue Or = DAG.getNode(Opcode: ISD::OR, DL, VT, N1: ShiftLeftHi, N2: ShiftRightLo);
2820 SDValue ShiftRightHi = DAG.getNode(Opcode: IsSRA ? ISD::SRA : ISD::SRL,
2821 DL, VT, N1: Hi, N2: Shamt);
2822 SDValue Cond = DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i32, N1: Shamt,
2823 N2: DAG.getConstant(Val: VT.getSizeInBits(), DL, VT: MVT::i32));
2824 SDValue Ext = DAG.getNode(Opcode: ISD::SRA, DL, VT, N1: Hi,
2825 N2: DAG.getConstant(Val: VT.getSizeInBits() - 1, DL, VT));
2826
2827 if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) {
2828 SDVTList VTList = DAG.getVTList(VT1: VT, VT2: VT);
2829 return DAG.getNode(Opcode: Subtarget.isGP64bit() ? MipsISD::DOUBLE_SELECT_I64
2830 : MipsISD::DOUBLE_SELECT_I,
2831 DL, VTList, N1: Cond, N2: ShiftRightHi,
2832 N3: IsSRA ? Ext : DAG.getConstant(Val: 0, DL, VT), N4: Or,
2833 N5: ShiftRightHi);
2834 }
2835
2836 Lo = DAG.getNode(Opcode: ISD::SELECT, DL, VT, N1: Cond, N2: ShiftRightHi, N3: Or);
2837 Hi = DAG.getNode(Opcode: ISD::SELECT, DL, VT, N1: Cond,
2838 N2: IsSRA ? Ext : DAG.getConstant(Val: 0, DL, VT), N3: ShiftRightHi);
2839
2840 SDValue Ops[2] = {Lo, Hi};
2841 return DAG.getMergeValues(Ops, dl: DL);
2842}
2843
2844static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2845 SDValue Chain, SDValue Src, unsigned Offset) {
2846 SDValue Ptr = LD->getBasePtr();
2847 EVT VT = LD->getValueType(ResNo: 0), MemVT = LD->getMemoryVT();
2848 EVT BasePtrVT = Ptr.getValueType();
2849 SDLoc DL(LD);
2850 SDVTList VTList = DAG.getVTList(VT1: VT, VT2: MVT::Other);
2851
2852 if (Offset)
2853 Ptr = DAG.getNode(Opcode: ISD::ADD, DL, VT: BasePtrVT, N1: Ptr,
2854 N2: DAG.getConstant(Val: Offset, DL, VT: BasePtrVT));
2855
2856 SDValue Ops[] = { Chain, Ptr, Src };
2857 return DAG.getMemIntrinsicNode(Opcode: Opc, dl: DL, VTList, Ops, MemVT,
2858 MMO: LD->getMemOperand());
2859}
2860
2861// Expand an unaligned 32 or 64-bit integer load node.
2862SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2863 LoadSDNode *LD = cast<LoadSDNode>(Val&: Op);
2864 EVT MemVT = LD->getMemoryVT();
2865
2866 if (Subtarget.systemSupportsUnalignedAccess())
2867 return Op;
2868
2869 // Return if load is aligned or if MemVT is neither i32 nor i64.
2870 if ((LD->getAlign().value() >= (MemVT.getSizeInBits() / 8)) ||
2871 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2872 return SDValue();
2873
2874 bool IsLittle = Subtarget.isLittle();
2875 EVT VT = Op.getValueType();
2876 ISD::LoadExtType ExtType = LD->getExtensionType();
2877 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2878
2879 assert((VT == MVT::i32) || (VT == MVT::i64));
2880
2881 // Expand
2882 // (set dst, (i64 (load baseptr)))
2883 // to
2884 // (set tmp, (ldl (add baseptr, 7), undef))
2885 // (set dst, (ldr baseptr, tmp))
2886 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2887 SDValue LDL = createLoadLR(Opc: MipsISD::LDL, DAG, LD, Chain, Src: Undef,
2888 Offset: IsLittle ? 7 : 0);
2889 return createLoadLR(Opc: MipsISD::LDR, DAG, LD, Chain: LDL.getValue(R: 1), Src: LDL,
2890 Offset: IsLittle ? 0 : 7);
2891 }
2892
2893 SDValue LWL = createLoadLR(Opc: MipsISD::LWL, DAG, LD, Chain, Src: Undef,
2894 Offset: IsLittle ? 3 : 0);
2895 SDValue LWR = createLoadLR(Opc: MipsISD::LWR, DAG, LD, Chain: LWL.getValue(R: 1), Src: LWL,
2896 Offset: IsLittle ? 0 : 3);
2897
2898 // Expand
2899 // (set dst, (i32 (load baseptr))) or
2900 // (set dst, (i64 (sextload baseptr))) or
2901 // (set dst, (i64 (extload baseptr)))
2902 // to
2903 // (set tmp, (lwl (add baseptr, 3), undef))
2904 // (set dst, (lwr baseptr, tmp))
2905 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2906 (ExtType == ISD::EXTLOAD))
2907 return LWR;
2908
2909 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2910
2911 // Expand
2912 // (set dst, (i64 (zextload baseptr)))
2913 // to
2914 // (set tmp0, (lwl (add baseptr, 3), undef))
2915 // (set tmp1, (lwr baseptr, tmp0))
2916 // (set tmp2, (shl tmp1, 32))
2917 // (set dst, (srl tmp2, 32))
2918 SDLoc DL(LD);
2919 SDValue Const32 = DAG.getConstant(Val: 32, DL, VT: MVT::i32);
2920 SDValue SLL = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i64, N1: LWR, N2: Const32);
2921 SDValue SRL = DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i64, N1: SLL, N2: Const32);
2922 SDValue Ops[] = { SRL, LWR.getValue(R: 1) };
2923 return DAG.getMergeValues(Ops, dl: DL);
2924}
2925
2926static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2927 SDValue Chain, unsigned Offset) {
2928 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2929 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2930 SDLoc DL(SD);
2931 SDVTList VTList = DAG.getVTList(VT: MVT::Other);
2932
2933 if (Offset)
2934 Ptr = DAG.getNode(Opcode: ISD::ADD, DL, VT: BasePtrVT, N1: Ptr,
2935 N2: DAG.getConstant(Val: Offset, DL, VT: BasePtrVT));
2936
2937 SDValue Ops[] = { Chain, Value, Ptr };
2938 return DAG.getMemIntrinsicNode(Opcode: Opc, dl: DL, VTList, Ops, MemVT,
2939 MMO: SD->getMemOperand());
2940}
2941
2942// Expand an unaligned 32 or 64-bit integer store node.
2943static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2944 bool IsLittle) {
2945 SDValue Value = SD->getValue(), Chain = SD->getChain();
2946 EVT VT = Value.getValueType();
2947
2948 // Expand
2949 // (store val, baseptr) or
2950 // (truncstore val, baseptr)
2951 // to
2952 // (swl val, (add baseptr, 3))
2953 // (swr val, baseptr)
2954 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2955 SDValue SWL = createStoreLR(Opc: MipsISD::SWL, DAG, SD, Chain,
2956 Offset: IsLittle ? 3 : 0);
2957 return createStoreLR(Opc: MipsISD::SWR, DAG, SD, Chain: SWL, Offset: IsLittle ? 0 : 3);
2958 }
2959
2960 assert(VT == MVT::i64);
2961
2962 // Expand
2963 // (store val, baseptr)
2964 // to
2965 // (sdl val, (add baseptr, 7))
2966 // (sdr val, baseptr)
2967 SDValue SDL = createStoreLR(Opc: MipsISD::SDL, DAG, SD, Chain, Offset: IsLittle ? 7 : 0);
2968 return createStoreLR(Opc: MipsISD::SDR, DAG, SD, Chain: SDL, Offset: IsLittle ? 0 : 7);
2969}
2970
2971// Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2972static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG,
2973 bool SingleFloat) {
2974 SDValue Val = SD->getValue();
2975
2976 if (Val.getOpcode() != ISD::FP_TO_SINT ||
2977 (Val.getValueSizeInBits() > 32 && SingleFloat))
2978 return SDValue();
2979
2980 EVT FPTy = EVT::getFloatingPointVT(BitWidth: Val.getValueSizeInBits());
2981 SDValue Tr = DAG.getNode(Opcode: MipsISD::TruncIntFP, DL: SDLoc(Val), VT: FPTy,
2982 Operand: Val.getOperand(i: 0));
2983 return DAG.getStore(Chain: SD->getChain(), dl: SDLoc(SD), Val: Tr, Ptr: SD->getBasePtr(),
2984 PtrInfo: SD->getPointerInfo(), Alignment: SD->getAlign(),
2985 MMOFlags: SD->getMemOperand()->getFlags());
2986}
2987
2988SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2989 StoreSDNode *SD = cast<StoreSDNode>(Val&: Op);
2990 EVT MemVT = SD->getMemoryVT();
2991
2992 // Lower unaligned integer stores.
2993 if (!Subtarget.systemSupportsUnalignedAccess() &&
2994 (SD->getAlign().value() < (MemVT.getSizeInBits() / 8)) &&
2995 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2996 return lowerUnalignedIntStore(SD, DAG, IsLittle: Subtarget.isLittle());
2997
2998 return lowerFP_TO_SINT_STORE(SD, DAG, SingleFloat: Subtarget.isSingleFloat());
2999}
3000
3001SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
3002 SelectionDAG &DAG) const {
3003
3004 // Return a fixed StackObject with offset 0 which points to the old stack
3005 // pointer.
3006 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
3007 EVT ValTy = Op->getValueType(ResNo: 0);
3008 int FI = MFI.CreateFixedObject(Size: Op.getValueSizeInBits() / 8, SPOffset: 0, IsImmutable: false);
3009 return DAG.getFrameIndex(FI, VT: ValTy);
3010}
3011
3012SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
3013 SelectionDAG &DAG) const {
3014 if (Op.getValueSizeInBits() > 32 && Subtarget.isSingleFloat())
3015 return SDValue();
3016
3017 EVT FPTy = EVT::getFloatingPointVT(BitWidth: Op.getValueSizeInBits());
3018 SDValue Trunc = DAG.getNode(Opcode: MipsISD::TruncIntFP, DL: SDLoc(Op), VT: FPTy,
3019 Operand: Op.getOperand(i: 0));
3020 return DAG.getNode(Opcode: ISD::BITCAST, DL: SDLoc(Op), VT: Op.getValueType(), Operand: Trunc);
3021}
3022
3023SDValue MipsTargetLowering::lowerConstantFP(SDValue Op,
3024 SelectionDAG &DAG) const {
3025 SDLoc DL(Op);
3026 EVT VT = Op.getSimpleValueType();
3027 SDNode *N = Op.getNode();
3028 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Val: N);
3029
3030 if (!CFP->isNaN() || Subtarget.isNaN2008()) {
3031 return SDValue();
3032 }
3033
3034 APFloat NaNValue = CFP->getValueAPF();
3035 auto &Sem = NaNValue.getSemantics();
3036
3037 // The MSB of the mantissa should be zero for QNaNs in the MIPS legacy NaN
3038 // encodings, and one for sNaNs. Check every NaN constants and make sure
3039 // they are correctly encoded for legacy encodings.
3040 if (!NaNValue.isSignaling()) {
3041 APFloat RealQNaN = NaNValue.getSNaN(Sem);
3042 return DAG.getConstantFP(Val: RealQNaN, DL, VT);
3043 }
3044 return SDValue();
3045}
3046
3047//===----------------------------------------------------------------------===//
3048// Calling Convention Implementation
3049//===----------------------------------------------------------------------===//
3050
3051//===----------------------------------------------------------------------===//
3052// TODO: Implement a generic logic using tblgen that can support this.
3053// Mips O32 ABI rules:
3054// ---
3055// i32 - Passed in A0, A1, A2, A3 and stack
3056// f32 - Only passed in f32 registers if no int reg has been used yet to hold
3057// an argument. Otherwise, passed in A1, A2, A3 and stack.
3058// f64 - Only passed in two aliased f32 registers if no int reg has been used
3059// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
3060// not used, it must be shadowed. If only A3 is available, shadow it and
3061// go to stack.
3062// vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack.
3063// vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3}
3064// with the remainder spilled to the stack.
3065// vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases
3066// spilling the remainder to the stack.
3067//
3068// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
3069//===----------------------------------------------------------------------===//
3070
3071static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
3072 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
3073 CCState &State, ArrayRef<MCPhysReg> F64Regs) {
3074 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
3075 State.getMachineFunction().getSubtarget());
3076
3077 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
3078
3079 const MipsCCState * MipsState = static_cast<MipsCCState *>(&State);
3080
3081 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
3082
3083 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
3084
3085 // Do not process byval args here.
3086 if (ArgFlags.isByVal())
3087 return true;
3088
3089 // Promote i8 and i16
3090 if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
3091 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
3092 LocVT = MVT::i32;
3093 if (ArgFlags.isSExt())
3094 LocInfo = CCValAssign::SExtUpper;
3095 else if (ArgFlags.isZExt())
3096 LocInfo = CCValAssign::ZExtUpper;
3097 else
3098 LocInfo = CCValAssign::AExtUpper;
3099 }
3100 }
3101
3102 // Promote i8 and i16
3103 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
3104 LocVT = MVT::i32;
3105 if (ArgFlags.isSExt())
3106 LocInfo = CCValAssign::SExt;
3107 else if (ArgFlags.isZExt())
3108 LocInfo = CCValAssign::ZExt;
3109 else
3110 LocInfo = CCValAssign::AExt;
3111 }
3112
3113 unsigned Reg;
3114
3115 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
3116 // is true: function is vararg, argument is 3rd or higher, there is previous
3117 // argument which is not f32 or f64.
3118 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 ||
3119 State.getFirstUnallocated(Regs: F32Regs) != ValNo;
3120 Align OrigAlign = ArgFlags.getNonZeroOrigAlign();
3121 bool isI64 = (ValVT == MVT::i32 && OrigAlign == Align(8));
3122 bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo);
3123
3124 // The MIPS vector ABI for floats passes them in a pair of registers
3125 if (ValVT == MVT::i32 && isVectorFloat) {
3126 // This is the start of an vector that was scalarized into an unknown number
3127 // of components. It doesn't matter how many there are. Allocate one of the
3128 // notional 8 byte aligned registers which map onto the argument stack, and
3129 // shadow the register lost to alignment requirements.
3130 if (ArgFlags.isSplit()) {
3131 Reg = State.AllocateReg(Regs: FloatVectorIntRegs);
3132 if (Reg == Mips::A2)
3133 State.AllocateReg(Reg: Mips::A1);
3134 else if (Reg == 0)
3135 State.AllocateReg(Reg: Mips::A3);
3136 } else {
3137 // If we're an intermediate component of the split, we can just attempt to
3138 // allocate a register directly.
3139 Reg = State.AllocateReg(Regs: IntRegs);
3140 }
3141 } else if (ValVT == MVT::i32 ||
3142 (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
3143 Reg = State.AllocateReg(Regs: IntRegs);
3144 // If this is the first part of an i64 arg,
3145 // the allocated register must be either A0 or A2.
3146 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
3147 Reg = State.AllocateReg(Regs: IntRegs);
3148 LocVT = MVT::i32;
3149 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
3150 // Allocate int register and shadow next int register. If first
3151 // available register is Mips::A1 or Mips::A3, shadow it too.
3152 Reg = State.AllocateReg(Regs: IntRegs);
3153 if (Reg == Mips::A1 || Reg == Mips::A3)
3154 Reg = State.AllocateReg(Regs: IntRegs);
3155
3156 if (Reg) {
3157 LocVT = MVT::i32;
3158
3159 State.addLoc(
3160 V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3161 MCRegister HiReg = State.AllocateReg(Regs: IntRegs);
3162 assert(HiReg);
3163 State.addLoc(
3164 V: CCValAssign::getCustomReg(ValNo, ValVT, Reg: HiReg, LocVT, HTP: LocInfo));
3165 return false;
3166 }
3167 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
3168 // we are guaranteed to find an available float register
3169 if (ValVT == MVT::f32) {
3170 Reg = State.AllocateReg(Regs: F32Regs);
3171 // Shadow int register
3172 State.AllocateReg(Regs: IntRegs);
3173 } else {
3174 Reg = State.AllocateReg(Regs: F64Regs);
3175 // Shadow int registers
3176 MCRegister Reg2 = State.AllocateReg(Regs: IntRegs);
3177 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
3178 State.AllocateReg(Regs: IntRegs);
3179 State.AllocateReg(Regs: IntRegs);
3180 }
3181 } else
3182 llvm_unreachable("Cannot handle this ValVT.");
3183
3184 if (!Reg) {
3185 unsigned Offset = State.AllocateStack(Size: ValVT.getStoreSize(), Alignment: OrigAlign);
3186 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, HTP: LocInfo));
3187 } else
3188 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3189
3190 return false;
3191}
3192
3193static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
3194 MVT LocVT, CCValAssign::LocInfo LocInfo,
3195 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3196 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
3197
3198 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
3199}
3200
3201static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
3202 MVT LocVT, CCValAssign::LocInfo LocInfo,
3203 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3204 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
3205
3206 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
3207}
3208
3209static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
3210 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
3211 CCState &State) LLVM_ATTRIBUTE_UNUSED;
3212
3213#include "MipsGenCallingConv.inc"
3214
3215 CCAssignFn *MipsTargetLowering::CCAssignFnForCall() const{
3216 return CC_Mips_FixedArg;
3217 }
3218
3219 CCAssignFn *MipsTargetLowering::CCAssignFnForReturn() const{
3220 return RetCC_Mips;
3221 }
3222//===----------------------------------------------------------------------===//
3223// Call Calling Convention Implementation
3224//===----------------------------------------------------------------------===//
3225
3226SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
3227 SDValue Chain, SDValue Arg,
3228 const SDLoc &DL, bool IsTailCall,
3229 SelectionDAG &DAG) const {
3230 if (!IsTailCall) {
3231 SDValue PtrOff =
3232 DAG.getNode(Opcode: ISD::ADD, DL, VT: getPointerTy(DL: DAG.getDataLayout()), N1: StackPtr,
3233 N2: DAG.getIntPtrConstant(Val: Offset, DL));
3234 return DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo());
3235 }
3236
3237 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
3238 int FI = MFI.CreateFixedObject(Size: Arg.getValueSizeInBits() / 8, SPOffset: Offset, IsImmutable: false);
3239 SDValue FIN = DAG.getFrameIndex(FI, VT: getPointerTy(DL: DAG.getDataLayout()));
3240 return DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: FIN, PtrInfo: MachinePointerInfo(), Alignment: MaybeAlign(),
3241 MMOFlags: MachineMemOperand::MOVolatile);
3242}
3243
3244void MipsTargetLowering::
3245getOpndList(SmallVectorImpl<SDValue> &Ops,
3246 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3247 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
3248 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
3249 SDValue Chain) const {
3250 // Insert node "GP copy globalreg" before call to function.
3251 //
3252 // R_MIPS_CALL* operators (emitted when non-internal functions are called
3253 // in PIC mode) allow symbols to be resolved via lazy binding.
3254 // The lazy binding stub requires GP to point to the GOT.
3255 // Note that we don't need GP to point to the GOT for indirect calls
3256 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
3257 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
3258 // used for the function (that is, Mips linker doesn't generate lazy binding
3259 // stub for a function whose address is taken in the program).
3260 if (IsPICCall && !InternalLinkage && IsCallReloc) {
3261 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
3262 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
3263 RegsToPass.push_back(x: std::make_pair(x&: GPReg, y: getGlobalReg(DAG&: CLI.DAG, Ty)));
3264 }
3265
3266 // Build a sequence of copy-to-reg nodes chained together with token
3267 // chain and flag operands which copy the outgoing args into registers.
3268 // The InGlue in necessary since all emitted instructions must be
3269 // stuck together.
3270 SDValue InGlue;
3271
3272 for (auto &R : RegsToPass) {
3273 Chain = CLI.DAG.getCopyToReg(Chain, dl: CLI.DL, Reg: R.first, N: R.second, Glue: InGlue);
3274 InGlue = Chain.getValue(R: 1);
3275 }
3276
3277 // Add argument registers to the end of the list so that they are
3278 // known live into the call.
3279 for (auto &R : RegsToPass)
3280 Ops.push_back(Elt: CLI.DAG.getRegister(Reg: R.first, VT: R.second.getValueType()));
3281
3282 // Add a register mask operand representing the call-preserved registers.
3283 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3284 const uint32_t *Mask =
3285 TRI->getCallPreservedMask(MF: CLI.DAG.getMachineFunction(), CLI.CallConv);
3286 assert(Mask && "Missing call preserved mask for calling convention");
3287 if (Subtarget.inMips16HardFloat()) {
3288 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: CLI.Callee)) {
3289 StringRef Sym = G->getGlobal()->getName();
3290 Function *F = G->getGlobal()->getParent()->getFunction(Name: Sym);
3291 if (F && F->hasFnAttribute(Kind: "__Mips16RetHelper")) {
3292 Mask = MipsRegisterInfo::getMips16RetHelperMask();
3293 }
3294 }
3295 }
3296 Ops.push_back(Elt: CLI.DAG.getRegisterMask(RegMask: Mask));
3297
3298 if (InGlue.getNode())
3299 Ops.push_back(Elt: InGlue);
3300}
3301
3302void MipsTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
3303 SDNode *Node) const {
3304 switch (MI.getOpcode()) {
3305 default:
3306 return;
3307 case Mips::JALR:
3308 case Mips::JALRPseudo:
3309 case Mips::JALR64:
3310 case Mips::JALR64Pseudo:
3311 case Mips::JALR16_MM:
3312 case Mips::JALRC16_MMR6:
3313 case Mips::TAILCALLREG:
3314 case Mips::TAILCALLREG64:
3315 case Mips::TAILCALLR6REG:
3316 case Mips::TAILCALL64R6REG:
3317 case Mips::TAILCALLREG_MM:
3318 case Mips::TAILCALLREG_MMR6: {
3319 if (!EmitJalrReloc ||
3320 Subtarget.inMips16Mode() ||
3321 !isPositionIndependent() ||
3322 Node->getNumOperands() < 1 ||
3323 Node->getOperand(Num: 0).getNumOperands() < 2) {
3324 return;
3325 }
3326 // We are after the callee address, set by LowerCall().
3327 // If added to MI, asm printer will emit .reloc R_MIPS_JALR for the
3328 // symbol.
3329 const SDValue TargetAddr = Node->getOperand(Num: 0).getOperand(i: 1);
3330 StringRef Sym;
3331 if (const GlobalAddressSDNode *G =
3332 dyn_cast_or_null<const GlobalAddressSDNode>(Val: TargetAddr)) {
3333 // We must not emit the R_MIPS_JALR relocation against data symbols
3334 // since this will cause run-time crashes if the linker replaces the
3335 // call instruction with a relative branch to the data symbol.
3336 if (!isa<Function>(Val: G->getGlobal())) {
3337 LLVM_DEBUG(dbgs() << "Not adding R_MIPS_JALR against data symbol "
3338 << G->getGlobal()->getName() << "\n");
3339 return;
3340 }
3341 Sym = G->getGlobal()->getName();
3342 }
3343 else if (const ExternalSymbolSDNode *ES =
3344 dyn_cast_or_null<const ExternalSymbolSDNode>(Val: TargetAddr)) {
3345 Sym = ES->getSymbol();
3346 }
3347
3348 if (Sym.empty())
3349 return;
3350
3351 MachineFunction *MF = MI.getParent()->getParent();
3352 MCSymbol *S = MF->getContext().getOrCreateSymbol(Name: Sym);
3353 LLVM_DEBUG(dbgs() << "Adding R_MIPS_JALR against " << Sym << "\n");
3354 MI.addOperand(Op: MachineOperand::CreateMCSymbol(Sym: S, TargetFlags: MipsII::MO_JALR));
3355 }
3356 }
3357}
3358
3359/// LowerCall - functions arguments are copied from virtual regs to
3360/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
3361SDValue
3362MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3363 SmallVectorImpl<SDValue> &InVals) const {
3364 SelectionDAG &DAG = CLI.DAG;
3365 SDLoc DL = CLI.DL;
3366 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3367 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3368 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3369 SDValue Chain = CLI.Chain;
3370 SDValue Callee = CLI.Callee;
3371 bool &IsTailCall = CLI.IsTailCall;
3372 CallingConv::ID CallConv = CLI.CallConv;
3373 bool IsVarArg = CLI.IsVarArg;
3374
3375 MachineFunction &MF = DAG.getMachineFunction();
3376 MachineFrameInfo &MFI = MF.getFrameInfo();
3377 const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
3378 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
3379 bool IsPIC = isPositionIndependent();
3380
3381 // Analyze operands of the call, assigning locations to each operand.
3382 SmallVector<CCValAssign, 16> ArgLocs;
3383 MipsCCState CCInfo(
3384 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
3385 MipsCCState::getSpecialCallingConvForCallee(Callee: Callee.getNode(), Subtarget));
3386
3387 const ExternalSymbolSDNode *ES =
3388 dyn_cast_or_null<const ExternalSymbolSDNode>(Val: Callee.getNode());
3389
3390 // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which
3391 // is during the lowering of a call with a byval argument which produces
3392 // a call to memcpy. For the O32 case, this causes the caller to allocate
3393 // stack space for the reserved argument area for the callee, then recursively
3394 // again for the memcpy call. In the NEWABI case, this doesn't occur as those
3395 // ABIs mandate that the callee allocates the reserved argument area. We do
3396 // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though.
3397 //
3398 // If the callee has a byval argument and memcpy is used, we are mandated
3399 // to already have produced a reserved argument area for the callee for O32.
3400 // Therefore, the reserved argument area can be reused for both calls.
3401 //
3402 // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START
3403 // present, as we have yet to hook that node onto the chain.
3404 //
3405 // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this
3406 // case. GCC does a similar trick, in that wherever possible, it calculates
3407 // the maximum out going argument area (including the reserved area), and
3408 // preallocates the stack space on entrance to the caller.
3409 //
3410 // FIXME: We should do the same for efficiency and space.
3411
3412 // Note: The check on the calling convention below must match
3413 // MipsABIInfo::GetCalleeAllocdArgSizeInBytes().
3414 bool MemcpyInByVal = ES && StringRef(ES->getSymbol()) == "memcpy" &&
3415 CallConv != CallingConv::Fast &&
3416 Chain.getOpcode() == ISD::CALLSEQ_START;
3417
3418 // Allocate the reserved argument area. It seems strange to do this from the
3419 // caller side but removing it breaks the frame size calculation.
3420 unsigned ReservedArgArea =
3421 MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CC: CallConv);
3422 CCInfo.AllocateStack(Size: ReservedArgArea, Alignment: Align(1));
3423
3424 CCInfo.AnalyzeCallOperands(Outs, Fn: CC_Mips, FuncArgs&: CLI.getArgs(),
3425 Func: ES ? ES->getSymbol() : nullptr);
3426
3427 // Get a count of how many bytes are to be pushed on the stack.
3428 unsigned StackSize = CCInfo.getStackSize();
3429
3430 // Call site info for function parameters tracking.
3431 MachineFunction::CallSiteInfo CSInfo;
3432
3433 // Check if it's really possible to do a tail call. Restrict it to functions
3434 // that are part of this compilation unit.
3435 bool InternalLinkage = false;
3436 if (IsTailCall) {
3437 IsTailCall = isEligibleForTailCallOptimization(
3438 CCInfo, NextStackOffset: StackSize, FI: *MF.getInfo<MipsFunctionInfo>());
3439 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee)) {
3440 InternalLinkage = G->getGlobal()->hasInternalLinkage();
3441 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() ||
3442 G->getGlobal()->hasPrivateLinkage() ||
3443 G->getGlobal()->hasHiddenVisibility() ||
3444 G->getGlobal()->hasProtectedVisibility());
3445 }
3446 }
3447 if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall())
3448 report_fatal_error(reason: "failed to perform tail call elimination on a call "
3449 "site marked musttail");
3450
3451 if (IsTailCall)
3452 ++NumTailCalls;
3453
3454 // Chain is the output chain of the last Load/Store or CopyToReg node.
3455 // ByValChain is the output chain of the last Memcpy node created for copying
3456 // byval arguments to the stack.
3457 unsigned StackAlignment = TFL->getStackAlignment();
3458 StackSize = alignTo(Value: StackSize, Align: StackAlignment);
3459
3460 if (!(IsTailCall || MemcpyInByVal))
3461 Chain = DAG.getCALLSEQ_START(Chain, InSize: StackSize, OutSize: 0, DL);
3462
3463 SDValue StackPtr =
3464 DAG.getCopyFromReg(Chain, dl: DL, Reg: ABI.IsN64() ? Mips::SP_64 : Mips::SP,
3465 VT: getPointerTy(DL: DAG.getDataLayout()));
3466 std::deque<std::pair<unsigned, SDValue>> RegsToPass;
3467 SmallVector<SDValue, 8> MemOpChains;
3468
3469 CCInfo.rewindByValRegsInfo();
3470
3471 // Walk the register/memloc assignments, inserting copies/loads.
3472 for (unsigned i = 0, e = ArgLocs.size(), OutIdx = 0; i != e; ++i, ++OutIdx) {
3473 SDValue Arg = OutVals[OutIdx];
3474 CCValAssign &VA = ArgLocs[i];
3475 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
3476 ISD::ArgFlagsTy Flags = Outs[OutIdx].Flags;
3477 bool UseUpperBits = false;
3478
3479 // ByVal Arg.
3480 if (Flags.isByVal()) {
3481 unsigned FirstByValReg, LastByValReg;
3482 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3483 CCInfo.getInRegsParamInfo(InRegsParamRecordIndex: ByValIdx, BeginReg&: FirstByValReg, EndReg&: LastByValReg);
3484
3485 assert(Flags.getByValSize() &&
3486 "ByVal args of size 0 should have been ignored by front-end.");
3487 assert(ByValIdx < CCInfo.getInRegsParamsCount());
3488 assert(!IsTailCall &&
3489 "Do not tail-call optimize if there is a byval argument.");
3490 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3491 FirstReg: FirstByValReg, LastReg: LastByValReg, Flags, isLittle: Subtarget.isLittle(),
3492 VA);
3493 CCInfo.nextInRegsParam();
3494 continue;
3495 }
3496
3497 // Promote the value if needed.
3498 switch (VA.getLocInfo()) {
3499 default:
3500 llvm_unreachable("Unknown loc info!");
3501 case CCValAssign::Full:
3502 if (VA.isRegLoc()) {
3503 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3504 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3505 (ValVT == MVT::i64 && LocVT == MVT::f64))
3506 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: LocVT, Operand: Arg);
3507 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3508 SDValue Lo = DAG.getNode(Opcode: MipsISD::ExtractElementF64, DL, VT: MVT::i32,
3509 N1: Arg, N2: DAG.getConstant(Val: 0, DL, VT: MVT::i32));
3510 SDValue Hi = DAG.getNode(Opcode: MipsISD::ExtractElementF64, DL, VT: MVT::i32,
3511 N1: Arg, N2: DAG.getConstant(Val: 1, DL, VT: MVT::i32));
3512 if (!Subtarget.isLittle())
3513 std::swap(a&: Lo, b&: Hi);
3514
3515 assert(VA.needsCustom());
3516
3517 Register LocRegLo = VA.getLocReg();
3518 Register LocRegHigh = ArgLocs[++i].getLocReg();
3519 RegsToPass.push_back(x: std::make_pair(x&: LocRegLo, y&: Lo));
3520 RegsToPass.push_back(x: std::make_pair(x&: LocRegHigh, y&: Hi));
3521 continue;
3522 }
3523 }
3524 break;
3525 case CCValAssign::BCvt:
3526 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: LocVT, Operand: Arg);
3527 break;
3528 case CCValAssign::SExtUpper:
3529 UseUpperBits = true;
3530 [[fallthrough]];
3531 case CCValAssign::SExt:
3532 Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: LocVT, Operand: Arg);
3533 break;
3534 case CCValAssign::ZExtUpper:
3535 UseUpperBits = true;
3536 [[fallthrough]];
3537 case CCValAssign::ZExt:
3538 Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: LocVT, Operand: Arg);
3539 break;
3540 case CCValAssign::AExtUpper:
3541 UseUpperBits = true;
3542 [[fallthrough]];
3543 case CCValAssign::AExt:
3544 Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: LocVT, Operand: Arg);
3545 break;
3546 }
3547
3548 if (UseUpperBits) {
3549 unsigned ValSizeInBits = Outs[OutIdx].ArgVT.getSizeInBits();
3550 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3551 Arg = DAG.getNode(
3552 Opcode: ISD::SHL, DL, VT: VA.getLocVT(), N1: Arg,
3553 N2: DAG.getConstant(Val: LocSizeInBits - ValSizeInBits, DL, VT: VA.getLocVT()));
3554 }
3555
3556 // Arguments that can be passed on register must be kept at
3557 // RegsToPass vector
3558 if (VA.isRegLoc()) {
3559 RegsToPass.push_back(x: std::make_pair(x: VA.getLocReg(), y&: Arg));
3560
3561 // If the parameter is passed through reg $D, which splits into
3562 // two physical registers, avoid creating call site info.
3563 if (Mips::AFGR64RegClass.contains(Reg: VA.getLocReg()))
3564 continue;
3565
3566 // Collect CSInfo about which register passes which parameter.
3567 const TargetOptions &Options = DAG.getTarget().Options;
3568 if (Options.EmitCallSiteInfo)
3569 CSInfo.ArgRegPairs.emplace_back(Args: VA.getLocReg(), Args&: i);
3570
3571 continue;
3572 }
3573
3574 // Register can't get to this point...
3575 assert(VA.isMemLoc());
3576
3577 // emit ISD::STORE whichs stores the
3578 // parameter value to a stack Location
3579 MemOpChains.push_back(Elt: passArgOnStack(StackPtr, Offset: VA.getLocMemOffset(),
3580 Chain, Arg, DL, IsTailCall, DAG));
3581 }
3582
3583 // Transform all store nodes into one single node because all store
3584 // nodes are independent of each other.
3585 if (!MemOpChains.empty())
3586 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: MemOpChains);
3587
3588 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3589 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3590 // node so that legalize doesn't hack it.
3591
3592 EVT Ty = Callee.getValueType();
3593 bool GlobalOrExternal = false, IsCallReloc = false;
3594
3595 // The long-calls feature is ignored in case of PIC.
3596 // While we do not support -mshared / -mno-shared properly,
3597 // ignore long-calls in case of -mabicalls too.
3598 if (!Subtarget.isABICalls() && !IsPIC) {
3599 // If the function should be called using "long call",
3600 // get its address into a register to prevent using
3601 // of the `jal` instruction for the direct call.
3602 if (auto *N = dyn_cast<ExternalSymbolSDNode>(Val&: Callee)) {
3603 if (Subtarget.useLongCalls())
3604 Callee = Subtarget.hasSym32()
3605 ? getAddrNonPIC(N, DL: SDLoc(N), Ty, DAG)
3606 : getAddrNonPICSym64(N, DL: SDLoc(N), Ty, DAG);
3607 } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Val&: Callee)) {
3608 bool UseLongCalls = Subtarget.useLongCalls();
3609 // If the function has long-call/far/near attribute
3610 // it overrides command line switch pased to the backend.
3611 if (auto *F = dyn_cast<Function>(Val: N->getGlobal())) {
3612 if (F->hasFnAttribute(Kind: "long-call"))
3613 UseLongCalls = true;
3614 else if (F->hasFnAttribute(Kind: "short-call"))
3615 UseLongCalls = false;
3616 }
3617 if (UseLongCalls)
3618 Callee = Subtarget.hasSym32()
3619 ? getAddrNonPIC(N, DL: SDLoc(N), Ty, DAG)
3620 : getAddrNonPICSym64(N, DL: SDLoc(N), Ty, DAG);
3621 }
3622 }
3623
3624 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee)) {
3625 if (Subtarget.isTargetCOFF() &&
3626 G->getGlobal()->hasDLLImportStorageClass()) {
3627 assert(Subtarget.isTargetWindows() &&
3628 "Windows is the only supported COFF target");
3629 auto PtrInfo = MachinePointerInfo();
3630 Callee = DAG.getLoad(VT: Ty, dl: DL, Chain,
3631 Ptr: getDllimportSymbol(N: G, DL: SDLoc(G), Ty, DAG), PtrInfo);
3632 } else if (IsPIC) {
3633 const GlobalValue *Val = G->getGlobal();
3634 InternalLinkage = Val->hasInternalLinkage();
3635
3636 if (InternalLinkage)
3637 Callee = getAddrLocal(N: G, DL, Ty, DAG, IsN32OrN64: ABI.IsN32() || ABI.IsN64());
3638 else if (Subtarget.useXGOT()) {
3639 Callee = getAddrGlobalLargeGOT(N: G, DL, Ty, DAG, HiFlag: MipsII::MO_CALL_HI16,
3640 LoFlag: MipsII::MO_CALL_LO16, Chain,
3641 PtrInfo: FuncInfo->callPtrInfo(MF, GV: Val));
3642 IsCallReloc = true;
3643 } else {
3644 Callee = getAddrGlobal(N: G, DL, Ty, DAG, Flag: MipsII::MO_GOT_CALL, Chain,
3645 PtrInfo: FuncInfo->callPtrInfo(MF, GV: Val));
3646 IsCallReloc = true;
3647 }
3648 } else
3649 Callee = DAG.getTargetGlobalAddress(GV: G->getGlobal(), DL,
3650 VT: getPointerTy(DL: DAG.getDataLayout()), offset: 0,
3651 TargetFlags: MipsII::MO_NO_FLAG);
3652 GlobalOrExternal = true;
3653 }
3654 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Val&: Callee)) {
3655 const char *Sym = S->getSymbol();
3656
3657 if (!IsPIC) // static
3658 Callee = DAG.getTargetExternalSymbol(
3659 Sym, VT: getPointerTy(DL: DAG.getDataLayout()), TargetFlags: MipsII::MO_NO_FLAG);
3660 else if (Subtarget.useXGOT()) {
3661 Callee = getAddrGlobalLargeGOT(N: S, DL, Ty, DAG, HiFlag: MipsII::MO_CALL_HI16,
3662 LoFlag: MipsII::MO_CALL_LO16, Chain,
3663 PtrInfo: FuncInfo->callPtrInfo(MF, ES: Sym));
3664 IsCallReloc = true;
3665 } else { // PIC
3666 Callee = getAddrGlobal(N: S, DL, Ty, DAG, Flag: MipsII::MO_GOT_CALL, Chain,
3667 PtrInfo: FuncInfo->callPtrInfo(MF, ES: Sym));
3668 IsCallReloc = true;
3669 }
3670
3671 GlobalOrExternal = true;
3672 }
3673
3674 SmallVector<SDValue, 8> Ops(1, Chain);
3675 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
3676
3677 getOpndList(Ops, RegsToPass, IsPICCall: IsPIC, GlobalOrExternal, InternalLinkage,
3678 IsCallReloc, CLI, Callee, Chain);
3679
3680 if (IsTailCall) {
3681 MF.getFrameInfo().setHasTailCall();
3682 SDValue Ret = DAG.getNode(Opcode: MipsISD::TailCall, DL, VT: MVT::Other, Ops);
3683 DAG.addCallSiteInfo(Node: Ret.getNode(), CallInfo: std::move(CSInfo));
3684 return Ret;
3685 }
3686
3687 Chain = DAG.getNode(Opcode: MipsISD::JmpLink, DL, VTList: NodeTys, Ops);
3688 SDValue InGlue = Chain.getValue(R: 1);
3689
3690 DAG.addCallSiteInfo(Node: Chain.getNode(), CallInfo: std::move(CSInfo));
3691
3692 // Create the CALLSEQ_END node in the case of where it is not a call to
3693 // memcpy.
3694 if (!(MemcpyInByVal)) {
3695 Chain = DAG.getCALLSEQ_END(Chain, Size1: StackSize, Size2: 0, Glue: InGlue, DL);
3696 InGlue = Chain.getValue(R: 1);
3697 }
3698
3699 // Handle result values, copying them out of physregs into vregs that we
3700 // return.
3701 return LowerCallResult(Chain, InGlue, CallConv, isVarArg: IsVarArg, Ins, dl: DL, DAG,
3702 InVals, CLI);
3703}
3704
3705/// LowerCallResult - Lower the result values of a call into the
3706/// appropriate copies out of appropriate physical registers.
3707SDValue MipsTargetLowering::LowerCallResult(
3708 SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool IsVarArg,
3709 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3710 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
3711 TargetLowering::CallLoweringInfo &CLI) const {
3712 // Assign locations to each value returned by this call.
3713 SmallVector<CCValAssign, 16> RVLocs;
3714 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
3715 *DAG.getContext());
3716
3717 const ExternalSymbolSDNode *ES =
3718 dyn_cast_or_null<const ExternalSymbolSDNode>(Val: CLI.Callee.getNode());
3719 CCInfo.AnalyzeCallResult(Ins, Fn: RetCC_Mips, RetTy: CLI.RetTy,
3720 Func: ES ? ES->getSymbol() : nullptr);
3721
3722 // Copy all of the result registers out of their specified physreg.
3723 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3724 CCValAssign &VA = RVLocs[i];
3725 assert(VA.isRegLoc() && "Can only return in registers!");
3726
3727 SDValue Val = DAG.getCopyFromReg(Chain, dl: DL, Reg: RVLocs[i].getLocReg(),
3728 VT: RVLocs[i].getLocVT(), Glue: InGlue);
3729 Chain = Val.getValue(R: 1);
3730 InGlue = Val.getValue(R: 2);
3731
3732 if (VA.isUpperBitsInLoc()) {
3733 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
3734 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3735 unsigned Shift =
3736 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3737 Val = DAG.getNode(
3738 Opcode: Shift, DL, VT: VA.getLocVT(), N1: Val,
3739 N2: DAG.getConstant(Val: LocSizeInBits - ValSizeInBits, DL, VT: VA.getLocVT()));
3740 }
3741
3742 switch (VA.getLocInfo()) {
3743 default:
3744 llvm_unreachable("Unknown loc info!");
3745 case CCValAssign::Full:
3746 break;
3747 case CCValAssign::BCvt:
3748 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: VA.getValVT(), Operand: Val);
3749 break;
3750 case CCValAssign::AExt:
3751 case CCValAssign::AExtUpper:
3752 Val = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: VA.getValVT(), Operand: Val);
3753 break;
3754 case CCValAssign::ZExt:
3755 case CCValAssign::ZExtUpper:
3756 Val = DAG.getNode(Opcode: ISD::AssertZext, DL, VT: VA.getLocVT(), N1: Val,
3757 N2: DAG.getValueType(VA.getValVT()));
3758 Val = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: VA.getValVT(), Operand: Val);
3759 break;
3760 case CCValAssign::SExt:
3761 case CCValAssign::SExtUpper:
3762 Val = DAG.getNode(Opcode: ISD::AssertSext, DL, VT: VA.getLocVT(), N1: Val,
3763 N2: DAG.getValueType(VA.getValVT()));
3764 Val = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: VA.getValVT(), Operand: Val);
3765 break;
3766 }
3767
3768 InVals.push_back(Elt: Val);
3769 }
3770
3771 return Chain;
3772}
3773
3774static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
3775 EVT ArgVT, const SDLoc &DL,
3776 SelectionDAG &DAG) {
3777 MVT LocVT = VA.getLocVT();
3778 EVT ValVT = VA.getValVT();
3779
3780 // Shift into the upper bits if necessary.
3781 switch (VA.getLocInfo()) {
3782 default:
3783 break;
3784 case CCValAssign::AExtUpper:
3785 case CCValAssign::SExtUpper:
3786 case CCValAssign::ZExtUpper: {
3787 unsigned ValSizeInBits = ArgVT.getSizeInBits();
3788 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3789 unsigned Opcode =
3790 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3791 Val = DAG.getNode(
3792 Opcode, DL, VT: VA.getLocVT(), N1: Val,
3793 N2: DAG.getConstant(Val: LocSizeInBits - ValSizeInBits, DL, VT: VA.getLocVT()));
3794 break;
3795 }
3796 }
3797
3798 // If this is an value smaller than the argument slot size (32-bit for O32,
3799 // 64-bit for N32/N64), it has been promoted in some way to the argument slot
3800 // size. Extract the value and insert any appropriate assertions regarding
3801 // sign/zero extension.
3802 switch (VA.getLocInfo()) {
3803 default:
3804 llvm_unreachable("Unknown loc info!");
3805 case CCValAssign::Full:
3806 break;
3807 case CCValAssign::AExtUpper:
3808 case CCValAssign::AExt:
3809 Val = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: ValVT, Operand: Val);
3810 break;
3811 case CCValAssign::SExtUpper:
3812 case CCValAssign::SExt:
3813 Val = DAG.getNode(Opcode: ISD::AssertSext, DL, VT: LocVT, N1: Val, N2: DAG.getValueType(ValVT));
3814 Val = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: ValVT, Operand: Val);
3815 break;
3816 case CCValAssign::ZExtUpper:
3817 case CCValAssign::ZExt:
3818 Val = DAG.getNode(Opcode: ISD::AssertZext, DL, VT: LocVT, N1: Val, N2: DAG.getValueType(ValVT));
3819 Val = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: ValVT, Operand: Val);
3820 break;
3821 case CCValAssign::BCvt:
3822 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: ValVT, Operand: Val);
3823 break;
3824 }
3825
3826 return Val;
3827}
3828
3829//===----------------------------------------------------------------------===//
3830// Formal Arguments Calling Convention Implementation
3831//===----------------------------------------------------------------------===//
3832/// LowerFormalArguments - transform physical registers into virtual registers
3833/// and generate load operations for arguments places on the stack.
3834SDValue MipsTargetLowering::LowerFormalArguments(
3835 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
3836 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3837 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3838 MachineFunction &MF = DAG.getMachineFunction();
3839 MachineFrameInfo &MFI = MF.getFrameInfo();
3840 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3841
3842 MipsFI->setVarArgsFrameIndex(0);
3843
3844 // Used with vargs to acumulate store chains.
3845 std::vector<SDValue> OutChains;
3846
3847 // Assign locations to all of the incoming arguments.
3848 SmallVector<CCValAssign, 16> ArgLocs;
3849 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3850 *DAG.getContext());
3851 CCInfo.AllocateStack(Size: ABI.GetCalleeAllocdArgSizeInBytes(CC: CallConv), Alignment: Align(1));
3852 const Function &Func = DAG.getMachineFunction().getFunction();
3853 Function::const_arg_iterator FuncArg = Func.arg_begin();
3854
3855 if (Func.hasFnAttribute(Kind: "interrupt") && !Func.arg_empty())
3856 report_fatal_error(
3857 reason: "Functions with the interrupt attribute cannot have arguments!");
3858
3859 CCInfo.AnalyzeFormalArguments(Ins, Fn: CC_Mips_FixedArg);
3860 MipsFI->setFormalArgInfo(Size: CCInfo.getStackSize(),
3861 HasByval: CCInfo.getInRegsParamsCount() > 0);
3862
3863 unsigned CurArgIdx = 0;
3864 CCInfo.rewindByValRegsInfo();
3865
3866 for (unsigned i = 0, e = ArgLocs.size(), InsIdx = 0; i != e; ++i, ++InsIdx) {
3867 CCValAssign &VA = ArgLocs[i];
3868 if (Ins[InsIdx].isOrigArg()) {
3869 std::advance(i&: FuncArg, n: Ins[InsIdx].getOrigArgIndex() - CurArgIdx);
3870 CurArgIdx = Ins[InsIdx].getOrigArgIndex();
3871 }
3872 EVT ValVT = VA.getValVT();
3873 ISD::ArgFlagsTy Flags = Ins[InsIdx].Flags;
3874 bool IsRegLoc = VA.isRegLoc();
3875
3876 if (Flags.isByVal()) {
3877 assert(Ins[InsIdx].isOrigArg() && "Byval arguments cannot be implicit");
3878 unsigned FirstByValReg, LastByValReg;
3879 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3880 CCInfo.getInRegsParamInfo(InRegsParamRecordIndex: ByValIdx, BeginReg&: FirstByValReg, EndReg&: LastByValReg);
3881
3882 assert(Flags.getByValSize() &&
3883 "ByVal args of size 0 should have been ignored by front-end.");
3884 assert(ByValIdx < CCInfo.getInRegsParamsCount());
3885 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, FuncArg: &*FuncArg,
3886 FirstReg: FirstByValReg, LastReg: LastByValReg, VA, State&: CCInfo);
3887 CCInfo.nextInRegsParam();
3888 continue;
3889 }
3890
3891 // Arguments stored on registers
3892 if (IsRegLoc) {
3893 MVT RegVT = VA.getLocVT();
3894 Register ArgReg = VA.getLocReg();
3895 const TargetRegisterClass *RC = getRegClassFor(VT: RegVT);
3896
3897 // Transform the arguments stored on
3898 // physical registers into virtual ones
3899 unsigned Reg = addLiveIn(MF&: DAG.getMachineFunction(), PReg: ArgReg, RC);
3900 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl: DL, Reg, VT: RegVT);
3901
3902 ArgValue =
3903 UnpackFromArgumentSlot(Val: ArgValue, VA, ArgVT: Ins[InsIdx].ArgVT, DL, DAG);
3904
3905 // Handle floating point arguments passed in integer registers and
3906 // long double arguments passed in floating point registers.
3907 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3908 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3909 (RegVT == MVT::f64 && ValVT == MVT::i64))
3910 ArgValue = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: ValVT, Operand: ArgValue);
3911 else if (ABI.IsO32() && RegVT == MVT::i32 &&
3912 ValVT == MVT::f64) {
3913 assert(VA.needsCustom() && "Expected custom argument for f64 split");
3914 CCValAssign &NextVA = ArgLocs[++i];
3915 unsigned Reg2 =
3916 addLiveIn(MF&: DAG.getMachineFunction(), PReg: NextVA.getLocReg(), RC);
3917 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl: DL, Reg: Reg2, VT: RegVT);
3918 if (!Subtarget.isLittle())
3919 std::swap(a&: ArgValue, b&: ArgValue2);
3920 ArgValue = DAG.getNode(Opcode: MipsISD::BuildPairF64, DL, VT: MVT::f64,
3921 N1: ArgValue, N2: ArgValue2);
3922 }
3923
3924 InVals.push_back(Elt: ArgValue);
3925 } else { // VA.isRegLoc()
3926 MVT LocVT = VA.getLocVT();
3927
3928 assert(!VA.needsCustom() && "unexpected custom memory argument");
3929
3930 // Only arguments pased on the stack should make it here.
3931 assert(VA.isMemLoc());
3932
3933 // The stack pointer offset is relative to the caller stack frame.
3934 int FI = MFI.CreateFixedObject(Size: LocVT.getSizeInBits() / 8,
3935 SPOffset: VA.getLocMemOffset(), IsImmutable: true);
3936
3937 // Create load nodes to retrieve arguments from the stack
3938 SDValue FIN = DAG.getFrameIndex(FI, VT: getPointerTy(DL: DAG.getDataLayout()));
3939 SDValue ArgValue = DAG.getLoad(
3940 VT: LocVT, dl: DL, Chain, Ptr: FIN,
3941 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI));
3942 OutChains.push_back(x: ArgValue.getValue(R: 1));
3943
3944 ArgValue =
3945 UnpackFromArgumentSlot(Val: ArgValue, VA, ArgVT: Ins[InsIdx].ArgVT, DL, DAG);
3946
3947 InVals.push_back(Elt: ArgValue);
3948 }
3949 }
3950
3951 for (unsigned i = 0, e = ArgLocs.size(), InsIdx = 0; i != e; ++i, ++InsIdx) {
3952
3953 if (ArgLocs[i].needsCustom()) {
3954 ++i;
3955 continue;
3956 }
3957
3958 // The mips ABIs for returning structs by value requires that we copy
3959 // the sret argument into $v0 for the return. Save the argument into
3960 // a virtual register so that we can access it from the return points.
3961 if (Ins[InsIdx].Flags.isSRet()) {
3962 unsigned Reg = MipsFI->getSRetReturnReg();
3963 if (!Reg) {
3964 Reg = MF.getRegInfo().createVirtualRegister(
3965 RegClass: getRegClassFor(VT: ABI.IsN64() ? MVT::i64 : MVT::i32));
3966 MipsFI->setSRetReturnReg(Reg);
3967 }
3968 SDValue Copy = DAG.getCopyToReg(Chain: DAG.getEntryNode(), dl: DL, Reg, N: InVals[i]);
3969 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, N1: Copy, N2: Chain);
3970 break;
3971 }
3972 }
3973
3974 if (IsVarArg)
3975 writeVarArgRegs(OutChains, Chain, DL, DAG, State&: CCInfo);
3976
3977 // All stores are grouped in one node to allow the matching between
3978 // the size of Ins and InVals. This only happens when on varg functions
3979 if (!OutChains.empty()) {
3980 OutChains.push_back(x: Chain);
3981 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: OutChains);
3982 }
3983
3984 return Chain;
3985}
3986
3987//===----------------------------------------------------------------------===//
3988// Return Value Calling Convention Implementation
3989//===----------------------------------------------------------------------===//
3990
3991bool
3992MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3993 MachineFunction &MF, bool IsVarArg,
3994 const SmallVectorImpl<ISD::OutputArg> &Outs,
3995 LLVMContext &Context, const Type *RetTy) const {
3996 SmallVector<CCValAssign, 16> RVLocs;
3997 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3998 return CCInfo.CheckCallReturn(ArgsFlags: Outs, Fn: RetCC_Mips, RetTy);
3999}
4000
4001bool MipsTargetLowering::shouldSignExtendTypeInLibCall(Type *Ty,
4002 bool IsSigned) const {
4003 if ((ABI.IsN32() || ABI.IsN64()) && Ty->isIntegerTy(Bitwidth: 32))
4004 return true;
4005
4006 return IsSigned;
4007}
4008
4009SDValue
4010MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
4011 const SDLoc &DL,
4012 SelectionDAG &DAG) const {
4013 MachineFunction &MF = DAG.getMachineFunction();
4014 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
4015
4016 MipsFI->setISR();
4017
4018 return DAG.getNode(Opcode: MipsISD::ERet, DL, VT: MVT::Other, Ops: RetOps);
4019}
4020
4021SDValue
4022MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
4023 bool IsVarArg,
4024 const SmallVectorImpl<ISD::OutputArg> &Outs,
4025 const SmallVectorImpl<SDValue> &OutVals,
4026 const SDLoc &DL, SelectionDAG &DAG) const {
4027 // CCValAssign - represent the assignment of
4028 // the return value to a location
4029 SmallVector<CCValAssign, 16> RVLocs;
4030 MachineFunction &MF = DAG.getMachineFunction();
4031
4032 // CCState - Info about the registers and stack slot.
4033 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
4034
4035 // Analyze return values.
4036 CCInfo.AnalyzeReturn(Outs, Fn: RetCC_Mips);
4037
4038 SDValue Glue;
4039 SmallVector<SDValue, 4> RetOps(1, Chain);
4040
4041 // Copy the result values into the output registers.
4042 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4043 SDValue Val = OutVals[i];
4044 CCValAssign &VA = RVLocs[i];
4045 assert(VA.isRegLoc() && "Can only return in registers!");
4046 bool UseUpperBits = false;
4047
4048 switch (VA.getLocInfo()) {
4049 default:
4050 llvm_unreachable("Unknown loc info!");
4051 case CCValAssign::Full:
4052 break;
4053 case CCValAssign::BCvt:
4054 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: VA.getLocVT(), Operand: Val);
4055 break;
4056 case CCValAssign::AExtUpper:
4057 UseUpperBits = true;
4058 [[fallthrough]];
4059 case CCValAssign::AExt:
4060 Val = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: VA.getLocVT(), Operand: Val);
4061 break;
4062 case CCValAssign::ZExtUpper:
4063 UseUpperBits = true;
4064 [[fallthrough]];
4065 case CCValAssign::ZExt:
4066 Val = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: VA.getLocVT(), Operand: Val);
4067 break;
4068 case CCValAssign::SExtUpper:
4069 UseUpperBits = true;
4070 [[fallthrough]];
4071 case CCValAssign::SExt:
4072 Val = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: VA.getLocVT(), Operand: Val);
4073 break;
4074 }
4075
4076 if (UseUpperBits) {
4077 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
4078 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
4079 Val = DAG.getNode(
4080 Opcode: ISD::SHL, DL, VT: VA.getLocVT(), N1: Val,
4081 N2: DAG.getConstant(Val: LocSizeInBits - ValSizeInBits, DL, VT: VA.getLocVT()));
4082 }
4083
4084 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: Val, Glue);
4085
4086 // Guarantee that all emitted copies are stuck together with flags.
4087 Glue = Chain.getValue(R: 1);
4088 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
4089 }
4090
4091 // The mips ABIs for returning structs by value requires that we copy
4092 // the sret argument into $v0 for the return. We saved the argument into
4093 // a virtual register in the entry block, so now we copy the value out
4094 // and into $v0.
4095 if (MF.getFunction().hasStructRetAttr()) {
4096 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
4097 unsigned Reg = MipsFI->getSRetReturnReg();
4098
4099 if (!Reg)
4100 llvm_unreachable("sret virtual register not created in the entry block");
4101 SDValue Val =
4102 DAG.getCopyFromReg(Chain, dl: DL, Reg, VT: getPointerTy(DL: DAG.getDataLayout()));
4103 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
4104
4105 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: V0, N: Val, Glue);
4106 Glue = Chain.getValue(R: 1);
4107 RetOps.push_back(Elt: DAG.getRegister(Reg: V0, VT: getPointerTy(DL: DAG.getDataLayout())));
4108 }
4109
4110 RetOps[0] = Chain; // Update chain.
4111
4112 // Add the glue if we have it.
4113 if (Glue.getNode())
4114 RetOps.push_back(Elt: Glue);
4115
4116 // ISRs must use "eret".
4117 if (DAG.getMachineFunction().getFunction().hasFnAttribute(Kind: "interrupt"))
4118 return LowerInterruptReturn(RetOps, DL, DAG);
4119
4120 // Standard return on Mips is a "jr $ra"
4121 return DAG.getNode(Opcode: MipsISD::Ret, DL, VT: MVT::Other, Ops: RetOps);
4122}
4123
4124//===----------------------------------------------------------------------===//
4125// Mips Inline Assembly Support
4126//===----------------------------------------------------------------------===//
4127
4128/// getConstraintType - Given a constraint letter, return the type of
4129/// constraint it is for this target.
4130MipsTargetLowering::ConstraintType
4131MipsTargetLowering::getConstraintType(StringRef Constraint) const {
4132 // Mips specific constraints
4133 // GCC config/mips/constraints.md
4134 //
4135 // 'd' : An address register. Equivalent to r
4136 // unless generating MIPS16 code.
4137 // 'y' : Equivalent to r; retained for
4138 // backwards compatibility.
4139 // 'c' : A register suitable for use in an indirect
4140 // jump. This will always be $25 for -mabicalls.
4141 // 'l' : The lo register. 1 word storage.
4142 // 'x' : The hilo register pair. Double word storage.
4143 if (Constraint.size() == 1) {
4144 switch (Constraint[0]) {
4145 default : break;
4146 case 'd':
4147 case 'y':
4148 case 'f':
4149 case 'c':
4150 case 'l':
4151 case 'x':
4152 return C_RegisterClass;
4153 case 'R':
4154 return C_Memory;
4155 }
4156 }
4157
4158 if (Constraint == "ZC")
4159 return C_Memory;
4160
4161 return TargetLowering::getConstraintType(Constraint);
4162}
4163
4164/// Examine constraint type and operand type and determine a weight value.
4165/// This object must already have been set up with the operand type
4166/// and the current alternative constraint selected.
4167TargetLowering::ConstraintWeight
4168MipsTargetLowering::getSingleConstraintMatchWeight(
4169 AsmOperandInfo &info, const char *constraint) const {
4170 ConstraintWeight weight = CW_Invalid;
4171 Value *CallOperandVal = info.CallOperandVal;
4172 // If we don't have a value, we can't do a match,
4173 // but allow it at the lowest weight.
4174 if (!CallOperandVal)
4175 return CW_Default;
4176 Type *type = CallOperandVal->getType();
4177 // Look at the constraint type.
4178 switch (*constraint) {
4179 default:
4180 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4181 break;
4182 case 'd':
4183 case 'y':
4184 if (type->isIntegerTy())
4185 weight = CW_Register;
4186 break;
4187 case 'f': // FPU or MSA register
4188 if (Subtarget.hasMSA() && type->isVectorTy() &&
4189 type->getPrimitiveSizeInBits().getFixedValue() == 128)
4190 weight = CW_Register;
4191 else if (type->isFloatTy())
4192 weight = CW_Register;
4193 break;
4194 case 'c': // $25 for indirect jumps
4195 case 'l': // lo register
4196 case 'x': // hilo register pair
4197 if (type->isIntegerTy())
4198 weight = CW_SpecificReg;
4199 break;
4200 case 'I': // signed 16 bit immediate
4201 case 'J': // integer zero
4202 case 'K': // unsigned 16 bit immediate
4203 case 'L': // signed 32 bit immediate where lower 16 bits are 0
4204 case 'N': // immediate in the range of -65535 to -1 (inclusive)
4205 case 'O': // signed 15 bit immediate (+- 16383)
4206 case 'P': // immediate in the range of 65535 to 1 (inclusive)
4207 if (isa<ConstantInt>(Val: CallOperandVal))
4208 weight = CW_Constant;
4209 break;
4210 case 'R':
4211 weight = CW_Memory;
4212 break;
4213 }
4214 return weight;
4215}
4216
4217/// This is a helper function to parse a physical register string and split it
4218/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
4219/// that is returned indicates whether parsing was successful. The second flag
4220/// is true if the numeric part exists.
4221static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
4222 unsigned long long &Reg) {
4223 if (C.front() != '{' || C.back() != '}')
4224 return std::make_pair(x: false, y: false);
4225
4226 // Search for the first numeric character.
4227 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
4228 I = std::find_if(first: B, last: E, pred: isdigit);
4229
4230 Prefix = StringRef(B, I - B);
4231
4232 // The second flag is set to false if no numeric characters were found.
4233 if (I == E)
4234 return std::make_pair(x: true, y: false);
4235
4236 // Parse the numeric characters.
4237 return std::make_pair(x: !getAsUnsignedInteger(Str: StringRef(I, E - I), Radix: 10, Result&: Reg),
4238 y: true);
4239}
4240
4241EVT MipsTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
4242 ISD::NodeType) const {
4243 bool Cond = !Subtarget.isABI_O32() && VT.getSizeInBits() == 32;
4244 EVT MinVT = getRegisterType(VT: Cond ? MVT::i64 : MVT::i32);
4245 return VT.bitsLT(VT: MinVT) ? MinVT : VT;
4246}
4247
4248std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
4249parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
4250 const TargetRegisterInfo *TRI =
4251 Subtarget.getRegisterInfo();
4252 const TargetRegisterClass *RC;
4253 StringRef Prefix;
4254 unsigned long long Reg;
4255
4256 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
4257
4258 if (!R.first)
4259 return std::make_pair(x: 0U, y: nullptr);
4260
4261 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
4262 // No numeric characters follow "hi" or "lo".
4263 if (R.second)
4264 return std::make_pair(x: 0U, y: nullptr);
4265
4266 RC = TRI->getRegClass(i: Prefix == "hi" ?
4267 Mips::HI32RegClassID : Mips::LO32RegClassID);
4268 return std::make_pair(x: *(RC->begin()), y&: RC);
4269 } else if (Prefix.starts_with(Prefix: "$msa")) {
4270 // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
4271
4272 // No numeric characters follow the name.
4273 if (R.second)
4274 return std::make_pair(x: 0U, y: nullptr);
4275
4276 Reg = StringSwitch<unsigned long long>(Prefix)
4277 .Case(S: "$msair", Value: Mips::MSAIR)
4278 .Case(S: "$msacsr", Value: Mips::MSACSR)
4279 .Case(S: "$msaaccess", Value: Mips::MSAAccess)
4280 .Case(S: "$msasave", Value: Mips::MSASave)
4281 .Case(S: "$msamodify", Value: Mips::MSAModify)
4282 .Case(S: "$msarequest", Value: Mips::MSARequest)
4283 .Case(S: "$msamap", Value: Mips::MSAMap)
4284 .Case(S: "$msaunmap", Value: Mips::MSAUnmap)
4285 .Default(Value: 0);
4286
4287 if (!Reg)
4288 return std::make_pair(x: 0U, y: nullptr);
4289
4290 RC = TRI->getRegClass(i: Mips::MSACtrlRegClassID);
4291 return std::make_pair(x&: Reg, y&: RC);
4292 }
4293
4294 if (!R.second)
4295 return std::make_pair(x: 0U, y: nullptr);
4296
4297 if (Prefix == "$f") { // Parse $f0-$f31.
4298 // If the size of FP registers is 64-bit or Reg is an even number, select
4299 // the 64-bit register class. Otherwise, select the 32-bit register class.
4300 if (VT == MVT::Other)
4301 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
4302
4303 RC = getRegClassFor(VT);
4304
4305 if (RC == &Mips::AFGR64RegClass) {
4306 assert(Reg % 2 == 0);
4307 Reg >>= 1;
4308 }
4309 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
4310 RC = TRI->getRegClass(i: Mips::FCCRegClassID);
4311 else if (Prefix == "$w") { // Parse $w0-$w31.
4312 RC = getRegClassFor(VT: (VT == MVT::Other) ? MVT::v16i8 : VT);
4313 } else { // Parse $0-$31.
4314 assert(Prefix == "$");
4315 RC = getRegClassFor(VT: (VT == MVT::Other) ? MVT::i32 : VT);
4316 }
4317
4318 assert(Reg < RC->getNumRegs());
4319 return std::make_pair(x: *(RC->begin() + Reg), y&: RC);
4320}
4321
4322/// Given a register class constraint, like 'r', if this corresponds directly
4323/// to an LLVM register class, return a register of 0 and the register class
4324/// pointer.
4325std::pair<unsigned, const TargetRegisterClass *>
4326MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
4327 StringRef Constraint,
4328 MVT VT) const {
4329 if (Constraint.size() == 1) {
4330 switch (Constraint[0]) {
4331 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
4332 case 'y': // Same as 'r'. Exists for compatibility.
4333 case 'r':
4334 if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
4335 VT == MVT::i1) ||
4336 (VT == MVT::f32 && Subtarget.useSoftFloat())) {
4337 if (Subtarget.inMips16Mode())
4338 return std::make_pair(x: 0U, y: &Mips::CPU16RegsRegClass);
4339 return std::make_pair(x: 0U, y: &Mips::GPR32RegClass);
4340 }
4341 if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
4342 !Subtarget.isGP64bit())
4343 return std::make_pair(x: 0U, y: &Mips::GPR32RegClass);
4344 if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
4345 Subtarget.isGP64bit())
4346 return std::make_pair(x: 0U, y: &Mips::GPR64RegClass);
4347 // This will generate an error message
4348 return std::make_pair(x: 0U, y: nullptr);
4349 case 'f': // FPU or MSA register
4350 if (VT == MVT::v16i8)
4351 return std::make_pair(x: 0U, y: &Mips::MSA128BRegClass);
4352 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
4353 return std::make_pair(x: 0U, y: &Mips::MSA128HRegClass);
4354 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
4355 return std::make_pair(x: 0U, y: &Mips::MSA128WRegClass);
4356 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
4357 return std::make_pair(x: 0U, y: &Mips::MSA128DRegClass);
4358 else if (VT == MVT::f32)
4359 return std::make_pair(x: 0U, y: &Mips::FGR32RegClass);
4360 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
4361 if (Subtarget.isFP64bit())
4362 return std::make_pair(x: 0U, y: &Mips::FGR64RegClass);
4363 return std::make_pair(x: 0U, y: &Mips::AFGR64RegClass);
4364 }
4365 break;
4366 case 'c': // register suitable for indirect jump
4367 if (VT == MVT::i32)
4368 return std::make_pair(x: (unsigned)Mips::T9, y: &Mips::GPR32RegClass);
4369 if (VT == MVT::i64)
4370 return std::make_pair(x: (unsigned)Mips::T9_64, y: &Mips::GPR64RegClass);
4371 // This will generate an error message
4372 return std::make_pair(x: 0U, y: nullptr);
4373 case 'l': // use the `lo` register to store values
4374 // that are no bigger than a word
4375 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
4376 return std::make_pair(x: (unsigned)Mips::LO0, y: &Mips::LO32RegClass);
4377 return std::make_pair(x: (unsigned)Mips::LO0_64, y: &Mips::LO64RegClass);
4378 case 'x': // use the concatenated `hi` and `lo` registers
4379 // to store doubleword values
4380 // Fixme: Not triggering the use of both hi and low
4381 // This will generate an error message
4382 return std::make_pair(x: 0U, y: nullptr);
4383 }
4384 }
4385
4386 if (!Constraint.empty()) {
4387 std::pair<unsigned, const TargetRegisterClass *> R;
4388 R = parseRegForInlineAsmConstraint(C: Constraint, VT);
4389
4390 if (R.second)
4391 return R;
4392 }
4393
4394 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4395}
4396
4397/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4398/// vector. If it is invalid, don't add anything to Ops.
4399void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
4400 StringRef Constraint,
4401 std::vector<SDValue> &Ops,
4402 SelectionDAG &DAG) const {
4403 SDLoc DL(Op);
4404 SDValue Result;
4405
4406 // Only support length 1 constraints for now.
4407 if (Constraint.size() > 1)
4408 return;
4409
4410 char ConstraintLetter = Constraint[0];
4411 switch (ConstraintLetter) {
4412 default: break; // This will fall through to the generic implementation
4413 case 'I': // Signed 16 bit constant
4414 // If this fails, the parent routine will give an error
4415 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: Op)) {
4416 EVT Type = Op.getValueType();
4417 int64_t Val = C->getSExtValue();
4418 if (isInt<16>(x: Val)) {
4419 Result = DAG.getSignedTargetConstant(Val, DL, VT: Type);
4420 break;
4421 }
4422 }
4423 return;
4424 case 'J': // integer zero
4425 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: Op)) {
4426 EVT Type = Op.getValueType();
4427 int64_t Val = C->getZExtValue();
4428 if (Val == 0) {
4429 Result = DAG.getTargetConstant(Val: 0, DL, VT: Type);
4430 break;
4431 }
4432 }
4433 return;
4434 case 'K': // unsigned 16 bit immediate
4435 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: Op)) {
4436 EVT Type = Op.getValueType();
4437 uint64_t Val = (uint64_t)C->getZExtValue();
4438 if (isUInt<16>(x: Val)) {
4439 Result = DAG.getTargetConstant(Val, DL, VT: Type);
4440 break;
4441 }
4442 }
4443 return;
4444 case 'L': // signed 32 bit immediate where lower 16 bits are 0
4445 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: Op)) {
4446 EVT Type = Op.getValueType();
4447 int64_t Val = C->getSExtValue();
4448 if ((isInt<32>(x: Val)) && ((Val & 0xffff) == 0)){
4449 Result = DAG.getSignedTargetConstant(Val, DL, VT: Type);
4450 break;
4451 }
4452 }
4453 return;
4454 case 'N': // immediate in the range of -65535 to -1 (inclusive)
4455 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: Op)) {
4456 EVT Type = Op.getValueType();
4457 int64_t Val = C->getSExtValue();
4458 if ((Val >= -65535) && (Val <= -1)) {
4459 Result = DAG.getSignedTargetConstant(Val, DL, VT: Type);
4460 break;
4461 }
4462 }
4463 return;
4464 case 'O': // signed 15 bit immediate
4465 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: Op)) {
4466 EVT Type = Op.getValueType();
4467 int64_t Val = C->getSExtValue();
4468 if ((isInt<15>(x: Val))) {
4469 Result = DAG.getSignedTargetConstant(Val, DL, VT: Type);
4470 break;
4471 }
4472 }
4473 return;
4474 case 'P': // immediate in the range of 1 to 65535 (inclusive)
4475 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: Op)) {
4476 EVT Type = Op.getValueType();
4477 int64_t Val = C->getSExtValue();
4478 if ((Val <= 65535) && (Val >= 1)) {
4479 Result = DAG.getTargetConstant(Val, DL, VT: Type);
4480 break;
4481 }
4482 }
4483 return;
4484 }
4485
4486 if (Result.getNode()) {
4487 Ops.push_back(x: Result);
4488 return;
4489 }
4490
4491 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4492}
4493
4494bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
4495 const AddrMode &AM, Type *Ty,
4496 unsigned AS,
4497 Instruction *I) const {
4498 // No global is ever allowed as a base.
4499 if (AM.BaseGV)
4500 return false;
4501
4502 switch (AM.Scale) {
4503 case 0: // "r+i" or just "i", depending on HasBaseReg.
4504 break;
4505 case 1:
4506 if (!AM.HasBaseReg) // allow "r+i".
4507 break;
4508 return false; // disallow "r+r" or "r+r+i".
4509 default:
4510 return false;
4511 }
4512
4513 return true;
4514}
4515
4516bool
4517MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4518 // The Mips target isn't yet aware of offsets.
4519 return false;
4520}
4521
4522EVT MipsTargetLowering::getOptimalMemOpType(
4523 const MemOp &Op, const AttributeList &FuncAttributes) const {
4524 if (Subtarget.hasMips64())
4525 return MVT::i64;
4526
4527 return MVT::i32;
4528}
4529
4530bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
4531 bool ForCodeSize) const {
4532 if (VT != MVT::f32 && VT != MVT::f64)
4533 return false;
4534 if (Imm.isNegZero())
4535 return false;
4536 return Imm.isZero();
4537}
4538
4539bool MipsTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
4540 return isInt<16>(x: Imm);
4541}
4542
4543bool MipsTargetLowering::isLegalAddImmediate(int64_t Imm) const {
4544 return isInt<16>(x: Imm);
4545}
4546
4547unsigned MipsTargetLowering::getJumpTableEncoding() const {
4548 if (!isPositionIndependent())
4549 return MachineJumpTableInfo::EK_BlockAddress;
4550 if (ABI.IsN64())
4551 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
4552 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
4553}
4554
4555SDValue MipsTargetLowering::getPICJumpTableRelocBase(SDValue Table,
4556 SelectionDAG &DAG) const {
4557 if (!isPositionIndependent())
4558 return Table;
4559 return DAG.getGLOBAL_OFFSET_TABLE(VT: getPointerTy(DL: DAG.getDataLayout()));
4560}
4561
4562bool MipsTargetLowering::useSoftFloat() const {
4563 return Subtarget.useSoftFloat();
4564}
4565
4566void MipsTargetLowering::copyByValRegs(
4567 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains,
4568 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
4569 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
4570 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA,
4571 MipsCCState &State) const {
4572 MachineFunction &MF = DAG.getMachineFunction();
4573 MachineFrameInfo &MFI = MF.getFrameInfo();
4574 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
4575 unsigned NumRegs = LastReg - FirstReg;
4576 unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
4577 unsigned FrameObjSize = std::max(a: Flags.getByValSize(), b: RegAreaSize);
4578 int FrameObjOffset;
4579 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
4580
4581 if (RegAreaSize)
4582 FrameObjOffset =
4583 (int)ABI.GetCalleeAllocdArgSizeInBytes(CC: State.getCallingConv()) -
4584 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
4585 else
4586 FrameObjOffset = VA.getLocMemOffset();
4587
4588 // Create frame object.
4589 EVT PtrTy = getPointerTy(DL: DAG.getDataLayout());
4590 // Make the fixed object stored to mutable so that the load instructions
4591 // referencing it have their memory dependencies added.
4592 // Set the frame object as isAliased which clears the underlying objects
4593 // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all
4594 // stores as dependencies for loads referencing this fixed object.
4595 int FI = MFI.CreateFixedObject(Size: FrameObjSize, SPOffset: FrameObjOffset, IsImmutable: false, isAliased: true);
4596 SDValue FIN = DAG.getFrameIndex(FI, VT: PtrTy);
4597 InVals.push_back(Elt: FIN);
4598
4599 if (!NumRegs)
4600 return;
4601
4602 // Copy arg registers.
4603 MVT RegTy = MVT::getIntegerVT(BitWidth: GPRSizeInBytes * 8);
4604 const TargetRegisterClass *RC = getRegClassFor(VT: RegTy);
4605
4606 for (unsigned I = 0; I < NumRegs; ++I) {
4607 unsigned ArgReg = ByValArgRegs[FirstReg + I];
4608 unsigned VReg = addLiveIn(MF, PReg: ArgReg, RC);
4609 unsigned Offset = I * GPRSizeInBytes;
4610 SDValue StorePtr = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrTy, N1: FIN,
4611 N2: DAG.getConstant(Val: Offset, DL, VT: PtrTy));
4612 SDValue Store = DAG.getStore(Chain, dl: DL, Val: DAG.getRegister(Reg: VReg, VT: RegTy),
4613 Ptr: StorePtr, PtrInfo: MachinePointerInfo(FuncArg, Offset));
4614 OutChains.push_back(x: Store);
4615 }
4616}
4617
4618// Copy byVal arg to registers and stack.
4619void MipsTargetLowering::passByValArg(
4620 SDValue Chain, const SDLoc &DL,
4621 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
4622 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
4623 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
4624 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
4625 const CCValAssign &VA) const {
4626 unsigned ByValSizeInBytes = Flags.getByValSize();
4627 unsigned OffsetInBytes = 0; // From beginning of struct
4628 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4629 Align Alignment =
4630 std::min(a: Flags.getNonZeroByValAlign(), b: Align(RegSizeInBytes));
4631 EVT PtrTy = getPointerTy(DL: DAG.getDataLayout()),
4632 RegTy = MVT::getIntegerVT(BitWidth: RegSizeInBytes * 8);
4633 unsigned NumRegs = LastReg - FirstReg;
4634
4635 if (NumRegs) {
4636 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs();
4637 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
4638 unsigned I = 0;
4639
4640 // Copy words to registers.
4641 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
4642 SDValue LoadPtr = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrTy, N1: Arg,
4643 N2: DAG.getConstant(Val: OffsetInBytes, DL, VT: PtrTy));
4644 SDValue LoadVal = DAG.getLoad(VT: RegTy, dl: DL, Chain, Ptr: LoadPtr,
4645 PtrInfo: MachinePointerInfo(), Alignment);
4646 MemOpChains.push_back(Elt: LoadVal.getValue(R: 1));
4647 unsigned ArgReg = ArgRegs[FirstReg + I];
4648 RegsToPass.push_back(x: std::make_pair(x&: ArgReg, y&: LoadVal));
4649 }
4650
4651 // Return if the struct has been fully copied.
4652 if (ByValSizeInBytes == OffsetInBytes)
4653 return;
4654
4655 // Copy the remainder of the byval argument with sub-word loads and shifts.
4656 if (LeftoverBytes) {
4657 SDValue Val;
4658
4659 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
4660 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
4661 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
4662
4663 if (RemainingSizeInBytes < LoadSizeInBytes)
4664 continue;
4665
4666 // Load subword.
4667 SDValue LoadPtr = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrTy, N1: Arg,
4668 N2: DAG.getConstant(Val: OffsetInBytes, DL,
4669 VT: PtrTy));
4670 SDValue LoadVal = DAG.getExtLoad(
4671 ExtType: ISD::ZEXTLOAD, dl: DL, VT: RegTy, Chain, Ptr: LoadPtr, PtrInfo: MachinePointerInfo(),
4672 MemVT: MVT::getIntegerVT(BitWidth: LoadSizeInBytes * 8), Alignment);
4673 MemOpChains.push_back(Elt: LoadVal.getValue(R: 1));
4674
4675 // Shift the loaded value.
4676 unsigned Shamt;
4677
4678 if (isLittle)
4679 Shamt = TotalBytesLoaded * 8;
4680 else
4681 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
4682
4683 SDValue Shift = DAG.getNode(Opcode: ISD::SHL, DL, VT: RegTy, N1: LoadVal,
4684 N2: DAG.getConstant(Val: Shamt, DL, VT: MVT::i32));
4685
4686 if (Val.getNode())
4687 Val = DAG.getNode(Opcode: ISD::OR, DL, VT: RegTy, N1: Val, N2: Shift);
4688 else
4689 Val = Shift;
4690
4691 OffsetInBytes += LoadSizeInBytes;
4692 TotalBytesLoaded += LoadSizeInBytes;
4693 Alignment = std::min(a: Alignment, b: Align(LoadSizeInBytes));
4694 }
4695
4696 unsigned ArgReg = ArgRegs[FirstReg + I];
4697 RegsToPass.push_back(x: std::make_pair(x&: ArgReg, y&: Val));
4698 return;
4699 }
4700 }
4701
4702 // Copy remainder of byval arg to it with memcpy.
4703 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
4704 SDValue Src = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrTy, N1: Arg,
4705 N2: DAG.getConstant(Val: OffsetInBytes, DL, VT: PtrTy));
4706 SDValue Dst = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrTy, N1: StackPtr,
4707 N2: DAG.getIntPtrConstant(Val: VA.getLocMemOffset(), DL));
4708 Chain = DAG.getMemcpy(
4709 Chain, dl: DL, Dst, Src, Size: DAG.getConstant(Val: MemCpySize, DL, VT: PtrTy),
4710 Alignment: Align(Alignment), /*isVolatile=*/isVol: false, /*AlwaysInline=*/false,
4711 /*CI=*/nullptr, OverrideTailCall: std::nullopt, DstPtrInfo: MachinePointerInfo(), SrcPtrInfo: MachinePointerInfo());
4712 MemOpChains.push_back(Elt: Chain);
4713}
4714
4715void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4716 SDValue Chain, const SDLoc &DL,
4717 SelectionDAG &DAG,
4718 CCState &State) const {
4719 ArrayRef<MCPhysReg> ArgRegs = ABI.getVarArgRegs(isGP64bit: Subtarget.isGP64bit());
4720 unsigned Idx = State.getFirstUnallocated(Regs: ArgRegs);
4721 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4722 MVT RegTy = MVT::getIntegerVT(BitWidth: RegSizeInBytes * 8);
4723 const TargetRegisterClass *RC = getRegClassFor(VT: RegTy);
4724 MachineFunction &MF = DAG.getMachineFunction();
4725 MachineFrameInfo &MFI = MF.getFrameInfo();
4726 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
4727
4728 // Offset of the first variable argument from stack pointer.
4729 int VaArgOffset;
4730
4731 if (ArgRegs.size() == Idx)
4732 VaArgOffset = alignTo(Value: State.getStackSize(), Align: RegSizeInBytes);
4733 else {
4734 VaArgOffset =
4735 (int)ABI.GetCalleeAllocdArgSizeInBytes(CC: State.getCallingConv()) -
4736 (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
4737 }
4738
4739 // Record the frame index of the first variable argument
4740 // which is a value necessary to VASTART.
4741 int FI = MFI.CreateFixedObject(Size: RegSizeInBytes, SPOffset: VaArgOffset, IsImmutable: true);
4742 MipsFI->setVarArgsFrameIndex(FI);
4743
4744 // Copy the integer registers that have not been used for argument passing
4745 // to the argument register save area. For O32, the save area is allocated
4746 // in the caller's stack frame, while for N32/64, it is allocated in the
4747 // callee's stack frame.
4748 for (unsigned I = Idx; I < ArgRegs.size();
4749 ++I, VaArgOffset += RegSizeInBytes) {
4750 unsigned Reg = addLiveIn(MF, PReg: ArgRegs[I], RC);
4751 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl: DL, Reg, VT: RegTy);
4752 FI = MFI.CreateFixedObject(Size: RegSizeInBytes, SPOffset: VaArgOffset, IsImmutable: true);
4753 SDValue PtrOff = DAG.getFrameIndex(FI, VT: getPointerTy(DL: DAG.getDataLayout()));
4754 SDValue Store =
4755 DAG.getStore(Chain, dl: DL, Val: ArgValue, Ptr: PtrOff, PtrInfo: MachinePointerInfo());
4756 cast<StoreSDNode>(Val: Store.getNode())->getMemOperand()->setValue(
4757 (Value *)nullptr);
4758 OutChains.push_back(x: Store);
4759 }
4760}
4761
4762void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
4763 Align Alignment) const {
4764 const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
4765
4766 assert(Size && "Byval argument's size shouldn't be 0.");
4767
4768 Alignment = std::min(a: Alignment, b: TFL->getStackAlign());
4769
4770 unsigned FirstReg = 0;
4771 unsigned NumRegs = 0;
4772
4773 if (State->getCallingConv() != CallingConv::Fast) {
4774 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4775 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
4776 // FIXME: The O32 case actually describes no shadow registers.
4777 const MCPhysReg *ShadowRegs =
4778 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs;
4779
4780 // We used to check the size as well but we can't do that anymore since
4781 // CCState::HandleByVal() rounds up the size after calling this function.
4782 assert(
4783 Alignment >= Align(RegSizeInBytes) &&
4784 "Byval argument's alignment should be a multiple of RegSizeInBytes.");
4785
4786 FirstReg = State->getFirstUnallocated(Regs: IntArgRegs);
4787
4788 // If Alignment > RegSizeInBytes, the first arg register must be even.
4789 // FIXME: This condition happens to do the right thing but it's not the
4790 // right way to test it. We want to check that the stack frame offset
4791 // of the register is aligned.
4792 if ((Alignment > RegSizeInBytes) && (FirstReg % 2)) {
4793 State->AllocateReg(Reg: IntArgRegs[FirstReg], ShadowReg: ShadowRegs[FirstReg]);
4794 ++FirstReg;
4795 }
4796
4797 // Mark the registers allocated.
4798 Size = alignTo(Value: Size, Align: RegSizeInBytes);
4799 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
4800 Size -= RegSizeInBytes, ++I, ++NumRegs)
4801 State->AllocateReg(Reg: IntArgRegs[I], ShadowReg: ShadowRegs[I]);
4802 }
4803
4804 State->addInRegsParamInfo(RegBegin: FirstReg, RegEnd: FirstReg + NumRegs);
4805}
4806
4807MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
4808 MachineBasicBlock *BB,
4809 bool isFPCmp,
4810 unsigned Opc) const {
4811 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
4812 "Subtarget already supports SELECT nodes with the use of"
4813 "conditional-move instructions.");
4814
4815 const TargetInstrInfo *TII =
4816 Subtarget.getInstrInfo();
4817 DebugLoc DL = MI.getDebugLoc();
4818
4819 // To "insert" a SELECT instruction, we actually have to insert the
4820 // diamond control-flow pattern. The incoming instruction knows the
4821 // destination vreg to set, the condition code register to branch on, the
4822 // true/false values to select between, and a branch opcode to use.
4823 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4824 MachineFunction::iterator It = ++BB->getIterator();
4825
4826 // thisMBB:
4827 // ...
4828 // TrueVal = ...
4829 // setcc r1, r2, r3
4830 // bNE r1, r0, copy1MBB
4831 // fallthrough --> copy0MBB
4832 MachineBasicBlock *thisMBB = BB;
4833 MachineFunction *F = BB->getParent();
4834 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
4835 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
4836 F->insert(MBBI: It, MBB: copy0MBB);
4837 F->insert(MBBI: It, MBB: sinkMBB);
4838
4839 // Transfer the remainder of BB and its successor edges to sinkMBB.
4840 sinkMBB->splice(Where: sinkMBB->begin(), Other: BB,
4841 From: std::next(x: MachineBasicBlock::iterator(MI)), To: BB->end());
4842 sinkMBB->transferSuccessorsAndUpdatePHIs(FromMBB: BB);
4843
4844 // Next, add the true and fallthrough blocks as its successors.
4845 BB->addSuccessor(Succ: copy0MBB);
4846 BB->addSuccessor(Succ: sinkMBB);
4847
4848 if (isFPCmp) {
4849 // bc1[tf] cc, sinkMBB
4850 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Opc))
4851 .addReg(RegNo: MI.getOperand(i: 1).getReg())
4852 .addMBB(MBB: sinkMBB);
4853 } else {
4854 // bne rs, $0, sinkMBB
4855 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Opc))
4856 .addReg(RegNo: MI.getOperand(i: 1).getReg())
4857 .addReg(RegNo: Mips::ZERO)
4858 .addMBB(MBB: sinkMBB);
4859 }
4860
4861 // copy0MBB:
4862 // %FalseValue = ...
4863 // # fallthrough to sinkMBB
4864 BB = copy0MBB;
4865
4866 // Update machine-CFG edges
4867 BB->addSuccessor(Succ: sinkMBB);
4868
4869 // sinkMBB:
4870 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4871 // ...
4872 BB = sinkMBB;
4873
4874 BuildMI(BB&: *BB, I: BB->begin(), MIMD: DL, MCID: TII->get(Opcode: Mips::PHI), DestReg: MI.getOperand(i: 0).getReg())
4875 .addReg(RegNo: MI.getOperand(i: 2).getReg())
4876 .addMBB(MBB: thisMBB)
4877 .addReg(RegNo: MI.getOperand(i: 3).getReg())
4878 .addMBB(MBB: copy0MBB);
4879
4880 MI.eraseFromParent(); // The pseudo instruction is gone now.
4881
4882 return BB;
4883}
4884
4885MachineBasicBlock *
4886MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
4887 MachineBasicBlock *BB) const {
4888 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
4889 "Subtarget already supports SELECT nodes with the use of"
4890 "conditional-move instructions.");
4891
4892 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
4893 DebugLoc DL = MI.getDebugLoc();
4894
4895 // D_SELECT substitutes two SELECT nodes that goes one after another and
4896 // have the same condition operand. On machines which don't have
4897 // conditional-move instruction, it reduces unnecessary branch instructions
4898 // which are result of using two diamond patterns that are result of two
4899 // SELECT pseudo instructions.
4900 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4901 MachineFunction::iterator It = ++BB->getIterator();
4902
4903 // thisMBB:
4904 // ...
4905 // TrueVal = ...
4906 // setcc r1, r2, r3
4907 // bNE r1, r0, copy1MBB
4908 // fallthrough --> copy0MBB
4909 MachineBasicBlock *thisMBB = BB;
4910 MachineFunction *F = BB->getParent();
4911 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
4912 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
4913 F->insert(MBBI: It, MBB: copy0MBB);
4914 F->insert(MBBI: It, MBB: sinkMBB);
4915
4916 // Transfer the remainder of BB and its successor edges to sinkMBB.
4917 sinkMBB->splice(Where: sinkMBB->begin(), Other: BB,
4918 From: std::next(x: MachineBasicBlock::iterator(MI)), To: BB->end());
4919 sinkMBB->transferSuccessorsAndUpdatePHIs(FromMBB: BB);
4920
4921 // Next, add the true and fallthrough blocks as its successors.
4922 BB->addSuccessor(Succ: copy0MBB);
4923 BB->addSuccessor(Succ: sinkMBB);
4924
4925 // bne rs, $0, sinkMBB
4926 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Mips::BNE))
4927 .addReg(RegNo: MI.getOperand(i: 2).getReg())
4928 .addReg(RegNo: Mips::ZERO)
4929 .addMBB(MBB: sinkMBB);
4930
4931 // copy0MBB:
4932 // %FalseValue = ...
4933 // # fallthrough to sinkMBB
4934 BB = copy0MBB;
4935
4936 // Update machine-CFG edges
4937 BB->addSuccessor(Succ: sinkMBB);
4938
4939 // sinkMBB:
4940 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4941 // ...
4942 BB = sinkMBB;
4943
4944 // Use two PHI nodes to select two reults
4945 BuildMI(BB&: *BB, I: BB->begin(), MIMD: DL, MCID: TII->get(Opcode: Mips::PHI), DestReg: MI.getOperand(i: 0).getReg())
4946 .addReg(RegNo: MI.getOperand(i: 3).getReg())
4947 .addMBB(MBB: thisMBB)
4948 .addReg(RegNo: MI.getOperand(i: 5).getReg())
4949 .addMBB(MBB: copy0MBB);
4950 BuildMI(BB&: *BB, I: BB->begin(), MIMD: DL, MCID: TII->get(Opcode: Mips::PHI), DestReg: MI.getOperand(i: 1).getReg())
4951 .addReg(RegNo: MI.getOperand(i: 4).getReg())
4952 .addMBB(MBB: thisMBB)
4953 .addReg(RegNo: MI.getOperand(i: 6).getReg())
4954 .addMBB(MBB: copy0MBB);
4955
4956 MI.eraseFromParent(); // The pseudo instruction is gone now.
4957
4958 return BB;
4959}
4960
4961// FIXME? Maybe this could be a TableGen attribute on some registers and
4962// this table could be generated automatically from RegInfo.
4963Register
4964MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT,
4965 const MachineFunction &MF) const {
4966 // The Linux kernel uses $28 and sp.
4967 if (Subtarget.isGP64bit()) {
4968 Register Reg = StringSwitch<Register>(RegName)
4969 .Case(S: "$28", Value: Mips::GP_64)
4970 .Case(S: "sp", Value: Mips::SP_64)
4971 .Default(Value: Register());
4972 return Reg;
4973 }
4974
4975 Register Reg = StringSwitch<Register>(RegName)
4976 .Case(S: "$28", Value: Mips::GP)
4977 .Case(S: "sp", Value: Mips::SP)
4978 .Default(Value: Register());
4979 return Reg;
4980}
4981
4982MachineBasicBlock *MipsTargetLowering::emitLDR_W(MachineInstr &MI,
4983 MachineBasicBlock *BB) const {
4984 MachineFunction *MF = BB->getParent();
4985 MachineRegisterInfo &MRI = MF->getRegInfo();
4986 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
4987 const bool IsLittle = Subtarget.isLittle();
4988 DebugLoc DL = MI.getDebugLoc();
4989
4990 Register Dest = MI.getOperand(i: 0).getReg();
4991 Register Address = MI.getOperand(i: 1).getReg();
4992 unsigned Imm = MI.getOperand(i: 2).getImm();
4993
4994 MachineBasicBlock::iterator I(MI);
4995
4996 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) {
4997 // Mips release 6 can load from adress that is not naturally-aligned.
4998 Register Temp = MRI.createVirtualRegister(RegClass: &Mips::GPR32RegClass);
4999 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::LW))
5000 .addDef(RegNo: Temp)
5001 .addUse(RegNo: Address)
5002 .addImm(Val: Imm);
5003 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::FILL_W)).addDef(RegNo: Dest).addUse(RegNo: Temp);
5004 } else {
5005 // Mips release 5 needs to use instructions that can load from an unaligned
5006 // memory address.
5007 Register LoadHalf = MRI.createVirtualRegister(RegClass: &Mips::GPR32RegClass);
5008 Register LoadFull = MRI.createVirtualRegister(RegClass: &Mips::GPR32RegClass);
5009 Register Undef = MRI.createVirtualRegister(RegClass: &Mips::GPR32RegClass);
5010 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::IMPLICIT_DEF)).addDef(RegNo: Undef);
5011 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::LWR))
5012 .addDef(RegNo: LoadHalf)
5013 .addUse(RegNo: Address)
5014 .addImm(Val: Imm + (IsLittle ? 0 : 3))
5015 .addUse(RegNo: Undef);
5016 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::LWL))
5017 .addDef(RegNo: LoadFull)
5018 .addUse(RegNo: Address)
5019 .addImm(Val: Imm + (IsLittle ? 3 : 0))
5020 .addUse(RegNo: LoadHalf);
5021 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::FILL_W)).addDef(RegNo: Dest).addUse(RegNo: LoadFull);
5022 }
5023
5024 MI.eraseFromParent();
5025 return BB;
5026}
5027
5028MachineBasicBlock *MipsTargetLowering::emitLDR_D(MachineInstr &MI,
5029 MachineBasicBlock *BB) const {
5030 MachineFunction *MF = BB->getParent();
5031 MachineRegisterInfo &MRI = MF->getRegInfo();
5032 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
5033 const bool IsLittle = Subtarget.isLittle();
5034 DebugLoc DL = MI.getDebugLoc();
5035
5036 Register Dest = MI.getOperand(i: 0).getReg();
5037 Register Address = MI.getOperand(i: 1).getReg();
5038 unsigned Imm = MI.getOperand(i: 2).getImm();
5039
5040 MachineBasicBlock::iterator I(MI);
5041
5042 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) {
5043 // Mips release 6 can load from adress that is not naturally-aligned.
5044 if (Subtarget.isGP64bit()) {
5045 Register Temp = MRI.createVirtualRegister(RegClass: &Mips::GPR64RegClass);
5046 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::LD))
5047 .addDef(RegNo: Temp)
5048 .addUse(RegNo: Address)
5049 .addImm(Val: Imm);
5050 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::FILL_D)).addDef(RegNo: Dest).addUse(RegNo: Temp);
5051 } else {
5052 Register Wtemp = MRI.createVirtualRegister(RegClass: &Mips::MSA128WRegClass);
5053 Register Lo = MRI.createVirtualRegister(RegClass: &Mips::GPR32RegClass);
5054 Register Hi = MRI.createVirtualRegister(RegClass: &Mips::GPR32RegClass);
5055 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::LW))
5056 .addDef(RegNo: Lo)
5057 .addUse(RegNo: Address)
5058 .addImm(Val: Imm + (IsLittle ? 0 : 4));
5059 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::LW))
5060 .addDef(RegNo: Hi)
5061 .addUse(RegNo: Address)
5062 .addImm(Val: Imm + (IsLittle ? 4 : 0));
5063 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::FILL_W)).addDef(RegNo: Wtemp).addUse(RegNo: Lo);
5064 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::INSERT_W), DestReg: Dest)
5065 .addUse(RegNo: Wtemp)
5066 .addUse(RegNo: Hi)
5067 .addImm(Val: 1);
5068 }
5069 } else {
5070 // Mips release 5 needs to use instructions that can load from an unaligned
5071 // memory address.
5072 Register LoHalf = MRI.createVirtualRegister(RegClass: &Mips::GPR32RegClass);
5073 Register LoFull = MRI.createVirtualRegister(RegClass: &Mips::GPR32RegClass);
5074 Register LoUndef = MRI.createVirtualRegister(RegClass: &Mips::GPR32RegClass);
5075 Register HiHalf = MRI.createVirtualRegister(RegClass: &Mips::GPR32RegClass);
5076 Register HiFull = MRI.createVirtualRegister(RegClass: &Mips::GPR32RegClass);
5077 Register HiUndef = MRI.createVirtualRegister(RegClass: &Mips::GPR32RegClass);
5078 Register Wtemp = MRI.createVirtualRegister(RegClass: &Mips::MSA128WRegClass);
5079 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::IMPLICIT_DEF)).addDef(RegNo: LoUndef);
5080 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::LWR))
5081 .addDef(RegNo: LoHalf)
5082 .addUse(RegNo: Address)
5083 .addImm(Val: Imm + (IsLittle ? 0 : 7))
5084 .addUse(RegNo: LoUndef);
5085 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::LWL))
5086 .addDef(RegNo: LoFull)
5087 .addUse(RegNo: Address)
5088 .addImm(Val: Imm + (IsLittle ? 3 : 4))
5089 .addUse(RegNo: LoHalf);
5090 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::IMPLICIT_DEF)).addDef(RegNo: HiUndef);
5091 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::LWR))
5092 .addDef(RegNo: HiHalf)
5093 .addUse(RegNo: Address)
5094 .addImm(Val: Imm + (IsLittle ? 4 : 3))
5095 .addUse(RegNo: HiUndef);
5096 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::LWL))
5097 .addDef(RegNo: HiFull)
5098 .addUse(RegNo: Address)
5099 .addImm(Val: Imm + (IsLittle ? 7 : 0))
5100 .addUse(RegNo: HiHalf);
5101 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::FILL_W)).addDef(RegNo: Wtemp).addUse(RegNo: LoFull);
5102 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::INSERT_W), DestReg: Dest)
5103 .addUse(RegNo: Wtemp)
5104 .addUse(RegNo: HiFull)
5105 .addImm(Val: 1);
5106 }
5107
5108 MI.eraseFromParent();
5109 return BB;
5110}
5111
5112MachineBasicBlock *MipsTargetLowering::emitSTR_W(MachineInstr &MI,
5113 MachineBasicBlock *BB) const {
5114 MachineFunction *MF = BB->getParent();
5115 MachineRegisterInfo &MRI = MF->getRegInfo();
5116 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
5117 const bool IsLittle = Subtarget.isLittle();
5118 DebugLoc DL = MI.getDebugLoc();
5119
5120 Register StoreVal = MI.getOperand(i: 0).getReg();
5121 Register Address = MI.getOperand(i: 1).getReg();
5122 unsigned Imm = MI.getOperand(i: 2).getImm();
5123
5124 MachineBasicBlock::iterator I(MI);
5125
5126 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) {
5127 // Mips release 6 can store to adress that is not naturally-aligned.
5128 Register BitcastW = MRI.createVirtualRegister(RegClass: &Mips::MSA128WRegClass);
5129 Register Tmp = MRI.createVirtualRegister(RegClass: &Mips::GPR32RegClass);
5130 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::COPY)).addDef(RegNo: BitcastW).addUse(RegNo: StoreVal);
5131 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::COPY_S_W))
5132 .addDef(RegNo: Tmp)
5133 .addUse(RegNo: BitcastW)
5134 .addImm(Val: 0);
5135 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::SW))
5136 .addUse(RegNo: Tmp)
5137 .addUse(RegNo: Address)
5138 .addImm(Val: Imm);
5139 } else {
5140 // Mips release 5 needs to use instructions that can store to an unaligned
5141 // memory address.
5142 Register Tmp = MRI.createVirtualRegister(RegClass: &Mips::GPR32RegClass);
5143 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::COPY_S_W))
5144 .addDef(RegNo: Tmp)
5145 .addUse(RegNo: StoreVal)
5146 .addImm(Val: 0);
5147 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::SWR))
5148 .addUse(RegNo: Tmp)
5149 .addUse(RegNo: Address)
5150 .addImm(Val: Imm + (IsLittle ? 0 : 3));
5151 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::SWL))
5152 .addUse(RegNo: Tmp)
5153 .addUse(RegNo: Address)
5154 .addImm(Val: Imm + (IsLittle ? 3 : 0));
5155 }
5156
5157 MI.eraseFromParent();
5158
5159 return BB;
5160}
5161
5162MachineBasicBlock *MipsTargetLowering::emitSTR_D(MachineInstr &MI,
5163 MachineBasicBlock *BB) const {
5164 MachineFunction *MF = BB->getParent();
5165 MachineRegisterInfo &MRI = MF->getRegInfo();
5166 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
5167 const bool IsLittle = Subtarget.isLittle();
5168 DebugLoc DL = MI.getDebugLoc();
5169
5170 Register StoreVal = MI.getOperand(i: 0).getReg();
5171 Register Address = MI.getOperand(i: 1).getReg();
5172 unsigned Imm = MI.getOperand(i: 2).getImm();
5173
5174 MachineBasicBlock::iterator I(MI);
5175
5176 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) {
5177 // Mips release 6 can store to adress that is not naturally-aligned.
5178 if (Subtarget.isGP64bit()) {
5179 Register BitcastD = MRI.createVirtualRegister(RegClass: &Mips::MSA128DRegClass);
5180 Register Lo = MRI.createVirtualRegister(RegClass: &Mips::GPR64RegClass);
5181 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::COPY))
5182 .addDef(RegNo: BitcastD)
5183 .addUse(RegNo: StoreVal);
5184 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::COPY_S_D))
5185 .addDef(RegNo: Lo)
5186 .addUse(RegNo: BitcastD)
5187 .addImm(Val: 0);
5188 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::SD))
5189 .addUse(RegNo: Lo)
5190 .addUse(RegNo: Address)
5191 .addImm(Val: Imm);
5192 } else {
5193 Register BitcastW = MRI.createVirtualRegister(RegClass: &Mips::MSA128WRegClass);
5194 Register Lo = MRI.createVirtualRegister(RegClass: &Mips::GPR32RegClass);
5195 Register Hi = MRI.createVirtualRegister(RegClass: &Mips::GPR32RegClass);
5196 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::COPY))
5197 .addDef(RegNo: BitcastW)
5198 .addUse(RegNo: StoreVal);
5199 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::COPY_S_W))
5200 .addDef(RegNo: Lo)
5201 .addUse(RegNo: BitcastW)
5202 .addImm(Val: 0);
5203 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::COPY_S_W))
5204 .addDef(RegNo: Hi)
5205 .addUse(RegNo: BitcastW)
5206 .addImm(Val: 1);
5207 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::SW))
5208 .addUse(RegNo: Lo)
5209 .addUse(RegNo: Address)
5210 .addImm(Val: Imm + (IsLittle ? 0 : 4));
5211 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::SW))
5212 .addUse(RegNo: Hi)
5213 .addUse(RegNo: Address)
5214 .addImm(Val: Imm + (IsLittle ? 4 : 0));
5215 }
5216 } else {
5217 // Mips release 5 needs to use instructions that can store to an unaligned
5218 // memory address.
5219 Register Bitcast = MRI.createVirtualRegister(RegClass: &Mips::MSA128WRegClass);
5220 Register Lo = MRI.createVirtualRegister(RegClass: &Mips::GPR32RegClass);
5221 Register Hi = MRI.createVirtualRegister(RegClass: &Mips::GPR32RegClass);
5222 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::COPY)).addDef(RegNo: Bitcast).addUse(RegNo: StoreVal);
5223 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::COPY_S_W))
5224 .addDef(RegNo: Lo)
5225 .addUse(RegNo: Bitcast)
5226 .addImm(Val: 0);
5227 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::COPY_S_W))
5228 .addDef(RegNo: Hi)
5229 .addUse(RegNo: Bitcast)
5230 .addImm(Val: 1);
5231 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::SWR))
5232 .addUse(RegNo: Lo)
5233 .addUse(RegNo: Address)
5234 .addImm(Val: Imm + (IsLittle ? 0 : 3));
5235 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::SWL))
5236 .addUse(RegNo: Lo)
5237 .addUse(RegNo: Address)
5238 .addImm(Val: Imm + (IsLittle ? 3 : 0));
5239 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::SWR))
5240 .addUse(RegNo: Hi)
5241 .addUse(RegNo: Address)
5242 .addImm(Val: Imm + (IsLittle ? 4 : 7));
5243 BuildMI(BB&: *BB, I, MIMD: DL, MCID: TII->get(Opcode: Mips::SWL))
5244 .addUse(RegNo: Hi)
5245 .addUse(RegNo: Address)
5246 .addImm(Val: Imm + (IsLittle ? 7 : 4));
5247 }
5248
5249 MI.eraseFromParent();
5250 return BB;
5251}
5252