1//===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Subclass of MipsDAGToDAGISel specialized for mips32/64.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsSEISelDAGToDAG.h"
14#include "Mips.h"
15#include "MipsAnalyzeImmediate.h"
16#include "MipsMachineFunction.h"
17#include "MipsRegisterInfo.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/SelectionDAGNodes.h"
23#include "llvm/IR/Dominators.h"
24#include "llvm/IR/GlobalValue.h"
25#include "llvm/IR/Instructions.h"
26#include "llvm/IR/Intrinsics.h"
27#include "llvm/IR/IntrinsicsMips.h"
28#include "llvm/IR/Type.h"
29#include "llvm/Support/ErrorHandling.h"
30#include "llvm/Target/TargetMachine.h"
31using namespace llvm;
32
33#define DEBUG_TYPE "mips-isel"
34
35bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
36 Subtarget = &MF.getSubtarget<MipsSubtarget>();
37 if (Subtarget->inMips16Mode())
38 return false;
39 return MipsDAGToDAGISel::runOnMachineFunction(MF);
40}
41
42void MipsSEDAGToDAGISelLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
43 SelectionDAGISelLegacy::getAnalysisUsage(AU);
44}
45
46void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
47 MachineFunction &MF) {
48 MachineInstrBuilder MIB(MF, &MI);
49 unsigned Mask = MI.getOperand(i: 1).getImm();
50 RegState Flag =
51 IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef;
52
53 if (Mask & 1)
54 MIB.addReg(RegNo: Mips::DSPPos, Flags: Flag);
55
56 if (Mask & 2)
57 MIB.addReg(RegNo: Mips::DSPSCount, Flags: Flag);
58
59 if (Mask & 4)
60 MIB.addReg(RegNo: Mips::DSPCarry, Flags: Flag);
61
62 if (Mask & 8)
63 MIB.addReg(RegNo: Mips::DSPOutFlag, Flags: Flag);
64
65 if (Mask & 16)
66 MIB.addReg(RegNo: Mips::DSPCCond, Flags: Flag);
67
68 if (Mask & 32)
69 MIB.addReg(RegNo: Mips::DSPEFI, Flags: Flag);
70}
71
72MCRegister MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
73 uint64_t RegNum = RegIdx->getAsZExtVal();
74 return Mips::MSACtrlRegClass.getRegister(i: RegNum);
75}
76
77bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
78 const MachineInstr& MI) {
79 unsigned DstReg = 0, ZeroReg = 0;
80
81 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
82 if ((MI.getOpcode() == Mips::ADDiu) &&
83 (MI.getOperand(i: 1).getReg() == Mips::ZERO) &&
84 (MI.getOperand(i: 2).isImm()) &&
85 (MI.getOperand(i: 2).getImm() == 0)) {
86 DstReg = MI.getOperand(i: 0).getReg();
87 ZeroReg = Mips::ZERO;
88 } else if ((MI.getOpcode() == Mips::DADDiu) &&
89 (MI.getOperand(i: 1).getReg() == Mips::ZERO_64) &&
90 (MI.getOperand(i: 2).isImm()) &&
91 (MI.getOperand(i: 2).getImm() == 0)) {
92 DstReg = MI.getOperand(i: 0).getReg();
93 ZeroReg = Mips::ZERO_64;
94 }
95
96 if (!DstReg)
97 return false;
98
99 // Replace uses with ZeroReg.
100 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(RegNo: DstReg),
101 E = MRI->use_end(); U != E;) {
102 MachineOperand &MO = *U;
103 unsigned OpNo = U.getOperandNo();
104 MachineInstr *MI = MO.getParent();
105 ++U;
106
107 // Do not replace if it is a phi's operand or is tied to def operand.
108 if (MI->isPHI() || MI->isRegTiedToDefOperand(UseOpIdx: OpNo) || MI->isPseudo())
109 continue;
110
111 // Also, we have to check that the register class of the operand
112 // contains the zero register.
113 if (!MRI->getRegClass(Reg: MO.getReg())->contains(Reg: ZeroReg))
114 continue;
115
116 MO.setReg(ZeroReg);
117 }
118
119 return true;
120}
121
122void MipsSEDAGToDAGISel::emitMCountABI(MachineInstr &MI, MachineBasicBlock &MBB,
123 MachineFunction &MF) {
124 MachineInstrBuilder MIB(MF, &MI);
125 if (!Subtarget->isABI_O32()) { // N32, N64
126 // Save current return address.
127 BuildMI(BB&: MBB, I: &MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: Mips::OR64))
128 .addDef(RegNo: Mips::AT_64)
129 .addUse(RegNo: Mips::RA_64, Flags: RegState::Undef)
130 .addUse(RegNo: Mips::ZERO_64);
131 // Stops instruction above from being removed later on.
132 MIB.addUse(RegNo: Mips::AT_64, Flags: RegState::Implicit);
133 } else { // O32
134 // Save current return address.
135 BuildMI(BB&: MBB, I: &MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: Mips::OR))
136 .addDef(RegNo: Mips::AT)
137 .addUse(RegNo: Mips::RA, Flags: RegState::Undef)
138 .addUse(RegNo: Mips::ZERO);
139 // _mcount pops 2 words from stack.
140 BuildMI(BB&: MBB, I: &MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: Mips::ADDiu))
141 .addDef(RegNo: Mips::SP)
142 .addUse(RegNo: Mips::SP)
143 .addImm(Val: -8);
144 // Stops first instruction above from being removed later on.
145 MIB.addUse(RegNo: Mips::AT, Flags: RegState::Implicit);
146 }
147}
148
149void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
150 MF.getInfo<MipsFunctionInfo>()->initGlobalBaseReg(MF);
151
152 MachineRegisterInfo *MRI = &MF.getRegInfo();
153
154 for (auto &MBB: MF) {
155 for (auto &MI: MBB) {
156 switch (MI.getOpcode()) {
157 case Mips::RDDSP:
158 addDSPCtrlRegOperands(IsDef: false, MI, MF);
159 break;
160 case Mips::WRDSP:
161 addDSPCtrlRegOperands(IsDef: true, MI, MF);
162 break;
163 case Mips::BuildPairF64_64:
164 case Mips::ExtractElementF64_64:
165 if (!Subtarget->useOddSPReg()) {
166 MI.addOperand(Op: MachineOperand::CreateReg(Reg: Mips::SP, isDef: false, isImp: true));
167 break;
168 }
169 [[fallthrough]];
170 case Mips::BuildPairF64:
171 case Mips::ExtractElementF64:
172 if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1())
173 MI.addOperand(Op: MachineOperand::CreateReg(Reg: Mips::SP, isDef: false, isImp: true));
174 break;
175 case Mips::JAL:
176 case Mips::JAL_MM:
177 if (MI.getOperand(i: 0).isGlobal() &&
178 MI.getOperand(i: 0).getGlobal()->hasExternalLinkage() &&
179 MI.getOperand(i: 0).getGlobal()->getName() == "_mcount")
180 emitMCountABI(MI, MBB, MF);
181 break;
182 case Mips::JALRPseudo:
183 case Mips::JALR64Pseudo:
184 case Mips::JALR16_MM:
185 if (MI.getOperand(i: 2).isMCSymbol() &&
186 MI.getOperand(i: 2).getMCSymbol()->getName() == "_mcount")
187 emitMCountABI(MI, MBB, MF);
188 break;
189 case Mips::JALR:
190 if (MI.getOperand(i: 3).isMCSymbol() &&
191 MI.getOperand(i: 3).getMCSymbol()->getName() == "_mcount")
192 emitMCountABI(MI, MBB, MF);
193 break;
194 default:
195 replaceUsesWithZeroReg(MRI, MI);
196 }
197 }
198 }
199}
200
201void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
202 SDValue InGlue = Node->getOperand(Num: 2);
203 unsigned Opc = InGlue.getOpcode();
204 SDValue LHS = Node->getOperand(Num: 0), RHS = Node->getOperand(Num: 1);
205 EVT VT = LHS.getValueType();
206
207 // In the base case, we can rely on the carry bit from the addsc
208 // instruction.
209 if (Opc == ISD::ADDC) {
210 SDValue Ops[3] = {LHS, RHS, InGlue};
211 CurDAG->SelectNodeTo(N: Node, MachineOpc: Mips::ADDWC, VT1: VT, VT2: MVT::Glue, Ops);
212 return;
213 }
214
215 assert(Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!");
216
217 // The more complex case is when there is a chain of ISD::ADDE nodes like:
218 // (adde (adde (adde (addc a b) c) d) e).
219 //
220 // The addwc instruction does not write to the carry bit, instead it writes
221 // to bit 20 of the dsp control register. To match this series of nodes, each
222 // intermediate adde node must be expanded to write the carry bit before the
223 // addition.
224
225 // Start by reading the overflow field for addsc and moving the value to the
226 // carry field. The usage of 1 here with MipsISD::RDDSP / Mips::WRDSP
227 // corresponds to reading/writing the entire control register to/from a GPR.
228
229 SDValue CstOne = CurDAG->getTargetConstant(Val: 1, DL, VT: MVT::i32);
230
231 SDValue OuFlag = CurDAG->getTargetConstant(Val: 20, DL, VT: MVT::i32);
232
233 SDNode *DSPCtrlField = CurDAG->getMachineNode(Opcode: Mips::RDDSP, dl: DL, VT1: MVT::i32,
234 VT2: MVT::Glue, Op1: CstOne, Op2: InGlue);
235
236 SDNode *Carry = CurDAG->getMachineNode(
237 Opcode: Mips::EXT, dl: DL, VT: MVT::i32, Op1: SDValue(DSPCtrlField, 0), Op2: OuFlag, Op3: CstOne);
238
239 SDValue Ops[4] = {SDValue(DSPCtrlField, 0),
240 CurDAG->getTargetConstant(Val: 6, DL, VT: MVT::i32), CstOne,
241 SDValue(Carry, 0)};
242 SDNode *DSPCFWithCarry = CurDAG->getMachineNode(Opcode: Mips::INS, dl: DL, VT: MVT::i32, Ops);
243
244 // My reading of the MIPS DSP 3.01 specification isn't as clear as I
245 // would like about whether bit 20 always gets overwritten by addwc.
246 // Hence take an extremely conservative view and presume it's sticky. We
247 // therefore need to clear it.
248
249 SDValue Zero = CurDAG->getRegister(Reg: Mips::ZERO, VT: MVT::i32);
250
251 SDValue InsOps[4] = {Zero, OuFlag, CstOne, SDValue(DSPCFWithCarry, 0)};
252 SDNode *DSPCtrlFinal =
253 CurDAG->getMachineNode(Opcode: Mips::INS, dl: DL, VT: MVT::i32, Ops: InsOps);
254
255 SDNode *WrDSP = CurDAG->getMachineNode(Opcode: Mips::WRDSP, dl: DL, VT: MVT::Glue,
256 Op1: SDValue(DSPCtrlFinal, 0), Op2: CstOne);
257
258 SDValue Operands[3] = {LHS, RHS, SDValue(WrDSP, 0)};
259 CurDAG->SelectNodeTo(N: Node, MachineOpc: Mips::ADDWC, VT1: VT, VT2: MVT::Glue, Ops: Operands);
260}
261
262/// Match frameindex
263bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
264 SDValue &Offset) const {
265 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Val&: Addr)) {
266 EVT ValTy = Addr.getValueType();
267
268 Base = CurDAG->getTargetFrameIndex(FI: FIN->getIndex(), VT: ValTy);
269 Offset = CurDAG->getTargetConstant(Val: 0, DL: SDLoc(Addr), VT: ValTy);
270 return true;
271 }
272 return false;
273}
274
275/// Match frameindex+offset and frameindex|offset
276bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(
277 SDValue Addr, SDValue &Base, SDValue &Offset, unsigned OffsetBits,
278 unsigned ShiftAmount = 0) const {
279 if (CurDAG->isBaseWithConstantOffset(Op: Addr)) {
280 auto *CN = cast<ConstantSDNode>(Val: Addr.getOperand(i: 1));
281 if (isIntN(N: OffsetBits + ShiftAmount, x: CN->getSExtValue())) {
282 EVT ValTy = Addr.getValueType();
283
284 // If the first operand is a FI, get the TargetFI Node
285 if (FrameIndexSDNode *FIN =
286 dyn_cast<FrameIndexSDNode>(Val: Addr.getOperand(i: 0)))
287 Base = CurDAG->getTargetFrameIndex(FI: FIN->getIndex(), VT: ValTy);
288 else {
289 Base = Addr.getOperand(i: 0);
290 // If base is a FI, additional offset calculation is done in
291 // eliminateFrameIndex, otherwise we need to check the alignment
292 const Align Alignment(1ULL << ShiftAmount);
293 if (!isAligned(Lhs: Alignment, SizeInBytes: CN->getZExtValue()))
294 return false;
295 }
296
297 Offset = CurDAG->getTargetConstant(Val: CN->getZExtValue(), DL: SDLoc(Addr),
298 VT: ValTy);
299 if (Base.getOpcode() == ISD::ADD &&
300 (Subtarget->hasMips1() && !Subtarget->hasMips2())) {
301 // Instead of:
302 // lui $2, %hi($CPI1_0)
303 // addiu $2, $2, %lo($CPI1_0)
304 // lwc1 $f0, 4($2)
305 // Generate:
306 // lui $2, %hi($CPI1_0)
307 // lwc1 $f0, %lo($CPI1_0+4)($2)
308 if (Base.getOperand(i: 1).getOpcode() == MipsISD::Lo ||
309 Base.getOperand(i: 1).getOpcode() == MipsISD::GPRel) {
310 SDValue Opnd0 = Base.getOperand(i: 1).getOperand(i: 0);
311 if (isa<ConstantPoolSDNode>(Val: Opnd0) || isa<JumpTableSDNode>(Val: Opnd0))
312 Base = Base.getOperand(i: 0);
313 else if (GlobalAddressSDNode *GA =
314 dyn_cast<GlobalAddressSDNode>(Val&: Opnd0)) {
315 Base = Base.getOperand(i: 0);
316 const GlobalValue *GV = GA->getGlobal();
317 int64_t GAOffset = GA->getOffset();
318 Offset = CurDAG->getTargetGlobalAddress(
319 GV, DL: SDLoc(Addr), VT: MVT::i32, offset: GAOffset + CN->getZExtValue(),
320 TargetFlags: MipsII::MO_ABS_LO);
321 return true;
322 }
323 }
324 }
325 return true;
326 }
327 }
328 return false;
329}
330
331/// ComplexPattern used on MipsInstrInfo
332/// Used on Mips Load/Store instructions
333bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
334 SDValue &Offset) const {
335 // if Address is FI, get the TargetFrameIndex.
336 if (selectAddrFrameIndex(Addr, Base, Offset))
337 return true;
338
339 // on PIC code Load GA
340 if (Addr.getOpcode() == MipsISD::Wrapper) {
341 Base = Addr.getOperand(i: 0);
342 Offset = Addr.getOperand(i: 1);
343 return true;
344 }
345
346 if (!TM.isPositionIndependent()) {
347 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
348 Addr.getOpcode() == ISD::TargetGlobalAddress))
349 return false;
350 }
351
352 // Addresses of the form FI+const or FI|const
353 if (selectAddrFrameIndexOffset(Addr, Base, Offset, OffsetBits: 16))
354 return true;
355
356 // Operand is a result from an ADD.
357 if (Addr.getOpcode() == ISD::ADD) {
358 // When loading from constant pools, load the lower address part in
359 // the instruction itself. Example, instead of:
360 // lui $2, %hi($CPI1_0)
361 // addiu $2, $2, %lo($CPI1_0)
362 // lwc1 $f0, 0($2)
363 // Generate:
364 // lui $2, %hi($CPI1_0)
365 // lwc1 $f0, %lo($CPI1_0)($2)
366 if (Addr.getOperand(i: 1).getOpcode() == MipsISD::Lo ||
367 Addr.getOperand(i: 1).getOpcode() == MipsISD::GPRel) {
368 SDValue Opnd0 = Addr.getOperand(i: 1).getOperand(i: 0);
369 if (isa<ConstantPoolSDNode>(Val: Opnd0) || isa<GlobalAddressSDNode>(Val: Opnd0) ||
370 isa<JumpTableSDNode>(Val: Opnd0)) {
371 Base = Addr.getOperand(i: 0);
372 Offset = Opnd0;
373 return true;
374 }
375 }
376 }
377
378 return false;
379}
380
381/// ComplexPattern used on MipsInstrInfo
382/// Used on Mips Load/Store instructions
383bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
384 SDValue &Offset) const {
385 Base = Addr;
386 Offset = CurDAG->getTargetConstant(Val: 0, DL: SDLoc(Addr), VT: Addr.getValueType());
387 return true;
388}
389
390bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
391 SDValue &Offset) const {
392 return selectAddrRegImm(Addr, Base, Offset) ||
393 selectAddrDefault(Addr, Base, Offset);
394}
395
396bool MipsSEDAGToDAGISel::selectAddrRegImm9(SDValue Addr, SDValue &Base,
397 SDValue &Offset) const {
398 if (selectAddrFrameIndex(Addr, Base, Offset))
399 return true;
400
401 if (selectAddrFrameIndexOffset(Addr, Base, Offset, OffsetBits: 9))
402 return true;
403
404 return false;
405}
406
407/// Used on microMIPS LWC2, LDC2, SWC2 and SDC2 instructions (11-bit offset)
408bool MipsSEDAGToDAGISel::selectAddrRegImm11(SDValue Addr, SDValue &Base,
409 SDValue &Offset) const {
410 if (selectAddrFrameIndex(Addr, Base, Offset))
411 return true;
412
413 if (selectAddrFrameIndexOffset(Addr, Base, Offset, OffsetBits: 11))
414 return true;
415
416 return false;
417}
418
419/// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
420bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
421 SDValue &Offset) const {
422 if (selectAddrFrameIndex(Addr, Base, Offset))
423 return true;
424
425 if (selectAddrFrameIndexOffset(Addr, Base, Offset, OffsetBits: 12))
426 return true;
427
428 return false;
429}
430
431bool MipsSEDAGToDAGISel::selectAddrRegImm16(SDValue Addr, SDValue &Base,
432 SDValue &Offset) const {
433 if (selectAddrFrameIndex(Addr, Base, Offset))
434 return true;
435
436 if (selectAddrFrameIndexOffset(Addr, Base, Offset, OffsetBits: 16))
437 return true;
438
439 return false;
440}
441
442bool MipsSEDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base,
443 SDValue &Offset) const {
444 return selectAddrRegImm11(Addr, Base, Offset) ||
445 selectAddrDefault(Addr, Base, Offset);
446}
447
448bool MipsSEDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base,
449 SDValue &Offset) const {
450 return selectAddrRegImm12(Addr, Base, Offset) ||
451 selectAddrDefault(Addr, Base, Offset);
452}
453
454bool MipsSEDAGToDAGISel::selectIntAddr16MM(SDValue Addr, SDValue &Base,
455 SDValue &Offset) const {
456 return selectAddrRegImm16(Addr, Base, Offset) ||
457 selectAddrDefault(Addr, Base, Offset);
458}
459
460bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
461 SDValue &Offset) const {
462 if (selectAddrFrameIndexOffset(Addr, Base, Offset, OffsetBits: 7)) {
463 if (isa<FrameIndexSDNode>(Val: Base))
464 return false;
465
466 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val&: Offset)) {
467 unsigned CnstOff = CN->getZExtValue();
468 return (CnstOff == (CnstOff & 0x3c));
469 }
470
471 return false;
472 }
473
474 // For all other cases where "lw" would be selected, don't select "lw16"
475 // because it would result in additional instructions to prepare operands.
476 if (selectAddrRegImm(Addr, Base, Offset))
477 return false;
478
479 return selectAddrDefault(Addr, Base, Offset);
480}
481
482bool MipsSEDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base,
483 SDValue &Offset) const {
484
485 if (selectAddrFrameIndex(Addr, Base, Offset))
486 return true;
487
488 if (selectAddrFrameIndexOffset(Addr, Base, Offset, OffsetBits: 10))
489 return true;
490
491 return selectAddrDefault(Addr, Base, Offset);
492}
493
494bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
495 SDValue &Offset) const {
496 if (selectAddrFrameIndex(Addr, Base, Offset))
497 return true;
498
499 if (selectAddrFrameIndexOffset(Addr, Base, Offset, OffsetBits: 10, ShiftAmount: 1))
500 return true;
501
502 return selectAddrDefault(Addr, Base, Offset);
503}
504
505bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
506 SDValue &Offset) const {
507 if (selectAddrFrameIndex(Addr, Base, Offset))
508 return true;
509
510 if (selectAddrFrameIndexOffset(Addr, Base, Offset, OffsetBits: 10, ShiftAmount: 2))
511 return true;
512
513 return selectAddrDefault(Addr, Base, Offset);
514}
515
516bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
517 SDValue &Offset) const {
518 if (selectAddrFrameIndex(Addr, Base, Offset))
519 return true;
520
521 if (selectAddrFrameIndexOffset(Addr, Base, Offset, OffsetBits: 10, ShiftAmount: 3))
522 return true;
523
524 return selectAddrDefault(Addr, Base, Offset);
525}
526
527// Select constant vector splats.
528//
529// Returns true and sets Imm if:
530// * MSA is enabled
531// * N is a ISD::BUILD_VECTOR representing a constant splat
532bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
533 unsigned MinSizeInBits) const {
534 if (!Subtarget->hasMSA())
535 return false;
536
537 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(Val: N);
538
539 if (!Node)
540 return false;
541
542 APInt SplatValue, SplatUndef;
543 unsigned SplatBitSize;
544 bool HasAnyUndefs;
545
546 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
547 MinSplatBits: MinSizeInBits, isBigEndian: !Subtarget->isLittle()))
548 return false;
549
550 Imm = SplatValue;
551
552 return true;
553}
554
555// Select constant vector splats.
556//
557// In addition to the requirements of selectVSplat(), this function returns
558// true and sets Imm if:
559// * The splat value is the same width as the elements of the vector
560// * The splat value fits in an integer with the specified signed-ness and
561// width.
562//
563// This function looks through ISD::BITCAST nodes.
564// TODO: This might not be appropriate for big-endian MSA since BITCAST is
565// sometimes a shuffle in big-endian mode.
566//
567// It's worth noting that this function is not used as part of the selection
568// of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
569// instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
570// MipsSEDAGToDAGISel::selectNode.
571bool MipsSEDAGToDAGISel::
572selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
573 unsigned ImmBitSize) const {
574 APInt ImmValue;
575 EVT EltTy = N->getValueType(ResNo: 0).getVectorElementType();
576
577 if (N->getOpcode() == ISD::BITCAST)
578 N = N->getOperand(Num: 0);
579
580 if (selectVSplat(N: N.getNode(), Imm&: ImmValue, MinSizeInBits: EltTy.getSizeInBits()) &&
581 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
582
583 if (( Signed && ImmValue.isSignedIntN(N: ImmBitSize)) ||
584 (!Signed && ImmValue.isIntN(N: ImmBitSize))) {
585 Imm = CurDAG->getTargetConstant(Val: ImmValue, DL: SDLoc(N), VT: EltTy);
586 return true;
587 }
588 }
589
590 return false;
591}
592
593// Select constant vector splats whose value is a power of 2.
594//
595// In addition to the requirements of selectVSplat(), this function returns
596// true and sets Imm if:
597// * The splat value is the same width as the elements of the vector
598// * The splat value is a power of two.
599//
600// This function looks through ISD::BITCAST nodes.
601// TODO: This might not be appropriate for big-endian MSA since BITCAST is
602// sometimes a shuffle in big-endian mode.
603bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
604 APInt ImmValue;
605 EVT EltTy = N->getValueType(ResNo: 0).getVectorElementType();
606
607 if (N->getOpcode() == ISD::BITCAST)
608 N = N->getOperand(Num: 0);
609
610 if (selectVSplat(N: N.getNode(), Imm&: ImmValue, MinSizeInBits: EltTy.getSizeInBits()) &&
611 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
612 int32_t Log2 = ImmValue.exactLogBase2();
613
614 if (Log2 != -1) {
615 Imm = CurDAG->getTargetConstant(Val: Log2, DL: SDLoc(N), VT: EltTy);
616 return true;
617 }
618 }
619
620 return false;
621}
622
623// Select constant vector splats whose value only has a consecutive sequence
624// of left-most bits set (e.g. 0b11...1100...00).
625//
626// In addition to the requirements of selectVSplat(), this function returns
627// true and sets Imm if:
628// * The splat value is the same width as the elements of the vector
629// * The splat value is a consecutive sequence of left-most bits.
630//
631// This function looks through ISD::BITCAST nodes.
632// TODO: This might not be appropriate for big-endian MSA since BITCAST is
633// sometimes a shuffle in big-endian mode.
634bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
635 APInt ImmValue;
636 EVT EltTy = N->getValueType(ResNo: 0).getVectorElementType();
637
638 if (N->getOpcode() == ISD::BITCAST)
639 N = N->getOperand(Num: 0);
640
641 if (selectVSplat(N: N.getNode(), Imm&: ImmValue, MinSizeInBits: EltTy.getSizeInBits()) &&
642 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
643 // Check if we have a leading one, then check if the whole value is a
644 // shifted mask.
645 if (ImmValue.isNegative() && ImmValue.isShiftedMask()) {
646 Imm = CurDAG->getTargetConstant(Val: ImmValue.popcount() - 1, DL: SDLoc(N), VT: EltTy);
647 return true;
648 }
649 }
650
651 return false;
652}
653
654// Select constant vector splats whose value only has a consecutive sequence
655// of right-most bits set (e.g. 0b00...0011...11).
656//
657// In addition to the requirements of selectVSplat(), this function returns
658// true and sets Imm if:
659// * The splat value is the same width as the elements of the vector
660// * The splat value is a consecutive sequence of right-most bits.
661//
662// This function looks through ISD::BITCAST nodes.
663// TODO: This might not be appropriate for big-endian MSA since BITCAST is
664// sometimes a shuffle in big-endian mode.
665bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
666 APInt ImmValue;
667 EVT EltTy = N->getValueType(ResNo: 0).getVectorElementType();
668
669 if (N->getOpcode() == ISD::BITCAST)
670 N = N->getOperand(Num: 0);
671
672 if (selectVSplat(N: N.getNode(), Imm&: ImmValue, MinSizeInBits: EltTy.getSizeInBits()) &&
673 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
674 if (ImmValue.isMask()) {
675 Imm = CurDAG->getTargetConstant(Val: ImmValue.popcount() - 1, DL: SDLoc(N), VT: EltTy);
676 return true;
677 }
678 }
679
680 return false;
681}
682
683bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
684 SDValue &Imm) const {
685 APInt ImmValue;
686 EVT EltTy = N->getValueType(ResNo: 0).getVectorElementType();
687
688 if (N->getOpcode() == ISD::BITCAST)
689 N = N->getOperand(Num: 0);
690
691 if (selectVSplat(N: N.getNode(), Imm&: ImmValue, MinSizeInBits: EltTy.getSizeInBits()) &&
692 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
693 int32_t Log2 = (~ImmValue).exactLogBase2();
694
695 if (Log2 != -1) {
696 Imm = CurDAG->getTargetConstant(Val: Log2, DL: SDLoc(N), VT: EltTy);
697 return true;
698 }
699 }
700
701 return false;
702}
703
704// Select const vector splat of 1.
705bool MipsSEDAGToDAGISel::selectVSplatImmEq1(SDValue N) const {
706 APInt ImmValue;
707 EVT EltTy = N->getValueType(ResNo: 0).getVectorElementType();
708
709 if (N->getOpcode() == ISD::BITCAST)
710 N = N->getOperand(Num: 0);
711
712 return selectVSplat(N: N.getNode(), Imm&: ImmValue, MinSizeInBits: EltTy.getSizeInBits()) &&
713 ImmValue.getBitWidth() == EltTy.getSizeInBits() && ImmValue == 1;
714}
715
716bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
717 unsigned Opcode = Node->getOpcode();
718 SDLoc DL(Node);
719
720 ///
721 // Instruction Selection not handled by the auto-generated
722 // tablegen selection should be handled here.
723 ///
724 switch(Opcode) {
725 default: break;
726
727 case MipsISD::DOUBLE_SELECT_I:
728 case MipsISD::DOUBLE_SELECT_I64: {
729 MVT VT = Subtarget->isGP64bit() ? MVT::i64 : MVT::i32;
730 SDValue cond = Node->getOperand(Num: 0);
731 SDValue Hi1 = Node->getOperand(Num: 1);
732 SDValue Lo1 = Node->getOperand(Num: 2);
733 SDValue Hi2 = Node->getOperand(Num: 3);
734 SDValue Lo2 = Node->getOperand(Num: 4);
735
736 SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2};
737 EVT NodeTys[] = {VT, VT};
738 ReplaceNode(F: Node, T: CurDAG->getMachineNode(Opcode: Subtarget->isGP64bit()
739 ? Mips::PseudoD_SELECT_I64
740 : Mips::PseudoD_SELECT_I,
741 dl: DL, ResultTys: NodeTys, Ops: ops));
742 return true;
743 }
744
745 case ISD::ADDE: {
746 selectAddE(Node, DL);
747 return true;
748 }
749
750 case ISD::ConstantFP: {
751 auto *CN = cast<ConstantFPSDNode>(Val: Node);
752 if (Node->getValueType(ResNo: 0) == MVT::f64 && CN->isPosZero()) {
753 if (Subtarget->isGP64bit()) {
754 SDValue Zero = CurDAG->getCopyFromReg(Chain: CurDAG->getEntryNode(), dl: DL,
755 Reg: Mips::ZERO_64, VT: MVT::i64);
756 ReplaceNode(F: Node,
757 T: CurDAG->getMachineNode(Opcode: Mips::DMTC1, dl: DL, VT: MVT::f64, Op1: Zero));
758 } else if (Subtarget->isFP64bit()) {
759 SDValue Zero = CurDAG->getCopyFromReg(Chain: CurDAG->getEntryNode(), dl: DL,
760 Reg: Mips::ZERO, VT: MVT::i32);
761 ReplaceNode(F: Node, T: CurDAG->getMachineNode(Opcode: Mips::BuildPairF64_64, dl: DL,
762 VT: MVT::f64, Op1: Zero, Op2: Zero));
763 } else {
764 SDValue Zero = CurDAG->getCopyFromReg(Chain: CurDAG->getEntryNode(), dl: DL,
765 Reg: Mips::ZERO, VT: MVT::i32);
766 ReplaceNode(F: Node, T: CurDAG->getMachineNode(Opcode: Mips::BuildPairF64, dl: DL,
767 VT: MVT::f64, Op1: Zero, Op2: Zero));
768 }
769 return true;
770 }
771 break;
772 }
773
774 case ISD::Constant: {
775 auto *CN = cast<ConstantSDNode>(Val: Node);
776 int64_t Imm = CN->getSExtValue();
777 unsigned Size = CN->getValueSizeInBits(ResNo: 0);
778
779 if (isInt<32>(x: Imm))
780 break;
781
782 MipsAnalyzeImmediate AnalyzeImm;
783
784 const MipsAnalyzeImmediate::InstSeq &Seq =
785 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu: false);
786
787 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
788 SDLoc DL(CN);
789 SDNode *RegOpnd;
790 SDValue ImmOpnd = CurDAG->getTargetConstant(Val: SignExtend64<16>(x: Inst->ImmOpnd),
791 DL, VT: MVT::i64);
792
793 // The first instruction can be a LUi which is different from other
794 // instructions (ADDiu, ORI and SLL) in that it does not have a register
795 // operand.
796 if (Inst->Opc == Mips::LUi64)
797 RegOpnd = CurDAG->getMachineNode(Opcode: Inst->Opc, dl: DL, VT: MVT::i64, Op1: ImmOpnd);
798 else
799 RegOpnd =
800 CurDAG->getMachineNode(Opcode: Inst->Opc, dl: DL, VT: MVT::i64,
801 Op1: CurDAG->getRegister(Reg: Mips::ZERO_64, VT: MVT::i64),
802 Op2: ImmOpnd);
803
804 // The remaining instructions in the sequence are handled here.
805 for (++Inst; Inst != Seq.end(); ++Inst) {
806 ImmOpnd = CurDAG->getTargetConstant(Val: SignExtend64<16>(x: Inst->ImmOpnd), DL,
807 VT: MVT::i64);
808 RegOpnd = CurDAG->getMachineNode(Opcode: Inst->Opc, dl: DL, VT: MVT::i64,
809 Op1: SDValue(RegOpnd, 0), Op2: ImmOpnd);
810 }
811
812 ReplaceNode(F: Node, T: RegOpnd);
813 return true;
814 }
815
816 case ISD::INTRINSIC_W_CHAIN: {
817 const unsigned IntrinsicOpcode = Node->getConstantOperandVal(Num: 1);
818 switch (IntrinsicOpcode) {
819 default:
820 break;
821
822 case Intrinsic::mips_cfcmsa: {
823 SDValue ChainIn = Node->getOperand(Num: 0);
824 SDValue RegIdx = Node->getOperand(Num: 2);
825 SDValue Reg = CurDAG->getCopyFromReg(Chain: ChainIn, dl: DL,
826 Reg: getMSACtrlReg(RegIdx), VT: MVT::i32);
827 ReplaceNode(F: Node, T: Reg.getNode());
828 return true;
829 }
830 case Intrinsic::mips_ldr_d:
831 case Intrinsic::mips_ldr_w: {
832 unsigned Op = (IntrinsicOpcode == Intrinsic::mips_ldr_d) ? Mips::LDR_D
833 : Mips::LDR_W;
834
835 SDLoc DL(Node);
836 assert(Node->getNumOperands() == 4 && "Unexpected number of operands.");
837 const SDValue &Chain = Node->getOperand(Num: 0);
838 const SDValue &Intrinsic = Node->getOperand(Num: 1);
839 const SDValue &Pointer = Node->getOperand(Num: 2);
840 const SDValue &Constant = Node->getOperand(Num: 3);
841
842 assert(Chain.getValueType() == MVT::Other);
843 (void)Intrinsic;
844 assert(Intrinsic.getOpcode() == ISD::TargetConstant &&
845 Constant.getOpcode() == ISD::Constant &&
846 "Invalid instruction operand.");
847
848 // Convert Constant to TargetConstant.
849 const ConstantInt *Val =
850 cast<ConstantSDNode>(Val: Constant)->getConstantIntValue();
851 SDValue Imm =
852 CurDAG->getTargetConstant(Val: *Val, DL, VT: Constant.getValueType());
853
854 SmallVector<SDValue, 3> Ops{Pointer, Imm, Chain};
855
856 assert(Node->getNumValues() == 2);
857 assert(Node->getValueType(0).is128BitVector());
858 assert(Node->getValueType(1) == MVT::Other);
859 SmallVector<EVT, 2> ResTys{Node->getValueType(ResNo: 0), Node->getValueType(ResNo: 1)};
860
861 ReplaceNode(F: Node, T: CurDAG->getMachineNode(Opcode: Op, dl: DL, ResultTys: ResTys, Ops));
862
863 return true;
864 }
865 }
866 break;
867 }
868
869 case ISD::INTRINSIC_WO_CHAIN: {
870 switch (Node->getConstantOperandVal(Num: 0)) {
871 default:
872 break;
873
874 case Intrinsic::mips_move_v:
875 // Like an assignment but will always produce a move.v even if
876 // unnecessary.
877 ReplaceNode(F: Node, T: CurDAG->getMachineNode(Opcode: Mips::MOVE_V, dl: DL,
878 VT: Node->getValueType(ResNo: 0),
879 Op1: Node->getOperand(Num: 1)));
880 return true;
881 }
882 break;
883 }
884
885 case ISD::INTRINSIC_VOID: {
886 const unsigned IntrinsicOpcode = Node->getConstantOperandVal(Num: 1);
887 switch (IntrinsicOpcode) {
888 default:
889 break;
890
891 case Intrinsic::mips_ctcmsa: {
892 SDValue ChainIn = Node->getOperand(Num: 0);
893 SDValue RegIdx = Node->getOperand(Num: 2);
894 SDValue Value = Node->getOperand(Num: 3);
895 SDValue ChainOut = CurDAG->getCopyToReg(Chain: ChainIn, dl: DL,
896 Reg: getMSACtrlReg(RegIdx), N: Value);
897 ReplaceNode(F: Node, T: ChainOut.getNode());
898 return true;
899 }
900 case Intrinsic::mips_str_d:
901 case Intrinsic::mips_str_w: {
902 unsigned Op = (IntrinsicOpcode == Intrinsic::mips_str_d) ? Mips::STR_D
903 : Mips::STR_W;
904
905 SDLoc DL(Node);
906 assert(Node->getNumOperands() == 5 && "Unexpected number of operands.");
907 const SDValue &Chain = Node->getOperand(Num: 0);
908 const SDValue &Intrinsic = Node->getOperand(Num: 1);
909 const SDValue &Vec = Node->getOperand(Num: 2);
910 const SDValue &Pointer = Node->getOperand(Num: 3);
911 const SDValue &Constant = Node->getOperand(Num: 4);
912
913 assert(Chain.getValueType() == MVT::Other);
914 (void)Intrinsic;
915 assert(Intrinsic.getOpcode() == ISD::TargetConstant &&
916 Constant.getOpcode() == ISD::Constant &&
917 "Invalid instruction operand.");
918
919 // Convert Constant to TargetConstant.
920 const ConstantInt *Val =
921 cast<ConstantSDNode>(Val: Constant)->getConstantIntValue();
922 SDValue Imm =
923 CurDAG->getTargetConstant(Val: *Val, DL, VT: Constant.getValueType());
924
925 SmallVector<SDValue, 4> Ops{Vec, Pointer, Imm, Chain};
926
927 assert(Node->getNumValues() == 1);
928 assert(Node->getValueType(0) == MVT::Other);
929 SmallVector<EVT, 1> ResTys{Node->getValueType(ResNo: 0)};
930
931 ReplaceNode(F: Node, T: CurDAG->getMachineNode(Opcode: Op, dl: DL, ResultTys: ResTys, Ops));
932 return true;
933 }
934 }
935 break;
936 }
937
938 case MipsISD::FAbs: {
939 MVT ResTy = Node->getSimpleValueType(ResNo: 0);
940 assert((ResTy == MVT::f64 || ResTy == MVT::f32) &&
941 "Unsupported float type!");
942 unsigned Opc = 0;
943 if (ResTy == MVT::f64)
944 Opc = (Subtarget->isFP64bit() ? Mips::FABS_D64 : Mips::FABS_D32);
945 else
946 Opc = Mips::FABS_S;
947
948 if (Subtarget->inMicroMipsMode()) {
949 switch (Opc) {
950 case Mips::FABS_D64:
951 Opc = Mips::FABS_D64_MM;
952 break;
953 case Mips::FABS_D32:
954 Opc = Mips::FABS_D32_MM;
955 break;
956 case Mips::FABS_S:
957 Opc = Mips::FABS_S_MM;
958 break;
959 default:
960 llvm_unreachable("Unknown opcode for MIPS floating point abs!");
961 }
962 }
963
964 ReplaceNode(F: Node,
965 T: CurDAG->getMachineNode(Opcode: Opc, dl: DL, VT: ResTy, Op1: Node->getOperand(Num: 0)));
966
967 return true;
968 }
969
970 // Manually match MipsISD::Ins nodes to get the correct instruction. It has
971 // to be done in this fashion so that we respect the differences between
972 // dins and dinsm, as the difference is that the size operand has the range
973 // 0 < size <= 32 for dins while dinsm has the range 2 <= size <= 64 which
974 // means SelectionDAGISel would have to test all the operands at once to
975 // match the instruction.
976 case MipsISD::Ins: {
977
978 // Validating the node operands.
979 if (Node->getValueType(ResNo: 0) != MVT::i32 && Node->getValueType(ResNo: 0) != MVT::i64)
980 return false;
981
982 if (Node->getNumOperands() != 4)
983 return false;
984
985 if (Node->getOperand(Num: 1)->getOpcode() != ISD::Constant ||
986 Node->getOperand(Num: 2)->getOpcode() != ISD::Constant)
987 return false;
988
989 MVT ResTy = Node->getSimpleValueType(ResNo: 0);
990 uint64_t Pos = Node->getConstantOperandVal(Num: 1);
991 uint64_t Size = Node->getConstantOperandVal(Num: 2);
992
993 // Size has to be >0 for 'ins', 'dins' and 'dinsu'.
994 if (!Size)
995 return false;
996
997 if (Pos + Size > 64)
998 return false;
999
1000 if (ResTy != MVT::i32 && ResTy != MVT::i64)
1001 return false;
1002
1003 unsigned Opcode = 0;
1004 if (ResTy == MVT::i32) {
1005 if (Pos + Size <= 32)
1006 Opcode = Mips::INS;
1007 } else {
1008 if (Pos + Size <= 32)
1009 Opcode = Mips::DINS;
1010 else if (Pos < 32 && 1 < Size)
1011 Opcode = Mips::DINSM;
1012 else
1013 Opcode = Mips::DINSU;
1014 }
1015
1016 if (Opcode) {
1017 SDValue Ops[4] = {
1018 Node->getOperand(Num: 0), CurDAG->getTargetConstant(Val: Pos, DL, VT: MVT::i32),
1019 CurDAG->getTargetConstant(Val: Size, DL, VT: MVT::i32), Node->getOperand(Num: 3)};
1020
1021 ReplaceNode(F: Node, T: CurDAG->getMachineNode(Opcode, dl: DL, VT: ResTy, Ops));
1022 return true;
1023 }
1024
1025 return false;
1026 }
1027
1028 case MipsISD::ThreadPointer: {
1029 EVT PtrVT = getTargetLowering()->getPointerTy(DL: CurDAG->getDataLayout());
1030 unsigned RdhwrOpc, DestReg;
1031
1032 if (PtrVT == MVT::i32) {
1033 RdhwrOpc = Mips::RDHWR;
1034 DestReg = Mips::V1;
1035 } else {
1036 RdhwrOpc = Mips::RDHWR64;
1037 DestReg = Mips::V1_64;
1038 }
1039
1040 SDNode *Rdhwr =
1041 CurDAG->getMachineNode(Opcode: RdhwrOpc, dl: DL, VT1: Node->getValueType(ResNo: 0), VT2: MVT::Glue,
1042 Op1: CurDAG->getRegister(Reg: Mips::HWR29, VT: MVT::i32),
1043 Op2: CurDAG->getTargetConstant(Val: 0, DL, VT: MVT::i32));
1044 SDValue Chain = CurDAG->getCopyToReg(Chain: CurDAG->getEntryNode(), dl: DL, Reg: DestReg,
1045 N: SDValue(Rdhwr, 0), Glue: SDValue(Rdhwr, 1));
1046 SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl: DL, Reg: DestReg, VT: PtrVT,
1047 Glue: Chain.getValue(R: 1));
1048 ReplaceNode(F: Node, T: ResNode.getNode());
1049 return true;
1050 }
1051
1052 case ISD::BUILD_VECTOR: {
1053 // Select appropriate ldi.[bhwd] instructions for constant splats of
1054 // 128-bit when MSA is enabled. Fixup any register class mismatches that
1055 // occur as a result.
1056 //
1057 // This allows the compiler to use a wider range of immediates than would
1058 // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
1059 // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
1060 // 0x01010101 } without using a constant pool. This would be sub-optimal
1061 // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
1062 // same set/ of registers. Similarly, ldi.h isn't capable of producing {
1063 // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
1064
1065 const MipsABIInfo &ABI =
1066 static_cast<const MipsTargetMachine &>(TM).getABI();
1067
1068 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Val: Node);
1069 APInt SplatValue, SplatUndef;
1070 unsigned SplatBitSize;
1071 bool HasAnyUndefs;
1072 unsigned LdiOp;
1073 EVT ResVecTy = BVN->getValueType(ResNo: 0);
1074 EVT ViaVecTy;
1075
1076 if (!Subtarget->hasMSA() || !BVN->getValueType(ResNo: 0).is128BitVector())
1077 return false;
1078
1079 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
1080 HasAnyUndefs, MinSplatBits: 8,
1081 isBigEndian: !Subtarget->isLittle()))
1082 return false;
1083
1084 switch (SplatBitSize) {
1085 default:
1086 return false;
1087 case 8:
1088 LdiOp = Mips::LDI_B;
1089 ViaVecTy = MVT::v16i8;
1090 break;
1091 case 16:
1092 LdiOp = Mips::LDI_H;
1093 ViaVecTy = MVT::v8i16;
1094 break;
1095 case 32:
1096 LdiOp = Mips::LDI_W;
1097 ViaVecTy = MVT::v4i32;
1098 break;
1099 case 64:
1100 LdiOp = Mips::LDI_D;
1101 ViaVecTy = MVT::v2i64;
1102 break;
1103 }
1104
1105 SDNode *Res = nullptr;
1106
1107 // If we have a signed 10 bit integer, we can splat it directly.
1108 //
1109 // If we have something bigger we can synthesize the value into a GPR and
1110 // splat from there.
1111 if (SplatValue.isSignedIntN(N: 10)) {
1112 SDValue Imm = CurDAG->getTargetConstant(Val: SplatValue, DL,
1113 VT: ViaVecTy.getVectorElementType());
1114
1115 Res = CurDAG->getMachineNode(Opcode: LdiOp, dl: DL, VT: ViaVecTy, Op1: Imm);
1116 } else if (SplatValue.isSignedIntN(N: 16) &&
1117 ((ABI.IsO32() && SplatBitSize < 64) ||
1118 (ABI.IsN32() || ABI.IsN64()))) {
1119 // Only handle signed 16 bit values when the element size is GPR width.
1120 // MIPS64 can handle all the cases but MIPS32 would need to handle
1121 // negative cases specifically here. Instead, handle those cases as
1122 // 64bit values.
1123
1124 bool Is32BitSplat = ABI.IsO32() || SplatBitSize < 64;
1125 const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu;
1126 const MVT SplatMVT = Is32BitSplat ? MVT::i32 : MVT::i64;
1127 SDValue ZeroVal = CurDAG->getRegister(
1128 Reg: Is32BitSplat ? Mips::ZERO : Mips::ZERO_64, VT: SplatMVT);
1129
1130 const unsigned FILLOp =
1131 SplatBitSize == 16
1132 ? Mips::FILL_H
1133 : (SplatBitSize == 32 ? Mips::FILL_W
1134 : (SplatBitSize == 64 ? Mips::FILL_D : 0));
1135
1136 assert(FILLOp != 0 && "Unknown FILL Op for splat synthesis!");
1137 assert((!ABI.IsO32() || (FILLOp != Mips::FILL_D)) &&
1138 "Attempting to use fill.d on MIPS32!");
1139
1140 const unsigned Lo = SplatValue.getLoBits(numBits: 16).getZExtValue();
1141 SDValue LoVal = CurDAG->getTargetConstant(Val: Lo, DL, VT: SplatMVT);
1142
1143 Res = CurDAG->getMachineNode(Opcode: ADDiuOp, dl: DL, VT: SplatMVT, Op1: ZeroVal, Op2: LoVal);
1144 Res = CurDAG->getMachineNode(Opcode: FILLOp, dl: DL, VT: ViaVecTy, Op1: SDValue(Res, 0));
1145
1146 } else if (SplatValue.isSignedIntN(N: 32) && SplatBitSize == 32) {
1147 // Only handle the cases where the splat size agrees with the size
1148 // of the SplatValue here.
1149 const unsigned Lo = SplatValue.getLoBits(numBits: 16).getZExtValue();
1150 const unsigned Hi = SplatValue.lshr(shiftAmt: 16).getLoBits(numBits: 16).getZExtValue();
1151 SDValue ZeroVal = CurDAG->getRegister(Reg: Mips::ZERO, VT: MVT::i32);
1152
1153 SDValue LoVal = CurDAG->getTargetConstant(Val: Lo, DL, VT: MVT::i32);
1154 SDValue HiVal = CurDAG->getTargetConstant(Val: Hi, DL, VT: MVT::i32);
1155
1156 if (Hi)
1157 Res = CurDAG->getMachineNode(Opcode: Mips::LUi, dl: DL, VT: MVT::i32, Op1: HiVal);
1158
1159 if (Lo)
1160 Res = CurDAG->getMachineNode(Opcode: Mips::ORi, dl: DL, VT: MVT::i32,
1161 Op1: Hi ? SDValue(Res, 0) : ZeroVal, Op2: LoVal);
1162
1163 assert((Hi || Lo) && "Zero case reached 32 bit case splat synthesis!");
1164 Res =
1165 CurDAG->getMachineNode(Opcode: Mips::FILL_W, dl: DL, VT: MVT::v4i32, Op1: SDValue(Res, 0));
1166
1167 } else if (SplatValue.isSignedIntN(N: 32) && SplatBitSize == 64 &&
1168 (ABI.IsN32() || ABI.IsN64())) {
1169 // N32 and N64 can perform some tricks that O32 can't for signed 32 bit
1170 // integers due to having 64bit registers. lui will cause the necessary
1171 // zero/sign extension.
1172 const unsigned Lo = SplatValue.getLoBits(numBits: 16).getZExtValue();
1173 const unsigned Hi = SplatValue.lshr(shiftAmt: 16).getLoBits(numBits: 16).getZExtValue();
1174 SDValue ZeroVal = CurDAG->getRegister(Reg: Mips::ZERO, VT: MVT::i32);
1175
1176 SDValue LoVal = CurDAG->getTargetConstant(Val: Lo, DL, VT: MVT::i32);
1177 SDValue HiVal = CurDAG->getTargetConstant(Val: Hi, DL, VT: MVT::i32);
1178
1179 if (Hi)
1180 Res = CurDAG->getMachineNode(Opcode: Mips::LUi, dl: DL, VT: MVT::i32, Op1: HiVal);
1181
1182 if (Lo)
1183 Res = CurDAG->getMachineNode(Opcode: Mips::ORi, dl: DL, VT: MVT::i32,
1184 Op1: Hi ? SDValue(Res, 0) : ZeroVal, Op2: LoVal);
1185
1186 Res = CurDAG->getMachineNode(
1187 Opcode: Mips::SUBREG_TO_REG, dl: DL, VT: MVT::i64, Op1: SDValue(Res, 0),
1188 Op2: CurDAG->getTargetConstant(Val: Mips::sub_32, DL, VT: MVT::i64));
1189
1190 Res =
1191 CurDAG->getMachineNode(Opcode: Mips::FILL_D, dl: DL, VT: MVT::v2i64, Op1: SDValue(Res, 0));
1192
1193 } else if (SplatValue.isSignedIntN(N: 64)) {
1194 // If we have a 64 bit Splat value, we perform a similar sequence to the
1195 // above:
1196 //
1197 // MIPS32: MIPS64:
1198 // lui $res, %highest(val) lui $res, %highest(val)
1199 // ori $res, $res, %higher(val) ori $res, $res, %higher(val)
1200 // lui $res2, %hi(val) lui $res2, %hi(val)
1201 // ori $res2, %res2, %lo(val) ori $res2, %res2, %lo(val)
1202 // $res3 = fill $res2 dinsu $res, $res2, 0, 32
1203 // $res4 = insert.w $res3[1], $res fill.d $res
1204 // splat.d $res4, 0
1205 //
1206 // The ability to use dinsu is guaranteed as MSA requires MIPSR5.
1207 // This saves having to materialize the value by shifts and ors.
1208 //
1209 // FIXME: Implement the preferred sequence for MIPS64R6:
1210 //
1211 // MIPS64R6:
1212 // ori $res, $zero, %lo(val)
1213 // daui $res, $res, %hi(val)
1214 // dahi $res, $res, %higher(val)
1215 // dati $res, $res, %highest(cal)
1216 // fill.d $res
1217 //
1218
1219 const unsigned Lo = SplatValue.getLoBits(numBits: 16).getZExtValue();
1220 const unsigned Hi = SplatValue.lshr(shiftAmt: 16).getLoBits(numBits: 16).getZExtValue();
1221 const unsigned Higher = SplatValue.lshr(shiftAmt: 32).getLoBits(numBits: 16).getZExtValue();
1222 const unsigned Highest = SplatValue.lshr(shiftAmt: 48).getLoBits(numBits: 16).getZExtValue();
1223
1224 SDValue LoVal = CurDAG->getTargetConstant(Val: Lo, DL, VT: MVT::i32);
1225 SDValue HiVal = CurDAG->getTargetConstant(Val: Hi, DL, VT: MVT::i32);
1226 SDValue HigherVal = CurDAG->getTargetConstant(Val: Higher, DL, VT: MVT::i32);
1227 SDValue HighestVal = CurDAG->getTargetConstant(Val: Highest, DL, VT: MVT::i32);
1228 SDValue ZeroVal = CurDAG->getRegister(Reg: Mips::ZERO, VT: MVT::i32);
1229
1230 // Independent of whether we're targeting MIPS64 or not, the basic
1231 // operations are the same. Also, directly use the $zero register if
1232 // the 16 bit chunk is zero.
1233 //
1234 // For optimization purposes we always synthesize the splat value as
1235 // an i32 value, then if we're targetting MIPS64, use SUBREG_TO_REG
1236 // just before combining the values with dinsu to produce an i64. This
1237 // enables SelectionDAG to aggressively share components of splat values
1238 // where possible.
1239 //
1240 // FIXME: This is the general constant synthesis problem. This code
1241 // should be factored out into a class shared between all the
1242 // classes that need it. Specifically, for a splat size of 64
1243 // bits that's a negative number we can do better than LUi/ORi
1244 // for the upper 32bits.
1245
1246 if (Hi)
1247 Res = CurDAG->getMachineNode(Opcode: Mips::LUi, dl: DL, VT: MVT::i32, Op1: HiVal);
1248
1249 if (Lo)
1250 Res = CurDAG->getMachineNode(Opcode: Mips::ORi, dl: DL, VT: MVT::i32,
1251 Op1: Hi ? SDValue(Res, 0) : ZeroVal, Op2: LoVal);
1252
1253 SDNode *HiRes;
1254 if (Highest)
1255 HiRes = CurDAG->getMachineNode(Opcode: Mips::LUi, dl: DL, VT: MVT::i32, Op1: HighestVal);
1256
1257 if (Higher)
1258 HiRes = CurDAG->getMachineNode(Opcode: Mips::ORi, dl: DL, VT: MVT::i32,
1259 Op1: Highest ? SDValue(HiRes, 0) : ZeroVal,
1260 Op2: HigherVal);
1261
1262
1263 if (ABI.IsO32()) {
1264 Res = CurDAG->getMachineNode(Opcode: Mips::FILL_W, dl: DL, VT: MVT::v4i32,
1265 Op1: (Hi || Lo) ? SDValue(Res, 0) : ZeroVal);
1266
1267 Res = CurDAG->getMachineNode(
1268 Opcode: Mips::INSERT_W, dl: DL, VT: MVT::v4i32, Op1: SDValue(Res, 0),
1269 Op2: (Highest || Higher) ? SDValue(HiRes, 0) : ZeroVal,
1270 Op3: CurDAG->getTargetConstant(Val: 1, DL, VT: MVT::i32));
1271
1272 const TargetLowering *TLI = getTargetLowering();
1273 const TargetRegisterClass *RC =
1274 TLI->getRegClassFor(VT: ViaVecTy.getSimpleVT());
1275
1276 Res = CurDAG->getMachineNode(
1277 Opcode: Mips::COPY_TO_REGCLASS, dl: DL, VT: ViaVecTy, Op1: SDValue(Res, 0),
1278 Op2: CurDAG->getTargetConstant(Val: RC->getID(), DL, VT: MVT::i32));
1279
1280 Res = CurDAG->getMachineNode(
1281 Opcode: Mips::SPLATI_D, dl: DL, VT: MVT::v2i64, Op1: SDValue(Res, 0),
1282 Op2: CurDAG->getTargetConstant(Val: 0, DL, VT: MVT::i32));
1283 } else if (ABI.IsN64() || ABI.IsN32()) {
1284
1285 SDValue Zero64Val = CurDAG->getRegister(Reg: Mips::ZERO_64, VT: MVT::i64);
1286 const bool HiResNonZero = Highest || Higher;
1287 const bool ResNonZero = Hi || Lo;
1288
1289 if (HiResNonZero)
1290 HiRes = CurDAG->getMachineNode(
1291 Opcode: Mips::SUBREG_TO_REG, dl: DL, VT: MVT::i64, Op1: SDValue(HiRes, 0),
1292 Op2: CurDAG->getTargetConstant(Val: Mips::sub_32, DL, VT: MVT::i64));
1293
1294 if (ResNonZero)
1295 Res = CurDAG->getMachineNode(
1296 Opcode: Mips::SUBREG_TO_REG, dl: DL, VT: MVT::i64, Op1: SDValue(Res, 0),
1297 Op2: CurDAG->getTargetConstant(Val: Mips::sub_32, DL, VT: MVT::i64));
1298
1299 // We have 3 cases:
1300 // The HiRes is nonzero but Res is $zero => dsll32 HiRes, 0
1301 // The Res is nonzero but HiRes is $zero => dinsu Res, $zero, 32, 32
1302 // Both are non zero => dinsu Res, HiRes, 32, 32
1303 //
1304 // The obvious "missing" case is when both are zero, but that case is
1305 // handled by the ldi case.
1306 if (ResNonZero) {
1307 IntegerType *Int32Ty =
1308 IntegerType::get(C&: MF->getFunction().getContext(), NumBits: 32);
1309 const ConstantInt *Const32 = ConstantInt::get(Ty: Int32Ty, V: 32);
1310 SDValue Ops[4] = {HiResNonZero ? SDValue(HiRes, 0) : Zero64Val,
1311 CurDAG->getConstant(Val: *Const32, DL, VT: MVT::i32),
1312 CurDAG->getConstant(Val: *Const32, DL, VT: MVT::i32),
1313 SDValue(Res, 0)};
1314
1315 Res = CurDAG->getMachineNode(Opcode: Mips::DINSU, dl: DL, VT: MVT::i64, Ops);
1316 } else if (HiResNonZero) {
1317 Res = CurDAG->getMachineNode(
1318 Opcode: Mips::DSLL32, dl: DL, VT: MVT::i64, Op1: SDValue(HiRes, 0),
1319 Op2: CurDAG->getTargetConstant(Val: 0, DL, VT: MVT::i32));
1320 } else
1321 llvm_unreachable(
1322 "Zero splat value handled by non-zero 64bit splat synthesis!");
1323
1324 Res = CurDAG->getMachineNode(Opcode: Mips::FILL_D, dl: DL, VT: MVT::v2i64,
1325 Op1: SDValue(Res, 0));
1326 } else
1327 llvm_unreachable("Unknown ABI in MipsISelDAGToDAG!");
1328
1329 } else
1330 return false;
1331
1332 if (ResVecTy != ViaVecTy) {
1333 // If LdiOp is writing to a different register class to ResVecTy, then
1334 // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
1335 // since the source and destination register sets contain the same
1336 // registers.
1337 const TargetLowering *TLI = getTargetLowering();
1338 MVT ResVecTySimple = ResVecTy.getSimpleVT();
1339 const TargetRegisterClass *RC = TLI->getRegClassFor(VT: ResVecTySimple);
1340 Res = CurDAG->getMachineNode(Opcode: Mips::COPY_TO_REGCLASS, dl: DL,
1341 VT: ResVecTy, Op1: SDValue(Res, 0),
1342 Op2: CurDAG->getTargetConstant(Val: RC->getID(), DL,
1343 VT: MVT::i32));
1344 }
1345
1346 ReplaceNode(F: Node, T: Res);
1347 return true;
1348 }
1349
1350 }
1351
1352 return false;
1353}
1354
1355bool MipsSEDAGToDAGISel::SelectInlineAsmMemoryOperand(
1356 const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
1357 std::vector<SDValue> &OutOps) {
1358 SDValue Base, Offset;
1359
1360 switch(ConstraintID) {
1361 default:
1362 llvm_unreachable("Unexpected asm memory constraint");
1363 // All memory constraints can at least accept raw pointers.
1364 case InlineAsm::ConstraintCode::m:
1365 case InlineAsm::ConstraintCode::o:
1366 if (selectAddrRegImm16(Addr: Op, Base, Offset)) {
1367 OutOps.push_back(x: Base);
1368 OutOps.push_back(x: Offset);
1369 return false;
1370 }
1371 OutOps.push_back(x: Op);
1372 OutOps.push_back(x: CurDAG->getTargetConstant(Val: 0, DL: SDLoc(Op), VT: MVT::i32));
1373 return false;
1374 case InlineAsm::ConstraintCode::R:
1375 // The 'R' constraint is supposed to be much more complicated than this.
1376 // However, it's becoming less useful due to architectural changes and
1377 // ought to be replaced by other constraints such as 'ZC'.
1378 // For now, support 9-bit signed offsets which is supportable by all
1379 // subtargets for all instructions.
1380 if (selectAddrRegImm9(Addr: Op, Base, Offset)) {
1381 OutOps.push_back(x: Base);
1382 OutOps.push_back(x: Offset);
1383 return false;
1384 }
1385 OutOps.push_back(x: Op);
1386 OutOps.push_back(x: CurDAG->getTargetConstant(Val: 0, DL: SDLoc(Op), VT: MVT::i32));
1387 return false;
1388 case InlineAsm::ConstraintCode::ZC:
1389 // ZC matches whatever the pref, ll, and sc instructions can handle for the
1390 // given subtarget.
1391 if (Subtarget->inMicroMipsMode()) {
1392 // On microMIPS, they can handle 12-bit offsets.
1393 if (selectAddrRegImm12(Addr: Op, Base, Offset)) {
1394 OutOps.push_back(x: Base);
1395 OutOps.push_back(x: Offset);
1396 return false;
1397 }
1398 } else if (Subtarget->hasMips32r6()) {
1399 // On MIPS32r6/MIPS64r6, they can only handle 9-bit offsets.
1400 if (selectAddrRegImm9(Addr: Op, Base, Offset)) {
1401 OutOps.push_back(x: Base);
1402 OutOps.push_back(x: Offset);
1403 return false;
1404 }
1405 } else if (selectAddrRegImm16(Addr: Op, Base, Offset)) {
1406 // Prior to MIPS32r6/MIPS64r6, they can handle 16-bit offsets.
1407 OutOps.push_back(x: Base);
1408 OutOps.push_back(x: Offset);
1409 return false;
1410 }
1411 // In all cases, 0-bit offsets are acceptable.
1412 OutOps.push_back(x: Op);
1413 OutOps.push_back(x: CurDAG->getTargetConstant(Val: 0, DL: SDLoc(Op), VT: MVT::i32));
1414 return false;
1415 }
1416 return true;
1417}
1418
1419MipsSEDAGToDAGISelLegacy::MipsSEDAGToDAGISelLegacy(MipsTargetMachine &TM,
1420 CodeGenOptLevel OL)
1421 : MipsDAGToDAGISelLegacy(std::make_unique<MipsSEDAGToDAGISel>(args&: TM, args&: OL)) {}
1422
1423FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM,
1424 CodeGenOptLevel OptLevel) {
1425 return new MipsSEDAGToDAGISelLegacy(TM, OptLevel);
1426}
1427